KGD in an Era of Multi-Die Packaging and 3D Integration

Ivor Barber Director, Package Design & Characterization LSI Corporation Nov. 10 2011

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Abstract

KGD is Cool Again The surging industry interest in 2.5/3.5D packaging with its promise of

“Much More than Moore” silicon integration through the stacking of heterogeneous silicon products in a single package has made KGD a critical discipline for established and new players in the semiconductor industry. Familiar themes of supply chain, testability, fault coverage, IP protection, Failure Analysis vie with newer concepts of wide I/O testing, very high density microbumps, wear out mechanisms and even the recognition that everything cannot be tested leading to system level concepts of redundancy, fault tolerance and error correction.

In the era of 2.5D/3D the goals of a robust KGD strategy must move beyond the how to test and the what to test to include mitigation of what cannot be tested.

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2.5D/3D - An Idea Whose Time has Come

On résiste à l'invasion des armées; on ne résiste pas à l'invasion des idées.

“One can resist the invasion of armies; one cannot resist the invasion of ideas.” Victor Hugo (1802-1885)

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2.5D, 3D – A Bump in the Roadmap ?

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Motivations for 2.5D/3D Constructions

•  Reduced Latency for cache operations due to component proximity.

•  Significantly increased Bandwidth due to wide IO formats and elimination of many package to package signals.

•  Reduced Power through reduced capacitance, reduced driver strength.

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•  Miniaturization of component Footprint through concentration of multiple silicon in a single package.

•  Potential Cost reduction through elimination of multiple packages, partitioning of complex die, simplified, higher yielding final assembly etc.

Incremental improvement does not justify 3D, e.g, ~10% of latency improvement due to wire-length reduction. Need to identify killer application/novel architecture that can only be enabled by 3D integration – Professor Yuan Xie, Penn State

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DFT - Concurrent Testing

Courtesy :Teradyne

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http://wiki.sematech.org/3D-Standards-List

SEMATECH Forum Promotes 3D Interconnect Standards Development Online information sharing solution enables 3D IC industry to define and track the development of high-volume manufacturing standards ALBANY, N.Y. (November 7, 2011) – SEMATECH today announced a new online 3D Standards Dashboard solution to help meet the demand for an open, centralized forum for members of the 3D interconnect community to discuss and exchange information on standards activities

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Standards – a 4th Dimension •  We are faced with a bewildering array of emerging memory

configurations. •  Attributes include Density, Latency, Bandwidth, Power,

Footprint, Volatility, Longevity, Leakage and Cost. •  Emerging technologies such as RRAM, MRAM, FRAM.

TRAM, FBRAM and PCM are seeking a point of entry. •  Standards are required to ensure interoperability of

components resulting in predictable performance, competitive pricing and flexible supply chain.

•  Anticipate product intersection with emerging solutions. •  Individual Component versus Product life cycle is an

important consideration for DFT and Module Test Strategy

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Successful Implementation of 2.5/3D Solutions

• Design for Test from Product Inception. –  Known good die and known good stacks. – Anticipate revisions to some or all components during product life.

• Develop an Integrated Test & Manufacturing Strategy with plans to eliminate tests as yields improve for cost reduction. – Self Test, Error Correction, Fault Tolerance, Concurrent Testing.

• Guard band wafer level testing to ensure product level performance requirements are met.

• Work with the Product Owner and Customer to develop a strategy to mitigate the risk posed by those items which cannot be tested.

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