Chapter 4Digital Data Communications & Data Link Control

Asynchronous and Synchronous Transmission Errors Error Detection Error Correction Line Configurations Flow Control Error Control High-Level Data Link Control (HDLC)

Reference: William Stallings, Data and Computer Communications, 9th Edition

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Data Link Layer provides reliable transfer of information across the physical link; send blocks

(frames) with the necessary synchronization, error control, and flow control.

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Asynchronous and Synchronous Transmission

• Timing problems require a mechanism to synchronize the transmitter and receiver– receiver samples stream at bit intervals– if clocks are not aligned and drifting will sample at

wrong time after sufficient bits are sentExampleIf data rate is 1Mbps (sampling at 1ms) and there is a 1% drift between the sender’s and the receiver’s clocks. Sampling always at the center of the bit interval. After 50 samples, the receiver may be in error because it is sampling the wrong bit time (50x0.01=0.5ms)

• Two solutions to synchronizing clocks– Asynchronous transmission– Synchronous transmission

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Asynchronous Transmission

Data rate = 10 kbps (each bit = 100ms)Receiver is 6% faster(sampling rate is 94ms)

NRZ-LIdle state = 1 = -VStart bit = 0 = +VStop element = 1 = -V

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Asynchronous - Behavior

• Simple & Cheap• High overhead (2 or 3 bits per character)

(~20%)– Can reduce overhead by sending larger blocks of

bits, but also increase the cumulative timing error• Framing error– Eg., if bit 7 is 1 and bit 8 is 0, bit 8 could be

mistaken as a start bit.• Good for data with large gaps (eg.: keyboard)

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Synchronous Transmission

• Block of data transmitted sent as a frame• Clocks must be synchronized– can use separate clock line (error may still occur for long

distance transmission)– or embed clock signal in data

• Need to indicate start and end of block– use preamble and postamble

• More efficient (lower overhead) than asynchronous transmission

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Types of Error

• An error occurs when a bit is altered between transmission and reception

• Single bit errors– only one bit altered– caused by white noise

• Burst errors– contiguous sequence of B bits in which first, last and any

number of intermediate bits in error– caused by impulse noise or by fading in wireless– effect greater at higher data rates

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Error Detection

• Detect using error-detecting code, added by transmitter

• Recalculated and checked by receiver• Still chance of undetected error(s)• Parity– Parity bit set so character has even (even parity)

or odd (odd parity) number of ones– Even number of bit errors goes undetected

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Error Detection

Pb = Probability that a bit is received in error

P1 = Probability that a frame arrives with no bit error

P2 = Probability that, with an error-detecting algorithm in use, a frame arrives with one or more undetected errors

P3 = Probability that, with an error-detecting algorithm in use, a frame arrives with one or more detected bit errors but no undetected bit errors

Consider the case with no error detection, P3 = 0,

P1 = (1- Pb)F,

P2 = (1- P1);

F = # bits/frame.

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Error Detection Process

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Cyclic Redundancy Check (CRC)

• One of most common and powerful checks• For a block of k bits, transmitter generates an n bit

Frame Check Sequence (FCS)• Transmits (k+n) bits which is exactly divisible by some

number (pattern)• Receiver divides frame by that pattern– if no remainder, that means no error detected.

1. Modulo-2 Arithmetic2. Polynomial- CRC-12: X12+X11+X3+X2+X+1- CRC-16: X16+X15+X2+1- CRC-CCITT: X16+X12+X5+1- CRC-32: X32+X26+X23+X22+…+X+1

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Error Correction

• Correction of detected errors usually requires data block to be retransmitted

• Not appropriate for wireless applications– bit error rate is high causing lots of retransmissions– when propagation delay long (satellite) compared with

frame transmission time, resulting in retransmission of frame in error plus many subsequent frames

• It is desirable to correct errors on basis of bits received need Error Correction Code / Forward Error Correction (FEC)

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Error Correction Process

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How Error Correction Works• Adds redundancy to transmitted message• Deduce original despite some errors• eg. block error correction code– map k bit input onto an n bit codeword– each distinctly different– if get error assume codeword sent was closest to

that received• means have reduced effective data rate• Example: k = 2, n = 5 Data Block Codeword

00 0000001 0011110 1100111 11110

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Line Configuration - Topology

• Physical arrangement of stations on medium– Point-to-point - two stations• such as between two routers / computers

– multipoint - multiple stations

• traditionally mainframe computer and terminals• now typically a local area network (LAN)

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Line Configuration - Duplex

• Classify data exchange as half or full duplex• Half duplex (two-way alternate)– only one station may transmit at a time– requires one data path

• Full duplex (two-way simultaneous)– simultaneous transmission and reception between two

stations1. Two data paths

• separate media or frequencies used for each direction2. echo cancellation technique in the same line• process of removing echo from a voice communication

in order to improve voice quality on a telephone call