Juno ARM Development Platform SoC Technical Reference Manual · Manual (ARM DDI 0524). • ARM® Juno System Profiler Technical Reference Manual (ARM DDI 0520). • ARM® Development

Juno ARM® Development Platform SoCRevision: r0p0

Technical Reference ManualConfidential - Draft

Copyright © 2014. All rights reserved.ARM DDI 0515A-3b (ID050214)

Juno ARM Development Platform SoCTechnical Reference Manual

Copyright © 2014. All rights reserved.

Release Information

The following changes have been made to this book.

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Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Web Address

http://www.arm.com

Change history

Date Issue Confidentiality Change

21 October 2013 A-1a Confidential-Draft First draft of first release for r0p0

11 December 2013 A-2a Confidential-Draft Second draft of first release for r0p0

18 December 2013 A-2b Confidential-Draft Additional second draft of first release for r0p0

23 December 2013 A-2c Confidential-Draft Additional second draft of first release for r0p0

04 March 2014 A-3a Confidential-Draft Third draft of first release for r0p0

02 May 2014 A-3b Confidential-Draft Additional third draft of first release for r0p0

TBD A Confidential First release

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ContentsJuno ARM Development Platform SoC Technical Reference Manual

PrefaceAbout this book ........................................................................................................... viFeedback .................................................................................................................... xi

Chapter 1 Introduction1.1 About the ARM Development Platform (ADP) ......................................................... 1-21.2 Components ............................................................................................................ 1-31.3 Compliance .............................................................................................................. 1-51.4 Features ................................................................................................................... 1-81.5 Product documentation and architecture ................................................................. 1-91.6 IP revisions ............................................................................................................ 1-101.7 Product revisions ................................................................................................... 1-12

Chapter 2 Functional Description2.1 ADP components ..................................................................................................... 2-22.2 Application processors ............................................................................................. 2-32.3 Mali-T624 Graphics Processing Unit ....................................................................... 2-72.4 Memory .................................................................................................................... 2-82.5 Clocks and resets .................................................................................................. 2-102.6 ADP power-management ...................................................................................... 2-262.7 ADP power states .................................................................................................. 2-322.8 System Control Processor (SCP) .......................................................................... 2-432.9 Application processor peripherals .......................................................................... 2-482.10 Interconnect and memory system .......................................................................... 2-612.11 Security .................................................................................................................. 2-642.12 Timers .................................................................................................................... 2-752.13 Debug and profiling ................................................................................................ 2-83

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Contents

2.14 Boot ....................................................................................................................... 2-942.15 HDLCD controller ................................................................................................... 2-952.16 PCIe ....................................................................................................................... 2-962.17 Thin Links .............................................................................................................. 2-98

Chapter 3 Programmers Model3.1 About this programmers model ................................................................................ 3-23.2 Application processor interrupt map ........................................................................ 3-33.3 System Control Processor (SCP) interrupt map .................................................... 3-103.4 Application processor memory map ...................................................................... 3-133.5 System Control Processor (SCP) memory map .................................................... 3-293.6 ADP System Security Control Registers ................................................................ 3-343.7 System Configuration Controller (SCC) registers .................................................. 3-473.8 MHU Registers ...................................................................................................... 3-983.9 ADP System Control Registers ............................................................................ 3-1063.10 Debug Registers .................................................................................................. 3-1333.11 Identification Registers ........................................................................................ 3-1373.12 Power Policy Unit Registers ................................................................................ 3-1423.13 SoC peripherals NIC-400 Registers .................................................................... 3-1543.14 Compute subsystem NIC-400 Registers ............................................................. 3-1683.15 HDLCD Registers ................................................................................................ 3-1743.16 PCIe Control Registers ........................................................................................ 3-1913.17 PCIe Root Port configuration registers ................................................................ 3-2023.18 MSI Registers ...................................................................................................... 3-2323.19 Trusted Entropy Source Registers ....................................................................... 3-239

Appendix A Power and Access Control SequencesA.1 About power and access control sequences ........................................................... A-2

Appendix B Subcomponent ConfigurationsB.1 Cortex-A57 processor cluster .................................................................................. B-2B.2 Cortex-A53 processor cluster .................................................................................. B-3B.3 SCP Cortex-M3 processor configuration ................................................................. B-4B.4 Mali-T624 GPU ........................................................................................................ B-5B.5 CoreLink MMU-40x System Memory Management Unit components ..................... B-6B.6 CoreLink DMC-400 Dynamic Memory Controller .................................................... B-7B.7 CoreLink Static Memory Controller (SMC), PL354 .................................................. B-8B.8 USB host controller .................................................................................................. B-9B.9 I2S ......................................................................................................................... B-11B.10 I2C ......................................................................................................................... B-12

Appendix C Revisions

ARM DDI 0515A-3b Copyright © 2014. All rights reserved. ivID050214 Confidential - Draft

Preface

This preface introduces the Juno ARM Development Platform (ADP) Technical Reference Manual. It contains the following sections:• About this book on page vi.• Feedback on page xi.

ARM DDI 0515A-3b Copyright © 2014. All rights reserved. vID050214 Confidential - Draft

Preface

About this bookThis book is for the Juno ARM Development Platform (ADP). It provides a high-level overview of the ADP. It describes all architectural information, and as such, facilitates the creation of ADP software.

Product revision status

The rmpn identifier indicates the revision status of the product described in this book, for example, r0p0, where:rm Identifies the major revision of the product, for example, r0.pn Identifies the minor revision or modification status of the product, for example,

p0.

Intended audience

This book is written for software engineers who want to work with an ARM reference platform. The manual describes the functionality of the ADP.

Using this book

This book is organized into the following chapters:

Chapter 1 Introduction Read this for a high-level view of the ARM Development Platform (ADP) and a description of its features.

Chapter 2 Functional Description Read this for a description of the major interfaces and components of the ADP. This chapter also describes how the components operate.

Chapter 3 Programmers Model Read this for a description of the address map and registers of the ADP.

Appendix A Power and Access Control Sequences Read this for a description of the sequences for access control and power.

Appendix B Subcomponent Configurations Read this for a description of the parameter configurations for each of the system IP components used in the ARM Development Platform.

Appendix C Revisions Read this for a description of the technical changes between released issues of this book.

Glossary

The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.

The ARM Glossary is available on the ARM Infocenter at http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014-/index.html.

ARM DDI 0515A-3b Copyright © 2014. All rights reserved. viID050214 Confidential - Draft

Preface

Conventions

Conventions that this book can use are described in:• Typographical conventions.• Timing diagrams.• Signals on page viii.

Typographical conventions

The following table describes the typographical conventions:

Timing diagrams

The figure named Key to timing diagram conventions explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

Key to timing diagram conventions

Style Purpose

italic Introduces special terminology, denotes cross-references, and citations.

bold Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.

monospace Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.

monospace Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.

monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value.

monospace bold Denotes language keywords when used outside example code.

<and> Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>

SMALL CAPITALS Used in body text for a few terms that have specific technical meanings, that are defined in the ARM glossary. For example, IMPLEMENTATION DEFINED, UNKNOWN, and UNPREDICTABLE.

Clock

HIGH to LOW

Transient

HIGH/LOW to HIGH

Bus stable

Bus to high impedance

Bus change

High impedance to stable bus

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Preface

Timing diagrams sometimes show single-bit signals as HIGH and LOW at the same time and they look similar to the bus change shown in Key to timing diagram conventions on page vii. If a timing diagram shows a single-bit signal in this way then its value does not affect the accompanying description.

Signals

The signal conventions are:

Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:• HIGH for active-HIGH signals.• LOW for active-LOW signals.

Lower-case n At the start or end of a signal name denotes an active-LOW signal.

Additional reading

This section lists publications by ARM and by third parties.

See Infocenter, http://infocenter.arm.com for access to ARM documentation.

See onARM, http://www.onarm.com for embedded software development resources including the Cortex® Microcontroller Software Interface Standard (CMSIS).

ARM publications

This book contains information that is specific to this product. See the following documents for other relevant information:

• ARM® Versatile™ Express Juno Development Platform (V2M-Juno) Technical Reference Manual (ARM DDI 0524).

• ARM® Juno System Profiler Technical Reference Manual (ARM DDI 0520).

• ARM® Development Platform Software User Guide (ARM DUI 0586).

• ARM® Development Platform Software Integration Guide (ARM DUI 0585).

• ARM® Cortex®-A57 MPCore Technical Reference Manual (ARM DDI 0488). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0488d/index.html

• ARM® Cortex®-A53 MPCore Technical Reference Manual (ARM DDI 0500). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500d/index.html

• ARM® Cortex®-M3 Technical Reference Manual (ARM DDI 0337). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337i/index.html

• ARM® CoreLink™ CCI-400 Cache Coherent Interconnect Technical Reference Manual (ARM DDI 0470). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0470i

• ARM® CoreLink™ CCI-400 Cache Coherent Interconnect Integration Manual (ARM DII 0264).

• ARM® CoreLink™ NIC-400 Network Interconnect Technical Reference Manual (ARM DDI 0475). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0475a/index.html

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Preface

• ARM® CoreLink™ DMC-400 Dynamic Memory Controller Technical Reference Manual (ARM DDI 0466). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0466c/index.html

• ARM® CoreLink™ DMA-330 DMA Controller Technical Reference Manual (ARM DDI 0424). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424d/index.html

• ARM® CoreLink™ MMU-400 System Memory Management Unit Technical Reference Manual (ARM DDI 0472). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0472a/index.html

• ARM® CoreLink™ MMU-401 System Memory Management Unit Technical Reference Manual (ARM DDI 0521). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0521a/index.html

• ARM® CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual (ARM DDI 0471). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0471b/index.html

• ARM® CoreLink™ TZC-400 TrustZone® Address Space Controller Technical Reference Manual (ARM DDI 0424). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0504b/index.html

• ARM® Mali™-T600 Series GPU Technical Reference Manual (ARM DDI 0467).

• ARM® Mali™-T600 Series GPU Technical Overview (ARM DTO 0032).

• ARM® CoreSight™ Components Technical Reference Manual (ARM DDI 0314). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480b/index.html

• ARM® CoreSight™ Trace Memory Controller Technical Reference Manual (ARM DDI 0461). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0461b/index.html

• ARM® CoreSight™ System Trace Macrocell Technical Reference Manual (ARM DDI 0444). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0444b/index.html

• ARM® Watchdog Module (SP805) Technical Reference Manual (ARM DDI 0270). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0270b/index.html

• ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile (ARM DDI 0487). http://infocenter.arm.com/help/topic/com.arm.doc.ddi0487a.b/index.html

• ARM®v7M Architecture Reference Manual, Errata markup (ARM DUI0403D_ERRATA).

• ARM® Generic Interrupt Controller Architecture Specification, Architecture version 2.0 (ARM IHI 0048). http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html

• AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite (ARM IHI 0022). http://infocenter.arm.com/help/topic/com.arm.doc.ihi0022e/index.html

• AMBA® 3 ATB Protocol Specification (ARM IHI 0032). http://infocenter.arm.com/help/topic/com.arm.doc.ihi0032b/index.html

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Preface

• AMBA® 3 AHB-Lite Protocol Specification (ARM IHI 0033). http://infocenter.arm.com/help/topic/com.arm.doc.ihi0033a/index.html

• AMBA® APB Protocol Specification (ARM IHI 0024). http://infocenter.arm.com/help/topic/com.arm.doc.ihi0024c/index.html

• ARM® CoreLink™ QVN Protocol Specification (ARM IHI 0063).

• ARM® Architecture Standard Configurations (ARM DEN 0016).

• Principles of ARM® Memory Maps Platform Design Document (ARM DEN 0001).

• Trusted Base System Architecture Platform Design Document (ARM DEN 0007).

• Server Base System Architecture Platform Design Document (ARM-DEN-0029) http://infocenter.arm.com/help/topic/com.arm.doc.den0029/index.html.

Other publications

This section lists relevant documents published by third parties:

• PCI Express Base Specification, Revision 3.0.

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Preface

FeedbackARM welcomes feedback on this product and its documentation.

Feedback on this product

If you have any comments or suggestions about this product, contact your supplier and give:

• The product name.

• The product revision or version.

• An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate.

Feedback on content

If you have comments on content then send an e-mail to [email protected]. Give:• The title.• The number, ARM DDI 0515A-3b.• The page numbers to which your comments apply.• A concise explanation of your comments.

ARM also welcomes general suggestions for additions and improvements.

Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader.

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Chapter 1 Introduction

This chapter introduces the Juno ARM® Development Platform (ADP). It contains the following sections:• About the ARM Development Platform (ADP) on page 1-2.• Components on page 1-3.• Compliance on page 1-5.• Features on page 1-8.• Product documentation and architecture on page 1-9.• IP revisions on page 1-10.• Product revisions on page 1-12.

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Introduction

1.1 About the ARM Development Platform (ADP)The ADP is a development chip that integrates the following:• ARM application multi-core clusters.• A System Control Processor (SCP).• A Graphics Processing Unit (GPU).• Interconnects.• Memory controllers.• Peripherals.

The ADP uses many Intellectual Property (IP) components and implements defined system architectures and is to be used for software development.

The ADP is implemented on the TSMC 28HPM process and delivers the following:

• A platform for ARMv8 software and tool development to enable robust testing of software deliverables on Linaro-based kernels such as Linux and Android.

• A platform for optimized software and tool development of heterogeneous compute such as:— AArch 64 kernel and tools.— big.LITTLE™.— General-Purpose computing on Graphics Processing Units (GPGPU) compute, for

example, OpenCL.

• 3D graphics and GPU compute.

• Power and thermal management.

• 64-bit drivers, file system and middleware.

• 3rd party hypervisor integration.

• 3rd party Secure OS integration.

• A platform for secure software development that complies with the Trusted Base System Architecture CLIENT1 Platform Design Document.

• Platform tuning for power and performance.


Introduction

1.2 ComponentsThe ADP contains the following components:

• A compute platform including:— A Cortex-A57 cluster containing two cores and 2MB of L2 cache.— A Cortex-A53 cluster containing four cores and 1MB of L2 cache.— A Mali-T624 GPU containing four shader cores.

• Dual ARM HDCLCD Display Controllers with the resolution characteristics that Table 2-37 on page 2-52 shows.

• Dual 32-bit DDR3L. 1600MT/s.

• A Peripheral Component Interconnect Express (PCIe) Gen2.0 4 lanes, Root Port and PHY, that has both IO coherent and non-coherent modes.

• USB 2.0 Enhanced Host Controller Interface (EHCI), 480Mbps, ULPI interface to off-chip PHY.

• Static memory controller PL354, 64 MB NOR flash and board peripherals.

• DMA-330 Direct Memory Access (DMA) Controller.

• Two PL011 UARTs.

• Single I2S with four stereo channels.

• I2C.

• PVT monitors.

• Security peripherals:— Random Number Generator (RNG).— Simulated Non-Volatile (NV) Counters.— Simulated fuses.

• Thin Links based chip-to-chip interface.

Figure 1-1 on page 1-4 shows a block diagram of the ADP system.


Introduction

Figure 1-1 ADP block diagram

ADP

Compute Subsystem

Cortex-A53 MPCore

Cortex-A57 MPCore

Core 1 Core 2

L2 cache

Core 0 Core 1

L2 cache

Core 2 Core 3

CoreLinkNIC-400

Interconnect

Mali-T624

Shader 0

Shader 1

L2 cache

Shader 2

Shader 3

CoreLink MMU-400

CoreLink CCI-400 Cache Coherent Interconnect

CoreSight

Trace

Debug

ETR

CoreLink MMU-401

System Control Processor

Cortex-M3

Power

ROM

Timing

SCP switch

Clocks and

resets

CRG

PVT monitors

PVT

IC control, PMIC

I2C

Memories

Secure RAM

Secure ROM

Non-secure RAM

Non-secure ROM

Peripherals

Secure Watchdog

Others

Message handlingCoreLink DMC-400 Dynamic Memory Controller

CoreLink TZC-400 TrustZone Address Space Controller

Dual display controllers

HDLCD 0 HDLCD 1

CoreLink MMU-401

CoreLink MMU-401

MMU-401 MMU-401

CoreLink MMU-401

MMU-401

PCIe x 4

PCIe Gen2 + PHY

USB 2.0 EHCI

USB 2.0

General DMA

DMA PL330

IC-FPGA slave interface

TLX-400

LogicTile expansion connectorUSB 2.0 PHYPCIe switch

HDMIcontroller 1

HDMIcontroller 0

Security componentsES

NV counterROTPK

EK HUK

DDR3 1600 32-bit

DDR3L PHY

DDR3 1600 32-bit

DDR3L PHY

DDR3LMemory devices

channel 0

DDR3LMemory devices

channel 1

IC-FPGA master interface

TLX-400

HDMI audio

I2S

IC control

I2C

Dual serial UART

UART PL011

UART PL011

NOR flash

SMC PL354

LogicTile expansion connector

BoardICs

HDMI 0/1 RS232 interfaces,

0 and 1

IOFPGA

DSTREAM

PMIC

Clock sourcesResets

CoreLink GIC-400+ GICv2m extension

Interrupt sources

Peripheral switchMaster ext switch

Slave ext switch

PCIe slave interface

CoreLink NIC-400 Interconnect

CoreLink NIC-400 Interconnect


Introduction

1.3 ComplianceThe ADP complies with, or includes components that comply with, the following specifications:• ARM architecture.• Generic Interrupt Controller architecture.• Advanced Microcontroller Bus Architecture.• Platform Design Documents and white papers on page 1-6.• big.LITTLE on page 1-6.• Virtualization on page 1-6.

This TRM complements the TRMs for included components, architecture reference manuals, architecture specifications, protocol specifications, and relevant external standards. It does not duplicate information from these sources.

1.3.1 ARM architecture

The ADP implements the ARMv8 architecture. This includes:• Support for both AArch32 and AArch64 Execution states.• Support for all Exception levels, EL0, EL1, EL2, and EL3, in each Execution state.• The A32 instruction set, previously called the ARM instruction set.• The T32 instruction set, previously called the Thumb instruction set.• The A64 instruction set.

The processor clusters support the following features:• Advanced Single Instruction Multiple Data (SIMD) operations.• Floating-point operations.• Cryptography Extension.

The clusters do not support the T32EE (ThumbEE) instruction set.

See the ARM® Architecture Reference Manual ARMv8 for more information.

1.3.2 Generic Interrupt Controller architecture

The ADP implements the ARM Generic Interrupt Controller (GIC) v2m architecture, that the Server Base System Architecture (SBSA) Platform Design Document (PDD) defines.

GICv2m provides an extension to the GICv2 Generic Interrupt Controller Architecture, that the ARM Generic Interrupt Controller Architecture Specification, Architecture Version 2.0 defines. This enables PCI Express Message Signaled Interrupts (MSIs) to set GICv2 Shared Peripheral Interrupts (SPIs) to pending. This provides a similar mechanism to the message based interrupt features added in GICv3.

1.3.3 Advanced Microcontroller Bus Architecture

The ADP complies with the:

• AMBA® 4 Advanced eXtensible Interface (AXI) and ACE protocol. See the AMBA® AXI™ and ACE™ Protocol Specification AXI3™, AXI4™, and AXI4-Lite™ ACE and ACE-Lite™.

• AMBA Advanced Peripheral Bus (APB) protocol. See the AMBA® APB Protocol Specification.

• AMBA 3 Advanced Trace Bus (ATB) protocol. See the AMBA® 3 ATB Protocol Specification.


Introduction

1.3.4 Platform Design Documents and white papers

The ADP architecture complies with the following Platform Design Documents (PDDs):• Level 1 of Server Base System Architecture PDD

http://infocenter.arm.com/help/topic/com.arm.doc.den0029/index.html.• Trusted Board Boot Requirements PDD.• Trusted Base System Architecture CLIENT1 PDD.

There are some limitations to the TBSA. See Trusted Base System Architecture (TBSA) compliance on page 2-64.

The ADP architecture complies with the following white paper:• Principles of ARM® Memory Maps (v1.0)

http://infocenter.arm.com/help/topic/com.arm.doc.den0001c/.

1.3.5 big.LITTLE

The ADP includes the following coherent clusters:• Cortex-A57 cluster.• Cortex-A53 cluster.

The inclusion of two coherent clusters enables you to use big.LITTLE power-management strategies. This enables a single system to handle both high-intensity and low-intensity tasks in the most energy-efficient manner.

1.3.6 Virtualization

The Cortex-A57 and Cortex-A53 clusters implement the ARMv8 architecture that includes support for virtualization. The ADP provides additional support for virtualization as follows:

The CoreLink GIC-400 Generic Interrupt Controller supports virtualization of interrupts.

Stage 2 page table translation for masters, that the following provide:

• A CoreLink MMU-401 System Memory Management Unit (SMMU) for the following:— The Embedded Trace Router (ETR).— PCI Express.— Each HDLCD controller.— The DMA PL330.— Thin Links, TLX-400.

• A CoreLink MMU-400 SMMU for the Mali-T624 GPU.

Note The MMU-400 does not support the AArch64 page table format.

See also:

• ARM Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile Architecture Reference Manual.

• ARM® CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual.

• ARM® CoreLink™ MMU-400 System Memory Management Unit Technical Reference Manual.


Introduction



Introduction

1.4 FeaturesThe key features of the ADP are as follows:• Dual core Cortex-A57 cluster.• Quad core Cortex-A53 cluster.• System Control Processor (SCP) based on the Cortex-M3 processor.• Mali-T624 GPU with four shader cores.• CoreLink CCI-400 Cache Coherent Interconnect.• CoreLink NIC-400 Network Interconnect.• CoreLink MMU-400 System Memory Management Unit.• CoreLink MMU-401 System Memory Management Unit.• CoreLink DMC-400 DDR3 Dynamic Memory Controller (DMC).• CoreLink TZC-400 TrustZone Address Space Controller.• System Profiler.• ARM CoreSight technology.• I2S interface.• I2C interface.• PCI Express (PCIe).• Universal Serial Bus (USB).• High Definition Liquid Crystal Display (HDLCD) controller.


Introduction

1.5 Product documentation and architectureFor information on the relevant architectural standards and protocols, see Compliance on page 1-5.


Introduction

1.6 IP revisionsTable 1-1 shows the IP versions of components that the ADP uses.

Table 1-1 IP revisions

Product Vendor Revision

Cortex-A57 cluster ARM r0p0

Cortex-A53 cluster ARM r0p0

Cortex-M3 processor ARM r2p1

Mali-T624 GPU ARM r1p0

CoreLink NIC-400 Network Interconnect ARM r0p0

CoreLink CCI-400 Cache Coherent Interconnect ARM r1p0

CoreLink DMC-400 Dynamic Memory Controller ARM r1p2

CoreLink DMA-330 DMA Controller ARM r1p2

CoreLink TLX-400 Network Interconnect Thin Links ARM -

CoreLink MMU-400 System Memory Management Unit ARM r0p0

CoreLink MMU-401 System Memory Management Unit ARM r0p0

CoreLink GIC-400 Generic Interrupt Controller ARM r0p1

CoreLink TZC-400 TrustZone Address Space Controller ARM r0p1

CoreLink ADB-400 AMBA Domain Bridge ARM r1p0

BP136 AMBA 2 AHB to AMBA 3 AXI Bridges ARM r0p1

BP140 Internal Memory Interface ARM r0p0

BP210 Cortex-M System Design Kit ARM r0p0

PL354 Static Memory Controller ARM r2p2

PL011 UART ARM r1p5

HDLCD Controller ARM -

PVT ARM -

PMIC ARM -

RNG ARM -

CoreSight SoC ARM r1p0

SP805 Watchdog ARM r2p0

I2S - -

I2C - -

USB 2.0 Host Controller - -

PCIe Root Port - -

28HPM PCIe PHY - -


Introduction

28HPM PLL - -

28HPM GPIO ARM -

28HPM DDR3L PHY ARM -

Table 1-1 IP revisions (continued)

Product Vendor Revision


Introduction

1.7 Product revisionsThis section describes the differences in functionality between product revisions:

r0p0 First release.


Chapter 2 Functional Description

This chapter describes the functionality of the Juno ARM Development Platform (ADP).

It contains the following sections:• ADP components on page 2-2.• Application processors on page 2-3.• Mali-T624 Graphics Processing Unit on page 2-7.• Memory on page 2-8.• Clocks and resets on page 2-10.• ADP power-management on page 2-26.• ADP power states on page 2-32.• System Control Processor (SCP) on page 2-43.• Application processor peripherals on page 2-48.• Interconnect and memory system on page 2-61.• Security on page 2-64.• Timers on page 2-75.• Debug and profiling on page 2-83.• Boot on page 2-94.• HDLCD controller on page 2-95.• PCIe on page 2-96.• Thin Links on page 2-98.


Functional Description

2.1 ADP componentsThis chapter describes the functionality of the components that Figure 1-1 on page 1-4 shows.



2.2 Application processorsThis section describes:• Processor affinity.• Cortex-A57 cluster.• Cortex-A53 cluster.• Interrupts.• Interconnects on page 2-4.• Events on page 2-5.• SCP controlled Level 2 cache maintenance on page 2-5.

2.2.1 Processor affinity

Table 2-1 shows the affinity values assigned to each application processor.

2.2.2 Cortex-A57 cluster

The Cortex-A57 cluster contains the following:

• A Cortex-A57 cluster containing two cores and a Snoop Control Unit (SCU) that you can use to ensure coherency within the cluster, and with other devices, using the CoreLink CCI-400.

• An integrated Generic Timer for each core in the Cortex-A57 cluster.

2.2.3 Cortex-A53 cluster

The Cortex-A53 cluster contains the following:

• A Cortex-A53 cluster containing cores and a Snoop Control Unit (SCU) that you can use to ensure coherency within the cluster, and with other devices, using the CoreLink CCI-400.

• An integrated Generic Timer for each core in the Cortex-A53 cluster.

2.2.4 Interrupts

All Cortex-A57 and Cortex-A53 interrupts are routed through a shared Generic Interrupt Controller (GIC), the CoreLink GIC-400. The Cortex-M3 SCP has its own interrupt controller. Some interrupts from the SCP are routed to the shared GIC-400.

The GIC-400 provides registers for managing the following, for one or more:• Interrupt sources.• Interrupt behavior.• Interrupt routing.

Table 2-1 Application processor affinity values

ProcessorAffinity level 2value

Affinity level 1value

Affinity level 0value

Cortex-A57 cluster 0 0 0-1

Cortex-A53 cluster 0 1 0-3



The CoreLink GIC-400 supports Security Extensions and can:• Enable, disable, and generate interrupts from hardware or peripheral interrupt sources.• Generate software interrupts.• Mask and prioritize interrupts.

The CoreLink GIC-400 signals interrupts to each connected cluster as appropriate. It implements the following interrupt requests to a connected cluster:• IRQ.• VIRQ.• FIQ.• VFIQ.

Figure 2-1 shows the interrupt connections.

Figure 2-1 Application processor interrupt connections

2.2.5 Interconnects

This section describes the interconnects used in the ADP. It contains the following subsections:• CoreLink CCI-400 Cache Coherent Interconnect.• CoreLink NIC-400 Network Interconnect on page 2-5.• CoreLink DMC-400 Dynamic Memory Controller on page 2-5.

CoreLink CCI-400 Cache Coherent Interconnect

The CoreLink CCI-400 Cache Coherent Interconnect provides:• Full cache coherency between the Cortex-A57 and Cortex-A53 clusters.• IO coherency with the Mali-T624 GPU.• IO coherency for PCI Express (PCIe).

The CCI-400 also supports Distributed Virtual Memory (DVM) messaging for management of system MMUs. However, the ADP does not support the maintenance of the MMU-400 and MMU-401 system memory management units because they implement DVMv7 and the Cortex-A57 and Cortex-A53 clusters implement DVMv8. Therefore, all system MMUs must be maintained by using system MMU registers.

Compute Subsystem

Cortex-A53

GIC-400

Cortex-A57

Processor clusterGraphics

Mali-T624 GPU

Debug and trace

CoreSight

System Control Processor (SCP)

Cortex-M3 MHU

Compute Subsystem internal peripheral interrupts

Other peripherals



CoreLink NIC-400 Network Interconnect

The CoreLink NIC-400 Network Interconnect provides a complete high-performance, optimized, AMBA-compliant network infrastructure. CoreLink NIC-400 Network Interconnect components connect other system components into the CoreLink CCI-400 interconnect. The CoreLink NIC-400 connects:• Master components to a CCI-400 slave port.• Slave components to a CCI-400 master port.

CoreLink DMC-400 Dynamic Memory Controller

The CoreLink DMC-400 Dynamic Memory Controller connects from two 128-bit CCI-400 ACE-Lite master ports, and the HDLCD controllers, through the TZC-400, to the two 32-bit DDR PHY Interfaces (DFIs). Transactions from any of the three ACE-Lite ports can access either of the DFI interfaces.

2.2.6 Events

The EVENTO and EVENTI signals are cross-wired between the processor clusters, to ensure that Send Event (SEV) instructions that a core in one cluster executes causes cores in the other cluster to wake from Wait For Event (WFE).

The event signals are also cross-wired between the application processor clusters and the Cortex-M3 System Control Processor (SCP). SEV instructions executed on the SCP wake application processor clusters from a WFE. Similarly, SEV instructions executed on the application processor clusters wake the SCP from a WFE.

In the ARMv8 Architecture, if the global exclusive monitor for a cluster changes from the Exclusive state to the Open state, then an event for that cluster is generated. In the ADP, the DMC-400 implements the global exclusive monitor. The Cortex-A57 and Cortex-A53 clusters provide an interface to receive notification that this global exclusive monitor has made this state. To support this v8 behavior, an event signal from the DMC-400 is wired to the Cortex-A57 and Cortex-A53 clusters.

2.2.7 SCP controlled Level 2 cache maintenance

The Cortex-A57 and Cortex-A53 clusters each contain their own Level 2 (L2) cache that the cores within the cluster share. Before you power down any cache, you must flush its contents. As part of a power down sequence, you can flush Cortex-A57 and Cortex-A53 L2 caches by doing one of the following:

• With a core powered up, execute cache maintenance instructions on a core in the cluster. The core is then powered down before the L2 is powered down.

• With all cores powered down, use the SCP to control the cluster L2 cache flush interface.

Using the L2 cache flush interface enables the cores to be powered down earlier than is possible when using cache maintenance instructions to flush the L2. The L2 cache flush interface mechanism can also enable the SCP to transition from a power state with all cores off, but the L2 on or in retention, to a power state with the L2 off, without it being necessary to power up a core for the sole purpose of flushing the L2.

The following registers control the L2 cache maintenance:• Cortex-A57 L2 Flush Control Register on page 3-126.• Cortex-A53 L2 Flush Control Register on page 3-127.



You can use the following pulse interrupts to the SCP as part of the L2 cache maintenance sequence:• Cortex-A57 L2FLUSHDONE interrupt.• Cortex-A53 L2FLUSHDONE interrupt.

The SCP triggers an interrupt when the L2FLUSHDONE output from the cluster changes from either:• LOW to HIGH.• HIGH to LOW.

For the location of these interrupts within the SCP interrupt map, see System Control Processor (SCP) interrupt map on page 3-10.

For information about how to use the L2 flush interface as part of the power down sequence of the clusters, see Appendix A Power and Access Control Sequences.



2.3 Mali-T624 Graphics Processing UnitThe Mali-T624 GPU is a high-performance hardware accelerator for 2D and 3D graphics systems.

The GPU consists of:

• A job manager that controls the graphics processing that is sent to the GPU.

• Four Shader Cores that perform all the rendering and computation operations.

• A hierarchical tiler that lists all the objects in a scene, so that the shader cores can process the objects efficiently.

• A Memory-Management Unit (MMU) that performs address translation of data reads and writes from components in the system.

• A Power-Management Unit (PMU).

The GPU uses multiple texture formats that you must enable in the GPU Texture Format Register on page 3-65.

The GPU and its associated software is compatible with the following standards:• OpenCL 1.1.• OpenGL ES 1.1 and 2.0.• OpenVG 1.1.• EGL 1.4.

The Mali-T624 GPU is built using a 256KB L2 RAM configuration. For more information about the Mali-T624 GPU, see:• The Mali™-T600 Series GPU Technical Overview.• The Mali™-T600 Series GPU Technical Reference Manual.



2.4 MemoryThe following sections describe the memory organization in the ADP:• Application memory map.• System Control Processor (SCP) memory map.• CoreLink DMC-400 Memory Controller.• Memory bus architecture.• TrustZone system design.• CoreLink TZC-400 TrustZone Controller on page 2-9.

2.4.1 Application memory map

See Application memory map summary on page 3-24.

2.4.2 System Control Processor (SCP) memory map

See System Control Processor (SCP) memory map on page 3-29.

2.4.3 CoreLink DMC-400 Memory Controller

The DMC-400 is a memory controller designed for use with high-performance systems based around ARM processor and GPU cores. It offers many fully-programmable Quality of Service (QoS) settings and supports DDR3L JEDEC-compatible memory devices.

The DMC-400 is configured to support dual 32-bit DDR3L memory. The memory controller is configured with two interfaces to the CCI-400, two asynchronous QVN AXI slave interfaces used to connect non-coherent masters, and two DFI 2.1 compliant interfaces for DRAM PHYs. For more information about the DMC-400, see the ARM® CoreLink™ DMC-400 Dynamic Memory Controller Technical Reference Manual.

2.4.4 Memory bus architecture

The memory system in the ADP utilizes advanced QoS methods to manage latency and bandwidth for the components and interfaces.

The bus architecture is based on the AMBA4 protocol and is configured to provide a low latency access path to the external memory device to the processors in the system and also provides sufficient bandwidth to the high bandwidth components. It is based on the CoreLink NIC-400 Network Interconnect and CCI-400 Cache Coherent Interconnect. See the ARM® CoreLink™ NIC-400 Network Interconnect Technical Reference Manual.

2.4.5 TrustZone system design

The ADP design provides security features at the system level to facilitate the use of trusted software on the system. It provides a base set of security infrastructure within the ADP. However, you must add components that are application or silicon process-dependent to match the security requirements. Examples of these include entropy sources, and true non-volatile counters. The ADP enables you to create a Trusted Base System Architecture CLIENT1 compliant platform when you add components such as a Random Number Generator and eFuse to the system.

A combination of the application processor cluster security model, and system-based components provide security compliance with the requirements of the ARM® Trusted Base System Architecture CLIENT1 Platform Design Document. See the ARM® Trusted Base System Architecture CLIENT1 Platform Design Document.



The following sections describe the system-based components and extensions:• Secure on-chip memories.• Interconnect IP.• CoreLink TZC-400 TrustZone Controller.

Secure on-chip memories

The system contains the following individual memory regions in the base memory map that are marked as always being Secure access only:• A memory region for the on-chip ROM.• A memory region for the on-chip SRAM.

Note The SCP also contains Secure ROM and SRAM.

Interconnect IP

Only a subset of masters within the system can generate Secure accesses. These include:• The SCP.• The application processors.• Debug and trace logic, when it is operating in Secure mode.

Additionally, software can configure the GPU and displays to generate Secure accesses. Some peripherals are also mapped as Secure access only, and you can use software to configure others to be Secure access only.

CoreLink TZC-400 TrustZone Controller

TrustZone is the security architecture developed by ARM. The TZC-400 TrustZone Address Space Controller is an important component in systems that use the TrustZone architecture. The TZC-400 controls access to address regions. The TZC-400 is programmed to enable certain masters to access particular regions of memory, and block access from other masters. In the ADP, the TZC-400 is located in-front of the DMC-400 Dynamic Memory Controller.

See the ARM® CoreLink™ TZC-400 TrustZone® Address Space Controller Technical Reference Manual.



2.5 Clocks and resetsThis section describes the ADP clocks and resets and contains the following subsections:• Clock inputs.• Clock outputs on page 2-11.• System PLLs on page 2-11.• System clocks on page 2-12.• Reset inputs on page 2-14.• Reset outputs on page 2-15.• Clock generation on page 2-15.• PLL lock control on page 2-15.• Internal reset generation on page 2-16.

2.5.1 Clock inputs

Table 2-2 shows the clock inputs from the board to the ADP.

Table 2-2 Clock inputs

Clock name Frequency range Description

SYS_REF_CLK 25-100MHza System PLL reference clock.

A57_REF_CLK 25-100MHza Cortex-A57 PLL reference clock.

A53_REF_CLK 25-100MHza Cortex-A53 PLL reference clock.

GPU_REF_CLK 25-100MHza GPU PLL reference clock.

PXL_REF_CLK 25-100MHza HDLCD PLL reference clock.

AON_REF_CLK 25-100MHz SCP subsystem and AHB expansion area clock. Also used as a reference clock in the PVT monitors.

PXL_CLK_IN 25-100MHz HDLCD direct clock input used for low resolution displays.

S32K_CLK 32.768KHz Real time clock to the SCP used in low power modes.

I2S_CLK 10MHz Integrated-IC sound clock.

I2C_CLK 50MHz Reference clock used to generate I2C SCLK.

UART_CLK 7.2738MHz UART reference clock.

TCK 25MHz Combined JTAG and Serial Wire Debug (SWD) clock.

ULPI_CLK 60MHz ULPI clock from the external USB 2.0 PHY.

USB_CLK48 48MHz Primary clock input to the USB OHCI controller.

PCIE_PHY_REF_CLK_M 100MHz PCIe differential reference clock.

PCIE_PHY_REF_CLK_P

SMC_MCLK 50MHz PL354 Static Memory Controller interface clock.

SMC_FB_CLK 50MHz Feedback clock to read data back into PL354 in synchronous mode.



2.5.2 Clock outputs

Table 2-3 shows all the output clocks from the ADP to the board.

2.5.3 System PLLs

The ADP includes the following PLLs for high-frequency clock generation:• Cortex-A57 PLL.• Cortex-A53 PLL.• GPU PLL.• System PLL.• HDLCD PLL.

Each PLL has a separate reference clock and a mandatory 5μs minimum reset period. A reset timer ensures that this is met. The timer counts down from 0x1FFF and guarantees a minimum of 5μs up to a 180MHz reference clock.

CFG_CLK 25MHz System Configuration Controller (SCC) serial interface clock.

TSIF_CLKI 61.5MHz Thin Links based AXI slave interface clock in the receive direction. TSIF_CLKO is the clock in the reverse direction exported out of the chip.

TMIF_CLKI 61.5MHz Thin Links based AXI master interface clock in the receive direction. TMIF_CLKO is the clock in the transmit direction exported out of the chip.

a. The default values in the PLL control registers in System Configuration Controller (SCC) registers on page 3-47 are set up for a 50MHz reference clock.

Table 2-2 Clock inputs (continued)

Clock name Frequency range Description

Table 2-3 Clock outputs

Clock name Frequency range Comments

TRACE_CLKA 145.45MHz Trace clock to connector 1

TRACE_CLKB 145.45MHz Trace clock to connector 2

TSIF_CLKO 61.5MHz Thin Links based AXI slave interface clock that is exported out with the transmit data.

TMIF_CLKO 61.5MHz Thin Links based AXI master interface clock that is exported out with the transmit data.

SMC_CLK_OUT 50MHz Static Memory Interface clock output

HDLCDC0_PXL_CLK_OUT 220MHz HDLCD interface 0 pixel clock output

HDLCDC1_PXL_CLK_OUT 220MHz HDLCD interface 1 pixel clock output

A57_CLK_OUT_DIV32 < 50MHz Divided by 32 version of the Cortex-A57 processor PLL output

A53_CLK_OUT_DIV32 < 50MHz Divided by 32 version of the Cortex-A53 processor PLL output

GPU_CLK_OUT_DIV32 < 50MHz Divided by 32 version of the GPU PLL output

SYS_CLK_OUT_DIV32 < 50MHz Divided by 32 version of the SYS PLL output

PXL_CLK_OUT_DIV32 < 50MHz Divided by 32 version of the HDLCD PLL output



Table 2-4 shows the system PLLs.

See ADP System Control Registers on page 3-106.

2.5.4 System clocks

The ADP internally derives clocks that parts of the ADP use. The ADP generates these clocks only when the VSYS.SYSTOP power region is powered, and you can control each clock individually. Table 2-5 shows the system clocks.

Table 2-4 System PLLs

PLL Description

A57PLL Cluster-specific PLL that generates the A57_PLL_CLK clock for the Cortex-A57 cluster.

A53PLL Cluster-specific PLL that generates the A53_PLL_CLK clock for the Cortex-A53 cluster.

GPUPLL Cluster-specific PLL that generates the GPU_PLL_CLK clock for the Mali-T624 GPU cluster.

SYSPLL ADP system PLL that generates the main CSS system clock, SYS_PLL_CLK.

HDCLCDPLL HDCLD pixel PLL that generates an alternative clock, PXL_CLK_PLL, for the HDLCD controllers.

Table 2-5 System clocks

Clock Description

ATCLK ATB clock.

CCICLK CCI-400 clock.

NICPERCLK Peripheral NIC-400 clock.

NICSCPCLK SCP and debug NIC-400 clock.

DMCCLK DMC-400 clock.

SPCLK System Profiler clock.

GICCLK GIC-400 clock.

TRACECLKIN CoreSight trace clock.

FAXICLK Clock for the compute subsystem coherent slave expansion port and the masters on that interface.

SAXICLK Clock for the compute subsystem master AXI expansion port, and all of the performance-critical slaves on that interface.

HDLCDCLK HDLCD bus interface clock.

PCIEACLK Clock for the AXI logic associated with the PCIe Root Port.

PCIETCLK Transaction layer clock in the PCIe Root Port.

USBHCLK Primary clock for the BIU of the USB EHCI and OHCI host controllers.

TMIF2XCLK Clock for the Thin Links master interface in the forward direction.

TSIF2XCLK Clock for the Thin Links slave interface in the reverse direction.



The clocks in Table 2-5 on page 2-12 are asynchronous to each other and you can manage them independently using the following controls in the ADP System Control Registers on page 3-106:

• Clock source selection between the SYSIN PLL clock and the SYS_REF_CLK input signals.

• Clock enabled, disabled, or force enabled:Disabled When a clock is disabled, it is always turned off. This is only

available for certain clocks.

Note Only disable clocks when the power region, or regions, for all

components that use the clock, are in a low power state, as controlled by the Power Policy Units (PPUs).

Enabled When a clock is enabled, it is available when required, but hardware can transparently gate it to reduce power consumption.

Force-enabled When a clock is force-enabled, it is always turned on. This is only available for certain clocks. This mode is only intended for use when debugging clock-control software. Some clocks do not have this mode because they do not have any transparent hardware clock-gating, and this mode is therefore not required.

• Post-source selection division ratio, all integer ratios in the range 1-16.

Clock selection is glitchless and dividers produce a clock with a 50:50 duty cycle.

Some clocks cannot be scaled without causing undesired side-effects and interruption to operation. Therefore, you must take care when scaling the following clocks:

DMCCLK Scaling of these clocks while the memory system is active can cause a DDR PHY DLL phase unlock, and incorrect or sub-optimal refresh rates.

See ADP power-management on page 2-26.

Debug clock, PCLKDBG

The ADP generates a debug clock, PCLKDBG, from ATCLK, that System clocks on page 2-12 describes. PCLKDBG is synchronous to ATCLK, but can be additionally divided using the PCLKDBG Clock Control Register on page 3-118.

Cortex-A57 and Cortex-A53 clusters, and Mali-T624 clocks

The ADP generates an individual internal clock for each of the Cortex-A57 cluster, Cortex-A53 cluster, and Mali-T624 GPU. These internal clocks are called A57CLK, A53CLK, and GPUCLK respectively.

APBCLK Clock for the APB peripherals.

SCFCLK Reference clock for PVT sensors.

USBCLK12 Fixed 12MHz clock for the USB OHCI controller. It is derived from USB_CLK48.

Table 2-5 System clocks (continued)

Clock Description



You can manage the clock for each of these components individually using the following controls in the ADP System Control Clock and Reset Generator registers:

• Clock enabled or disabled.

• Clock source selection between SYSPLL, SYS_REF_CLK, and the PLL for the cluster.

• When a clock is disabled, it is always turned off. This is only available for some clocks.

Note Only disable clocks when the power region for all components using the clock, are in a

low power state, as controlled the PPUs control.

• Division ratio, all integer ratios in the range 1-16, used when SYS_REF_CLK input signal or the SYSPLL PLL is selected as the clock source.

• Division ratio, all integer ratios in the range 1-16, used when the PLL clock input is selected as the clock source.

See:• System PLLs on page 2-11.• ADP System Control Registers on page 3-106.

PLL lock control

System PLLs on page 2-11 shows PLL lock signals associated with each PLL input clock. These PLL lock input signals generate interrupts to the Cortex-M3 SCP Nested Vectored Interrupt Controller (NVIC).

The following additional support exists for these signals in the SCP:

• Interrupt pulse generated on either edge of the lock signal.

• Bits in the System Status Register on page 3-125 to determine the current level of the lock signal.

• All other interrupt status and masking is performed within the SCP Cortex-M3 processor NVIC.

See:• System PLLs on page 2-11.• ADP System Control Registers on page 3-106.• System Status Register on page 3-125.• System Control Processor (SCP) interrupt map on page 3-10.• The Cortex®-M3 Technical Reference Manual.

2.5.5 Reset inputs

The ADP contains the following primary reset inputs from the board:

nPORESET Main powerup reset for the ADP. Deassertion of this input triggers powerup sequencing.

nTRST JTAG reset. This input resets the CoreSight Debug Access Port (DAP) and the TAP controllers used for boundary scan and MBIST.

CFG_nRESET Reset signal for the serial interface to the System Configuration Controller (SCC).



All reset inputs are active LOW and asynchronous. They are all re-synchronized within the chip to the clock domain in which they are used. The only exception is the CFG_nRESET. This is timed to the CFG_CLK input clock, and not internally synchronized.

The PLL resets are generated independently from the SCP memory mapped registers in the SCC.

2.5.6 Reset outputs

This section describes:• DDR3L reset.• Watchdog reset request, WDOGRESAON.

DDR3L reset

Use the DDR3LRESETn reset out to reset the DDR3L memory.

Watchdog reset request, WDOGRESAON

The WDOGRESAON output is a sticky HIGH request for the Juno board to reset the ADP because of a trusted watchdog or SCP watchdog timeout. The Juno board uses this signal to assert the nPORESET input, and place the external system into a state where it can reboot. For example, Power Management ICs (PMICs) are reset, to restore them to their default state, and supply power to all the power domains that system boot requires.

2.5.7 Clock generation

The ADP includes logic to generate clocks to areas of the ADP. The SCP controls clock-generation that is implemented in the always-on VSYS.AON power region. The ADP preserves configuration values during the powerdown cycle of any power-gated region. The clock-generation logic is in the VSYS.SYSTOP power region. See System Control Processor (SCP) on page 2-43.

2.5.8 PLL lock control

System PLLs on page 2-11 shows PLL lock signals associated with each PLL input clock. These PLL lock input signals generate interrupts to the Cortex-M3 Nested Vectored Interrupt Controller (NVIC).

The following additional support exists for these signals in the SCP:

• Interrupt pulse generated on either edge of the lock signal.

• Bits in the System Status Register on page 3-125 to determine the current level of the lock signal.

• The Cortex-M3 processor NVIC performs all other interrupt status and masking.

See:• System PLLs on page 2-11.• ADP System Control Registers on page 3-106.• System Status Register on page 3-125.• System Control Processor (SCP) interrupt map on page 3-10.• Cortex-M3 Technical Reference Manual.



2.5.9 Internal reset generation

You can reset components in the ADP using:

• Reset input signals.

• Warm reset requests from cores.

• Watchdog timers.

• The SYSRESETREQ bit in the Application Interrupt and Reset Control Register (AIRCR) of the Cortex-M3 SCP. See the Cortex®-M3 Technical Reference Manual.

• Power Policy Unit (PPU) registers. See Power domain control on page 2-37.

This section describes the causes of resets for all components in the ADP. The tables use the key that Table 2-6 shows.

This section describes:• Cortex-A57 cluster reset control.• Cortex-A53 cluster reset control on page 2-17.• Mali-T624 reset conditions on page 2-19.• Other component reset conditions on page 2-20.• System debug reset request on page 2-25.• Reset Syndrome Register, RSR on page 2-25.

Cortex-A57 cluster reset control

The tables in this section show how the ADP applies resets to the reset input signals of the Cortex-A57 cluster. For information on how this component uses these reset inputs, see the ARM® Cortex®-A57 MPCore Technical Reference Manual.

Table 2-7 shows the reset conditions for the Cortex-A57 cluster, excluding PPUs.

Table 2-6 Key to rest conditions

Symbol Meaning

Yes Reset condition is a direct cause of reset

No Reset condition is not a cause of reset

* Reset condition is an indirect cause of reset, the reset condition resets the PPU, and this then triggers this reset

Table 2-7 Cortex-A57 reset conditions, excluding PPUs

Componentreset signal

Reset source

nTRST nPORESET M3 AIRCR.SYSRESETREQ Field name in manual reset registers

nCPUPORESET[0] Noa *b *b -

nCORERESET[0] Noa *b *b -

nCPUPORESET[1] Noa *b *b -



Table 2-8 shows the Cortex-A57 processor PPU reset conditions.

Cortex-A53 cluster reset control

Table 2-9 on page 2-18 shows how the ADP applies reset to the reset input signals of the Cortex-A53 cluster.

For information on how this component uses these reset inputs, see the ARM® Cortex®-A53 MPCore Technical Reference Manual.


nL2RESET Noa *b *b A57nL2RESET

nPRESETDBG Noa *b *b A57nPRESETDBG

a. Reset condition is not a cause of reset.b. Reset condition is an indirect cause of reset, the reset condition resets the PPU, and this then triggers this reset.

Table 2-7 Cortex-A57 reset conditions, excluding PPUs (continued)


Reset source

nTRST nPORESET M3 AIRCR.SYSRESETREQ Field name in manual reset registers

Table 2-8 Cortex-A57 PPU reset conditions


Reset source

A57CPU[0]PPUpower down

A57CPU[0]PPU emulatedpower downor WARM_RSTpolicy

A57CPU[1]PPUpower down


A57SSTOPPPUpower down

A57SSTOPPPU emulatedpower down

nCPUPORESET[0] Yesa Nob Nob Nob Nob Nob

nCORERESET[0] Yesa Yesa Nob Nob Nob Nob

nCPUPORESET[1] Nob Nob Yesa Nob Nob Nob

nCORERESET[1] Nob Nob Yesa Yesa Nob Nob

nL2RESET Nob Nob Nob Nob Yesa Yesa

nPRESETDBG Nob Nob Nob Nob Yesa No

a. Reset condition is a direct cause of reset.b. Reset condition is not a cause of reset.



Table 2-9 shows the Cortex-A53 reset conditions, excluding PPUs.

Table 2-10 shows the first part of the Cortex-A53 PPU reset conditions.

Table 2-9 Cortex-A53 reset conditions, excluding PPUs


Reset source

nTRST nPORESET M3 AIRCR.SYSRESETREQField name in manualreset registers,system control registers

nCOREPORESET[0] Noa *b *b -








nL2RESET Noa *b *b A53nL2RESET

nPRESETDBG Noa *b *b A53nPRESETDBG


Table 2-10 Cortex-A53 PPU reset conditions, part 1


Reset source

A53CPU[0]PPUpowerdown

A53CPU[0]PPU emulatedpower down orWARM_RSTpolicy

A53CPU[1]PPUpower-down


A53CPU[2]PPU powerdown

nCOREPORESET[0] Yesa Nob Nob Nob Nob

nCORERESET[0] Yesa Yesa Nob Nob Nob

nCOREPORESET[1] Nob Nob Yesa Nob Nob

nCORERESET[1] Nob Nob Yesa Yesa Nob

nCOREPORESET[2] Nob Nob Nob Nob Yesa

nCORERESET[2] Nob Nob Nob Nob Yesa

nCOREPORESET[3] Nob Nob Nob Nob Nob



Table 2-11 shows the second part of the Cortex-A53 PPU reset conditions.

Mali-T624 reset conditions

Table 2-12 on page 2-20 and Table 2-13 on page 2-20 show how the ADP applies reset to the Mali-T624 GPU. In particular, they show how the sources of reset map onto the reset signals of the GPU.

nCORERESET[3] Nob Nob Nob Nob Nob

nL2RESET Nob Nob Nob Nob Nob

nPRESETDBG Nob Nob Nob Nob Nob

a. Reset condition is a direct cause of reset.b. Reset condition is not a cause of reset.

Table 2-10 Cortex-A53 PPU reset conditions, part 1 (continued)


Reset source

A53CPU[0]PPUpowerdown


A53CPU[1]PPUpower-down



Table 2-11 Cortex-A53 PPU reset conditions, part 2


Reset source




A53SSTOPPPUpower down

A53SSTOPPPU emulatedpower down

nCOREPORESET[0] Noa Noa Noa Noa Noa

nCORERESET[0] Noa Noa Noa Noa Noa


nCORERESET[1] Noa Noa Noa Noa Noa


nCORERESET[2] Yesb Noa Noa Noa Noa

nCOREPORESET[3] Noa Yesb Noa Noa Noa

nCORERESET[3] Noa Yesb Yesb Noa Noa

nL2RESET Noa Noa Noa Yesb Yesb

nPRESETDBG Noa Noa Noa Yesb Noa

a. Reset condition is not a cause of reset.b. Reset condition is a direct cause of reset.



Table 2-12 shows the Mali-T624 PPU reset conditions, excluding PPUs.

Table 2-13 shows the Mali-T624 PPU reset conditions.

Other component reset conditions

Table 2-14 to Table 2-16 on page 2-24 show how the ADP applies reset to the other components in the ADP, and to the components connected to the output reset SCPHRESETn. In particular, the tables show how the sources of reset map onto the reset signals of the components.

When a component contains multiple resets, to which the ADP applies different reset conditions, the tables describe each of the resets of the component separately.

Table 2-14 shows the first part of the additional component reset conditions, excluding PPUs.

Table 2-12 Mali-T624 reset conditions, excluding PPUs


Reset source

nTRST nPORESET M3 AIRCR.SYSRESETREQField name in manual resetregisters, system control registers

nRESET Noa *b *b GPUTOP


Table 2-13 Mali-T624 PPU reset conditions


Reset source

GPUTOP PPU power downField name in manual reset registers,system control registers

nRESET Yesa

a. Reset condition is a direct cause of reset.

GPUTOP

Table 2-14 Additional component reset conditions, excluding PPUs, part 1

Component

Reset source

Reset signal,if applicable

nTRST nPORESETSCPfirmwarewatchdog

Field namein manualresetregisters,systemcontrolregisters

GIC-400, Message Signaled Interrupt (MSI)

- Noa *b - None

CCI-400, NIC-400 - Noa *b - None

System Trace Macrocell (STM) ARESETn Noa *b - None

STMRESETn Noa *b - DBGSYSRESET



MMU-401 for the ETR - Noa *b - None

MMU-401 for the PCIe - Noa *b - None

MMU-400 for the GPU - Noa *b - None

TZC-400 - Noa *b - None

DMC-400 - Noa *b - None

Juno System Profiler - Noa *b - None

SYSTOPRESETn output - Noa *b - None

DDR3 - Noa Noa - DDR3RESET

MHU - Noa Yesc - None

REFCLK counter - Noa Yesc - None

S32KCLK counter - Noa Yesc - None

SCP REFCLK timer - Noa Yesc - None

AP_REFCLK_S timer - Noa Yesc - None

AP_REFCLK_NS Timer - Noa Yesc - None

SCP S32KCLK timer - Noa Yesc - None

SCP firmware watchdog, trusted watchdog

- Noa Yesc - None

Cortex-M3 SCP SYSRESETn Noa Yesc - None

nPORESET Noa Yesc - None

DAPRESETn Noa Yesc - None

Primary DP - Yesc Noa - None

SCP DP - Yesc Noa - None

DBGSYS CoreSight components - Noa *b - DBGSYSRESET

DBGSYSRESETn output - Noa *b - DBGSYSRESET

SCPHRESETn output - Noa Yesc - None

Reset Syndrome Register, RSR on page 3-128

- Noa Yesc - None

Table 2-14 Additional component reset conditions, excluding PPUs, part 1 (continued)

Component

Reset source






Table 2-15 shows the second part of the additional component reset conditions, excluding PPUs.

SSC_GPRETN Register on page 3-41

- Noa Yesc - None

DBGSYS power registers, DBGSYS PPU

- Noa Yesc - None

Other power registers and PPUs - Noa Yesc - None

ADP System Control Registers on page 3-106

- Noa Yesc - None

Other SCP registers - Noa Yesc - None

WDOGRESAON output signal - - - Yesc None

a. Reset condition is not a cause of reset.b. Reset condition is an indirect cause of reset, the reset condition resets the PPU, and this then triggers this reset.c. Reset condition is a direct cause of reset.


Component

Reset source




Table 2-15 Additional component reset conditions, excluding PPUs, part 2

Component

Reset source


Trusted watchdog M3 AIRCR.SYSRESETREQ

GIC-400, MSI - - *a

CCI-400, NIC-400 - - *a

STM ARESETn - *a

STMRESETn - *a

MMU-401 for the ETR - - *a

MMU-401 for the PCIe - - *a

One, or multiple MMU-400 for the GPU - - *a

TZC-400 - - *a

DMC-400 - - *a

System Profiler - - *a

SYSTOPRESETn output - - *a



DDR3 - - Nob

MHU - - Yesc

REFCLK counter - - Yesc

S32KCLK counter - - Yesc

SCP REFCLK timer - - Yesc

AP_REFCLK_S timer - - Yesc

AP_REFCLK_NS Timer - - Yesc

SCP S32KCLK timer - - Yesc

SCP firmware watchdog, trusted watchdog - - Yesc

Cortex-M3 SCP SYSRESETn - Yesc

nPORESET - Yesc

DAPRESETn - Yesc

Primary DP - - Nob

SCP DP - - Nob

DBGSYS CoreSight components - - *a

Reset Syndrome Register, RSR on page 3-128 - - Nob

SSC_GPRETN Register on page 3-41 - - Nob

DBGSYS power registers, DBGSYS PPU - - Yesc

Other power registers and PPUs - - Yesc

ADP System Control Registers on page 3-106 - - Yesc

Other SCP registers - - Yesc

WDOGRESAON - Yesc -

a. Reset condition is an indirect cause of reset, the reset condition resets the PPU, and this then triggers this reset.b. Reset condition is not a cause of reset.c. Reset condition is a direct cause of reset.


Component

Reset source


Trusted watchdog M3 AIRCR.SYSRESETREQ



Table 2-16 shows the additional component PPU reset conditions.

Table 2-16 Additional component PPU reset conditions

ComponentReset signal,if applicable

Reset source

GPUTOPPPU power down

SYSTOPPPU power down

DBGSYSPPU power down

GIC-400, MSI - Noa Yesb Noa

CCI-400, NIC-400 - Noa Yesb Noa

MMU-401 for the ETR - Noa Yesb Noa

MMU-401 for the PCIe - Noa Yesb Noa

MMU-400 for the GPU - Yesb Noa Noa

TZC-400 - Noa Yesb Noa

DMC-400 - Noa Yesb Noa

Juno System Profiler - Noa Yesb Noa

SYSTOPRESETn output - Noa Yesb Noa

MHU - Noa Noa Noa

REFCLK counter - Noa Noa Noa

S32KCLK counter - Noa Noa Noa

SCP REFCLK timer - Noa Noa Noa

SCP S32KCLK timer - Noa Noa Noa

Cortex-M3 SCP SYSRESETn Noa Noa Noa

nPORRESET Noa Noa Noa

nTRST Noa Noa Noa

Main DAP - Noa Noa Noa

CoreSight components - Noa Noa Yesb

Reset Syndrome Register, RSR on page 3-128

- Noa Noa Noa

SSC_GPRETN Register on page 3-41 - Noa Noa Noa

DBGSYS power registers, DBGSYS PPU - Noa Noa Noa

Other SCP Registers, other PPUs - Noa Noa Noa

a. Reset condition is not a cause of reset.b. Reset condition is a direct cause of reset.



System debug reset request

The SWJ Debug Port (DP) within the main DAP contains CDBGRSTREQ and CDBGRSTACK bits in its Control and Status Registers that handshake a debug system reset request. Figure 2-2 on page 2-25 shows the handshake between CDBGRSTREQ and CDBGRSTACK.

Figure 2-2 CDBGRSTREQ and CDBGRSTACK handshake

The CDBGRSTREQ bit of the Control and Status Registers requests a reset of the debug system. In the ADP, the SCP handles this request. Any change to the CDBGRSTREQ bit triggers an interrupt to the Cortex-M3 SCP. The current value of the CDBGRSTREQ bit is visible in the Debug Status Register on page 3-134.

The SCP generates a response using the Debug Control Register on page 3-133, and this becomes visible in the CDBGRSTACK bit of the DAP.

In response to this request, SCP firmware is expected to use the DBGSYSRESET fields in the SCP System Control Registers to cause a reset of the debug system. See Debug Status Register on page 3-134.

Reset Syndrome Register, RSR

The SCP incorporates a Reset Syndrome Register that provides information about the last cause of a ADP reset. See Reset Syndrome Register, RSR on page 3-128. The SCPM3LOCKUP bit in this register is set if the Cortex-M3 processor is in the lockup state when a reset occurs.

See the ARM®v7M Architecture Reference Manual, B1.5.15 Unrecoverable exception cases.

CDBGRSTACK, SCP

CDBGRSTREQ, DP



2.6 ADP power-managementThis section describes power-management in the ADP. It contains the following subsections:• Features.• Voltage supplies.• DVFS.• Thermal management on page 2-27.• Power domain operating modes on page 2-27.• Cortex-A57 cluster power domains on page 2-28.• Cortex-A53 cluster power domains on page 2-28.• Mali-T624 power domains on page 2-29.• System power domain on page 2-29.• AON power domain on page 2-30.

2.6.1 Features

The following features support power-management in the ADP:• System Control Processor (SCP):

— A Cortex-M3 processor that controls power, clock, reset, and the system.— Low-area and low-power.

• Multiple voltage domains to enable application processor and GPU Dynamic Voltage and Frequency Scaling (DVFS).

• Multiple power-gated regions with comprehensive leakage management.• Low-power, autonomous wake, sleep modes targeted at mobile device requirements.• Globally Asynchronous Locally Synchronous (GALS) clocking architecture:

— All primary clock domains are independent from each other.— Simplifies frequency scaling and interfacing.— Enables an accelerated route to a higher quality result for the physical design.

• Clock-gating across the system for:— Application processor clusters.— GPU.— Interconnect system.— Memory controller.

• Dynamic memory power-management with comprehensive low-power mode support using the DMC-400.

2.6.2 Voltage supplies

A System on Chip (SoC) contains multiple voltage supplies, that the PMIC, or regulators on the board, control.

2.6.3 DVFS

Dynamic Voltage and Frequency Scaling (DVFS) is an energy-saving technique that you can use either with or without using big.LITTLE technology. The following equation provides the dynamic power consumption of a system:

P = C × V2 × f

Where the following definitions apply:P Dynamic power.



C Switching capacitance of the logic circuit in question.V Operational voltage.f Operational frequency.

Software can reduce the operating frequency of a core in a cluster in proportion to its current workload. This can result in a linear saving in dynamic power.

A silicon process technology can offer a reduced operating frequency at a lower voltage. This would result in a quadratic saving in dynamic power. By reducing the voltage, you can reduce the overall energy required to perform a task.

A given frequency of operation, together with its corresponding operational voltage, is expressed as a tuple and is known as an Operating Performance Point (OPP). For a given core, the range of attainable OPPs is collectively known as the DVFS curve.

Operating Systems (OSs) use DVFS to save energy and, where necessary, keep within thermal limits. The load on a core modulates its frequency of operation. The OS provides DVFS policies to manage the power consumed, and the desired performance.

A policy aimed at high-performance selects higher frequencies and uses more energy.

A policy aimed at saving energy selects lower frequencies and results in lower performance.

Each cluster in a DVFS-capable big.LITTLE system is implemented in an independent voltage domain with an independent clock source. Each of the clusters has a unique DVFS curve. Therefore, cores in the same cluster must traverse OPPs together, but can do so independently of cores in the other cluster.

2.6.4 Thermal management

The ADP contains temperature sensors that can be used for thermal management.

TBD link to section on sensors.

2.6.5 Power domains

This section contains the following subsections:• Power domain operating modes.• Cortex-A57 cluster power domains on page 2-28.• Cortex-A53 cluster power domains on page 2-28.• Mali-T624 power domains on page 2-29.• System power domain on page 2-29.• AON power domain on page 2-30.

Power domain operating modes

A SoC normally includes several power domains. Each power domain supports different operating modes as follows:

On A power domain always supports an On mode. This is the normal operating mode for the logic in the power domain. If the power domain supports DVFS, the different DVFS OPPs are applied while the power domain is in the On mode. This mode might use clock-gating to reduce dynamic power consumption.

Off A power domain can support an Off mode by including power gates or external-switchable. The power gates can remove the power supply to the power domain.



Powering down a power domain destroys the context held in that domain. To use this power mode, software must provide mechanisms to manage the context before entering the power mode, and on resuming execution after leaving the power mode. This means there is a significant time and energy cost to using these power states.

Retention In addition to power gates, this mode requires the flip-flops and RAMs in the domain to have retention capability. This power domain also requires a second power supply. Retention flip-flops and RAMs use this second power supply to retain their state when the main power supply is removed.Because state is retained, software is not required to manage the context included in the domain. This means that the time and energy cost of entering and exiting Retention mode is lower than for the Off mode. However, the power consumed in this mode is higher than in the Off mode.

Note The Retention mode is not available in the ADP.

Cortex-A57 cluster power domains

The VA57 voltage supply powers the Cortex-A57 cluster. VA57 operates in the range 0.8-1.0V to support Dynamic Voltage and Frequency Scaling (DVFS).

Table 2-17 shows the power domains and operating modes that the ADP implementation of the Cortex-A57 cluster supports in addition to the normal Cortex-A57 operating modes.

There are restrictions between the operating modes of some power domains. The defined power states limit the legal combinations of power domain operating modes. See ADP power states on page 2-32.

Cortex-A53 cluster power domains

The VA53 voltage supply powers the Cortex-A53 cluster. VA53 operates in the range 0.8-1.0V to support DVFS.

Table 2-17 Summary of Cortex-A57 cluster power domains implemented in the ADP

Name Power domain ADP implementation operating modes Operating modes

A57CPU[n] Each core On, Off On, Retentiona, Off

Debug APB, CTI, and CTM On, Off

A57SSTOP L2 Cache RAMs On, Offb On, Retentiona, Off

Non-CPU control logic On, Off

a. For L2 RAMs dynamic retention, the L2 Data, Dirty, Tag, Inclusion PF, and Snoop Tag RAMs are retained.For L2 cache Dormant mode, the L2 Data, Dirty, Tag, and Inclusion PF RAMs are retained.The Inclusion PF RAM is available only in r1p0 and later revisions of the Cortex-A57 processor.

b. External switch-off.



Table 2-18 shows the power domains and operating modes that the ADP implementation of the Cortex-A53 cluster supports in addition to the normal Cortex-A53 operating modes.


Mali-T624 power domains

The VGPU voltage supply powers the Mali-T624 GPU. VGPU operates in the range 0.8-1.0V to support DVFS.

Table 2-19 shows the power domains and operating modes that the ADP implementation of the Mali-T624 GPU supports in addition to the normal Mali-T624 GPU operating modes.

The core and core group power domains in the Mali-T624 GPU are controlled internal to the GPU by the Job Manager. See the ARM® Mali™-T600 Series GPU Technical Overview.

The single power domain implemented in the GPU by the ADP is controlled by a PPU in the SCP.


System power domain

The VSYS voltage supply powers the system. VSYS operates at 0.9V and does not support DVFS. VSYS is fixed at 0.9V, powers all the ADP including SYSTOP and has the following properties:

• Not switched internally. The PMIC can switch it externally.

Table 2-18 Summary of Cortex-A53 cluster power domains implemented in the ADP

Name Power domainADP implementationoperating modes

Operating modes

A53CPU[n] Each core On, Off On, Retentiona, Off

Advanced SIMD/FP pipeline in each core

A53SSTOP L2 Cache RAMs On, Offb

SCU-L2 and governors On, Off

a. For L2 RAMs dynamic retention, the L2 Data, Dirty, Tag, Inclusion PF, and Snoop Tag RAMs are retained.For L2 cache Dormant mode, the L2 Data, Dirty, Tag, and Inclusion PF RAMs are retained.The Inclusion PF RAM is available only in r1p0 and later revisions of the Cortex-A57 processor.

b. External switch-off.

Table 2-19 Summary of Mali-T624 GPU power domains implemented in the ADP

Name Power domain ADP implementation operating modes Operating modes

GPUTOP Job manager OnOff

OnOff

Core groups

Shader core



• SYSTOP Scratch and Secure RAMs support memory retention when VSYS is powered down.

Table 2-20 shows the power domains that the system supports.

Note The ADP has separate policy units for DBGSYS and SYSTOP. However, these are implemented as a single power domain that the SYSTOP power policy unit controls. The DBGSYS power policy unit still independently controls the reset state of debug components.

Figure 2-3 on page 2-31 shows the voltage domains and the power-gated regions.


AON power domain

The VAON voltage supply powers the AON region. VAON operates at 0.9V and does not support DVFS.

Table 2-21 shows the power domain that the AON supports.

Note In the ADP, the 28HPM RAM bitcells that the Cortex-A57, Cortex-A53, and GPU macros use do not support voltage scaling, and so the fixed VSYS voltage supply powers them. However, this introduces a restriction that the PMIC can switch off VA57, VA53, and VGPU can only when VSYS is also switched off.

Figure 2-3 on page 2-31 shows the voltage domains and power-gated regions.

Table 2-20 Summary of system power domains

Name Power domain ADP implementation operating modes

DBGSYS Debug subsystem On, Off

SYSTOP System logic

Scratch and Secure RAMs On, Retention, Off

Table 2-21 Summary of AON power domains

Name Power domain Operating mode

AON SCP subsystem On



Figure 2-3 Voltage domains and power-gated regions

VAON

Cortex-A57 cluster

PCIe

I2S

Secure I2C

RNG

Sys override

I2C

NV counter

Keys

UART0

UART1

Surge detector

PVT, core

PVT, GPU

PVT, SoC

PVT, std cell

PCIe Root Complex PCIe PHYPIPE

NIC-400

Config Memory

APB4

HDLCD 0 HDLCD 1APB3 APB3

HDLCD switchSS

MMU-400 MMU-400

M128-bit master switch

SS

M

TLX-400 slave

ADB-400

DMAPL330

S

MMU-400

PG PG

PG

Cortex-A53 cluster

PGPG

PG PG

PG

Mali-T624 MP4 cluster

Shader core 0

Shader core 1

Shader core 2

Shader core 3

L2 cache

ADB-400 ADB-400

ADB-400

CCI-400

VA57 VA53

VGPU

USB 2.0 host controller

APBtoAXI3

Async APB4 Async

APB4MMU-400

ULPI

NIC-400

Non-secure ROM

RET RET Secure ROM

Peripherals

DMC-400

TZC-400

ADB-400

DDR3LPHY

DDR3LPHY

1:2 DFIRatiobridge

1:2 DFIRatiobridge

RETRET

WB

ADB-400

DMA (S)DMA (NS)HDLCD1HDLCD0

SCC

PVT, AON

I2CSCP AHB-Lite

to APB

CRG

ADB-400

PCSM

Voltage domains

VAON peripherals

APB3, Secure, Non-secure

5 x PLL

CRG

64-bit slave switch S

M AXItoAPB Async

AXItoAPBHDLCD1 MMUHDLCD0 MMUDMA MMUUSB MMUPL354

M

SMCPL354

EBI

TXL-400master

ADB-400

AXI master port

Async64-32

MAsync64-32

M

USB EHCI AHB slave interface

USB OHCI AHB slave interface

ADB-400

MMU-400

128-64

CoreSightMMU-400

Debug and trace

VSYSVSYS

VSYS



2.7 ADP power statesThe ADP contains a set of power states that define the legal combinations of power domain operating modes. Power states can be in a hierarchy of power state tables. Each power state table describes the power states available at its level of hierarchy. These levels are necessary for effective power-management of a big.LITTLE system.

The ADP power state tables contain the following levels of hierarchy:

Core Applies to the cores inside the Cortex-A57 and Cortex-A53 clusters. See Core power states.

Cluster Applies to the Cortex-A57 and Cortex-A53 clusters. See Cluster power states on page 2-34.

Mali-T624 job manager Applies to the Mali-T624 GPU. See Mali-T624 power states on page 2-36.

System Applies to the entire system. See System power states on page 2-36.

Figure 2-4 shows the power state hierarchy for the ADP.

Figure 2-4 ADP Power state hierarchy

This section contains the following subsections:• Core power states.• Cluster power states on page 2-34.• System power states on page 2-36.• Mali-T624 power states on page 2-36.

2.7.1 Core power states

The ADP defines core power states that are consistent with the Server Base System Architecture (SBSA). The SBSA formalizes power-management requirements and defines the following core power states:

RUN The core is powered up and running code.

Core 0RUNIDLE

SLEEPOFF

Core 1RUNIDLE

SLEEPOFF

Core 0RUNIDLE

SLEEPOFF

Core 1RUNIDLE

SLEEPOFF

Core 2RUNIDLE

SLEEPOFF

Core 3RUNIDLE

SLEEPOFF

Cortex-A57 clusterRUN

SLEEPOFF

Cortex-A53 clusterRUN

SLEEPOFF

Mali-T624job manager

RUNOFF

System

RUNSLEEP

OFF



IDLE The core is in the STANDBYWFI state, but remains powered. It has full state retention, with no state saving or restoration required. Execution automatically resumes after:• Any interrupt.• An external debug request.• An enter debug request, EDBGRQ.• External access of debug registers.

SLEEP The core is powered down but hardware wakes the core autonomously, for example, when it receives a wake up interrupt. No core state is retained so you must explicitly save the state. A woken core starts at the reset vector, and then hardware-specific software restores the state.

OFF The core is powered down and is not required to be woken by interrupts. The only way to wake the core is by explicitly requesting the power controller, for example:• From system software running on another core.• An external source, such as a power_on_reset.You can use this state when the system software explicitly decides to remove the core from active service, giving the hardware the opportunity for more aggressive power saving. No core state is retained.

This section contains the following subsections:• Cortex-A57 core power states in the ADP.• Cortex-A53 core power states in the ADP.

Cortex-A57 core power states in the ADP

Because of implementation constraints, the Cortex-A57 cluster in the ADP does not support the Retention operating mode for the core power domain. This reduces the available power states to those that Table 2-22 shows.

Cortex-A53 core power states in the ADP

Because of implementation constraints, the Cortex-A53 processor cluster in the ADP does not support the Retention operating mode for the following:• Advanced SIMD/FP pipeline power domain.• Core power domain.

Table 2-22 Cortex-A57 cluster power states implemented in the ADP

Corepower state

Core power domainoperating mode

Description

RUN On Cores are running code.

IDLE WFI or WFE.

SLEEP Off Off. Interrupts are enabled for this core.

OFF Off. No interrupts are enabled for this core.



This enables you to physically implement these power domains as a single power domain. This reduces the available power states to those that Table 2-23 shows.

2.7.2 Cluster power states

The following processor cluster power states are available in the ADP:

RUN The cluster is powered up, and can support any core moving to any power state.

SLEEP The cluster is powered down, but can wake when it receives a wake-capable interrupt. This implies that at least one core in the cluster is in the SLEEP state, while other cores are in either the SLEEP or OFF states.Before a core in the cluster can move to a higher power state, the cluster must first move to the RUN state.

OFF The cluster is powered down, and does not wake when it receives an interrupt. This implies that all cores in the cluster are in the OFF state.Before a core in the cluster can move to a higher power state, the cluster must first be moved to an appropriate higher power state.

Note The SLEEP and OFF power states use the same power domain operating modes, but are semantically different at the system level because of the ability of the cluster to wake when a core in the cluster receives a wake-capable interrupt.

This section contains the following subsections:• Cortex-A57 cluster power states in the ADP on page 2-35.• Cortex-A53 cluster power states in the ADP on page 2-35.

Table 2-23 Cortex-A53 core power states implemented in the ADP

Core power state

Core andAdvanced SIMD/FPpower domainoperating mode

Description

RUN On Core is running code.

IDLE WFI or WFE.

SLEEP Off Off. Interrupts are enabled for this core.

OFF Off. No interrupts are enabled for this core.



Cortex-A57 cluster power states in the ADP

Because of implementation constraints, the Cortex-A57 cluster in the ADP does not support the Retention operating mode for the L2 Cache RAM power domain. This reduces the available power states to those that Table 2-24 shows.

In the ADP, the debug APB, CTI, and CTM logic power domain is merged with the non-core control logic power domain. Therefore, the ADP implementation of the Cortex-A57 cluster includes the same cluster power states as the Cortex-A53 cluster, with the exception that the SCU-L2 and governor power domain for the Cortex-A53 cluster is known as the ‘non-core control logic power domain’ for the Cortex-A57 cluster.

Cortex-A53 cluster power states in the ADP

Because of implementation constraints, the Cortex-A53 cluster in the ADP does not support the Retention operating mode for the L2 Cache RAM power domain. This enables these power domains to be physically implemented as a single power domain. This reduces the available power states to those that Table 2-25 shows.


Clusterpower state

Core power domain operating mode

Non-core control logic Description

RUN Any On Cores can run code.

SLEEP All cores in the SLEEP or OFF state, with at least one in the SLEEP state.

Off Cluster fully off. Can wake from interrupt.

OFF All cores in the OFF state. Off Off. No interrupts enabled for cores in this cluster.


Clusterpower state

Core power states

SCU-L2, governors,and L2 Cache RAMspower domainoperating mode

Description

RUN Any On Cores can run code.

SLEEP All cores in the SLEEP or OFF state, with at least one core in the SLEEP state.

Off Cluster fully off. Can wake from interrupt.

OFF All cores in the OFF state. Off Off. No interrupts enabled for cores in this cluster.



2.7.3 System power states

Table 2-26 shows the system power states implemented in the ADP.

2.7.4 Mali-T624 power states

Table 2-27 shows the Mali-T624 power states.

2.7.5 Power control

This section describes:• Voltage regulator control.• Power domain control on page 2-37.

Voltage regulator control

The SCP firmware controls the system voltage regulators. The physical interface to the PMIC must be mapped as a peripheral on the SCP AHB expansion bus.

To ensure successful platform initialization, see the ARM® Versatile™ Express Juno Development Platform (V2M-Juno) Technical Reference Manual. For digital supplies, consider the following:

• The digital supplies to the SCP and system, VAON, and VSYS, must be available at powerup reset to enable the SCP to start.

• To start the application processors during the system initialization sequence, to avoid PMIC-specific code in the SCP ROM, it is necessary to default power the VA57 and VA53 voltage supplies.

Table 2-26 System power states

Systempower state

Cluster states

Power domain

DescriptionSystem Timers

Secure andNon-secure RAM

RUN Any On On On Cores can run code, and can wake on any enabled interrupt.

SLEEP_RET All clusters in the SLEEP or OFF state, with at least one cluster in the SLEEP state.

Off On Retention Only interrupts from a wake-up timer, or other system events, for example, a wake-up button, can cause a wake-up.TBD - info. from Jinson.

SLEEP Off On Off

OFF All cores in the OFF state.

Off Off Off No interrupts are enabled. External wake-up only, for example, a powerup reset.

Table 2-27 Mali-T624 power states

GPU power state Job manager state GPU power domain Description

RUN Any On GPU available under control of the job manager

OFF Shutdowna Off SCP controls wakeup

a. Job manager ensures all core group and shader cores are in shutdown.



• Default powering of VGPU is not mandatory, but you must isolate the VGPU outputs in the VSYS supply to prevent corruption of active logic.

SCP firmware is also responsible for the variation of digital power supply levels in the power-management strategies, for example, DVFS and Adaptive Voltage Scaling (AVS).

Power domain control

The ADP includes a Power Policy Unit (PPU) for each power domain that the SCP controls. These provide a software interface for simple control over the required operating mode for the power domain.

Figure 2-5 shows the power-gating control.

Figure 2-5 Power domain control

This section describes:• Power policies.• PPU power states on page 2-38.• Power policy unit behavior on page 2-38.

Power policies

Table 2-28 shows the supported PPU power policies.

System Control Processor (SCP)

Processor core

Processor core

GPU job manager

PPU

PPU

PPU

Processor clusterSystem

PPU

PPU

Table 2-28 Supported PPU power policies

Power state Name Description

b10000 ON Powered up. Any functional or architectural clock-gating operates independently of power control in this state.

b01000 WARM_RST Powered up, but held in warm reset.

b00100 - Reserved. The ADP does not support this policy.

b00010 MEM _RET Memory retention only of memories supporting integrated, retention mechanisms. Power is removed from logic and from any memory arrays that do not support retention.

b00001 OFF All power is removed, and there is no retention of any part.



PPU power states

Table 2-29 shows the default and supported power states for each PPU.

Power policy unit behavior

Table 2-30 shows the behavior of the PPU in terms of software-visible register fields.

Table 2-29 Default and supported power states

PPU Default policy Supported policies

SYSTOP ON ON, MEM_RET, OFF

DBGSYS OFF ON, OFF

A57STOP OFF ON, OFF

A57CPU[x] OFF ON, WARM_RST, OFF

A53SSTOP OFF ON, OFF


GPUTOP OFF ON, OFF

Table 2-30 PPU Register field definitions

Register field Type Description

POLICY RW Enables software to determine the policy for the next power state transition. Transitions to higher power states start immediately.

Note This register does not always reflect the current power state value.

If a POLICY value, that the corresponding power region does not define or support, is written, it is ignored.Supported power states can be read from the Power Status Register.

POWSTAT RO Reflects the current power state of the domain. This does not reflect the fact that power state changes might be emulated.

EMULATED RO Supports low-level debug. This bit indicates whether the policy that POWSTAT indicates is being emulated. It is intended that it is ignored by functional software.

MRETSPT RO Indicates whether the PPU supports the memory retention policy, MEM_RET. For PPUs that are configurable, the value of this field indicates whether the PPU is configured to include support for the MEM_RET policy.



For information about the PPU Registers see Power Policy Unit Registers on page 3-142.

Table 2-31 shows the hardware signals that are directly relevant to the software control of the PPUs and power transitions.

2.7.6 Debug power requests

This section describes:• CoreSight debug power requests.• Debug power request, CDBGPWRUPREQ on page 2-41.• System power request, CSYSPWRUPREQ on page 2-41.• Core debug power requests on page 2-41.

CoreSight debug power requests

The debugger can set two levels of power request at the outputs of the Debug Access Port (DAP). This section describes power requests from the main system DAP. The equivalent Cortex-M3 SCP DAP power request outputs are not used as power requests.

HWCACTIVEEN RW Enables and disables device-active control as follows:• When enabled, hardware-active signals delay entry to any lower power state that has been

programmed until the HWCACTIVE signal is de-asserted.• When disabled, power state transitions can occur without checking the HWCACTIVE

input signal.

HWCSYSREQEN RW Enables or disables device handshake control as follows:• When enabled, the device request signaling is driven appropriately at each power transition,

and the device acknowledge response is required to complete the transition.• When disabled, the HWCSYSREQ signal is driven permanently HIGH, and the device

acknowledge signal state is ignored.

RETEN RW This is a multi-bit field, with each bit representing whether retention is to be enabled for a particular group of memories within the power region when in the MEM_RET state. This field can only be updated when the power region is in the ON state. Writes to this field when the power region is in any other state are ignored.

Table 2-30 PPU Register field definitions (continued)

Register field Type Description

Table 2-31 PPU hardware signals

Signal name Direction Description

IRQ Output When a power state transition is complete, the PPU generates an interrupt pulse to the SCP.In the case of emulated powerdown, only the first PPU transition, to an emulated state, triggers an interrupt pulse, even when subsequent removal of conditions for emulated powerdown can lead to an additional hardware power state transition.

HWCACTIVE Input The HWCACTIVE input indicates hardware dependencies before a PPU can enter a lower power state. When asserted, a PPU entry into a programmed lower power state is delayed until the signal is de-asserted. You can turn off this dependency by programming the HWCACTIVEEN bit. See Table 2-30 on page 2-38.

HWCSYSREQ and HWCSYSACK

Input, output

The HWCSYSREQ and HWCSYSACK signals initiate, and ensure completion of, any required hardware-only process before a PPU can progress entry into a lower power state. You can turn off this dependency by programming the HWCSYSREQEN bit. See Table 2-30 on page 2-38.



The debug power requests are as follows:

Debug power request, CDBGPWRUPREQ A request to power up all debug infrastructure. The CDBGPWRUPACK signal acknowledges the power up request.

System Power Request, CSYSPWRUPREQ A request to power up and clock all debugger-visible system resources. The CSYSPWRUPACK signal acknowledges the powerup request.

The mechanism used in both cases is a simple four-phase handshake, comprised of the request and acknowledge signals. Figure 2-6 shows this handshake.

Figure 2-6 Debug power request handshake

Table 2-32 shows the states of the handshake signals and the expected behavior.

The ADP manages the four-phase handshake as follows:

• Each request, CDBGPWRUPREQ and CSYSPWRUPREQ, is defined as an interrupt source to the SCP. The request signals are pre-conditioned so that both edges can generate an interrupt pulse.

• The status of each request signal is visible to the SCP software using a register to determine its polarity.

• On the rising edge of a request, detected using interrupt state and status visibility, the SCP firmware takes the appropriate action to power and clock the appropriate resources before any acknowledgement is given.

• The SCP firmware can drive the acknowledge signals, CDBGPWRUPACK and CSYSPWRUPACK, using its Debug Control Register on page 3-133.

The following describe the SCP firmware requirements for each request:• Debug power request, CDBGPWRUPREQ on page 2-41.• System power request, CSYSPWRUPREQ on page 2-41.• Core debug power requests on page 2-41.• Emulated power modes on page 2-42.• Warm reset requests on page 2-42.

CxxxPWRUPACK, SCP

CxxxPWRUPREQ, DP

Table 2-32 Debug power request handshake states

CSYSPWRUPREQ orCDBGPWRUPREQ

CSYSPWRUPACK orCDBGPWRUPACK

Description

1 0 Power request from debugger.

1 1 Power controller acknowledges that resources are powered and available.

0 1 Debugger removes power request.

0 0 Acknowledge removed. No action until next request.



Debug power request, CDBGPWRUPREQ

SCP firmware should power up the following before acknowledging the request:• SYSTOP.• All debug power regions.• All processor power regions.

The sequence for acknowledging the request is as follows:

1. SYSTOP powering is required to provide clocks to the processor and debug, and to power debug infrastructure passing between the DBGSYS and processor regions.

2. Debug and trace clocks, PCLKDBG, ATCLK, and TRACECLKIN, are explicitly enabled.

3. Power up DBGSYS.

4. The A53SSTOP and A57SSTOP power regions are powered up because they incorporate the external debug logic for each processor. If either region is off, the manual reset corresponding to the SCU or L2 functional logic is asserted prior to power up of the domain. This action ensures that functional logic that was off is not activated, and only debug logic is enabled for operation when the PPU reset is released.

5. If a functional powerup reason, event, or interrupt, for a processor system is detected, the appropriate SCU or L2 manual reset is released. No additional programming of the PPU is required.

6. When the debug power request is removed, the SCP powers off the A53SSTOP and A57SSTOP regions, with manual reset bits set, to indicate that the functional logic has not been enabled and would have still been powered down without a debug power request. See Cortex-A53 Manual Reset Status Register on page 3-131. Regions with manual reset bits cleared are left powered up until the SCP receives a powerdown request.

7. Debug regions are powered down. You can disable debug and trace clocks.

8. If all processor system regions are powered down, and all other SYSTOP powerdown criteria are met, then SYSTOP can be powered down.

System power request, CSYSPWRUPREQ

No strict debug architecture requirements exist, so SCP firmware should sequence the powering of all regions before acknowledging the request.

Core debug power requests

The external host debugger can set power-related requests, that the SCP handles, for individual cores by directly accessing debug registers within both the core and external debug logic at the core level.

The core-specific debug power requests are:

DBGPWRUPREQ[N-1:0] The debugger can set a core-specific powerup request in the external debug registers.



DBGNOPWRDN[N-1:0] Core-specific no powerdown request. The debugger has requested that core N is not powered down. The SCP must not remove power from core N, or memory, when this signal is HIGH, even during a powerdown event.

The ADP manages the DBGPWRUPREQ requests as follows:

1. Each processor powerup request, DBGPWRUPREQ, generates an interrupt pulse on either edge within the SCP. This is then used as an interrupt to the Cortex-M3 SCP.

2. The status of each request signal is visible in an SCP register so that its polarity can be determined, and the SCP firmware can power up or power down the appropriate processors accordingly.

3. The DBGPWRUPREQ signal for each processor also forms an OR term towards the corresponding PPU DBGEMUPWRDN input so that any powerdown, during the period that DBGPWRUPREQ is set, is emulated.

4. The DBGNOPWRDN signal for each processor forms an additional OR term towards the corresponding PPU DBGEMUPWRDN input so that any powerdown, during the period that DBGNOPWRDN is set, is emulated. DBGNOPWRDN has no architectural powerup requirement and therefore, no SCP support is required.

Emulated power modes

When a power state is emulated, the normal functional actions leading to powerdown are taken. However, the PPU does not handshake with the power gate control logic, so physical power switches are not opened, power remains on, and isolation is not enabled. See Power domain control on page 2-37. Power domains behave functionally as powerdown because of applied resets. The typical use for an emulated state is to retain the debug state while functional logic goes through the functional steps of a powerdown. This might mean that some debug resets are not asserted during an emulated powerdown.

For information about resets, see Internal reset generation on page 2-16.

For information about the emulation of powerdown in the ARM v8 Debug architecture, see the definition of the CORENPDRQ bit in the Device Powerdown and Reset Control Register, DBGPRCR, in the ARM® v8 Debug Architecture.

Warm reset requests

Each v8 application processor can generate the following types of warm reset request:• Warm Reset Request generated using the Reset Management Register (RMR).• Debug Reset Request generated using the External Debug Power/Reset Control Register

(EDPRCR).

The PPU and the SCP handle these requests. Both reset requests from each core are interrupt sources to the SCP.

When the SCP receives a reset request, it programs the PPU to enter the WARM_RST state. When the PPU enters this state, the SCP programs the PPU to enter the ON state.

The following tables show the effect of the WARM_RST state on the processors:• Table 2-8 on page 2-17.• Table 2-10 on page 2-18.• Table 2-11 on page 2-19.



2.8 System Control Processor (SCP)The System Control Processor (SCP) is a Cortex-M3 microcontroller-based system that exists alongside the application processors. Its main purpose is to control components both within the SoC, and outside the SoC, using a PMIC interface.

The SCP manages the overall power, clock, reset, and system control of the ADP. This is an always-on Cortex-M3 processor based subsystem.

The SCP uses the following registers to manage the system:• ADP System Control Registers.• ADP System Security Control Registers.• Registers for the ADP PPUs.

See Chapter 3 Programmers Model.

Figure 2-7 shows a block diagram of the SCP.

Figure 2-7 SCP block diagram

Private peripherals support the Cortex-M3 processor. The Cortex-M3 processor uses some of these peripherals for basic operation, such as timers, instructions, and data memories. Other peripherals are designed to directly drive power-control logic.

The key features of the SCP are as follows:

• Boot and system start-up and security integrity.

• Initial configuration and subsequent reset.

Debug andtrace

NVIC

Cortex-M3 processor

ROM SRAM

ICode DCode

AHB2APB

GTIMER, REFCLK

WATCHDOG

CS GCOUNTER

GCOUNTER, 32K

Power registers

Configuration and control registers

CRG

AHB2AXISystem ControlProcessor (SCP)

EPPB, IPPB, APB

PPU0PPU1PPU2

PPUn

SCP clocks

System statusand control

Expansion interface, AHB

System access

GCOUNTER, REFCLK,always on peripherals

SLEEPSLEEPDEEP

REFCLK interface

S32KCLK, 32,768Hz

SYSREFCLK

Subsystem interruptsExtension interrupts

TraceDebug interface

System,AHB

PPU interfaces

GTIMER, 32K



• Managing transitions between operating points, that is, external voltage regulator and clock management, to support DVFS.

• Handling hardware wake-up requests from components such as timers and interrupts.

• Saving and restoring all states in the interconnect and Dynamic Memory Controller (DMC) when powering down or powering up.

• Responsible for managing a consistent matrix of device states across the whole system.

This section describes:• Components.• Events on page 2-46.• Sleep modes on page 2-46.

2.8.1 Components

This section describes the major components of the SCP:• Cortex-M3 processor.• Peripherals.• Configuration and control registers on page 2-45.• Power registers on page 2-46.• Security on page 2-46.

Cortex-M3 processor

The Cortex-M3 processor is an ARMv7M architecture processor and contains the following:

Memory Protection Unit (MPU) A unified MPU that supports eight memory regions.

Nested Vectored Interrupt Controller (NVIC) The NVIC is configured to support 105 interrupt lines from the ADP.The Cortex-M3 System Control Space registers include this. See ADP System Control Registers on page 3-106.

Debug and trace system Debug and profiling on page 2-83 describes the debug and trace configuration.

Appendix B Subcomponent Configurations describes the exact configuration of the Cortex-M3 processor.

See the Cortex®-M3 Technical Reference Manual.

Peripherals

The SCP contains the following peripherals:

SRAM Private data and code SRAM memory.

ROM Private Secure boot ROM.

SCP timing peripherals The following system timing peripherals are included:• SCP firmware watchdog timer with a 32kHz time-base.• ARM Generic Timer, REFCLK.



• ARM Generic Timer, S32KCLK.• ARM Generic Counter, S32KCLK.• ARM Generic Counter, REFCLK, for CoreSight timestamps.

Power Policy Unit (PPU) Registers These are the control registers for the PPUs.

Configuration and control registers These registers configure the system and support clock, reset, and system control.

Message Handling Unit (MHU) Communicates with the application processor system.

Access to application processor system The SCP can access part of the AP memory map.

See:• Timers on page 2-75.• Application processor memory map on page 3-13.• System Control Processor (SCP) memory map on page 3-29.• Application processor interrupt map on page 3-3.• System Control Processor (SCP) interrupt map on page 3-10.

Configuration and control registers

Configuration and control software registers provide support for the following capabilities:

System configuration Provides configuration support for components in the ADP.

System clock configuration and control These registers manage the configuration and enable control for the clocks of the main system clock-generation unit that is located in the SYSTOP power region.

Note Because these registers are located in an always-powered region, re-configuration of the clock-generation after a SYSTOP power cycle is not mandatory.

Reset control In addition to the hardware-generated resets, these registers provide software control over the resets to power regions, in addition to debug and trace logic.

System control and status These registers provide support for a number of system control features including interconnect access control to support power-management and other dynamically-configured features. See ADP System Control Registers on page 3-106.

Debug power control and status These registers provide support for debug power control requests and response status. See Debug Registers on page 3-133.



Power registers

These registers control the PPUs and manage the power region state transitions that the SCP firmware controls.

See:• Power control on page 2-36.• Power domain control on page 2-37.• Power Policy Unit Registers on page 3-142.

Security

The SCP is a Secure device that has a dedicated Secure boot ROM. The SCP SRAM is also Secure. Only the Cortex-M3 processor can access the SCP ROM and SRAM. These memories are not shared with the main processor system and they are located in the AON power region. From a cold boot, the SCP runs initially from its local Secure ROM.

Security on page 2-64 describes the security model for the SCP and the wider ADP.

2.8.2 Events

The Cortex-M3 processor has TXEV output and RXEV input signals that enable it to support the WFE and SEV mechanism that the ARMv7-M architecture defines.

In the ADP SCP, these signals are cross-wired between the application processor and the Cortex-M3 SCP. Send Event (SEV) instructions executed on the SCP wake the application processors from a WFE. Similarly, SEV instructions executed on the application processors wake the SCP from a WFE.

See:• Events.• The Cortex®-M3 Technical Reference Manual.• The ARM®v7M Architecture Reference Manual.

2.8.3 Sleep modes

This section describes the SCP sleep mode entry and exit sequences that use the Cortex-M3 processor SLEEPING and SLEEPDEEP sleep modes.

The SLEEPDEEP bit in the Cortex-M3 processor System Control Register determines the sleep mode that the Cortex-M3 processor enters as follows:

• When this bit is set, and the processor enters sleep, the Cortex-M3 processor enters SLEEPDEEP mode.

• When this bit is clear, and the processor enters sleep, the Cortex-M3 processor enters SLEEPING mode.

The Cortex-M3 SCP enters a sleep mode when the Cortex-M3 System Control Register SLEEPDEEP bit is not set, and firmware executes a Wait For Instruction (WFI) or Wait For Event (WFE) instruction. The Cortex-M3 SCP also enters this sleep mode if the SLEEPONEXIT bit in the Cortex-M3 processor System Control Register is set and the processor exits from an Interrupt Service Routine (ISR) that returns to the base level of execution priority.

The Cortex-M3 SCP exits from the SLEEPING sleep mode when a WFI or WFE wakeup event occurs.



The SCP performs the following actions in each of these sleep modes:

SLEEPING In this sleep mode, the SCP gates the clock to the Cortex-M3 processor, but other logic in the SCP continues to run, and the SYSREFCLK output clock remains available.

SLEEPDEEP In this sleep mode, the SCP glitchlessly switches its internal clock source to S32KCLK, and de-asserts REFCLKREQ so that the SoC clock-generation logic can also enter a low-power mode. When exiting this sleep mode, the ADP wakes using S32KCLK and then requests REFCLK using the REFCLK request and acknowledge interface. It then switches its internal clock source back to REFCLK.

Note In the ARM Development Platform, REFCLK is never disabled. This means that the SLEEPDEEP mode does not provide any additional power saving to that provided by the SLEEPING mode.



2.9 Application processor peripheralsThe ADP contains the peripherals required to support a Rich OS. Other required peripherals are located outside the ADP. The peripherals encompass essential system-based timers.

This section contains the following subsections:• USB 2.0 host controller on page 2-50.• Direct Memory Access (DMA) controller on page 2-51.• HDLCD controller on page 2-52.• Coherency support for non-ACE-Lite masters on page 2-53.• Static Memory Controller (SMC), PL354 on page 2-54.• I2S interface on page 2-55.• I2C interface on page 2-55.• UART on page 2-57.• System override registers unit on page 2-58.• System configuration controller on page 2-59.

Table 2-33 shows all peripherals that are accessible to all application processors using the Application memory, excluding debug components that are mapped to the CoreSight AXI and APB areas. See Application processor memory map on page 3-13.

Table 2-33 Application processor peripherals

Name Description and references

NIC-400 GPV The NIC-400 programmers model. See SoC peripherals NIC-400 Registers on page 3-154 and Compute subsystem NIC-400 Registers on page 3-168.

SEC_REG ADP System Security Control Registers on page 3-34.

REFCLK CNTControl REFCLK Generic Counter, Control Registers. See REFCLK counter on page 2-78.

REFCLK CNTRead REFCLK Generic Counter, Status Registers. See REFCLK counter on page 2-78.

AP_REFCLK CNTCTL AP_REFCLK Generic Timers, Control Registers. See AP_REFCLK Generic Timer on page 2-80.

AP_REFCLK CNTBase0 AP_REFCLK Generic Timers, Control Registers. See AP_REFCLK Generic Timer on page 2-80.

AP_REFCLK CNTBase1

Trusted watchdog Trusted Watchdog. See the ARM® Watchdog Module (SP805) Technical Reference Manual.

Generic Watchdog Generic Watchdog. See the Server Base System Architecture Platform Design Document.

TZC-400 TZC-400 TrustZone Address Space Controller. See CoreLink TZC-400 security on page 2-66.

DMC_CFG Configuration interface of the DMC-400. See the ARM® CoreLink™ DMC-400 Dynamic Memory Controller Technical Reference Manual.

SCP_MHU Message Handling Unit. See Message Handling Unit (MHU) on page 3-45.

Juno System Profiler See the Juno System Profiler Technical Reference Manual.

GPU0_SMMU System MMU, MMU-400, components.See CoreLink MMU-401 and MMU-400 System Memory Management (SMMU) components on page 2-61.PCIe SMMU

ETR_SMMU



Table 2-34 shows the voltage domain, power domain, and clock domains for each of the peripherals in Table 2-33 on page 2-48.

GIC distributor CoreLink GIC-400 Generic Interrupt Controller.See Application processor interrupt map on page 3-3 and the ARM® GIC-400 Generic Interrupt Controller Technical Reference Manual.GIC physical core interface

GIC virtual interface control

GIC virtual core interface

GICv2m MSI Handles PCI Express Message Signaled Interrupts (MSIs).

CCI_PV CoreLink CCI-400 Cache Coherent Interconnect. See the ARM® CoreLink™ CCI-400 Cache Coherent Interconnect Technical Reference Manual.

Mali-T624 GPU GPU register interface. See the Mali™-T600 Series GPU Technical Reference Manual.

USB controller USB 2.0 host controller on page 2-50

DMA controller Direct Memory Access (DMA) controller on page 2-51

HDLCD controller HDLCD controller on page 2-52

Coherency Coherency support for non-ACE-Lite masters on page 2-53

SMC Static Memory Controller (SMC), PL354 on page 2-54

I2S interface I2S interface on page 2-55

I2C interface I2C interface on page 2-55

UART UART on page 2-57

System Override Registers System override registers unit on page 2-58

System Configuration Controller System configuration controller on page 2-59

Table 2-33 Application processor peripherals (continued)

Name Description and references

Table 2-34 Voltage, power, and clock domains of the application processor peripherals

Name Voltage domain Power regions Clock domains

NIC-400 VSYS SYSTOP NICSCPCLK, NICPERCLK

SEC_REG VSYS AON NICSCPCLK

REFCLK CNTControl VSYS AON REFCLK, S32KCLK

AP_REFCLK CNTCTL VSYS SYSTOP REFCLK

Trusted watchdog VSYS SYSTOP NICPERCLK

Generic Watchdog VSYS SYSTOP REFCLK

TZC-400 VSYS SYSTOP CCICLK

REFCLK CNTRead VSYS AON REFCLK, S32KCLK

AP_REFCLK CNTBase0 VSYS SYSTOP REFCLK

AP_REFCLK CNTBase1 VSYS

DMC_CFG VSYS SYSTOP DMCCLK, DMCAUXCLK



2.9.1 USB 2.0 host controller

The ADP supports USB 2.0 with a data rate of 480Mbps, and can be used to attach common system peripherals such as keyboard, mouse, and flash drive.

• The USB 2.0 Host Controller is fully compliant with the EHCI specification.

• The USB Host Controller IP has been configured to include a single EHCI controller and a single companion OHCI controller. The EHCI controller supports USB high-speed data rates of 480Mbps. The OHCI controller supports USB full and low speed device data rates.

• The USB host controller is located on the chip and is connected to a USB PHY on the board using a 60MHz 12-pin ULPI SDR interface.

• Debug is an optional feature in EHCI, and the USB 2.0 Host Controller does not support it.

SCP_MHU VSYS AON NICSCPCLK

System Profiler VSYS SYSTOP SPCLK

GPU_SMMU VGPU GPUTOP GPUCLK

PCIe_SMMU VSYS SYSTOP CCICLK

ETR_SMMU NICSCPCLK

GIC distributor VSYS SYSTOP GICCLK

GIC physical core interface

GIC virtual interface control

GIC virtual core interface

GICv2m MSI

CCI_PV VSYS SYSTOP CCICLK

Mali-T624 GPU VGPU GPUTOP GPUCLK

USB controller VSYS SYSTOP TBD

DMA controller VSYS SYSTOP TBD

HDLCD controller VSYS SYSTOP TBD

Coherency VSYS SYSTOP TBD

SMC VSYS SYSTOP TBD

I2S interface VSYS SYSTOP TBD

I2C interface VSYS SYSTOP TBD

UART VSYS SYSTOP TBD

System Override Registers VSYS SYSTOP TBD

System Configuration Controller VSYS SYSTOP TBD

Table 2-34 Voltage, power, and clock domains of the application processor peripherals (continued)

Name Voltage domain Power regions Clock domains



• 64-bit EHCI addressing capability is enabled on the ADP to be ARMv8 compatible.

• Legacy emulation interface and PCI power-management features of the USB Host Controller IP not used for Juno.

USB host controller IP configuration

See USB host controller configuration options on page B-9.

2.9.2 Direct Memory Access (DMA) controller

The ADP includes a system DMA-330 controller as a master on the compute subsystem I/O coherent slave interface. The DMA controller can transfer data within memory, or between memory and peripherals.

The DMA-330 implements TrustZone. The boot_manager_ns input signal on the DMA-330 controls the security state of the device as follows:

0 When the pin is 0, the DMA manager is in the Secure state and instructions are issued through the secure APB interface. Any instructions issued through the Non-secure APB are ignored.

1 When the pin is 1, the DMA manager is in the Non-secure state, and either the Secure or the Non-secure APB interface can control the DMA channel.

In the ADP, the DMA_BOOT_MANAGER_NS bit of the DMA Control Register 0 on page 3-65 controls this pin.

Table 2-35 shows the DMA-330 configuration parameters used.

Table 2-35 DMA-330 configuration

DMA-330 configuration Value

AXI data width 128

Icache lines 16

Icache words 8

Number of channels 8

Write issuing capacity 8

Read issuing capacity 8

Read LSQ depth 16

Write LSQ depth 16

FIFO depth 1024

Number of interrupts 8

Number of peripheral request interfaces 8



The system DMA controller also includes peripheral request interfaces to support transfer between peripherals and memory, without the intervention of the processor. Table 2-36 shows the peripheral request IDs.

2.9.3 HDLCD controller

The ADP includes two independent HDLCD display controllers. Table 2-37 shows the display resolutions supported, and the pixel clock frequencies required.

HDLCD controller configuration

Table 2-38 shows the HDLCD controller configuration parameters.

Table 2-36 DMA-330 peripheral request interface mapping

Peripheral request ID ADP peripheral

0 STM

1 UART0 RX

2 UART0 TX

3 UART1 RX

4 UART1 TX

5 I2S

6 External source, FPGA

7 Reserved

Table 2-37 Display resolutions

Type Resolution Frame rate Pixel clock frequency, MHz

VGA 640 × 480 60 23.75

UXGA 1600 × 1200 60 63.5

Full HD 1920 × 1080 60 148.5

QXGA, 40% blanking 2048 × 1536 30 132

WQXGA, 40% blanking 2560 × 1600 30 172

WQXGA, reduced blanking 2560 × 1600 60 210

Table 2-38 HDLCD controller configuration parameters

Parameter DefaultJunosetting

Description

FIFO_ADDRESS_BITS 8 9 Number of address bits used to access the pixel data FIFO.FIFO size is 8 bytes × 29 = 4KB.

COUNTER_BITS 11 12 Number of bits used for all timing counters and configuration registers.Maximum resolution supported is 212 × 212 = 4096 × 4096. This is sufficient for QFHD and 4K2K.



2.9.4 Coherency support for non-ACE-Lite masters

The DMA and USB masters are AXI3 masters and do not support ACE-Lite natively. To enable these masters to snoop the hardware coherent caches of the CPUs, Juno supports a limited form of ACE-Lite signaling. This is done by driving the AxDOMAIN signals appropriately from the MMU-401 associated with the master.

This scheme supports a restricted set of ACE-Lite transactions, that is, only the ACE-Lite transactions that are compatible with AXI4 and NIC-400. Table 2-39 and Table 2-40 show the supported types of ACE-Lite transactions for write and read transactions. For this scheme to work, the only additional signal an AXI3 master requires is the shareability domain, and the MMU-401 supports this.

Table 2-39 shows the permitted ACE-Lite write transactions.

Table 2-40 shows the permitted ACE-Lite read transactions.

The USB and DMA MMU-401s are configured as AXI3. These MMU-401s communicate the calculated domain and inner cacheability values using AxUSER bits[21]. If the AxUSER width on the MMU-401 slave interface is 0, then the mapping of AxUSER bits is as follows:

AxUSER[5:4] Domain attributes.

AxUSER[3:0] Inner Cacheability attributes.

User bits AxUSER[5:4] communicate the shareability settings of the USB and DMA transactions, including MMU-401 translation table walks, to the coherent slave port of the compute subsystem. USB and DMA masters are considered to be part of outer domain, and so the inner cacheability attributes, AxUSER[3:0], from the MMU-401s are ignored.

Table 2-41 shows the coherency signals from the USB MMU-401.

Table 2-39 Permitted ACE-Lite write transactions

Type AWSNOOP[2:0] AWDOMAIN[1:0] Transaction

Non-coherent 0b000 0b00, 0b11 WriteNoSnoop

Coherent 0b000 0b01, 0b10 WriteUnique

Table 2-40 Permitted ACE-Lite read transactions

Type ARSNOOP[3:0] ARDOMAIN[1:0] Transaction

Non-coherent 0b0000 0b00, 0b11 ReadNoSnoop

Coherent 0b0000 0b01, 0b10 ReadOnce

Table 2-41 Coherency signals from USB MMU-401

Destination Source Description

CSS ARUSERSC[1:0] USB MMU-400 ARUSER[5:4] Shareability domain of USB reads

CSS ARUSERSC[5:2] Tied to 0b0000 Shareability type of USB reads

CSS AWUSERSC[1:0] USB MMU-400 AWUSER[5:4] Shareability domain of USB writes

CSS AWUSERSC[4:2] Tied to 0b000 Shareability type of USB writes



Table 2-42 shows the coherency signals from the DMA MMU-401.

2.9.5 Static Memory Controller (SMC), PL354

The static memory interface in the ADP supports both NOR and eMMC memories. In addition, the static memory interface also supports some peripherals through the FPGA on the board. The ADP supports NOR flash natively and it is intended to be a simple boot mechanism during early board bring-up work.

The PL354 supports two SRAM style memory interfaces. Each memory interface supports four chip selects, providing eight chip selects in total. Juno uses six of the eight available chip selects. To reduce the pin count on the package, the two memory interfaces on the PL354 share the same set of test chip pins using the External Bus Interface (EBI), PL220, block. The EBI handles the required arbitration between the memory interfaces. The PL354 configuration space is memory-mapped at 0x00_7FFD_0000.

Table 2-43 shows the default address ranges for the chip selects. However, you can change this by programming appropriate address mask and match values in the SCC registers using the serial interface when the chip is held in reset. Select the address mask and match values such that no address maps to more than one chip select.

CoreLink Static Memory Controller (SMC), PL354 on page B-8 describes the PL354 configuration parameters.

Table 2-43 shows the PL354 chip selects and address ranges.

Table 2-42 Coherency signals from DMA MMU-401

Destination Source Description

CSS ARUSERSC[1:0] DMA MMU-400 ARUSER[5:4] Shareability domain of DMA reads

CSS ARUSERSC[5:2] Tied to 0b0000 Shareability type of DMA reads

CSS AWUSERSC[1:0] DMA MMU-400 AWUSER[5:4] Shareability domain of DMA writes

CSS AWUSERSC[4:2] Tied to 0b000 Shareability type of DMA writes

Table 2-43 PL354 chip selects and address ranges

Chip select Address range Board peripherals

CS0 0x00_0800_0000 to 0x00_0BFF_FFFF NOR

CS4 0x00_0C00_0000 to 0x00_0FFF_FFFF eMMC

CS5 0x00_1000_0000 to 0x00_13FF_FFFF SMC USB

CS1 0x00_1400_0000 to 0x00_17FF_FFFF PSRAM, only 32MB

CS2 0x00_1800_0000 to 0x00_1BFF_FFFF SMC Ethernet

CS3 0x00_1C00_0000 to 0x00_1EFF_FFFF IOFPGA system peripherals

CS6 Not used -

CS7 Not used -



2.9.6 I2S interface

The ADP includes an I2S interface that supports 4 stereo audio channels for high-quality audio to the external display. The I2S bus only handles audio data, and so the control signaling is handled through a separate I2C bus.

The ADP board includes two DisplayPort connectors for attaching displays. The DisplayPort supports 8-channel audio streams with sampling rates up to 24 bits at 192kHz. This dictates the maximum audio resolution configured on the Juno I2S controller.

Stereo data pairs, left and right, that are written by the CPU using the APB interface are shifted out serially in the appropriate data output, SD0, SD1, SD2, or SD3. The shifting is timed with respect to I2SCLK. WS is the word select line and selects between left and right data.

The clock output from Juno to the slave device has been gated by two signals, SCLK_GATE and SCLK_EN. SCLK_GATE is the clock enable signal that disables the output clock when the controller has been disabled. The SCLK_EN signal is the gating signal when data resolution of the transmit channel is less than the current word select size.

Figure 2-8 shows the I2S integration.

Figure 2-8 I2S integration

The I2S used in the ADP is APB mapped. I2S on page B-11 shows the configuration. The key features are as follows:

• Four stereo transmit channels.

• All the 4 TX channels have been configured with a maximum audio resolution of 24. If required, the TX channels can be reprogrammed during operation to any supported resolution lesser than 24.

• Word select length has been set to 24. This can be reprogrammed during operation to supported values.

• I2SCLK is asynchronous to APB clock.

See I2S configuration options on page B-11.

2.9.7 I2C interface

The ADP includes the following I2C controllers:

1. An I2C that is mapped in the SCP AHB expansion area and exclusively controls the PMIC.

I2S controller

SDO3SDO2SDO1SDO0

WS

SCLK_GATE

APBINTR

I2SCLK

SCLK_ENI2SCLKOUT



2. An I2C that is mapped in the application processor area and performs board functions such as HDMI controller configuration.

3. An I2C that is mapped in the application processor area and exclusively controls trusted user input from a keypad.

The I2C controller used in the ADP is an APB mapped peripheral. Table B-9 on page B-11 shows the IP configuration.

The key features are as follows.

• Two wire, Serial Data Line (SDA) and Serial CLock (SCL).

• IP configured to support the following speed modes:Standard Up to 100Kbps.Fast Up to 400Kbps.High-speed High-speed mode, up to 3.4Mbps, has been disabled.

• Interrupt and polled mode operation supported.

• 7-bit addressing selected.

• The I2C IP can only be operated in either master or slave mode, but not both. For the ADP, all three I2C instances operate in master mode.

• The I2C controller requires that ic_clk is the same frequency or faster then APB interface clock. To guarantee this requirement is always met, in the ADP, the primary input clock, I2CCLK, drives both ic_clk and the APB interface. An asynchronous APB bridge is then added to ensure the APB interface can be operated asynchronously with rest of the system.

Table 2-44 shows the minimum ic_clk values for Standard and Fast modes, with high and low count values for SCL generation. The maximum suppressed spike length registers IC_FS_SPKLEN and IC_HS_SPKLEN are programmed to 1. In the ADP, ic_clk is the same as the APB interface clock that is 100MHz and considerably higher than the minimum ic_clk frequency permitted.

Figure 2-9 on page 2-57 shows the pad connections for the I2C interface. You can use the PBIDIR pad from the 28HPM I/O library for the I2C signals.

ic_clk_oe and ic_data_oe are the I2C clock and data outputs respectively. Both these are open drain signals and require external pull up on the board.

ic_clk_in and ic_data_in are incoming I2C clock and data.

Figure 2-9 on page 2-57 shows the I2C interface pad connections.

Table 2-44 Minimum ic_clk frequency

Speed mode ic_clk (MHz)SCL lowcount

SCL lowprogramvalue

SCL lowtime

SCLhighcount

SCL highprogram value

SCL hightime

SS 2.7 13 12 4.7µs 14 7 5.2µs

FS 12.0 16 15 1.33µs 14 7 1.16µs



Figure 2-9 I2C interface pad connections

2.9.8 UART

The ADP includes UARTs, SOC UART 0, and SOC UART 1, for:• Firmware messages.• Debugging OS kernel.

The UART signals connect to RS232 connectors on the board. Figure 2-10 shows the PL011 integration.

Figure 2-10 UART integration

The key features are as follows.

• The PL011 provides a DMA request interface that in the ADP, is connected to the PL330 system DMA controller PL330.

• IrDA transmit and receive signals are not used.

• UARTCLK is a primary input to the ADP and is asynchronous to APB clock.

Figure 2-10 shows the UART integration.

The UART supports a wide range of baud rates depending on the frequency of the input UARTCLK in addition to the integer, UARTIBRD, and fractional, UARTFBRD, divisor registers in PL011 [].

SCL SDA

ic_clk_in

ic_clk_oe

ic_data_in

ic_data_oe

UART

UARTTXDUARTRXDnUARTCTSnUARTDSRnUARTDCDnUARTDTRnUARTRTS

nUARTRInSIROUTnSIRIN

1'b1

1'b1

To RS-232 connector

UARTRXINTRUARTTXINTR

UARTCLK

APB

DMA interfaceIrDA interface not used



Table 2-45 shows the typical Baud rates and the divisor values, assuming a UARTCLK clock frequency of 7.2738MHz from the crystal. The fractional divisor is not used in this specific case. If a non-friendly UARTCLK frequency is used, there can be slight error in the generated Baud rate compared to required Baud rate.

2.9.9 System override registers unit

System Override Registers Unit is an APB peripheral in the application processor memory map. It contains registers that you can use to override various aspects of the system outside the compute subsystem, such as the security state of peripherals, shareability settings of masters that do not support ACE-Lite signalling and so on. The base address of the peripheral is 0x7FFF_0000.

Table 2-46 shows the summary of the System Override Registers. It is a secure access only peripheral. If a Non-secure access attempts to access any of these registers, the interconnect responds with a DECERR response. Any Secure access to unimplemented areas within the 4K region is RAZ, WI. The block also includes the following general purpose registers for software use:• GPR_0.• GPR_1.

System Override Registers Overview

Table 2-46 shows an overview of the System Override Registers.

Table 2-45 Baud rates

Integer divisor Baud rate

0x1 460800

0x2 230400

0x4 115200

0x6 76800

0x8 57600

0xC 38400

0x18 19200

0x20 14400

0x30 9600

Table 2-46 System Override Registers summary

Register name Type Reset value Offset Comments

SEC_HDLCD RW 0x0 0x000 HDLCD Controller security state

GPR_0 RW 0x0 0x004 General purpose register 0

GPR_1 RW 0x0 0x008 General purpose register 1

PID4 RO 0x04 0xFD0 Peripheral ID 4

PID0 RO 0xAB 0xFE0 Peripheral ID 0

PID1 RO 0xB0 0xFE4 Peripheral ID 1



SEC_HDLCD Register

Table 2-47 shows the bit assignments.

GPR_0 Register


GPR_1 Register


2.9.10 System configuration controller

This section contains the following subsections:• About the System Configuration Controller (SCC) on page 2-60.• Design information on page 2-60.

PID2 RO 0x0B 0xFE8 Peripheral ID 2

PID3 RO 0x00 0xFEC Peripheral ID 3

COMPID0 RO 0x0D 0xFF0 Component ID 0

COMPID1 RO 0xF0 0xFF4 Component ID 1

COMPID2 RO 0x05 0xFF8 Component ID 2

COMPID2 RO 0xB1 0xFFC Component ID 3

Table 2-46 System Override Registers summary (continued)

Register name Type Reset value Offset Comments

Table 2-47 SEC_HDLCD Register

0x000 Internal signal name Default Type Description

[31:2] - - - Reserved.

[1] HDLCD1_SEC 0x0 RW Selects the security state of the HDLCD controller 1:0 Secure.1 Non-secure.

[0] HDLCD0_SEC 0x0 RW Selects the security state of the HDLCD controller 0:0 Secure.1 Non-secure.

Table 2-48 GPR_0 Register


[31:0] GPR_0 0x0 RW General Purpose Register 0

Table 2-49 GPR_1 Register


[31:0] GPR_1 0x0 RW General Purpose Register 1



• APB interface.

About the System Configuration Controller (SCC)

The System Configuration Controller (SCC) is an APB peripheral that configures the SoC. The SCC registers are memory-mapped on the CSS System Controller Processor (SCP) expansion bus, and are secure by definition.

Because the ADP is a development platform, the SCC also provides a low pin count serial interface so that, if necessary, an off-chip SCC can program the registers during silicon bring up. This interface also controls the PLLs while running manufacturing test patterns on the tester.

When programmed, the configuration data can be read back from the device and checked.

Design information

SCC has an APB interface that enables the SCP firmware to read or modify SoC configuration settings. The SCC is provided with a 4KB APB address space. Address 0xE00 is reserved for APB control clear. Addresses 0xFD0 to 0xFFC are reserved for the peripheral and component ID. All other address locations can be used for configuration data.

To support the serial interface mode, the design also includes of a very simple serial shift-in register for loading new configuration data and a serial shift-out register, in addition to the bank of Configuration registers.

APB interface

All SCC registers can be programmed by the CSS System Control Processor (SCP) through the SCP expansion bus.

The SCC APB interface is at base address 0xFFFF_F000, with Configuration and ID registers available at the same offset as the serial interface.

After reset, the default values, or those loaded from the serial configuration, control the configuration into the chip.

Post reset software can freely read and write to the configuration registers, however when a register is written to, all 32 bits of that register become under software control, and the serially loaded values are no longer used.

You must therefore take care when writing to these registers.

If required, it is also possible to revert back to the serially loaded values. This is achieved by writing the magic number {0xA50F5, base_offset[11:0]} to SCC address offset 0xE00. This reverts the control of the register at base_offset[11:0] to the serial interface.

It is expected that the new configuration data is written using the serial configuration interface or is known prior to a reversion being requested.



2.10 Interconnect and memory systemThis section describes the interconnect and memory system components:• CoreLink CCI-400 Cache Coherent Interconnect.• CoreLink NIC-400 Network Interconnect.• CoreLink MMU-401 and MMU-400 System Memory Management (SMMU) components.• CoreLink DMC-400 Dynamic Memory Controller on page 2-62.• CoreLink TZC-400 TrustZone Address Space Controller on page 2-62.

2.10.1 CoreLink CCI-400 Cache Coherent Interconnect

The CoreLink CCI-400 Cache Coherent Interconnect provides:• Full cache coherency between the application processors.• IO coherency with the Mali-T624 GPU.• IO coherency for PCIe.

The CCI-400 also supports Distributed Virtual Memory (DVM) messaging for managing caches and Translation Lookaside Buffers (TLBs) in ACE-Lite components.

Note • DVM messages do not maintain the MMU-401 for the ETR.

• DVM messages sent from the Cortex-A57 and Cortex-A53 processors are DVMv8 and are not required to maintain MMU-400 or MMU-401 because these are DVMv7 components. Therefore, you must use the registers for each component to maintain the system MMUs.

The Mali-T624 GPU connects to a single CCI-400 ACE-Lite slave port.

See the ARM® CoreLink™ CCI-400 Cache Coherent Interconnect Technical Reference Manual.

2.10.2 CoreLink NIC-400 Network Interconnect

CoreLink NIC-400 Network Interconnect components connects other system components into the CCI-400. For example, NIC-400s connect master components into CCI-400 slave ports, and slave components to CCI-400 master ports.

See:• Figure 1-1 on page 1-4.• ARM® CoreLink™ NIC-400 Network Interconnect Technical Reference Manual.

2.10.3 CoreLink MMU-401 and MMU-400 System Memory Management (SMMU) components

The ADP includes system Memory Management Units (MMUs) to support system virtualization, where guest Operating Systems (OSs) are running on a hypervisor and are only aware of Intermediate Physical Address (IPA). The system MMU components handle stage 2 address translations, that is IPA to Physical Address (PA), enables this.

CoreLink MMU-401 components are placed in-front of the following:• IO coherent PCI Express Root Port.• CoreLink CCI-400.• SCP switch in the NIC-400.• TLX-400 slave port.• DMA controller, PL330.



• Two HDLCD controllers.• USB host controller.

A CoreLink MMU-400 is located between the Mali-T624 GPU and the CCI-400.

Virtual memory maintenance does not use Distributed Virtual Memory (DVM) transactions. Instead, in the ADP, the translation tables are maintained in software by writing to the APB4 programming interface of the MMU blocks.

DMA virtualization information:

• The DMA-300 is configured to have one manager thread and eight channel threads. The DMA outputs the channel information using the AXI ARID[3:0] and AWID[3:0] signals. An AxID value of 0x0 corresponds to channel 0, an AxID value of 0x1 corresponds to channel 1, and so on, until the AxID value of 0x7 correspond to channel 7. Transactions belonging to the manager thread have an AxID value of 0x8.

• The DMA MMU-401 includes a Security State Determination (SSD) table containing nine entries. The SSD table indexing is performed using AxID[3:0]. An AxID value of 0 corresponds to SSD entry 0, an AxID value of 1 corresponds to SSD entry 1, and so on, until the AxID value of 8 correspond to SSD entry 8.

• The DMA MMU-401 is configured to support four contexts. The AxID of incoming transaction is compared with the eight stream matching registers to map to one of the four contexts.

CoreLink MMU-40x System Memory Management Unit components on page B-6 shows the MMU-40x configuration options.

See the following:



2.10.4 CoreLink DMC-400 Dynamic Memory Controller

The CoreLink DMC-400 Dynamic Memory Controller connects the ADP memory system to the DDR3 PHY that provides access to the SDRAMs.

See the ARM® CoreLink™ DMC-400 Dynamic Memory Controller Technical Reference Manual.

2.10.5 CoreLink TZC-400 TrustZone Address Space Controller

The TZC-400 is located in-front of the DMC-400. The TZC-400 enables the Trusted OS to define multiple regions within the SDRAM memory that have different security access permissions. See ADP device security model on page 2-64 for information about this component.

2.10.6 Virtual networks

Some components in the ADP use the QVN protocol extensions to AMBA to provide virtual networks. The use of virtual networks improves performance in systems where multiple masters are all accessing a shared DMC-400 Memory Controller. It helps to manage CPU latencies when other masters in the system, such as a GPU or DMA, saturate the memory controller, that can prevent the flow of latency-critical transactions. This section describes:• Virtual networks for fully coherent and IO coherent masters on page 2-63.



• Virtual networks for non-coherent masters.• Token pre-allocation.

Virtual networks for fully coherent and IO coherent masters

Table 2-50 shows the assignment of different traffic types for traffic from masters on the coherent interconnect path to the DMC-400. This path consists of the fully-coherent processor clusters and IO coherent masters such as GPU, PCIe, DMA, TLX-400 and USB.

Virtual networks for non-coherent masters

Table 2-51 shows the assignment of different traffic types on the non-coherent path direct to the DMC-400 Dynamic Memory Controller.

Token pre-allocation

Virtual networks can be configured with pre-allocated tokens to reduce the latency of the transactions they carry. The VN0-C virtual network is configured with token pre-allocation. All other virtual networks are configured without token pre-allocation.

Table 2-50 Virtual network assignment through coherent interconnect

Virtual network Policy

VN0-C Processor cluster traffic, low latency traffic

VN1-C GPU traffic, saturating high bandwidth traffic

VN2-C DMA, USB and TLX-400 best effort traffic

VN3-C PCI Express

Table 2-51 Virtual network assignment through non-coherent interconnect

Virtual network Policy

VN0-NC HDLCD-0 and HDLCD-1 masters, both real-time traffic

VN1-NC Unused

VN2-NC Unused

VN3-NC Unused



2.11 SecurityThis section describes:• About security.• Trusted Base System Architecture (TBSA) compliance.• ADP device security model.• Trusted entropy source on page 2-70.• Trusted root-key storage on page 2-72.• Trusted non-volatile counters on page 2-73.• Trusted HDLCD controller on page 2-73.

2.11.1 About security

The section describes the support that the ADP platform provides for the Secure platform that Level 1 of the Trusted Base System Architecture CLIENT1 Platform Design Document (PDD) defines.

2.11.2 Trusted Base System Architecture (TBSA) compliance

Although the ADP intends to comply with TBSA v1, there are some differences to keep the platform design simple and to support more use cases.

• The HDLCD controller does not support issuing secure accesses. It is modified to support secure accesses by driving the AxPROT[1] bits from secure memory mapped registers.

• Trusted root key storage requires fuses. The ADP implements key storage using registers with the key values tied-off in hardware.

• Trusted non-volatile counters are expected to be implemented using fuses. This is implemented using registers:— A 31 state counter is hardwired with a value of 31.— A 223 state counter is hardwired with a value of 223.— A Secure storage counter is supported off-chip through the secure Inter-Integrated

Circuit (I2C) interface.

• The ADP instantiates the following ROMs:— Secure SCP.— Secure AP.— Non-secure AP.Because the ADP is a development chip, it includes a mechanism to bypass the boot ROMs, and fetch the code directly from the external NOR flash memory. This alternative boot is enabled by loading special values in the alternate boot registers in the SCC. See System Configuration Controller (SCC) registers on page 3-47.

2.11.3 ADP device security model

The following subsections provide additional information to that in the TBSA, and focuses on key devices, modules, and interfaces in the system that contribute to security:• Application processor security on page 2-65.• CoreLink GIC-400 Generic Interrupt Controller security on page 2-65.• Interconnect security on page 2-66.• CoreLink TZC-400 security on page 2-66.• SCP security on page 2-67.



• Debug, trace, and profiling security on page 2-68.• Power down and Secure control register states on page 2-69.• Trusted on-chip boot ROM on page 2-69.• Trusted on-chip SRAM on page 2-69.• DDR memory controller and DFI interfaces on page 2-69.• Watchdog security on page 2-70.

Application processor security

The application processors in the ADP support the ARMv8 architecture including the Security Extensions.

Note The CP15SDISABLE input signals to the Cortex-A57 and Cortex-A53 clusters are tied LOW.

See the following:• ARM® Cortex®-A57 MPCore Technical Reference Manual.• ARM® Cortex®-A53 MPCore Technical Reference Manual.

CoreLink GIC-400 Generic Interrupt Controller security

A CoreLink GIC-400 Generic Interrupt Controller that implements the GICv2 architecture is present, and all application processors in the ADP share it. The GIC-400 supports security extensions.

This enables the GIC-400 to support the following:

• Banking of key registers to provide the following views:— Trusted world view.— Non-trusted world view.

• Configuring each interrupt as either:— Secure, trusted world.— Non-secure, non-trusted world.

• Signaling Secure interrupts to the target processor using either the IRQ or the FIQ exception request.

• A unified scheme for handling the priority of Secure and Non-secure interrupts.

• Optional lockdown of the configuration of some Secure interrupts.

The CoreLink GIC-400 supports 16 Software Generated Interrupts (SGIs). You can program these to implement the following concurrently:• Eight Non-secure software-generated interrupts.• Eight Secure software-generated interrupts.

See the ARM® Generic Interrupt Controller Architecture Specification, Architecture version 2.0.



Interconnect security

The CCI-400 and the NIC-400 support the transfer of the Non-secure (NS) flag on the ARPROT[1] and AWPROT[1] signals from all slave interfaces to master interfaces. These define the security setting of an access:

AWPROT[1] Specifies whether a write transaction is trusted or non trusted:0 Trusted if set to 0.1 Non-trusted if set to 1.

ARPROT[1] Specifies whether a read transaction is trusted or non trusted:0 Trusted if set to 0.1 Non-trusted if set to 1.

For more information about ARPROT and AWPROT, see the AMBA® AXI and ACE Protocol Specification - AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite.

Within the ADP, peripherals are placed into Secure or Non-secure world either by:

• The peripheral itself, interpreting the NS flag.

• The NIC-400. Either permanently as Secure or Non-secure, or software-configurable using the programmers model registers of the NIC-400. For information on how the peripherals are security-mapped, see:— Application processor memory map on page 3-13.— System Control Processor (SCP) memory map on page 3-29.

The NIC-400 registers that affect security are Secure access only.

For more information about the CCI-400 and NIC-400 registers, see:• The CoreLink™ CCI-400 Cache Coherent Interconnect Technical Reference Manual.• SoC peripherals NIC-400 Registers on page 3-154.• Compute subsystem NIC-400 Registers on page 3-168.• The CoreLink™ NIC-400 Network Interconnect Technical Reference Manual.

CoreLink TZC-400 security

In the ADP, the TZC-400 is located between the CoreLink CCI-400 Cache Coherent Interconnect, and the CoreLink DMC-400 Dynamic Memory Controller. The TZC-400 enables the Trusted OS to define multiple regions within the DDR memory that has different security access permissions. The TZC-400 in the ADP is configured as follows:

• Four filter units, one for each ACE-Lite interface of the DMC-400. These filter units share the same region configurations.

• Nine regions, that include one base region, region 0, and eight fully software-configurable regions, regions 1-8. These enable you to define up to eight independent regions with different security requirements.

• The ADP supports 13 Non-Secure Access ID (NSAID) values, including the default ID, and this enables up to 12 masters, or groups of masters, to be uniquely identified so that they can be given different Non-secure access permissions. NSAID values are mapped as follows:0 Default ID that any masters use that are not necessary to be

identified separately from the rest, including CCI-400. This value is used by default.



Note The CCI-400 does not store the NSAID values of cache lines that it

temporarily stores. As a result, if the CCI-400 performs line write backs, it does not reinstate the NSAID values of the original accesses. Therefore, you must not set Non-secure memory areas that are protected by NSAID as sharable. Otherwise, this can result in security violations.

1 PCIe.2 HDLCD0.3 HDLCD1.4 USB.5 DMA.6 Thin Links.7-8 Reserved. Do not use.9 Application processors.10 Mali-T624 GPU.11 SCP.12 All CoreSight accesses.13-15 Reserved. Do not use.

Note When programming the TZC-400 regions, ensure that all regions are 64KB-aligned, and that each region has a size that is at least 64KB, or a multiple of 64KB, to comply with the TBSA. See the Trusted Base System Architecture PDD.

For more information about the TZC-400, see the ARM® CoreLink™ TZC-400 TrustZone® Address Space Controller Technical Reference Manual.

SCP security

See System Control Processor (SCP) on page 2-43.

Because the SCP subsystem has access to clock, resets, power, and peripheral register states, it is essential that malware does not compromise the subsystem. Therefore, the subsystem, including its internal RAM and ROM memories, is treated as inherently trusted and this means that:

• The SCP boots from its private on-chip trusted SCP ROM so that the boot code cannot be modified.

• The main SCP firmware is initially placed in an external device, for example, flash, and the application processor must authenticate it before it is copied to the SCP on-chip trusted RAM. To facilitate this, the application processor must be able to start up before the main firmware for the SCP is available.

• Any access from the SCP subsystem to the rest of the system is trusted.

• Any Secure data that it stores, for example, data related to Secure state save and restore operations, must be stored in its own internal private SRAM that is not accessible from outside the subsystem, or in areas that are Secure access only, for example, the trusted on-chip SRAM.



Note All SCP software must be considered to be equal or higher security than the trusted boot code or trusted OS code.

Debug, trace, and profiling security

The ADP debug solution also integrates TrustZone technology based security, above the basic protection provided using global external debug enable, DEVICEEN.

Table 2-52 shows the additional debug access controls that are added to selectively enable or disable debug access in each mode. Invasive debug generally refers to the use of JTAG debug access, and non-invasive debug generally refers to the use of the trace functionality.

The SSC_AUXDBGCFG Register on page 3-39 controls the DBGEN and NIDEN inputs to the application processors.

All application processors, and the CoreSight subsystem, in the ADP implement DBGEN, NIDEN, SPIDEN, and SPNIDEN input signals. SUIDEN and SUNIDEN are implemented as Secure privileged access only software-programmable bits in the application processor system registers.

Software can configure the SPIDEN and SPNIDEN signals of all application processors, and the CoreSight subsystem in the ADP. These configuration registers and internal source registers are accessible using the following registers:• SSC_DBGCFG_STAT Register on page 3-36.• SSC_DBGCFG_SET Register on page 3-37.• SSC_DBGCFG_CLR Register on page 3-38.

See ADP System Security Control Registers on page 3-34.

In the SCP, the Cortex-M3 processor and its associated debug logic does not directly support TrustZone. It only implements the DBGEN and NIDEN inputs. However, the SCP is inherently a trusted subsystem, and therefore, the DBGEN and NIDEN inputs are driven as follows:• SPIDEN drives DBGEN in the SCP.• SPNIDEN drives NIDEN in the SCP.

This section describes:• CoreSight DAP to system access.• Embedded trace router on page 2-69.

CoreSight DAP to system access

The ADP CoreSight subsystem provides an interface so that the debugger has direct access to the application memory map using an independent AXI interface from the CoreSight Debug Access Port (DAP). Registers in the AXI Memory Access Port, AXI_AP, in the DAP, that the debugger can access, define the security level of accesses through this interface. For more information about the AXI_AP, see the AXI Memory Access Port AXI-AP Technical Reference Manual.

Table 2-52 Secure debug access controls

Debug access controls Invasive Non-invasive

Privileged SPIDEN SPNIDEN

User SUIDEN SUNIDEN



Embedded trace router

The ADP CoreSight subsystem includes an Embedded Trace Router (ETR) that is a configuration of the Trace Memory Controller (TMC). The ETR enables trace data to be routed into system memory. The ETR implements an AXI master interface that supports Secure memory access. However, any attempt to perform a Secure memory access when SPIDEN is LOW results in an immediate error response and no transactions are issued on the AXI interface. For more information about TMC, see the ARM® CoreSight™ Trace Memory Controller Technical Reference Manual.

Power down and Secure control register states

The Power Down Status and Secure Control Registers are on the VAON power region and are powered all the time. This is so that their states are maintained even through the deep power saving states where the VSYS voltage domain is switched off. These registers control the security of important interfaces and devices, and store important state information prior to powering down this region.

The only time these states are lost is during the complete power down of the entire ADP where VSYS voltage supply is removed, the OFF power state. All these registers are Secure access only. See ADP System Security Control Registers on page 3-34.

Trusted on-chip boot ROM

The following Secure access only on-die boot ROMs are implemented in the ADP:• Trusted boot ROM for application processor boot code.• Trusted boot ROM for the SCP.

Trusted boot ROM for application processor boot code

The trusted boot ROM for application processor boot code is permanently mapped to address 0x00_0000_0000, the reset vector for the application processors, and is on-chip.

Trusted boot ROM for the SCP

The trusted boot ROM for the SCP is mapped to address 0x0000_0000 in the SCP memory map. This is on-chip.

Trusted on-chip SRAM

Application processor trusted software can use a Secure access only on-die RAM area. The NIC-400 is configured to make this SRAM Secure access only.

DDR memory controller and DFI interfaces

The DDR Memory Controller, DMC-400, and the DDR PHY interface attached to the ADP do not directly support TrustZone technology based security. However, the configuration register spaces for the DMC-400 are mapped in the NIC-400 as software-configurable Secure access and defaults at reset to Secure.

In the case of the DDR PHY interfaces, the integrator adding PHY solutions must ensure that the configuration interface of the PHY is mapped as either Secure access only, or as software-configurable Secure access, and defaulting at reset to Secure. This protects against software attacks targeting important configuration registers, for example, timing or DDR type registers, and chip select address mappings.



Watchdog security

The ADP provides two secure watchdog timers and these provide the ability to force an automatic hardware reset of the whole system when they time-out. The watchdog timers are:

• The watchdog timer in the SCP subsystem. Because it is in the SCP subsystem, only Secure software can access it.

• The trusted watchdog in the application processor system.

Both watchdogs are accessible by Secure accesses only. These watchdogs also support halt on debug functionality, enabling cross triggers to halt the watchdog. Halt on debug must be enabled using the SSC_SWDHOD Register on page 3-40 using Secure accesses only.

Note A Generic Watchdog also exists in the application processor system, that both Secure and Non-Secure software can access. This watchdog cannot cause an automatic hardware reset.

See:• SSC_SWDHOD Register on page 3-40.• Watchdog timers on page 2-81.• Cross triggers on page 2-87.• Trusted entropy source.• Trusted root-key storage on page 2-72.• Trusted non-volatile counters on page 2-73.• Trusted HDLCD controller on page 2-73.

2.11.4 Trusted entropy source

The ADP includes a Trusted Entropy Source based on a design from ARM Research and Development. The Trusted Entropy Source generates one 128-bit random number at a time. Software then generates 512 different random numbers based on that seed.

See Trusted Entropy Source Registers on page 3-239.

Flow diagrams

The flow diagrams below provide a general idea on how the RNG peripheral would be programmed and used to generate the 128-bit random number value.

Configuration for interrupt-based

Figure 2-11 on page 2-71 shows the configuration flow chart.



Figure 2-11 Configuration flow chart

Interrupt Service Routine (ISR)

Figure 2-12 shows the Interrupt Service Routine (ISR) flow chart.

Figure 2-12 ISR flow chart

Start configuration

End configuration

Read and verify contents for Comp ID and Periph ID Registers

Match? No

Yes

Clear out interrupts by writing to the STATUS Register

Program the Enable Pulse width in the Osc_Time Register

Configure the ‘ready’ interrupt mask by writing to the INTMASK Register

Enable the RNG peripheral by writing to the CONTROL Register

Report error and end process

Start ISR

End ISR

Read the STATUS Register to verify that the ‘ready’ bit is asserted

Ready=1? No

Yes

Read the value from the OUTPUT Registers, two 32-bit registers

Acknowledge the ‘ready’ interrupt by writing to the STATUS Register

Error: Interrupt without ‘ready’ asserted

Report the error to the application processor



2.11.5 Trusted root-key storage

The Trusted Root-Key Storage is implemented as an APB mapped register bank with the programmers view that Table 2-53 shows. The secure platform certification process requires the reset value of these registers to be always be the same, and this requires the values to be hardcoded.

If a Non-secure access attempts to access any of the registers in these registers, the interconnect responds with a DECERR. Any secure access to unimplemented areas within the 4K region is RAZ, WI.

Table 2-53 Trusted root-key storage registers

Offset R/W Reset value Name Description

0x00 R 0xB2043562 TZ_PUB_KEY_HASH_0 Lowest 32 bits [31:0] of 256-bit Trust Public Key (ROTPK)

0x04 R 0x1B702EFD TZ_PUB_KEY_HASH_1 Intermediate bits of 256-bit ROTPK

0x08 R 0x930AEA03 TZ_PUB_KEY_HASH_2 -

0x0C R 0x648C4055 TZ_PUB_KEY_HASH_3 -

0x10 R 0x4365DFF1 TZ_PUB_KEY_HASH_4 -

0x14 R 0x0D6EEB27 TZ_PUB_KEY_HASH_5 -

0x18 R 0xE43AEDCB TZ_PUB_KEY_HASH_6 -

0x1C R 0xED61412A TZ_PUB_KEY_HASH_7 Highest 32 bits [255:224] of 256-bit ROTPK

0x20 R 0xFC1C5C16 HU_KEY_0 Lowest 32 bits [31:0] of 128-bit Hardware Unique Key (HUK)

0x24 R 0x0D34E9D0 HU_KEY_1 Intermediate bits of 128-bit HUK

0x28 R 0xA573A314 HU_KEY_2 -

0x2C R 0x666E5E53 HU_KEY_3 Highest 32-bits [127:96] of 128-bit HUK

0x44 R 0x57AA4A40 END_KEY_0 Lowest 32 bits [31:0] of 256-bit Private Endorsement Key (PEK)

0x48 R 0x2E0E0993 END_KEY_1 Intermediate bits of 256-bit PEK

0x4C R 0x8606B765 END_KEY_2 -

0x50 R 0x08F0220F END_KEY_3 -

0x54 R 0x28C80B76 END_KEY_4 -

0x58 R 0x58E55816 END_KEY_5 -

0x5C R 0x2CF04CC5 END_KEY_6 -

0x60 R 0xE7D5DDE1 END_KEY_7 Highest 32 bits [255:224] of 256-bit PEK

0xFD0 RO 0x04 PID4 Peripheral ID 4

0xFE0 RO 0xA8 PID0 Peripheral ID 0

0xFE4 RO 0xB0 PID1 Peripheral ID 1

0xFE8 RO 0x0B PID2 Peripheral ID 2

0xFEC RO 0x00 PID3 Peripheral ID 3

0xFF0 RO 0x0D COMPID0 Component ID 0



2.11.6 Trusted non-volatile counters

The trusted non-volatile counters are implemented as an APB-mapped register bank with the programmers view that Table 2-54 shows. The secure platform certification process requires the reset value of these registers to be always be the same, and this requires the values to be hardcoded.

If a Non-secure access attempts to access any of the registers in these registers, the interconnect respond with a DECERR. Any secure access to unimplemented areas within the 4K region are RAZ, WI.

2.11.7 Trusted HDLCD controller

The HDLCD controller must be able to display trusted frame data. This means that the controller must read trusted frame buffer using secure access.

The ARM HDLCD controller does not support security. In the ADP, the security state of the HDLCD controller is determined by the SSD table present in the MMU-401. The security state of HDLCD Controller can transition between Secure and Non-secure under the control of Secure software. If the SSD table entry is marked as Secure, then the Non-secure transactions from the HDLCD controller arriving at the MMU-401 are converted to Secure transactions before being sent to the memory.

0xFF4 RO 0xF0 COMPID1 Component ID 1

0xFF8 RO 0x05 COMPID2 Component ID 2

0xFFC RO 0xB1 COMPID3 Component ID 3

Table 2-53 Trusted root-key storage registers (continued)

Offset R/W Reset value Name Description

Table 2-54 Trusted non-volatile counters

Offset R/W Reset value Register name Description

0x00 R 0x1F TZ_FW_CNT Trusted Firmware Updates Counter, as required by R39.a from TBSA v1, tied to 31

0x04 R 0xDF NON_TZ_FW_CNT Non-trusted Firmware Updates Counter, as required by R74.b from TBSA v2, tied to 223

0xFD0 RO 0x04 PID4 Peripheral ID 4

0xFE0 RO 0xA9 PID0 Peripheral ID 0

0xFE4 RO 0xB0 PID1 Peripheral ID 1

0xFE8 RO 0x0B PID2 Peripheral ID 2

0xFEC RO 0x00 PID3 Peripheral ID 3

0xFF0 RO 0x0D COMPID0 Component ID 0

0xFF4 RO 0xF0 COMPID1 Component ID 1

0xFF8 RO 0x05 COMPID2 Component ID 2

0xFFC RO 0xB1 COMPID3 Component ID 3



The ADP also permits the HDLCD transactions to be marked as Secure by writing to the SEC_HDLCD register in the System Override Registers Unit. This forces all HDLCD transactions to be Secure. That is, ARPROT[1] = 0, independent of the MMU-401 settings. Figure 2-13 shows this scheme.

The APB interfaces of the HDLCD controllers have programmable security settings on the interconnect. The default state is Secure access only but you can update it by programming the interconnect.

By using this scheme, the Trusted Base System Architecture Platform Design Document recommends the following:

• Ensure that the security settings in the MMU-401 SSD table and APB configuration interface of the HDLCD controller are switched at the same time when the display is inactive.

• The mode should not be switched while there are valid AXI transactions on the bus.

• When the HDLCD controller is configured to be Secure, it must point to trusted frame buffer in trusted memory.

• When switching from Secure to Non-secure, any pixel data in the display must be wiped if it is accessible.

Figure 2-13 shows the trusted display controller.

Figure 2-13 Trusted display controller

System NIC-400

SEC_HDLCD Register

AXI slave

AXI master

HDLCD controller

APB

AXI master

AWPROT[1]

To display

MMU-401

SSD



2.12 TimersThis section describes:• Time domains.• Counter and timer components on page 2-78.• Processor power modes on page 2-80.• Watchdog timers on page 2-81.

2.12.1 Time domains

The ADP contains the following separate time domains:

REFCLK time View of time that the application processors observe. Low-power modes can affect this time domain.

32kHz time Additional view of time that is private to the SCP subsystem. It is always on, and always running.

CoreSight timestamp time View of time used exclusively for the generation of CoreSight timestamps.

This section describes:• REFCLK time domain.• 32kHz time domain on page 2-76.• CoreSight timestamp time domain on page 2-76.• Time domain relationship on page 2-76.• Restoring the REFCLK time domain on page 2-77.• Restoring the CoreSight timestamp time domain on page 2-78.

REFCLK time domain

The application processors operate in a time domain called REFCLK time. This time domain is based on the main reference clock, SYS_REF_CLK and is also visible to the SCP.

A Generic Counter component, called the REFCLK counter, generates a time value for the REFCLK time domain. The component meets the requirements of the memory-mapped counter module that the ARM v7AR Architecture Reference Manual describes. It is in the VSYS.AON power domain.

You can halt the REFCLK time domain during debug.

The REFCLK time domain contains the following timers:

Generic Timer All application processors in the ADP implement the ARM Generic Timer. Interrupts from these timers are mapped to Private Peripheral Interrupts (PPIs) in the CoreLink GIC-400 Generic Interrupt Controller. Accesses to these Generic Timers are through a low-latency system-mapped registers.

SCP REFCLK Generic Timer The SCP subsystem contains a memory-mapped Generic Timer. For more information, see SCP REFCLK Generic Timer on page 2-79.

Additional REFCLK Generic Timers Two additional REFCLK Generic Timers, one Secure and one Non-secure that the applications processors can use.



REFCLK also drives the Mali-T624 global timestamp counter.

When all components that can observe the REFCLK time domain are in OFF or MEM_RET power modes, the SCP can disable the REFCLK clock to make the REFCLK time domain unavailable.

After restoring REFCLK, and before putting a component that can observe the REFCLK time domain into the ON power mode, the SCP firmware must ensure a consistent time value is set in the REFCLK counter before putting the system into a state in which a component could observe REFCLK time. When restoring the REFCLK counter, the firmware uses the 32kHz time domain as a reference.

See:• CoreSight timestamp time domain.• The Cortex®-A57 MPCore Technical Reference Manual.• The Cortex®-A53 MPCore Technical Reference Manual.• The ARM® Architecture Reference Manual v7AR Edition.

32kHz time domain

The SCP subsystem has a private time domain called 32kHz time. This time domain is based on the 32768Hz real time clock.

A Generic Counter, called the 32kHz counter, generates a time value for the 32kHz time domain. The counter implements the memory-mapped counter module that the ARM v7AR Architecture Reference Manual describes.

The counter is in the VAON power region and is clocked by the S32K_CLK input clock to the SoC. This time domain can be halted during debug. The 32kHz time domain contains a single timer, 32kHz Generic Timer on page 2-80.

CoreSight timestamp time domain

An additional time domain exists that exclusively generates CoreSight timestamps. This time domain is also based on the main reference clock REFCLK, but differs from the REFCLK time domain because it cannot be halted during debug. The SCP can save and restore the value of this counter in the same way that it does for the REFCLK time domain. See CoreSight timestamps on page 2-92.

Time domain relationship

The following equation describes the relationship between the S32K_CLK time domain and the other two time domains. The current REFCLK time, or CoreSight timestamp time, can be calculated from the combination of:• The current 32kHz time.• The ratio between the frequency of 32kHz and the SYS_REF_CLK input clock.• Known time values of the 32kHz counter and the REFCLK, or CoreSight timestamp

counters, at a single point.

tREF = ([fREF ÷ f32K] × [t32K - T32K]) + TREF

Where:

tREF Is the current time value in the REFCLK time domain, or CoreSight timestamp time domain.

t32K Is the current time value in the 32kHz time domain.



TREF Is a time value in the REFCLK time domain, or CoreSight timestamp time domain, at a synchronization point in the past.

T32K Is a time value in the 32kHz time domain at a synchronization point in the past.

fREF Is the frequency of REFCLK, in Hertz.

f32K Is 32768 Hertz.

This relationship enables the REFCLK time and the CoreSight timestamp time to be both linearly scaled and offset from 32kHz time. The scaling factor is constant. The offsets, TREF and T32K, must be recalculated at each power down so that all application software updates are preserved. Figure 2-14 shows the time domain relationship.

Figure 2-14 Time domain relationship

Restoring the REFCLK time domain

As part of any power control sequence that transitions to a power mode in which the REFCLK time domain can be observed, and after REFCLK has been disabled, the SCP firmware must calculate the current REFCLK time from the current 32kHz time and update the value of the REFCLK counter.

During a power control sequence that restores the REFCLK time domain, the SCP firmware must calculate the new REFCLK domain time using the current 32kHz domain time and update the value of the REFCLK counter.

Note For maximum accuracy, time this update to a 32kHz clock edge.

See:• Time domain relationship on page 2-76.• REFCLK counter on page 2-78.

TREF

T32K

TREF t32K – T32K

Time

t32KTREF

(fREF / f32K)(t32K - T32K)



Restoring the CoreSight timestamp time domain

The CoreSight timestamp time domain can be restored in the same way as the REFCLK time domain that Restoring the REFCLK time domain on page 2-77 describes.

2.12.2 Counter and timer components

This section describes:• REFCLK counter.• 32kHz counter on page 2-79.• CoreSight timestamp counter on page 2-79.• SCP REFCLK Generic Timer on page 2-79.• AP_REFCLK Generic Timer on page 2-80.• 32kHz Generic Timer on page 2-80.• Memory map frames on page 2-80.

REFCLK counter

The REFCLK counter is an implementation of the memory-mapped counter module that the ARM v7AR Architecture Reference Manual defines. The counter is visible in both the application processor and SCP memory maps, labeled REFCLK CNTControl and REFCLK CNTRead in the application processor memory map. The counter is implemented in the VAON power region.

This counter has the following single frequency mode:

Mode 0 REFCLK frequency mode.

The frequency mode table entry for the REFCLK frequency mode is writeable. It is intended that firmware initializes this entry during the boot sequence.

See:• Table 3-6 on page 3-24.• REFCLK CNTControl on page 3-151.

This counter contains additional registers in the CNTControl frame to facilitate accurate restoration of the REFCLK time domain using the equation in Time domain relationship on page 2-76. The ARM v7AR Architecture Reference Manual does not define these. REFCLK CNTControl on page 3-151 defines these additional registers.

The synchronized count value registers, CNTControl Synchronized Counter Value Register, CNTSVU on page 3-153 and CNTControl Synchronized Counter Value Register, CNTSVL on page 3-152, contain the counter value sampled at rising edges of S32K_CLK. The value of TREF can be read from this register before REFCLK is removed.

CNTControl Counter Synchronization Control Register, CNTSCR on page 3-152 contains a single bit, ENSYNC, that is asserted to synchronize the counter enable bit, CNTCR.EN, to the rising edges of S32K_CLK.

The counter value can only be written when the counter is disabled, CNTCR.EN is cleared. When REFCLK is restored and stable, the counter is in its disabled state. CNTSCR.ENSYNC is set before the calculated value of tREF is written to the counter value register, CNTCV. When the counter is enabled, CNTCR.EN, the loading of the new counter value is delayed until the next rising edge of S32K_CLK and so accurately restoring REFCLK time.

This counter can be halted during debug using the cross trigger network.



See:• Time domain relationship on page 2-76.• Cross triggers on page 2-87.• REFCLK CNTControl on page 3-151.• The ARM® Architecture Reference Manual, ARMv7A and ARMv7R Edition:

— Section E.2 Memory-mapped counter module.— Section E.3 Counter module control and status register summary.

32kHz counter

The 32kHz counter is an implementation of the memory-mapped counter module that the ARM® Architecture Reference Manual defines. The counter is only visible in the SCP memory map, labeled 32K CNTControl in the SCP memory map. The CNTRead counter frame defined by the counter architecture is not made available for this counter. See Table 3-7 on page 3-32.

This counter has the following single frequency mode:

Mode 0 32kHz frequency mode.

When enabled, this counter increments at 32kHz.

The frequency mode table entry for the 32kHz frequency mode is writeable, but must always be programmed to 32768. This entry is intended to be initialized by firmware during the boot sequence.

This counter can be halted during debug using the cross trigger network.

See:

• Cross triggers on page 2-87.

• The ARM® Architecture Reference Manual, ARMv7A and ARMv7R Edition, Section D.2 Memory-mapped counter module.

• The ARM® Architecture Reference Manual, ARMv7A and ARMv7R Edition, Section D.3 Counter module control and status registers.

CoreSight timestamp counter

The CoreSight timestamp counter is an implementation of the memory-mapped counter module that the ARM® Architecture Reference Manual defines. The counter is visible in the SCP memory map, labeled CS CNTControl. The CNTRead counter frame that the counter architecture defines is not made available for this counter. This counter is the basis for CoreSight timestamp generation, that CoreSight timestamps on page 2-92 describes.

This counter has the same features as REFCLK counter on page 2-78. However, there is no mechanism to stop this counter using debug.

SCP REFCLK Generic Timer

The SCP subsystem includes a private memory-mapped ARM Generic Timer, that the ARM Architecture Reference Manual v7AR Edition defines. This provides a single timer frame, without a second view, and without a virtual timer capability. This timer is called the SCP REFCLK Generic Timer, REFCLK CNTCTL and REFCLK CNTBase0 in the SCP memory map, and is in the VSYS.AON power domain. See Table 3-7 on page 3-32.



AP_REFCLK Generic Timer

The ADP includes two memory-mapped ARM Generic Timers, that the ARM Architecture Reference Manual v7AR Edition defines. This provides two timer frames, each without a second view, and each without a virtual timer capability. The timer is called the AP REFCLK Generic Timer, and the individual timers are named AP_REFCLK CNTCTL, AP_REFCLK CNTBase0, and AP_REFCLK CNTBase1, in the applications memory map, and are in the VSYS.SYSTOP power domain. One timer is Secure and the other is Non-secure.

32kHz Generic Timer

The SCP subsystem includes a memory-mapped ARM Generic Timer, that the ARM Architecture Reference Manual v7AR Edition defines. This provides a single timer frame, without a second view, and without a virtual timer capability. This timer is called the SCP S32KCLK Generic Timer, 32K CNTCTL, and 32K CNTBase0 in the SCP memory map, and is in the VSYS.AON power domain.

Memory map frames

Table 2-55 shows the frames that the application processor and SCP memory map contain, that relate to the counter and timer components.

2.12.3 Processor power modes

A processor can generate timer interrupts after entering into WFI or WFE mode. Processor cores can enter WFI and WFE modes without any side-effects relating to their timers. When a cluster is powered down, Generic Timer state is lost, so you must perform additional steps.

The following models for powering down a processor, called AP wakeup and SCP wakeup, exist:

AP wakeup In this model, software must ensure that no timers are active on the cluster that is to be powered down. The cluster can then be powered down by making a request to the SCP. The cluster can later be powered up by a core in another cluster making a request to the SCP.

Table 2-55 Frames for counter and timer components

Frame Description

REFCLK CNTControl Frame that contains the control registers for the REFCLK counter

REFCLK CNTRead Frame that contains the status registers for the REFCLK counter

32K CNTControl Frame that contains the control registers for the 32kHz counter

REFCLK CNTCTL CNTCTLBase frame for the SCP REFCLK timer

REFCLK CNTBase0 CNTBase0 frame for the SCP REFCLK timer

32K CNTCTL CNTCTLBase frame for the SCP 32kHz timer

32K CNTBase0 CNTBase0 frame for the SCP 32kHz timer

CS CNTControl Frame that contains the control registers for the CoreSight timestamp counter

AP_REFCLK CNTCTL CNTCTLBase frame for the AP_REFCLK timers

AP_REFCLK CNTBase0 CNTBase0 frame for the AP_REFCLK timer, and is only accessible using secure accesses

AP_REFCLK CNTBase1 CNTBase1 frame for the AP_REFCLK timer



AP_REFCLK wakeup This model applies when powering down the last application processor. Timer state must be saved to the AP_REFCLK Generic Timers as part of the power down sequence. Interrupts are masked during this sequence. You make a request to the SCP to power down the processor. The AP_REFCLK Generic Timers cause the processor to be woken when the timer expires because the GIC initiates a power up request interrupt to the SCP.Before the SCP powers down VSYS.SYSTOP, it must first check whether a wakeup time has been programmed into the AP_REFCLK Generic Timers. If these have been programmed the SCP must:• Save the state of the AP_REFCLK Generic Timers before

powering down VSYS.SYSTOP. Other software saves the state of the GIC before VSYS.SYSTOP is powered down.

• Use the state from the AP_REFCLK Generic Timers to schedule the wakeup of VSYS.SYSTOP at, or slightly before, the time programmed into these timers. The SCP can use the SCP_REFCLK Generic Timer to do this.

• After waking VSYS.SYSTOP, the SCP restores state to the AP_REFCLK Generic Timers, and this triggers an interrupt. Other software restores state to the GIC. The interrupt causes a wakeup interrupt for the core, that the SCP handles.

2.12.4 Watchdog timers

This section describes:• SCP firmware watchdog.• Trusted watchdog.• Generic watchdog on page 2-82.

SCP firmware watchdog

The SCP subsystem includes an ARM SP805 watchdog timer that protects against lockups in the firmware.The first time the SCP firmware watchdog expires an interrupt to the SCP is generated. If this fails to clear the watchdog, and it expires for a second time, a global reset is generated.

This watchdog increments at 32kHz. It can be halted in debug using the cross trigger network, but only when the SCPWD_HOD_EN field in the SSC_SWDHOD register is set to HIGH.

See:• Debug, trace, and profiling security on page 2-68.• Cross triggers on page 2-87.• ADP System Security Control Registers on page 3-34.• SSC_SWDHOD Register on page 3-40.

Trusted watchdog

The application processor subsystem includes an ARM SP805 watchdog timer that protects the Secure boot process when it is necessary to run un-trusted device drivers.



The first time the trusted watchdog expires, an interrupt to the CoreLink GIC-400 Generic Interrupt Controller is generated. If Secure boot software fails to clear the watchdog, and it expires for a second time, a global reset is generated.

This watchdog increments at 32kHz. This watchdog can also be halted in debug using the cross trigger network, but only when the SYSWD_HOD_EN field in the SSC_SWDHOD register is set to HIGH.

See:• Debug, trace, and profiling security on page 2-68.• Cross triggers on page 2-87.• ADP System Security Control Registers on page 3-34.• SSC_SWDHOD Register on page 3-40.

Generic watchdog

The Server Base System Architecture defines and requires a generic watchdog for use by EL2 software. This watchdog generates the following interrupts.

1. This interrupt is expected to be configured as an EL2 interrupt, and is routed as an SPI.

2. This interrupt must cause EL2 and higher levels to be reset. Because the applications processors in the ADP both implement EL3, the reset of EL2 is supported by routing this interrupt as an SPI that you can configure as an EL3 interrupt.

The generic watchdog is managed by two memory mapped register frames. In the ADP, Secure and Non-Secure accesses can access these frames.

For information about the programmers model of the generic watchdog, see:• Application processor interrupt map on page 3-3.• Application processor memory map on page 3-13.• The Trusted Base System Architecture Platform Design Document.



2.13 Debug and profilingThis section describes:• ADP debug architecture.• Cortex-A57 and Cortex-A53 processor debug architecture on page 2-85.• SCP debug architecture on page 2-85.• Trace on page 2-86.• Cross triggers on page 2-87.• System Trace Macrocell on page 2-88.• Embedded Trace Macrocell on page 2-91.• Debugger connectivity on page 2-91.• Debug power control on page 2-92.• CoreSight timestamps on page 2-92.• System Profiler on page 2-93.

2.13.1 ADP debug architecture

Figure 2-15 on page 2-84 shows a high-level representation of the ADP debug architecture. It excludes timestamp distribution. See CoreSight timestamps on page 2-92. Most of the debug-related components are located in the CoreSight subsystem and others are located within the Cortex-A57 and Cortex-A53 processors, the SCP subsystem, and in the main system.



Figure 2-15 ADP debug architecture, excluding timestamp distribution

Juno ARM Development Platform (SoC)

DAP

Cortex-A57 Cluster

Cortex-A53 Cluster

Funnel Cortex-A53

Core 3

Core 2

Core 1

Core 0

DAP

Input 0

Input 1

Input 2

Input 3

Funnel main

Triggers

Trusted watchdog

Gcounter, refclk Trigger

Trigger

Trigger

Input 0Input 1Input 2Input 3Input 4Input 5Input 6

SMMU

Cross trigger channels

Cross trigger extension interface

ATB extension interfaces

JTAG/SWD glue logic

JTAG portDebug APB extension interface

APB access from system

ATB

ATBATB

APB

Replicator

APB switch APB-AP

Cortex-M3 core

AXI-AP

CTI

CTM

CTI

CTI

CTM

CTI

CTI

CTI

CTM

CTI

CTI

CTI

ETM

ETM

ETM

ETM

ITM

ETM

Debug APB

AXI from ETR

STM

ROM table

ROM table

PMU

PMU

PMU

PMU

System Profiler

Funnel SCP

Input 0Input 1

Gcounter, 32KHz

Gcounter, debug Watchdog

Core 1

Core 0

ETM

PMU

ETM

PMUFunnel

Cortex-A57

Input 1

Input 0

Trigger component

Trace component

SWJ-DP

SWJ-DP

DAP bus

APB

Cross trigger channels

Key

ATB busAXI busAPB bus

64-bit AXI port

Trace port

AXI port to system

AXI port from system

ETF

TPIU

ETR

Replicator

SCP subsytem

SWO



2.13.2 Cortex-A57 and Cortex-A53 processor debug architecture

The ADP contains two application processors. Each processor, internally, contains debug components, and for the Cortex-A57 processor cores, these are:

• A Performance Monitor Unit (PMU) for each processor. This module implements Cortex-A57 embedded performance monitoring functionality.

• An Embedded Trace Macrocell (ETM) for each processor. This module generates real-time trace information that trace tools can use to reconstruct the execution of all or part of a program. Each ETM generates an ATB trace output that is sent to a funnel before going to the CoreSight subsystem.

• A trace funnel, to arbitrate up to four trace sources down to one ATB trace output before being sent to the CoreSight subsystem.

• A Cross Trigger Interface (CTI) for each processor, with a Cross Trigger Matrix (CTM) for the cluster. This enables debug subsystems to interact, that is, cross trigger, with each other. This connects to a CTM in the CoreSight subsystem.

• Debug control with an APB register interface to provide accessibility to debug registers in the processor.

• A local debug ROM table that contains a list of components in the processor, enabling the debugger to determine the components that are implemented locally in the processor.

Each core in the Cortex-A57 and Cortex-A53 clusters also generates and receives the following debug-related signaling:

• Debug communication signal outputs that drive interrupts at the GIC-400. See Application processor interrupt map on page 3-3.

• Power control requests from each processor, each driving an interrupt input of the SCP, A57DBGPWRUPREQ or A53DBGPWRUPREQ. See System Control Processor (SCP) interrupt map on page 3-10.

Each processor also contains a debug authentication interface, with the signals DBGEN, NIDEN, SPIDEN, and SPNIDEN. DBGEN and NIDEN are tied HIGH. The ADP System Security Control Registers on page 3-34 controls SPIDEN and SPNIDEN.

For more information about the Cortex-A57 and Cortex-A53 debug architecture, see:• The Cortex®-A57 MPCore Technical Reference Manual.• The Cortex®-A53 MPCore Technical Reference Manual.

2.13.3 SCP debug architecture

The SCP subsystem contains a Cortex-M3 processor, and the following debug components:

• A Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.

• A Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.

• An Instrumentation Trace Macrocell (ITM) for support of printf() style debugging. This unit generates trace data that is sent to an ATB funnel in the CoreSight subsystem and to Serial Wire Output (SWO).

• An ETM for instruction trace. This unit also generates trace data that is sent to an ATB funnel in the CoreSight subsystem.



• A trace funnel combines the trace sources from ITM and ETM down to one trace output before it is sent to the primary CoreSight subsystem.

• A Serial Wire Output (SWO) to provide ITM only trace output as an alternative to the Trace Port Interface Unit (TPIU) in the CoreSight subsystem.

• A CTI for support of cross triggering with other debug components in the system. This connects to the CTM within the CoreSight subsystem. This CTI also controls the 32kHz and REFCLK Generic Counter, 32K CNTControl in the SCP memory map, and REFCLK CNTControl in the Application memory map, enabling debug triggers to halt the counter.

• A local debug ROM table, that contains a list of components in the SCP subsystem enabling the debugger to determine the components that are implemented locally.

• A Generic Counter, running on REFCLK, for CoreSight timestamp generation. This Generic Counter generates timestamps for CoreSight debug-related components to use. The SCP controls this counter, and only the SCP and ADP CNTControl in the SCP memory map can view it. It does not have an associated CTI, and therefore cannot be halted using cross triggers.

All debug components in the SCP subsystem are memory-mapped onto the Cortex-M3 SCP private peripheral bus area.

See System Control Processor (SCP) memory map on page 3-29.

Debugger access to the debug components registers uses an AHB Memory Access Port, AHB-AP, that is also within the SCP subsystem. This connects to the JTAG Debug Port, Serial Wire JTAG Debug Port (SWJ-DP), in the CoreSight subsystem using a DAP bus.

For more information about the Cortex-M3 debug architecture, see:• System Control Processor (SCP) on page 2-43.• The Cortex®-M3 Technical Reference Manual.• The ARM® Architecture Reference Manual, ARMv7A and ARMv7R Edition.

2.13.4 Trace

The ADP contains the following trace sources:• An ETM for each Cortex-A57 and Cortex-A53 processor.• An ITM in the SCP subsystem.• An ETM in the SCP subsystem.• An STM.• The System Profiler.• Two 64-bit ATB extension interfaces.

Each processor contains an ATB funnel associated with it, Cortex-A57 funnel, and Cortex-A53 funnel, that funnels all trace sources from each processor down to one ATB interface each. Each funnel contains four ATB slave ports, with slave port 0 connected to processor 0, slave port 1 connected to processor 1, and so on.

The SCP subsystem also contains an ATB funnel that funnels the two trace sources from the ITM and the ETM down to one ATB interface.

The three trace outputs are then combined with the rest of the trace sources using another funnel, funnel main, before being fed into the Embedded Trace FIFO (ETF). The funnel inputs are connected as follows:

ATB Slave Port 0 Connected to the ATB bus from the Cortex-A57 funnel.



ATB Slave Port 1 Connected to the ATB bus from the Cortex-A53 funnel.

ATB Slave Port 2 Connected to the STM.

ATB Slave Port 4 Connected to the System Profiler.

ATB Slave Port 5 Connected using an asynchronous bridge and provided as an ATB extension interface, ATB extension 0.

ATB Slave Port 6 Connected using an asynchronous bridge and provided as an ATB extension interface, ATB extension1.

The ETF implements a 64KB buffer that enables buffering of trace data. The output trace data stream is then replicated before being sent to either the TPIU that sends it out using the traceport, or sends it to the ETR that can write the trace data to memory located in the application memory space.

The MMU-401 translates addresses of accesses from the ETR to memory to support the use of intermediate physical address at the ETR. The ETF can also operate as a trace buffer enabling either:• The debugger to capture the trace data using the JTAG interface.• The application processors to access it when performing self-hosted debug.

For more information about these components, see:• The CoreSight™ Components Technical Reference Manual.• The CoreSight™ Trace Memory Controller Technical Reference Manual.• The CoreSight™ System Trace Macrocell Technical Reference Manual.

2.13.5 Cross triggers

Cross triggers provide a way for cores and devices to trigger each other in a controlled manner. Triggers to and from a device or processor connect to a CTI module that maps them onto channels that are then connected to one or more CTMs to replicate the channels to all CTIs in the system.

Table 2-56 shows the components that have trigger sources and sinks in the ADP and how they are connected.

Table 2-56 Trigger sources, sinks and their connectivity

Module name Source Sinks CTI and CTM connectivity

Cortex-A57 cores Y Y Triggers from each core are connected to a CTI associated with the cluster, and all CTIs in the cluster then connect to a CTM within the cluster before connecting to a CTM in the CoreSight subsystem.

Cortex-A53 cores Y Y Triggers from each core are connected to a CTI associated with the cluster, and all CTIs in the cluster then connect to a CTM within the cluster before connecting to a CTM in the CoreSight subsystem.

Cortex-M3 SCP Y Y Triggers from each processor are connected to a CTI shared with the 32kHz Generic Counter in the SCP. This CTI then connects to the CTM within the CoreSight subsystem.

32kHz Generic Counter32k CNTControl

N Y This Generic Counter takes two trigger sources from the CTI, shared with the Cortex-M3 SCP, to provide the ability to halt the counter.



For more information about CTI and CTM, see the ARM® CoreSight™ Components Technical Reference Manual.

2.13.6 System Trace Macrocell

The System Trace Macrocell (STM) is a trace source that provides high bandwidth trace of instrumentation embedded into software. This instrumentation is made up of memory-mapped writes to the STM using its AXI slave interface. In addition, the STM provides a hardware event interface, generating trace data on the rising edge of the signals on the hardware event interface. It also implements an APB interface that connects to the APB bus from the CoreSight subsystem.

The STM AXI interface occupies a 16MB address space in the application memory map. However, for each processor in the ADP, and also each unique master interface, or group of master interfaces, in the system, the STM presents a separate view of the 16MB AXI space to each as if each processor or master has its own private STM, therefore providing up to a full 65536 extended stimulus port for each processor or master interface.

Table 2-57 on page 2-89 shows the STM views and the master or processor cores with which each is associated.

Note The STM provides at total of 64 views, and some are reserved. Table 2-57 on page 2-89 also shows how these are mapped to STPv2 master ID on the ATB trace port.

STM Y Y The STM provides trigger outputs TRIGOUTSPTE, TRIGOUTSW, TRIGOUTHETE, and ASYNCOUT.It is necessary to have two trigger inputs to drive four inputs on its hardware event interface, with two driving HWEVENTS[0] and HWEVENTS[2] directly, and the same signals, after inverting, driving HWEVENTS[1] and HWEVENTS[3].These are connected to CTI0 in the CoreSight subsystem.

ETF Y Y The ETF generates two triggers, FULL and ACQCOMP, and takes trigger inputs to drive FLUSHIN and TRIGIN. These are connected to CTI0 in the CoreSight subsystem.

ETR Y Y The ETR generates two triggers, FULL and ACQCOMP, and takes trigger inputs for FLUSHIN and TRIGIN. These are connected to CTI0 in the CoreSight subsystem.

TPIU N Y The TPIU takes trigger inputs for FLUSHIN and TRIGIN. These are connected to CTI0 in the CoreSight subsystem.

REFCLK Generic CounterREFCLK CNTControl

N Y This Generic Counter takes two triggers to provide the ability to halt the counter. These sources are from CTI1 in the CoreSight subsystem.

System Profiler Y Y The System Profiler takes a single trigger input and provides a single trigger output. These are connected to CTI1 in the CoreSight subsystem.

SCP watchdog N Y The watchdog takes two trigger sources from the CTI, shared with the Cortex-M3 SCP, to provide the ability to halt the watchdog timer.

Trusted watchdog N Y The trusted watchdog takes two trigger sources to provide the ability to halt the watchdog timer. These sources are from CTI1 in the CoreSight subsystem.

Table 2-56 Trigger sources, sinks and their connectivity (continued)

Module name Source Sinks CTI and CTM connectivity



When accessing the STM using the AXI slave expansion interface, each external master is identified using the same ARUSER[9:6] and AWUSER[8:5] bits that the TZC-400 NSAID inputs also use. For each access to the STM from the AXI slave expansion interface, the value on ARUSER[9:6] and AWUSER[8:5] identifies the view of the expansion master view that is required, with the value of x+1 selecting the expansion master x view, where x is in the range 0-7.

If the value of the ARUSER[9:6] and AWUSER[8:5] bits is not in the range 1-8, and the access does not belong to any logical system master that Table 2-57 shows, then the default master view, 62, is selected.

Table 2-58 on page 2-90 shows how each of the hardware event inputs is driven. HWEVENTS[25] to HWEVENTS[31] are driven by the STM hardware event expansion interface to enable you to generate events trace from your hardware.

Table 2-57 STM views and associated STPv2 Master ID

View Logical system masterSTPv2 master ID forSecure accesses

STPv2 master ID forNon-secure accesses

[0] Cortex-A57 core 0 0 64


[2:3] Reserved - -





[8:31] Reserved - -

[32] Mali-T624 GPU 32 96

[33] Cortex-M3 SCP 33 97

[34] Expansion master 0 34 98








[42:62] Reserved - -

[62] Default master 62 126

[63] DAP-AXI-AP 63 127



Most of the ADP internal hardware events relate to:• The state of the SCP.• Message interrupts between the SCP and the application processors.• Interrupts from the PPUs.

Table 2-58 shows the STM hardware events inputs.

For more information about the STM, see the ARM® CoreSight™ System Trace Macrocell Technical Reference Manual.

Table 2-58 STM hardware events inputs

STM event input Event Description

HWEVENTS[0] CTI0TRIGOUT[4] Trigger output CTI0TRIGOUT[4] from CTI0, rising edge detection

HWEVENTS[1] CTI0TRIGOUTN[4] Trigger output CTI0TRIGOUT[4] from CTI0, falling edge detection

HWEVENTS[2] CTI0TRIGOUT[5] Trigger output CTI0TRIGOUT[5] from CTI0, rising edge detection

HWEVENTS[3] CTI0TRIGOUTN[5] Trigger output CTI0TRIGOUT[5] from CTI0, falling edge detection

HWEVENTS[4] SCP_SLEEP SCP sleep entry

HWEVENTS[5] SCP_SLEEP_N SCP sleep exit

HWEVENTS[6] - MHU to SCP high priority Non-secure interrupt

HWEVENTS[7] - MHU to SCP low priority Non-secure interrupt

HWEVENTS[8] - MHU to SCP Secure interrupt

HWEVENTS[9] - MHU to GIC high priority Non-secure interrupt

HWEVENTS[10] - MHU to GIC low priority Non-secure interrupt

HWEVENTS[11] - MHU to GIC Secure interrupt

HWEVENTS[12] - Cortex-A57 core 0 PPU interrupt


HWEVENTS[14] - Reserved

HWEVENTS[15] - Reserved

HWEVENTS[16] - Cortex-A57 subsystem PPU interrupt





HWEVENTS[21] - Cortex-A53 subsystem PPU interrupt

HWEVENTS[22] - GPU subsystem PPU interrupt

HWEVENTS[23] - Debug subsystem PPU interrupt

HWEVENTS[24] - SYSTOP PPU interrupt

HWEVENTS[31:25] - STM hardware events expansion interface



2.13.7 Embedded Trace Macrocell

Both the Cortex-A53 and Cortex-A57 clusters implement the ARMv8 debug architecture profile. The Cortex-A57 and Cortex-A53 clusters support trace through an Embedded Trace Macrocell (ETM) interface.

The Cortex-M3 processor implements a CoreSight system and debug features that the ARMv7-M architecture defines, and supports trace through an ETM interface.

See the ARM® CoreSight™ System Trace Macrocell Technical Reference Manual.

2.13.8 Debugger connectivity

You debug the entire ADP using a common debug interface. This debug architecture is devised as a combination of the following debug subsystems that are accessible using the common JTAG debug interface and they are:• Primary CoreSight debug subsystem.• SCP debug subsystem.

Primary CoreSight debug subsystem

This debug subsystem includes the Cortex-A57 and Cortex-A53 clusters, and associated debug components that are accessible using the application memory map. External debug access to this subsystem uses a DAP that consist of the following:

• A SWJ_DP that is a combined JTAG-DP and SW-DP, enabling debug access either using JTAG or SWD.

• An APB-AP, that is an APB Memory Access Port. In the ADP, this module enables the debugger to directly connect to the APB bus within the CoreSight subsystem that connects using an APB switch to all debug related components mapped to the CoreSight debug and trace APB region within the peripherals region of the application memory map.

• An APB switch, that enables APB accesses from the system and from the APB-AP to either access CoreSight subsystem components, or components on the debug APB expansion interface.

• An AXI-AP, that is an AXI Memory Access Port.In the ADP, this module enables the debugger to access memory, peripherals, and devices mapped to the application memory map using an AXI interface.

SCP debug subsystem

This debug solution includes the Cortex-M3 SCP and associated debug components that are only accessible using the SCP memory map. Debug access to this subsystem is performed using a debug access port, SWJ-DP, that then connects to an AHB-AP within the Cortex-M3 processor, and enables the debugger to access all memory-mapped devices within the SCP memory map.

The SWJ_DP of both systems are daisy-chained and presented as a single combined JTAG port.

The JTAG port is also multiplexed with the serial wire port. The segregation of the two debug subsystems enables a mode of operation where the majority of the ADP, including most of the associated debug functionality, is powered down, OFF, while the SCP subsystem is powered, ON. This ensures that the SCP is independently available for debug.

Programming a DEVICEEN value in the ADP System Security Control Registers on page 3-34 enables you to disable external debug access.



For more information about all the DAP components, see the ARM® CoreSight™ Components Technical Reference Manual.

2.13.9 Debug power control

The combined JTAG and SWD interface of both debug subsystem and the associated chaining glue logic within the DAP is on the always-on power region, AON. Control bits in the Control, Status, CTRL, STAT, Registers in the primary CoreSight DAP always-on domain then enable the debugger to request the rest of the primary CoreSight debug subsystem, or the rest of the ADP, to be powered up for access using the debugger.

2.13.10 Debug through reset

Debug tools might require the ability to debug the Cortex-M3 processor, and Cortex-A57 and Cortex-A53 processors before the processor leaves reset. For example, it might be necessary to set watchpoints or breakpoints that cause the processor to enter debug mode immediately after leaving reset. The ADP provides this ability using a dedicated debug system reset input, nSRST.

The powerup reset, nPORESET, must be driven HIGH when nSRST is used to permit debug through reset.

The debug system reset, nSRST, must be driven HIGH during normal operation.

When nSRST is driven from HIGH to LOW, the system performs a power up reset, with the same effect as asserting nPORESET. While nSRST remains LOW, reset control logic in the ADP releases the reset to components reset by nPORESET, except for the following reset signals that are held in reset:• nCORERESET to each core in the Cortex-A57 and Cortex-A53 clusters.• SYSRESETn to the Cortex-M3 SCP.

These resets are released when nSRST becomes HIGH. Additionally, if CDBGPWRUPREQ or CSYSPWRUPREQ is set in the primary DP, then the SYSRESETn reset to the Cortex-M3 SCP is released so that the SCP can handle the power up request, enabling it to power up debug components.

For more information about debug power up requests, see:• Debug power request, CDBGPWRUPREQ on page 2-41.• System power request, CSYSPWRUPREQ on page 2-41.

2.13.11 CoreSight timestamps

All debug components in the ADP operate in a separate time domain to those of the application processors and the system control processor that Timers on page 2-75 describes. A separate Generic Counter, CS CNTControl, is implemented that provides a timestamp only for use as the CoreSight timestamp. This Generic Counter operates on the main reference clock that is distributed to all CoreSight components.

The CoreSight system requires a higher resolution, higher clock frequency 64-bit time value that timestamps trace data from trace sources. The 56 least significant bits of the REFCLK time count value from CS CNTControl are the 56 most significant bits of the timestamp value. The least significant eight bits of the timestamp are generated by a CoreSight Interpolator component, using a local high frequency clock and interpolation.

The following equation describes how to generate the high resolution Timestamp from the original low resolution Timestamp Counter:



Timestamp = (Timestamp Counter << 8) + interpolated bits

A 10-bit narrow CoreSight timestamp interface is also provided as an output from the ADP. This interface is synchronous to an external EXTDBGTSCLK that is asynchronous to all other clocks in the ADP. This enables you, when adding extra trace sources, to also generate a synchronized local time stamp within your systems by adding an external timestamp decoder and a timestamp interpolator.

The timestamp value that the STM reports is natural binary encoded and 64 bits wide.

2.13.12 System Profiler

In the ADP, many factors affect the overall performance of the system. To assist software developers in optimizing software, while at the same time also providing features that enable operation systems and applications to optimize themselves during operation, the ADP implements a System Profiler with the following monitors:• AXI Bus Monitor (ABM).• CCI Performance Monitor (CPM).• Memory Performance Monitor (MPM).

ABM The ABMs are implemented on any AXI interfaces that have high bandwidth or are latency-critical.

CPM The CPM is attached to the performance event buses from the CCI-400.

MPM The MPM is attached to the performance event buses from the DMC-400.

These monitors collect data relating to the wider system, outside the bounds of the individual clusters, and software or external debuggers can analyze this. See the ARM® Juno System Profiler Technical Reference Manual.



2.14 BootThis section describes:• About booting.• Initial power, clock, and reset requirements for boot.

2.14.1 About booting

The ADP supports the Trusted Board Boot on ARM Reference Hardware Platform Design Document. To support boot, the ADP provides:

• A Cortex-M3-based SCP designed to function as a trusted subsystem. This subsystem also includes:— A local trusted on-chip ROM.— Support for a local trusted on-chip SRAM to execute the main SCP firmware.

• A Cortex-A Series based system with the following features:— Able to support trusted on-chip boot ROM that stores associated cryptography

functionality.— Support for a non-trusted on-chip ROM that includes drivers for SoC interfaces

from the manufacturer.— Able to support trusted on-chip SRAM.

See:• The Trusted Board Boot Platform Design Document.• The Trusted Base System Architecture Platform Design Document.

2.14.2 Initial power, clock, and reset requirements for boot

For the ADP to successfully boot-up, the SCP must be supplied with power and clocks, and its reset de-asserted, without any software support. This means the following conditions must be met:

• The ADP Board power-management IC supplies VAON, VSYS, VA57, VA53, and VGPU.

• The real time clock, S32K_CLK, starts automatically.

• Powerup reset, nPORESET, is de-asserted when S32K_CLK is running.

• AON_REF_CLK always exists.



2.15 HDLCD controllerThe HDLCD controller, supporting High Definition (HD) resolutions, has the following features:

• Resolution:VGA 640 × 480 at 60fps and pixel clock frequency of 23.75MHz.UXGA 1600 × 1200 at 60fps and pixel clock frequency of 63.5MHz.Full HD 1920 × 1080 at 60fps and pixel clock frequency of 148.5MHz.QXGA, 40% blanking

2048 × 1536 at 30fps and pixel clock frequency of 132MHz.WQXGA, 40% blanking

2560 × 1600 at 30fps and pixel clock frequency of 172MHz.WQXGA, reduced blanking

2560 × 1600 at 60fps and pixel clock frequency of 210MHz.

• Frame buffer:— Supports all common non-indexed RGB formats.— Frame buffer can be placed anywhere in memory.— Scan lines must be a multiple of 8 bytes long, and aligned to 8-byte boundaries.

There are no other restrictions on size or placement. Line pitch configurable in multiples of 8 bytes.

• Management:— Frame buffer address can be updated at any time, and applies from the next full

frame.— Frame buffer size, color depth, and timing can only be changed while the display is

disabled.

• Maskable interrupts:— DMA-end, last part of frame read from bus.— VSYNC.— Underrun.— Bus error.

• Color depths:— Supports 8-bit per color. Frame buffers with other color depths are truncated or

interpolated to 8 bits per component.

• Interfaces:— AMBA 3 APB interface for configuration.— Read-only AXI bus for frame buffer reads.— Standard LCD external interface. All timings and polarities are configurable.— APB, AXI, and pixel clock can run on separate asynchronous clocks.

• Buffering:— Internal 1KB buffer.— After underrun, it blanks the rest of the frame and re-synchronizes from the next

frame.



2.16 PCIeThe ADP includes a 4-lane PCIe Root Port capable of operating at up to 5GT/s per lane. This supports high bandwidth connectivity with external peripherals such as SATA disk controllers and Gigabit Ethernet NIC. The PCIe Root Port and PHY are integrated on the chip.

This section contains the following subsections:• Configuration space.• Interrupts.• MSI.• Clock requirements.• Limitations.

2.16.1 Configuration space

The Root Port supports the Enhanced Configuration Access Mechanism (ECAM) for access to the PCIe configuration spaces of all devices in the PCIe subsystem. See the PCI Express Base Specification Revision 3.0 for more information on ECAM.

2.16.2 Interrupts

The ADP includes a Message Signaled Interrupt (MSI) unit that complies with the GICv2m architecture. The Server Base System Architecture (SBSA) defines the GICv2m architecture. The MSI unit converts memory writes, that target GICv2m registers, into edge-triggered interrupt signals that are connected to the GIC-400 Generic Interrupt Controller. Application processor interrupt map on page 3-3 shows the SPIs allocated to the MSI unit. The GICv2m architecture enables an IMPLEMENTATION DEFINED number of Non-Secure MSI frames to be implemented. The MSI unit implements four of these frames. Application processor memory map on page 3-13 shows these.

The PCIe macro provides interrupts that Table 3-3 on page 3-4 shows. All the interrupts are of type level except for the System Error Interrupt, that is of type edge.

2.16.3 MSI

The ADP can convert memory writes to an interrupt using an MSI component that implements the GICv2m architecture.

See:• Server Base System Architecture Platform Design Document.• ARM® Generic Interrupt Controller Architecture Specification, Architecture version 2.0.

In the ADP, the MSI component supports four Non-secure frames. Each frame occupies a 64KB region and has 32 SPIs.

2.16.4 Clock requirements

The tl_clk signal must be 133MHz for correct operation of the PCIe macro. See Clock Control, PCIETLCLK, Register on page 3-55.

2.16.5 Limitations

The PCIe macro does not support the following features:• Beacons.• Wake-up on LAN support.



• Retention of PCIe configuration, sticky registers in the PCI Express Base Specification, Revision 3.0, when the SoC is powered down.

• Relaxed Ordering.• ID based ordering.• Virtual Channels.• Address Translation Services.• Slot power limit.• Peer-to-peer.



2.17 Thin LinksThis section contains the following subsections:• About Thin Links.• TLX master and slave bridges.• System latency on page 2-101.

2.17.1 About Thin Links

The ADP supports the addition of peripherals such as GPUs and codecs to the external FPGA LogicTile for use cases such as prototyping and development of device drivers. This requires the ADP to provide both AXI slave and master interfaces to connect to external peripherals. However, exporting the full AXI interface from the chip is very expensive in terms of pin count and die area.

Therefore, the ADP uses a simple low pin-count solution using the TLX-400 Thin Links. The chip-to-chip interface does not use any high-speed I/O, SerDes or PHY, because these components are not available in the 28HPM process.

The CoreLink TLX-400 Network Interconnect Thin Links is an extension to the CoreLink NIC-400 Network Interconnect base product and provides a mechanism to reduce the number of signals in an AXI point-to-point connection and enable it to be routed over a longer distance.

See the ARM® CoreLink™ NIC-400 Network Interconnect Implementation Guide.

2.17.2 TLX master and slave bridges

This section describes:• AXI interfaces.• TLX-400 bandwidth on page 2-100.

AXI interfaces

Two Thin Link bridges are required for off-chip communication using the AXI protocol.

This section describes:• AXI interface requirements.• AXI slave interface on page 2-99.• AXI master interface on page 2-99.

AXI interface requirements

The chip-to-chip interface in the ADP consists of a Thin Links based AXI master and AXI slave interface to integrate off-chip logic. External masters on the FPGA, such as the GPU and video codecs, use the AXI slave interface to access the ADP memory. The cores in the ADP use the AXI master interface to configure the peripherals on the FPGA.

Figure 2-16 on page 2-99 shows the AXI interfaces between the ADP and the FPGA.



Figure 2-16 TLX-400 AXI interfaces

AXI slave interface

Location This is located at the top of the ADP. The AXI master port in the FPGA connects to the AXI slave port in the ADP.

Configurations This is an AXI4 interface that can connect to an AXI master interface, or multiple AXI masters on the FPGA. The interface supports the following.• 128-bit data.• 40-bit address.• 6 ID bits.• The ARUSERTLXS[5:0] and AWUSERTLXS[4:0] signals

support coherency signals on the ACE-Lite interface, excluding ARBAR and AWBAR:ARSNOOP[3:0] Indicates that the transaction type of a

shareable access is mapped to ARUSERTLXS[5:2].

ARDOMAIN[1:0] Indicates that the shareability domain of the transaction is mapped to ARUSERTLXS[1:0].

AWSNOOP[2:0] Indicates that the transaction type of a shareable access is mapped to AWUSERTLXS[4:2].

AWDOMAIN[1:0] Indicates that the shareability domain of the transaction is mapped to AWUSERTLXS[1:0].

Bandwidth Requirement Table 2-59 shows the bandwidth required on the AXI slave interface.

AXI master interface

Location This is located at the bottom of the ADP. AXI Master Port in the ADP is connected with AXI Slave Port in FPGA.

ADPAXI

slave

AXI master

FPGA

AXI slave

AXI master>250MB/s

Table 2-59 Bandwidth requirements of external masters

External masterRequired bandwidth onThin Links based AXI slave port

Vithar GPU, assuming 50MHz in V7 250 MB/s

Mali 450 8PP, assuming 50MHz in V7 >250 MB/s

Video, assuming 75MHz 100 MB/s



Configurations This is an AXI4 interface that can connect to an AXI slave interface, or multiple AXI interfaces, on the FPGA. The interface supports the following.• 64-bit data.• 40-bit address.• 14 ID bits.• ARUSERTLXM[3:0] and AWUSERTLXM[3:0] signals identify

masters. That is, the ID of the master that generated the transaction to the AXI master interface. The master could be either in the Compute Sub-system or outside at the SoC level.

Bandwidth Requirement The AXI master interface bandwidth is not critical because the traffic is mostly APB configuration writes, but occasional clearing of frame buffer in the FPGA tile is required.

TLX-400 bandwidth

This section describes:• Thin Links based AXI slave interface.• Thin Links based AXI master interface.

Thin Links based AXI slave interface

To support the bandwidth requirements on the AXI slave interface, the ADP uses the following link widths:• 56 in the forward direction, AW, AR, W.• 48 in the reverse direction, R, B.

The 128-bit AXI bus internal to the ADP runs at up to 533MHz that provides a bandwidth capacity of 8.5GB/s. The Thin Links configuration in the ADP supports the following, assuming the same 533MHz clock:• 25% of the maximum AXI bandwidth, 2.13GB/s, in the forward direction.• 31% of the maximum AXI bandwidth, 2.64GB/s, in the reverse direction.

However, the ADP-FPGA interface only supports up to 61.5MHz clock. Therefore the bandwidth supported on the ADP slave interface is as follows:• Forward direction, 2.13GB/s x (61.5/533) = 246MB/s.• Reverse direction, 2.64GB/s × (61.5/533) = 305MB/s.

The Thin Links based slave interface can accept 16 outstanding reads and 16 outstanding writes from an external master.

Thin Links based AXI master interface

The AXI master interface has a data width of 64 bits. This means that the AXI width is different to AXI slave interface. The 64-bit AXI bus internal to the ADP runs at up to 400MHz and supports a maximum bandwidth of 4GB/s.

The AXI master interface bandwidth is not critical at the slave interface. Therefore, a link width of 16, single direction, is selected for the ADP. This scheme supports bandwidths of:• 68MB/s, forward.• 78MB/s, reverse.



2.17.3 System latency

Table 2-60 shows the system latency.

Table 2-60 System latency

Block Clock frequency PeriodLatency

AR R AW W B

TLX-400 slave interface 61.5MHz 16.26ns 8 cycles 8 8 11 6

TLX-400 master interface 61.5MHz 16.26ns 12 cycles 11 12 17 7


Chapter 3 Programmers Model

This chapter describes the Juno ARM Development Platform (ADP) registers, and provides information on how to program the ADP.

It contains the following sections:• About this programmers model on page 3-2.• Application processor interrupt map on page 3-3.• System Control Processor (SCP) interrupt map on page 3-10.• Application processor memory map on page 3-13.• System Control Processor (SCP) memory map on page 3-29.• ADP System Security Control Registers on page 3-34.• System Configuration Controller (SCC) registers on page 3-47.• MHU Registers on page 3-98.• ADP System Control Registers on page 3-106.• Debug Registers on page 3-133.• Identification Registers on page 3-137.• Power Policy Unit Registers on page 3-142.• SoC peripherals NIC-400 Registers on page 3-154.• Compute subsystem NIC-400 Registers on page 3-168.• HDLCD Registers on page 3-174.• PCIe Control Registers on page 3-191.• PCIe Root Port configuration registers on page 3-202.• MSI Registers on page 3-232.• Trusted Entropy Source Registers on page 3-239.


Programmers Model

3.1 About this programmers modelThe following information applies to all registers:

• Do not attempt to access reserved or unused address locations. Attempting to access these locations can result in UNPREDICTABLE behavior.

• Unless otherwise stated in the accompanying text:— Do not modify undefined register bits.— Ignore undefined register bits on reads.— All register bits are reset to a logic 0 by a system or powerup reset.

• The following describes the access type:RW Read and write.RO Read-only.WO Write-only.


Programmers Model

3.2 Application processor interrupt mapThis section describes:• CPUID definition.• Application processors interrupt map.• Board interrupts on page 3-8.• Message Signaled Interrupt (MSI) unit on page 3-9.• System error interrupts on page 3-9.

3.2.1 CPUID definition

The ARM Development Platform (ADP) supports a configurable number of cores across two clusters.

Interrupts from processor cores connect to a GIC-400 generic interrupt controller that both clusters share. The ARM Generic Interrupt Controller Architecture associates each core with a core ID value.

Table 3-1 shows the core ID values assigned for each core.

3.2.2 Application processors interrupt map

The Generic Interrupt Controller Architecture defines the following types of interrupt:• Private Peripheral Interrupts (PPIs) separately exist for every microprocessor.• Shared Peripheral Interrupts (SPIs) are shared for all microprocessors.

Table 3-2 shows the PPI map for the application processors in the ADP.

Table 3-1 GIC core IDs for ADP configurations

Cortex-A57 cluster Cortex-A53 cluster

Core 0 Core 1 Core 0 Core 1 Core 2 Core 3

0 1 2 3 4 5

Table 3-2 Private peripheral interrupts

Interrupt ID Source Output Description

25 Cortex-A57 or Cortex-A53 cluster - Virtual maintenance interrupt, PPI6

26 nCNTHPIRQ Non-secure PL2 timer event, PPI5

27 nCNTVIRQ Virtual timer event, PPI4

28 Not implemented - Legacy nFIQ signal, PPI0

29 Cortex-A57 or Cortex-A53 cluster nCNTPSIRQ Secure PL1 physical timer event, PPI1

30 nCNTPNSIRQ Non-secure PL1 physical timer event, PPI2

31 Not implemented - Legacy nIRQ signal, PPI3


Programmers Model

Table 3-3 shows the SPI map for the application processor cores in the ADP. In the ADP, for configurations that include fewer than eight cores, interrupts for unimplemented cores are reserved.

Table 3-3 Application processor cluster shared peripheral interrupt map

Interrupt ID Source Description

32 Cortex-A57 cluster Cortex-A57 core 0 comms channel transmit

33 Cortex-A57 core 0 comms channel receive

34 Cortex-A57 core 0 performance monitor

35 Cortex-A57 core 0 cross trigger

36 Cortex-A57 core 1 comms channel transmit













Programmers Model

48 Cortex-A53 cluster Cortex-A53 core 0 comms channel transmit
















64 Mali-T624 GPU interrupt request

65 Job interrupt request

66 MMU interrupt request

67 MHU MHU high-priority interrupt

68 MHU low-priority interrupt

69 MHU Secure interrupt

70 GPU SMMU Combined Non-secure interrupt

71 Combined Secure interrupt

72 PCI Express SMMU Combined Non-secure interrupt


74 ETR SMMU Combined Non-secure interrupt


76 CCI Imprecise error response interrupt

77 PMU overflow interrupt

78 - Reserved

79

80 TZC-400 TrustZone address space controller interrupt

Table 3-3 Application processor cluster shared peripheral interrupt map (continued)



Programmers Model

81 System Profiler System Profiler interrupt

82 - Reserved

83 STM STM synchronization interrupt

84 CTI CTI trigger output 0 from CSSYS

85 CTI trigger output 1 from CSSYS

86 Trusted watchdog Trusted watchdog interrupt

87 Cortex-A53 cluster nEXTERRIRQ AXI write error condition

88 nINTERRIRQ L2 RAM double-bit ECC error

89 Cortex-A57 cluster nEXTERRIRQ AXI write error condition

90 nINTERRIRQ L2 RAM double-bit ECC error

91 AP_REFCLK Generic Timer, Secure AP_REFCLK Generic Timer Interrupt, Secure

92 AP_REFCLK Generic Timer, Non-secure AP_REFCLK Generic Timer Interrupt, Non-secure

93 EL2 Generic Watchdog Watchdog EL2 Interrupt

94 Watchdog EL3 Interrupt

95-99 - Reserved

100 Board RTC

101-114 - Reserved

115 On-chip UART 0 UART interrupt

116 On-chip UART 1 UART interrupt

117 HDLCD Controller 0 HDLCD Controller interrupt

118 SMC PL354 Interface 0 interrupt

119 Interface 1 interrupt

120 DMA controller DMA-330 Interrupt 0

121 Interrupt 1

122 Interrupt 2

123 Interrupt 3

124 Abort interrupt

125 HDLCD Controller 1 HDLCD Controller interrupt

126 DMA controller SMMU Combined Secure interrupt

127 Combined Non-secure interrupt

128 HDLCD controller 0 SMMU Combined Secure interrupt





Programmers Model

130 HDLCD controller 1 SMMU Combined Secure interrupt


132 USB controller SMMU Combined Secure interrupt


134 ThinLinks TLX-400 SMMU Combined Secure interrupt


136 ADP I2C interrupt

137 ADP Secure I2C interrupt

138 ADP I2S interrupt

139 ADP TRNG

140 ADP DMA Controller [4]




144 ADP DDR3 PHY0

145 ADP DDR3 PHY1

146 - Reserved

147

148 ADP USB OHCI Controller

149 ADP USB EHCI Controller

150-159 ADP Reserved

160 PCIe Root Port AXI address translation post error interrupt

161 PCIe Root Port AXI address translation fetch error interrupt

162 PCIe Root Port AXI address translation discard error interrupt

163 PCIe Root Port AXI address translation doorbell interrupt

164 PCIe Root Port PCIe address translation post error interrupt

165 PCIe Root Port PCIe address translation fetch error interrupt

166 PCIe Root Port PCIe address translation discard error interrupt

167 PCIe Root Port PCIe address translation doorbell interrupt

168 PCIe Root Port PCI interrupt line A

169 PCIe Root Port PCI interrupt line B

170 PCIe Root Port PCI interrupt line C

171 PCIe Root Port PCI interrupt line D




Programmers Model

See:• ARM® Generic Interrupt Controller Architecture Specification v2.0.• ARM® CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual.

3.2.3 Board interrupts

Table 3-4 shows the board interrupts.

All board interrupts are level-sensitive. The IOFPGA conditions any edge-triggered interrupt before routing them to the ADP, and also provide appropriate registers for software to clear the interrupt.

172 PCIe Root Port Message Signaled Interrupt (MSI) received

173 PCIe Root Port AER event

174 PCIe Root Port PM/Hotplug event

175 PCIe Root Port System error


192-201 Board Board Peripherals


224-351 ADP GICv2m PCI Express MSI



Table 3-4 Board interrupts

Interrupt ID ADP input pin name Source

100 EXT_IRQ[0] RTC

101 EXT_IRQ[1] UART 0

102 EXT_IRQ[2] UART 1

192 EXT_IRQ[3] Ethernet

193 EXT_IRQ[4] USB

194 EXT_IRQ[5] eMMC

195 EXT_IRQ[6] RTCC

196 EXT_IRQ[7] WDT

197 EXT_IRQ[8] KMI

198 EXT_IRQ[9] Timer

199 EXT_IRQ[10] System registers

200 EXT_IRQ[11] Tile Site1

201 PB_IRQ Push Button


Programmers Model

3.2.4 Message Signaled Interrupt (MSI) unit

See Interrupts on page 2-96.

3.2.5 System error interrupts

ARMv8 supports an SError exception, an interrupt mechanism for system error events. The GICv2 does not support these, so the nREI and nSEI inputs to the Cortex-A57 and Cortex-A53 clusters are unused and tied HIGH.


Programmers Model

3.3 System Control Processor (SCP) interrupt mapThe following sources send interrupts to the SCP:• Application processor system wakeup interrupts.• CoreSight power and reset request interrupts.• SCP subsystem interrupts.

These interrupts are routed to the NVIC that is included in the Cortex-M3 processor, where software can manage them. Table 3-5 shows the SCP interrupt map.

Table 3-5 SCP interrupt map

ID Source Description

0 SCP watchdog SCP system watchdog

1 SCP 32kHz Generic Timer 32kHz physical timer interrupt

2 SCP REFCLK Generic Timer REFCLK physical timer interrupt

3 MHU MHU high priority Non-secure interrupt

4 MHU low priority Non-secure interrupt

5 MHU Secure interrupt

6 SCP CoreSight SCP CTI trigger interrupt

7

8 CoreSight CoreSight debug power up request

9 CoreSight system power up request

10 CoreSight debug reset request

11 Cortex-A57 cluster Cortex-A57 core 0 debug power up request

12 Cortex-A57 core 1 debug power up request

13 - Reserved

14

15 Cortex-A53 cluster Cortex-A53 core 0 debug power up request




19 Snoop Access Control Cortex-A57 snoop access wakeup request

20 Cortex-A53 snoop access wakeup request

21 External Expansion interface wake-up request

22 Expansion interface service request

23 Expansion interface coherency request


Programmers Model

24 GIC-400 Cortex-A57 core 0 IRQ wakeup request

25 Cortex-A57 core 0 FIQ wakeup request

26 Cortex-A57 core 1 IRQ wakeup request


28 - Reserved

29

30

31

32 GIC-400 Cortex-A53 core 0 IRQ wakeup request








40 PPUs Cortex-A57 core 0 power policy unit interrupt

41 Cortex-A57 core 1 power policy unit interrupt

42 - Reserved

43

44 PPUs A57SSTOP subsystem power policy unit interrupt





49 A53SSTOP subsystem power policy unit interrupt

50 GPUTOP subsystem power policy unit interrupt

51 Debug subsystem power policy unit interrupt

52 SYSTOP power policy unit interrupt

53 PLLs Cortex-A57 cluster PLL lock interrupt

54 Cortex-A53 cluster PLL lock interrupt

55 GPU PLL lock interrupt

56 System PLL lock interrupt

Table 3-5 SCP interrupt map (continued)



Programmers Model

57 GIC expansion interrupts External GIC interrupt wakeup interrupt

58 Cortex-A57 cluster Cortex-A57 core 0 warm reset request

59 Cortex-A57 core 1 warm reset request

60-61 - Reserved

62 Cortex-A53 cluster Cortex-A53 core 0 warm reset request




66 Cortex-A57 cluster Cortex-A57 core 0 debug reset request

67 Cortex-A57 core 1 debug reset request

68-69 External interrupts 32 interrupts for SCP expansion

70 Cortex-A53 cluster Cortex-A53 core 0 debug reset request




74 Cortex-A57 cluster Cortex-A57 L2FLUSHDONE interrupt

75 Cortex-A53 cluster Cortex-A53 L2FLUSHDONE interrupt

76-95 - Reserved

96 - I2C Interrupt

97 PVT monitor Cortex-A53, sensor group interface

98 Cortex-A57, sensor group interface

99 Mali, sensor group interface

100 SoC, sensor group interface

101 AON, sensor group interface

102 Std Cell, sensor group interface

103 - Surge Detector Interrupt 0 or Surge Detector Interrupt 1

104 - DFI PHY Retrain Request Interrupt

105-127 - Reserved

Table 3-5 SCP interrupt map (continued)



Programmers Model

3.4 Application processor memory mapThe application memory map is the memory map of the application processor subsystem. It contains mappings for most components in the system, such as the application processors, GPU, and peripherals. It also includes mapping for the AXI expansion interfaces around the ADP.

The following can view the application memory map:• Application processors.• Mali-T624.• Embedded trace router.• Main Debug Access Port (DAP).• USB.• DMA.• PCIe Root Port.

Figure 3-1 on page 3-14 shows a top-level representation of the application memory map that complies with the Principles of ARM Memory Maps. It shows 1024GB of address space, accessible using 40-bit addressing, and is divided up into the following types of sub-regions:

DRAM memory areas These areas are mapped to DRAM through the DMC-400 Dynamic Memory Controller. For more information about how the DMC-400 maps these areas to DRAM, see DRAM on page 3-23.

Expansion area These areas are mapped to the asynchronous AXI master expansion interface to enable partners to interface to the subsystem.

ADP private peripherals and memory area This region is divided into the following regions:• A 128MB boot region. See Boot region on page 3-15.• A 256MB peripherals region. See Peripherals region on page 3-17.• Reserved areas. Accesses to these areas results in a decode error

response.

The memory map that this section describes also shows the overall security attributes associated with each area of memory. These are split into the following groups:

Always Secure access A component or region that is only accessible to Secure transactions. Any Non-secure access targeting these results in a DECERR response.

Secure and Non-secure access A component or region that is accessible to both Secure and Non-secure transactions.

Programmable access security, also called securable Components or regions that are defined to be independently software-configurable. Trusted software can change them between the ‘always Secure access’ and ‘Secure and Non-secure access’ access. You can configure these in the NIC-400, or in the component itself, and the default state is ‘Secure access only’ from reset.


Programmers Model

User-defined These are areas that are mapped to expansion interfaces and components outside of the ADP define their access security. These components must use the ARPROT[1] or AWPROT[1] bits provided on the expansion interfaces to determine the security permission of each access. Accesses that fail any external security checks must result in a DECERR response.

Figure 3-1 shows the ADP top-level application memory map, but it does not show areas with multiple security attributes.

Figure 3-1 ADP top-level application memory map

In general, unless explicitly stated otherwise:

• Where a region maps a peripheral or device, if the peripheral or device occupied less than the region size used, for example, if a peripheral only occupied 4KB from the 64KB of the region reserved for it, access to unmapped region results in a DECERR response.

• Accesses to reserved areas within the memory map result in a DECERR response.

• When accessing areas occupied by peripherals or devices, these peripherals or devices determine the response to return. These can include unmapped or reserved areas within the areas that the peripheral or device occupies.

The following sections describe the boot and ADP peripheral areas, and how the DMC area maps to DRAM memory using the memory controller. This section describes:• Boot region on page 3-15.• Peripherals region on page 3-17.• DRAM on page 3-23.• Application memory map summary on page 3-24.

PCIe expansion

Reserved

0x00_0000_0000

0x00_8000_0000

0x00_0800_0000

0x01_0000_0000

0x00_3000_0000

0x08_8000_0000

0x10_0000_0000

0x40_0000_0000

0x80_0000_0000

0x100_0000_0000

256MB

6GB

256GB

216GB

512GB

30GB2GB512MB512MB

0x00_6000_0000

0x00_4000_0000

272MB0x00_2F00_0000

368MB128MB

0x00_1F00_0000

PCIe expansion

Reserved

Reserved

Boot

ADP peripherals

DRAM

DRAM

Expansion interfaces

Address space

Reserved

SMC interface

Reserved

ADP peripherals

Application processor memory map


Programmers Model

3.4.1 Boot region

Figure 3-2 shows that the first 128MB of the address map is defined as a Secure boot region and only Secure accesses can access it.

Figure 3-2 ADP boot area memory map

This region is split into ROM and RAM areas. It contains:• 64KB of trusted boot ROM.• 256KB of trusted RAM.

Reserved

Reserved

0x0000_0000

0x0001_0000

0x0400_0000

0x0404_0000

0x0800_0000

65280KB

256KB

65472KB

64KBTrusted boot ROM

Trusted RAM


Address space

Reserved

PCIe expansion

Reserved

PCIe expansion

Reserved

Reserved

Boot

ADP peripherals

DRAM

DRAM

SMC interface

Reserved

ADP peripherals



Programmers Model

3.4.2 SMC interface region

Figure 3-3 shows that a 368MB region starting from address 0x00_0800_0000 is defined as the ADP SMC interface area.

Figure 3-3 ADP SMC interface area memory map

0x0800_0000

0x0C00_000064KBCS0, NOR


Address space

Reserved

PCIe expansion

Reserved

PCIe expansion

Reserved

Reserved

Boot

ADP peripherals

DRAM

DRAM

SMC interface

Reserved

ADP peripherals


64KBCS4, eMMC64KBCS5, SMC USB64KBCS1, PSRAM 32MB64KBCS2, SMC Ethernet48KBCS3, IOFPGA system peripherals

0x1000_0000

0x1400_0000

0x1800_0000

0x1C00_0000


Programmers Model

3.4.3 Peripherals region

This region defines the memory map for peripherals and memories that are part of the ADP.

This section contains the following subsections:• ADP Peripherals region, 0x1F00_0000-0x2F00_0000.• ADP Peripherals region, 0x6000_0000-0x8000_0000 on page 3-21.

ADP Peripherals region, 0x1F00_0000-0x2F00_0000

Figure 3-4 shows that a 256MB region starting from address 0x00_1F00_0000 is defined as the ADP peripherals and memory area.

Figure 3-4 ADP peripherals region memory map, 0x1F00_0000-0x2F00_0000

This section contains the following subsections:• Non-trusted ROM.• CoreSight debug and trace on page 3-18.• System peripherals regions on page 3-19.• Processor peripherals region on page 3-19.• Graphics peripherals region on page 3-20.• Non-trusted SRAM on page 3-21.

Non-trusted ROM

This non-trusted ROM area contains non-trusted boot code. See the Trusted Base System Architecture Platform Design Document.

CoreSight

0x1F00_0000

0x1F00_1000

0x2A00_0000

0x2B61_0000

0x2D00_0000

0x2E00_0000

0x2F00_0000

22592KB

14144KB

10MB

16MB0x2900_0000

144MB

0x2000_0000

16380KB

4KB

0x2C01_0000

0x2C23_00002404KB

64KB

16320KB0x2D01_0000

32KB

16352KB0x2E00_8000

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Non-trusted SRAM

Graphics

Processor peripherals

System peripherals

Non-trusted ROM


Address space

Reserved

PCIe expansion

Reserved

PCIe expansion

Reserved

Reserved

Boot

ADP peripherals

DRAM

DRAM

SMC interface

Reserved

ADP peripherals



Programmers Model

CoreSight debug and trace

Figure 3-5 shows the CoreSight debug and trace region.

Figure 3-5 CoreSight debug and trace region memory map

STM AXI slave

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

0x2000_0000

0x2008_0000

0x2001_0000

0x2010_0000

0x2004_0000

0x2011_0000

0x2012_0000

64KB

16MB

15168KB

64KB64KB64KB

128KB0x2007_0000

0x2005_000064KB64KB

0x2003_0000

64KB64KB

0x2002_0000

0x2013_0000

512KB64KB

0x2100_0000

0x2200_0000

0x2235_0000

12992KB

0x2300_0000

0x2335_0000

0x2800_0000

0x2900_0000

0x2301_0000

0x230C_0000

0x2304_0000

0x230D_0000

0x2311_0000

256KB

64KB

448KB

0x2305_0000

64KB64KB

0x2303_0000

64KB64KB

0x2302_0000

0x2314_0000

0x2300_0000

Cortex-A57 ATB funnel

64KB64KB

64KB64KB

0x2312_0000

0x2313_0000

0x2315_0000

0x2201_0000

0x220C_0000

0x2204_0000

0x220D_0000

0x2211_0000

256KB

64KB

448KB

0x2205_0000

64KB64KB

0x2203_0000

64KB64KB

0x2202_0000

0x2014_0000

0x2200_0000

Cortex-A53 ATB funnel

64KB64KB

64KB64KB

0x2212_0000

0x2213_0000

0x2015_0000

64KB

768KB

0x2321_0000

0x2322_0000

0x2323_0000

0x2324_0000

0x2325_0000

0x2331_0000

0x2332_0000

0x2333_0000

0x2334_0000

0x2335_0000

64KB64KB

64KB64KB

768KB

64KB64KB

64KB64KB

64KB

CoreSight APB expansion

Reserved

Reserved

Cortex-A53 core 3 traceCortex-A53 core 3 PMUCortex-A53 core 3 CTI

Cortex-A53 core 3 debug






Cortex-A53 core 0 debugCortex-A53 ROM table




Cortex-A57 core 1 debugCortex-A57 ROM table

Funnel mainTPIU

SYS_CTI0ETF/ETBCS ROM

ETR

STM debug APBSYS_CTI1Replicator

Cortex-A57 debug APB interface

Cortex-A53 debug APB interface


Address space

Reserved


Programmers Model

System peripherals regions

Figure 3-6 shows the system peripherals region.

Figure 3-6 System peripherals memory map

Processor peripherals region

The processor peripherals region is reserved for peripherals that the application processors require.

This area contains the following:

• GIC-400. See the ARM® CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual.

• CCI-400 Programmers View. See the ARM® CoreLink™ CCI-400 Cache Coherent Interconnect Technical Reference Manual.

• GICv2m MSI unit. See Message Signaled Interrupt (MSI) unit on page 3-9.

Reserved

Reserved

Reserved

Reserved

0x2A00_0000

0x2A10_0000

0x2A42_0000

3200KB

3392KB

64KB64KB192KB

64KB64KB

1MB

64KB64KB

8576KB

64KB64KB

64KB64KB

64KB

1280KB

64KB

1MB

1MB

64KB

960KB

64KB

960KB

64KB

0x2A43_0000

0x2A44_0000

0x2A45_0000

0x2A46_0000

0x2A49_0000

0x2A4A_0000

0x2A4B_0000

0x2A80_0000

0x2A81_0000

0x2A82_0000

0x2A83_0000

0x2A84_0000

0x2B0A_0000

0x2B0B_0000

0x2B1F_0000

0x2B20_0000

0x2B30_0000

0x2B40_0000

0x2B41_0000

0x2B50_0000

0x2B51_0000

0x2B60_0000

0x2B61_0000

Reserved

Reserved

Reserved

Reserved

ETR MMU-401

PCIe MMU-401

GPU MMU-400

System Profiler

SCP Message Handling Unit (MHU)

DMC-400 configuration

AP_REFCLK_NS CNTBase0AP_REFCLK_S CNTBase0

AP_REFCLK CNTCTLREFCLK CNTRead

EL2 Generic Watchdog refreshEL2 Generic Watchdog control

REFCLK CNTControlSEC_REG

TZC-400Trusted Watchdog

NIC-400 GPV

CoreSight

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Non-trusted SRAM

Graphics


System peripherals

Non-trusted ROM


Address space

Reserved

PCIe expansion

Reserved

PCIe expansion

Reserved

Reserved

Boot

ADP peripherals

DRAM

DRAM

SMC interface

Reserved

ADP peripherals



Programmers Model

Figure 3-7 shows the processor peripherals region memory map.

Figure 3-7 Processor peripherals region memory map

Graphics peripherals region

The graphics region contains graphics-related processing units. Figure 3-8 on page 3-21 shows the graphics region memory map.

Reserved

Reserved

0x2C01_0000

0x2C05_1000

0x2C01_1000

0x2C03_1000

0x2C06_F000

0x2C07_1000

8KB

1152KB

0x2C04_F000

0x2C09_0000

120KB

4KB

0x2C02_F000

120KB

8KB

120KB

8KB

124KB

64KB0x2C0A_0000

0x2C1C_0000

256KB

0x2C20_0000128KB

64KB0x2C23_0000

Reserved

Reserved

Reserved

Reserved

GICv2m MSI

CCI-400

GIC-400 virtual CPU interface

GIC-400 virtual interface control

GIC-400 physical CPU interface

GIC-400 distributor

CoreSight

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Non-trusted SRAM

Graphics


System peripherals

Non-trusted ROM


Address space

Reserved

PCIe expansion

Reserved

PCIe expansion

Reserved

Reserved

Boot

ADP peripherals

DRAM

DRAM

SMC interface

Reserved

ADP peripherals



Programmers Model

Figure 3-8 Graphics region memory map

Non-trusted SRAM

The Non-trusted SRAM is a 32KB scratch RAM that application processor software uses.

ADP Peripherals region, 0x6000_0000-0x8000_0000

Figure 3-9 on page 3-22 shows that a 256MB region starting from address 0x00_1F00_0000 is defined as the ADP peripherals and memory area.

Mali T600 Series GPU

CoreSight

64KB

0x2D00_0000

0x2D01_0000

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Non-trusted ROM

System peripherals


Graphics

Non-trusted SRAMExpansion interfaces

Reserved

PCIe expansion

Reserved

PCIe expansion

Reserved

Reserved

Boot

ADP peripherals

DRAM

DRAM

SMC interface

Reserved

ADP peripherals



Programmers Model

Figure 3-9 ADP peripherals region memory map, 0x6000_0000-0x8000_0000

Reserved

Reserved

0x6000_0000

0x7000_0000

0x7FB0_0000

1MB

64KB64KB

256MB

64KB64KB

0x7FB1_0000

0x7FB2_0000

0x7FB3_0000

0x7FB4_0000

0x7FD0_0000

Reserved

USB_SMMUHDLCD0_SMMUHDLCD1_SMMU

DMA_SMMU

AXI master interface, only in remap 7

251MB

NIC400_SOC_GPV 1MB

0x7FE0_000064KB

0x7FE1_0000PVT standard cell

PVT SoCPVT Mali

64KB64KB

PVT Cortex-A57Power, Voltage, Temperature (PVT) Cortex-A57

64KB64KB

0x7FE2_0000

0x7FE3_0000

0x7FE4_0000

0x7FE5_0000Surge detector 64KB

0x7FE6_0000True Random Number Generator (TRNG) 64KB

0x7FE7_0000NV counter 64KB

0x7FE8_0000Keys 64KB

0x7FE9_0000Secure I2C 64KB

Reserved0x7FEE_0000

DFI PHY 1 configuration 64KBDFI PHY 0 configuration 64KB

DMA PL330 configuration 64KBSecure DMA PL330 configuration 64KB

PCIe control 64KBPCIe Root Port configuration 64KB

0x7FEF_0000

0x7FF0_0000

0x7FF1_0000

0x7FF2_0000

0x7FF3_0000

Reserved0x7FF5_0000

HDLCD 1 configuration 64KBHDLCD 0 configuration 64KB

SOC_UART1 64KBSOC_UART0 64KB

I2S 64KBI2C 64KB

USB Open Host Controller Interface (OHCI) 64KBUSB Enhanced Host Controller Interface (OHCI) 64KB

SMC PL354 configuration 64KB

Reserved

0x7FF6_0000

0x7FF7_0000

0x7FF8_0000

0x7FF9_0000

0x7FFA_0000

0x7FFB_0000

0x7FFC_0000

0x7FFD_0000

0x7FFF_0000System override registers 64KB

0x8000_0000


Address space

Reserved

PCIe expansion

Reserved

PCIe expansion

Reserved

Reserved

Boot

ADP peripherals

DRAM

DRAM

SMC interface

Reserved

ADP peripherals



Programmers Model

3.4.4 DRAM

The ADP can support up to a total of 512GB of DRAM, although the board supplies 8GB of DRAM. The DRAM regions of the memory map are provided in accordance with the Principle of ARM Memory Maps white paper. The ADP includes a DMC-400 Dynamic Memory Controller and a DDR3 PHY that enable it to access DRAM.

The CoreLink DMC-400 can protect areas of memory from unwanted memory map aliasing using address mask and address match registers. These registers determine whether a transaction to a location should result in a DECERR response. For more information, see the ARM® CoreLink™DMC-400 Dynamic Memory Controller Technical Reference Manual Supplement.

Figure 3-10 shows the DRAM memory map.

Figure 3-10 DRAM memory map

You must configure the DMC-400 to remap the distributed areas so that they form a contiguous area before accessing DRAM as Figure 3-10 shows. The DMC-400 configuration registers must also always be configured during secure boot so that when accesses target any unpopulated areas of memory in the DMC-400, it returns a DECERR, including any access that is beyond 512GB.

You must configure the DMC-400 configuration registers during Secure boot so that when access targets any unpopulated areas of memory in the DMC-400, it returns a DECERR, including any access that is beyond 512GB. See the ARM® CoreLink™ DMC-400 Dynamic Memory Controller Technical Reference Manual.

An option exists to program up to eight Secure or Non-secure access regions, excluding the base region, in the external memory using the TZC-400 Address Space Controller. See CoreLink TZC-400 security on page 2-66.

0x00_0000_0000

0x00_8000_0000

0x00_0800_0000

0x01_0000_0000

0x00_3000_0000

0x08_8000_0000

0x10_0000_0000

0x40_0000_0000

0x80_0000_0000

0x88_0000_0000

0x100_0000_0000

0x00_6000_0000

0x00_4000_0000

0x00_2F00_0000

0x00_1F00_0000

2GB

6GB

512GB

512GB

Reserved

DRAM

DRAM

Unmapped


Address space

Reserved


The DMC-400 remaps these to contiguous

addresses

PCIe expansion

Reserved

PCIe expansion

Reserved

Reserved

Boot

ADP peripherals

DRAM

DRAM

SMC interface

Reserved

ADP peripherals


Programmers Model

3.4.5 Application memory map summary

Table 3-6 shows a summary of the application memory map.

Table 3-6 Application memory map

Name Base address Size Top address Security

Trusted boot ROM 0x00_0000_0000 64KB 0x00_0000_FFFF Secure access only

Reserved 0x00_0001_0000 65472KB 0x00_03FF_FFFF -

Trusted RAM 0x00_0400_0000 256KB 0x00_0403_FFFF Secure access only


SMC interface 0x00_0800_0000 368MB 0x00_1EFF_FFFF

Non-trusted ROM 0x00_1F00_0000 4KB 0x00_1F00_0FFF Secure and Non-secure access

Reserved 0x00_1F00_1000 16380KB 0x00_1FFF_FFFF -

CS ROM 0x00_2000_0000 64KB 0x00_2000_FFFF Programmable access security

ETF/ETB 0x00_2001_0000 64KB 0x00_2001_FFFF

SYS_CTI0 0x00_2002_0000 64KB 0x00_2002_FFFF

TPIU 0x00_2003_0000 64KB 0x00_2003_FFFF

Funnel main 0x00_2004_0000 64KB 0x00_2004_FFFF

Reserved 0x00_2005_0000 128KB 0x00_2006_FFFF -

ETR 0x00_2007_0000 64KB 0x00_2007_FFFF Programmable access security

Reserved 0x00_2008_0000 512KB 0x00_200F_FFFF -

STM Debug APB 0x00_2010_0000 64KB 0x00_2010_FFFF Programmable access security

SYS_CTI1 0x00_2011_0000 64KB 0x00_2011_FFFF

Replicator 0x00_2012_0000 64KB 0x00_2012_FFFF


CoreSight APB Expansion 0x00_2100_0000 16MB 0x00_21FF_FFFF Programmable access security

Cortex-A57 ROM Table 0x00_2200_0000 64KB 0x00_2200_FFFF

Cortex-A57 core 0 Debug 0x00_2201_0000 64KB 0x00_2201_FFFF

Cortex-A57 core 0 CTI 0x00_2202_0000 64KB 0x00_2202_FFFF

Cortex-A57 core 0 PMU 0x00_2203_0000 64KB 0x00_2203_FFFF

Cortex-A57 core 0 Trace 0x00_2204_0000 64KB 0x00_2204_FFFF

Reserved 0x00_2205_0000 448KB 0x00_220B_FFFF -

Cortex-A57 ATB Funnel 0x00_220C_0000 64KB 0x00_220C_FFFF Programmable access security

Reserved 0x00_220D_0000 256KB 0x00_2210_FFFF -


Programmers Model

Cortex-A57 core 1 Debug 0x00_2211_0000 64KB 0x00_2211_FFFF Programmable access security





Cortex-A53 ROM Table 0x00_2300_0000 64KB 0x00_2300_FFFF Programmable access security

Cortex-A53 core 0 Debug 0x00_2301_0000 64KB 0x00_2301_FFFF




Reserved 0x00_2305_0000 448KB 0x00_230B_FFFF -

Cortex-A53 ATB Funnel 0x00_230C_0000 64KB 0x00_230C_FFFF Programmable access security

Reserved 0x00_230D_0000 256KB 0x00_2310_FFFF -
















STM AXI Slave 0x00_2800_0000 16MB 0x00_28FF_FFFF Secure and Non-secure access

Reserved 0x00_2900_0000 16MB 0x00_29FF_FFFF -

NIC-400 GPV 0x00_2A00_0000 1MB 0x00_2A0F_FFFF Secure access only

Reserved 0x00_2A10_0000 3200KB 0x00_2A41_FFFF -

Table 3-6 Application memory map (continued)



Programmers Model

SEC_REG 0x00_2A42_0000 64KB 0x00_2A42_FFFF Secure access only

REFCLK CNTControl 0x00_2A43_0000 64KB 0x00_2A43_FFFF

EL2 Generic Watchdog Control 0x00_2A44_0000 64KB 0x00_2A44_FFFF Secure and Non-secure access

EL2 Generic Watchdog Refresh 0x00_2A45_0000 64KB 0x00_2A45_FFFF

Reserved 0x00_2A46_0000 192KB 0x00_2A48_FFFF -

Trusted Watchdog 0x00_2A49_0000 64KB 0x00_2A49_FFFF Secure access only

TZC-400 0x00_2A4A_0000 64KB 0x00_2A4A_FFFF

Reserved 0x00_2A4B_0000 3392KB 0x00_2A7F_FFFF -

REFCLK CNTRead 0x00_2A80_0000 64KB 0x00_2A80_FFFF Secure and Non-secure access

AP_REFCLK CNTCTL 0x00_2A81_0000 64KB 0x00_2A81_FFFF Device, peripheral, defined security

AP_REFCLK CNTBase0 0x00_2A82_0000 64KB 0x00_2A82_FFFF Secure access only

AP_REFCLK CNTBase1 0x00_2A83_0000 64KB 0x00_2A83_FFFF Secure and Non-secure access

Reserved 0x00_2A84_0000 8576KB 0x00_2B09_FFFF -

DMC-400 CFG 0x00_2B0A_0000 64KB 0x00_2B0A_FFFF Programmable access security

Reserved 0x00_2B0B_0000 1280KB 0x00_2B1E_FFFF -

SCP_MHU 0x00_2B1F_0000 64KB 0x00_2B1F_FFFF Device, peripheral, defined security

System Profiler 0x00_2B20_0000 1MB 0x00_2B2F_FFFF

Reserved 0x00_2B30_0000 1MB 0x00_2B3F_FFFF -

GPU MMU-400 0x00_2B40_0000 64KB 0x00_2B40_FFFF Device, peripheral, defined security

Reserved 0x00_2B41_0000 960KB 0x00_2B4F_FFFF -

PCIe MMU-401 0x00_2B50_0000 64KB 0x00_2B50_FFFF Device, peripheral, defined security

Reserved 0x00_2B51_0000 960KB 0x00_2B5F_FFFF -

ETR MMU-401 0x00_2B60_0000 64KB 0x00_2B60_FFFF Device, peripheral, defined security

Reserved 0x00_2B61_0000 10240KB 0x00_2C0F_FFFF -

GIC Distributor 0x00_2C01_0000 4KB 0x00_2C01_0FFF Device, peripheral, defined security

Reserved 0x00_2C01_1000 120KB 0x00_2C02_EFFF -

GIC physical CPU interface 0x00_2C02_F000 8KB 0x00_2C03_0FFF Device, peripheral, defined security


GIC virtual interface control 0x00_2C04_F000 8KB 0x00_2C05_0FFF Device, peripheral, defined security


GIC virtual CPU interface 0x00_2C06_F000 8KB 0x00_2C07_0FFF Device, peripheral, defined security

Reserved 0x00_2C07_1000 124KB 0x00_2C08_FFFF -

CCI_PV 0x00_2C09_0000 64KB 0x00_2C09_FFFF Device, peripheral, defined security




Programmers Model

Reserved 0x00_2C0A_0000 1152KB 0x00_2C1B_FFFF -

GICv2m MSI Frame 0 0x00_2C1C_0000 64KB 0x00_2C1C_FFFF Secure and Non-secure access

GICv2m MSI Frame 1 0x00_2C1D_0000 64KB 0x00_2C1D_FFFF Secure and Non-secure access

GICv2m MSI Frame 2 0x00_2C1E_0000 64KB 0x00_2C1E_FFFF Secure and Non-secure access

GICv2m MSI Frame 3 0x00_2C1F_0000 64KB 0x00_2C1F_FFFF Secure and Non-secure access

Reserved 0x00_2C20_0000 192KB 0x00_2C22_FFFF -

Reserved 0x00_2C23_0000 14144KB 0x00_2CFF_FFFF

Mali-T624 GPU 0x00_2D00_0000 64KB 0x00_2D00_FFFF Programmable access security

Reserved 0x00_2D01_0000 16320KB 0x00_2DFF_FFFF -

Non-Trusted SRAM 0x00_2E00_0000 32KB 0x00_2E00_7FFF Secure and Non-secure access

Reserved 0x00_2E00_8000 16352KB 0x00_2EFF_FFFF -

Reserved 0x00_2F00_0000 16MB 0x00_2FFF_FFFF User-defined, exported security

Reserved 0x00_3000_0000 256MB 0x00_3FFF_FFFF

PCIe Enhanced Configuration Access Mechanism

0x00_4000_0000 256MB 0x00_4FFF_FFFF

PCIe memory address space 0x00_5000_0000 256MB 0x00_5FFF_FFFF

Thin-Links master interface 0x00_6000_0000 256MB 0x00_6FFF_FFFF

Reserved 0x00_7000_0000 251MB 0x00_7FAF_FFFF

DMA MMU-401 0x00_7FB0_0000 64KB 0x00_7FB0_FFFF Device, peripheral, defined security

HDLCD1 MMU-401 0x00_7FB1_0000 64KB 0x00_7FB1_FFFF

HDLCD0 MMU-401 0x00_7FB2_0000 64KB 0x00_7FB2_FFFF

USB MMU-401 0x00_7FB3_0000 64KB 0x00_7FB3_FFFF

SoC Interconnect NIC-400 GPV 0x00_7FD0_0000 1MB 0x00_7FDF_FFFF Secure access only

PVT Monitor, standard cell 0x00_7FE0_0000 4KB 0x00_7FE0_0FFF Programmable access security

PVT Monitor, SoC 0x00_7FE1_0000 4KB 0x00_7FE1_0FFF

PVT Monitor, Mali-T624 GPU 0x00_7FE2_0000 4KB 0x00_7FE2_0FFF

PVT Monitor, Cortex-A57 0x00_7FE3_0000 4KB 0x00_7FE3_0FFF

PVT Monitor, Cortex-A53 0x00_7FE4_0000 4KB 0x00_7FE4_0FFF

Surge detector 0x00_7FE5_0000 4KB 0x00_7FE5_0FFF

TRNG 0x00_7FE6_0000 4KB 0x00_7FE6_0FFF Secure access only

Trusted Non-Volatile Counters 0x00_7FE7_0000 4KB 0x00_7FE7_0FFF

Trusted Root-Key Storage 0x00_7FE8_0000 4KB 0x00_7FE8_0FFF

Secure I2C 0x00_7FE9_0000 256B 0x00_7FE9_00FF




Programmers Model

Note Depending on how many cores you configure in the Cortex-A57 and Cortex-A53 clusters, some areas within the Cortex-A57 and Cortex-A53 external debug APB interface areas become reserved.

DDR3 PHY 1 0x00_7FEE_0000 64KB 0x00_7FEE_FFFF Programmable access security

DDR3 PHY 0 0x00_7FEF_0000 64KB 0x00_7FEF_FFFF

DMA Non-secure 0x00_7FF0_0000 4KB 0x00_7FFF_0FFF

DMA Secure 0x00_7FF1_0000 4KB 0x00_7FF1_0FFF Secure access only

PCIe Control Registers 0x00_7FF2_0000 64KB 0x00_7FF2_FFFF Device, peripheral, defined security

PCIe Root Port Internal Configuration Registers

0x00_7FF3_0000 4KB 0x00_7FF3_0FFF

HDLCD 1 0x00_7FF5_0000 4KB 0x00_7FF5_0FFF Programmable access security

HDLCD 0 0x00_7FF6_0000 4KB 0x00_7FF6_0FFF

SOC UART 1 0x00_7FF7_0000 4KB 0x00_7FF7_0FFF

SOC UART 0 0x00_7FF8_0000 4KB 0x00_7FF8_0FFF

I2S 0x00_7FF9_0000 1KB 0x00_7FF9_03FF

I2C 0x00_7FFA_0000 256B 0x00_7FFA_00FF

USB OHCI 0x00_7FFB_0000 4KB 0x00_7FFB_0FFF

USB EHCI 0x00_7FFC_0000 4KB 0x00_7FFC_0FFF

PL354 0x00_7FFD_0000 4KB 0x00_7FFD_0FFF

System Override Registers 0x00_7FFF_0000 4KB 0x00_7FFF_0FFF Secure access only

DRAM 0x00_8000_0000 2GB 0x00_FFFF_FFFF Programmable access security

Reserved 0x01_0000_0000 30GB 0x08_7FFF_FFFF -

DRAM 0x08_8000_0000 6GB 0x0A_0000_0000 Programmable access security

Reserved 0x0A_0000_0001 216GB 0x3F_FFFF_FFFF -

PCIe memory address space 0x40_0000_0000 256GB 0x7F_FFFF_FFFF User-defined, exported security

Reserved 0x80_0000_0000 512GB 0xFF_FFFF_FFFF -




Programmers Model

3.5 System Control Processor (SCP) memory mapThe System Control Processor (SCP) subsystem is a Cortex-M3 processor based subsystem that implements a 32-bit address space. The Cortex-M3 processor uses a fixed high-level memory map that the ARMv7-M Architecture Reference Manual specifies.

Figure 3-11 on page 3-30 shows the SCP memory map.


Programmers Model

Figure 3-11 SCP memory map

The bottom 512MB of the address contains an 8KB boot ROM and a 128KB on-chip SRAM.

DRAM

0x4400_0000

0x4400_1000

0x4400_2000

0x4400_6000

0x4400_7000

0x4400_8000

0x4400_9000

0x4400_A000

0x4400_B000

0x4401_0000

0x4402_0000

0x4403_0000

0xE000_0000

0xE000_1000

0xE000_2000

0xE000_3000

0xE000_E000

0xE000_F000

0xE004_0000

0xE004_0000

0xE004_1000

0xE004_2000

0xE004_3000

0xE004_4000

0xE004_5000

0xE004_6000

0xE00F_F000

0x0000_0000

0x0000_2000

0x1000_0000

0x1002_0000

0x2000_0000

0x4000_0000

0x4400_0000

0x4403_0000

0x6000_0000

0xA000_0000

0xE000_0000

0xE004_0000

0xE010_0000

0xFFFF_FFFF

511MB

768KB256KB

1GB

128KB

8KB

Vendor expansion AHB

External device

SCP peripherals

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Secure access only components

Mapped to base memory map

Exported access security, user-defined

Reserved

ROM table

ATB replicatorCTI

SWOFunnel SCP

ETM

SCS

FPBDWTITM

Power registersConfiguration registers

CS CNTControl32K CNTBase032K CNTCTL

32K CNTControlWatchdog Timer

Refclk CNTBase0Refclk CNTCTL

1GB

0x0000_0000

0x0800_0000

0x1F00_0000

0x2F00_0000

0x4000_0000

0x8000_0000

Expansion AXI

Expansion AXISecurity


SCP resources

Address space

SCP peripherals

SRAM

Boot ROM

External Private Peripheral BusInternal Private Peripheral Bus

ADP peripherals

Boot

Reserved

Reserved

I2C, PMIC

SCC

AON PVT

0xE010_0000

0xE010_1000

0xE010_2000

0xFFFF_F000

0xFFFF_FFFF


Programmers Model

The first 1MB of the top 512MB of address space is reserved for the Private Peripheral Bus (PPB). This region is additionally divided into internal and external PPB as follows:

Internal PPB This is the bottom 256KB of the PPB space and is accessed using an AHB-Lite bus using the SCP subsystem. This space contains Cortex-M3 system components such as the following:• System Control Space (SCS).• Flash Patch and Breakpoint (FPB) unit.• Data Watchpoint and Trace (DWT).• Instrumentation Trace Macrocell (ITM).

External PPB Contains Cortex-M3 system components that are generally debug-related components, such as the following:• Serial Wire Output (SWO).• Embedded Trace Macrocell (ETM).• Cross Trigger Interface (CTI).• SCP funnel.• ROM table.The rest of the address space is reserved.

All other address space is accessed using the Cortex-M3 processor system bus and is divided into the following regions:

SCP peripherals, 192KB Contains the following:• SCP peripherals.• Generic Timers.• Generic Counters.• Watchdog timer.• Configuration registers.• Power registers.

Normal memory, 1GB This region is assumed to behave as normal memory and is mapped to a single contiguous 1GB region of the base memory map starting at 0x00_4000_0000. For the definition of normal type memory, see the ARMv7-M Architecture Reference Manual.Any SCP memory accesses in the 0x6000_0000-0x9FFF_FFFF external RAM region actually target memory locations in the 0x4000_0000-0x7FFF_FFFF region of the application memory map. It is unlikely that the SCP accesses this region of the application processor memory map in normal operation.

External device, 1GB This region is normally intended for off-chip device memory and is mapped to a single contiguous 1GB region of the base memory map starting at 0xA000_0000. For the definition of device type memory, see the ARMv7-M Architecture Reference Manual.Any SCP memory accesses in the 0xA000_0000-0xDFFF_FFFF external device region actually target memory locations in the 0x0000_0000-0x3FFF_FFFF region of the base memory map. This region of the base memory map contains the boot area and some of the ADP peripherals.


Programmers Model

Reserved areas All remaining areas are reserved. Any accesses targeting these areas results in a DECERR response.

Table 3-7 shows the SCP memory map.

Table 3-7 SCP memory map

Peripheral and region names Base address Reserved size Top address

Boot ROM 0x0000_0000 8KB 0x0000_1FFF

Reserved 0x0000_2000 262136KB 0x0FFF_FFFF

SRAM 0x1000_0000 128KB 0x1001_FFFF

Reserved 0x1002_0000 826106KB 0x43FF_FFFF

Refclk CNTCTL 0x4400_0000 4KB 0x4400_0FFF

Refclk CNTBase0 0x4400_1000 4KB 0x4400_1FFF

Reserved 0x4400_2000 16KB 0x4400_5FFF

Watchdog Timer 0x4400_6000 4KB 0x4400_6FFF

32K CNTControl 0x4400_7000 4KB 0x4400_7FFF

32K CNTCTL 0x4400_8000 4KB 0x4400_8FFF

32K CNTBase0 0x4400_9000 4KB 0x4400_9FFF

CS CNTControl 0x4400_A000 4KB 0x4400_AFFF

Reserved 0x4400_B000 20KB 0x4400_FFFF

Config Registers 0x4401_0000 64KB 0x4401_FFFF

Power Registers 0x4402_0000 64KB 0x4402_FFFF

Reserved 0x4403_0000 - 0x5FFF_FFFF

Application Memory Area 0x00_4000_0000 to 0x00_7FFF_FFFF 0x6000_0000 1GB 0x9FFF_FFFF

Application Memory Area 0x00_0000_0000 to 0x00_3FFF_FFFF 0xA000_0000 1GB 0xDFFF_FFFF

ITM 0xE000_0000 4KB 0xE000_0FFF

DWT 0xE000_1000 56KB 0xE000_1FFF

FPB 0xE000_2000 4KB 0xE000_2FFF

Reserved 0xE000_3000 - 0xE000_DFFF

Cortex-M3 System Control Space (SCS) 0xE000_E000 4KB 0xE000_EFFF

Reserved 0xE000_F000 - 0xE004_0FFF

ETM 0xE004_1000 4KB 0xE004_1FFF

SCP funnel 0xE004_2000 4KB 0xE004_2FFF

SWO 0xE004_3000 4KB 0xE004_3FFF

CTI 0xE004_4000 4KB 0xE004_4FFF

ATB replicator 0xE004_5000 4KB 0xE004_5FFF

Reserved 0xE004_6000 - 0xE00F_EFFF


Programmers Model

ROM table 0xE00F_F000 4KB 0xE00F_FFFF

I2C PMIC 0xE010_0000 256B 0xE010_00FF

PVT AON 0xE010_1000 4KB 0xE010_1FFF

SCC 0xFFFF_F000 4KB 0xFFFF_FFFF

Table 3-7 SCP memory map (continued)

Peripheral and region names Base address Reserved size Top address


Programmers Model

3.6 ADP System Security Control RegistersThe ADP System Security Control (SSC) Registers Unit provides an interface for controlling the system-wide security features of the ADP. These include the following:• Providing the selection and internal sources for debug authentication signals.• Controls to drive all Secure lock down type signals.• Controls to enable or disable Secure watchdog halt on debug functionality.• General purpose register for Secure state storage.

These registers are located in the AON power domain and their states are therefore maintained even if all of the system has been powered down, apart from the removal of VSYS.

3.6.1 About the ADP programmers model

The programmer-visible state in the ADP consists of the following domains:

• Private register map of the application processor.

• ADP peripherals register map that is equally visible to both the application processor and the SCP.

• Private register map of the SCP.

• Debug and trace programmer visible state.

Most of the programmer-visible register state is composed of standard ARM IP configurations and control registers that are an integral part of the components that constitute ADP. The following sections are not comprehensive descriptions, or even a full summary of all the visible register states. The focus is on summarizing the register state of peripherals that are not part of standard ARM IP distributions and have been developed specifically for the ADP when referencing the appropriate documents for all the standard ARM IP register states.

3.6.2 Register summary

Table 3-8 shows the SSC registers in offset order from the base memory address.

The SSC_BASE is the base address of the SSC. All registers in this module are Secure access only. If a Non-secure access attempts to access these Secure registers, or any unmapped unimplemented registers within the 4KB region starting from SSC_BASE, they receive a DECERR response. Any Secure accesses to unimplemented areas within the 4KB region starting from SSC_BASE RAZ, WI.

Table 3-8 System Security Control Register summary

Offset Name Type Reset Width Description

0x000 SSC_ICCFG_STAT RO 0x0000_0000 32 SSC_ICCFG_STAT Register on page 3-35

0x004 SSC_ICCFG_SET WO - 32 SSC_ICCFG_SET Register on page 3-35

0x008 SSC_ICCFG_CLR WO - 32 SSC_ICCFG_CLR Register on page 3-36

0x010 SSC_DBGCFG_STAT RO 0x0000_0000 32 SSC_DBGCFG_STAT Register on page 3-36

0x014 SSC_DBGCFG _SET WO - 32 SSC_DBGCFG_SET Register on page 3-37

0x018 SSC_DBGCFG _CLR WO - 32 SSC_DBGCFG_CLR Register on page 3-38

0x01C SSC_AUXDBCFG RW - 32 SSC_AUXDBGCFG Register on page 3-39


Programmers Model

3.6.3 Register descriptions

This section describes the System Security Control registers. Table 3-8 on page 3-34 provides cross references to individual registers.

SSC_ICCFG_STAT Register

The SSC_ICCFG_STAT Register characteristics are:

Purpose A Secure access only read-only memory-mapped register. It configures the security level of accesses that masters issue into the NIC-400 interconnect. This register is empty and all fields are reserved, and read as zeros.

Usage constraints Secure access only.

Attributes See Table 3-8 on page 3-34.

SSC_ICCFG_SET Register

The SSC_ICCFG_SET Register characteristics are:

Purpose A Secure access only write-only memory-mapped register. It sets bits in the SSC_ICCFG_STAT register. This register is empty and all fields are reserved, and read as zeros.



0x024 SSC_SWDHOD RW 0x0000_0000 32 SSC_SWDHOD Register on page 3-40

0x030 SSC_GPRETN RW 0x0000_0000 32 SSC_GPRETN Register on page 3-41

0x040 SSC_VERSION RO 0x0004_1030 32 SSC_VERSION Register on page 3-41

0xFD0 PID4 RO 0x00000004 32 PID_4 Register on page 3-42

0xFE0 PID0 RO 0x00000044 32 PID_0 Register on page 3-43

0xFE4 PID1 RO 0x000000B8 32 PID_1 Register on page 3-43

0xFE8 PID2 RO 0x0000000B 32 PID_2 Register on page 3-43

0xFEC PID3 RO 0x00000000 32 PID_3 Register on page 3-44

0xFF0 COMPID0 RO 0x0000000D 32 COMP_ID0 Register on page 3-44

0xFF4 COMPID1 RO 0x000000F0 32 COMP_ID1 Register on page 3-45

0xFF8 COMPID2 RO 0x00000005 32 COMP_ID2 Register on page 3-45

0xFFC COMPID3 RO 0x000000B1 32 COMP_ID3 Register on page 3-45

Table 3-8 System Security Control Register summary (continued)



Programmers Model

SSC_ICCFG_CLR Register

The SSC_ICCFG_CLR Register characteristics are:

Purpose A Secure access only write-only memory-mapped register. It clears bits in the SSC_ICCFG_STAT register. This register is empty and all fields are reserved, and read as zeros.



SSC_DBGCFG_STAT Register

The SSC_DBGCFG_STAT Register characteristics are:

Purpose The SSC_DBGCFG_STAT register:• Controls how to drive the debug authentication signals:

— From an external source to the ADP.— Internally using built-in register bits, implemented in this

register.• Defines the values of the debug authentication signals when you

configure them to be internally driven.The SSC_DBGCFG_STAT register is a Secure access only read-only memory-mapped register. To set or clear any fields within the register, use SSC_DBGCFG_SET Register on page 3-37 and SSC_DBGCFG_CLR Register on page 3-38.



Figure 3-12 shows the bit assignments.

Figure 3-12 SSC_DBGCFG_STAT Register bit assignments

Reserved

31 0

SPIDEN_SEL_STAT

3 12

SPIDEN_INT_STATSPNIDEN_SEL_STAT

4

SPNIDEN_INT_STAT

8 7 6 5

DEVICEEN_SEL_STATDEVICEEN_INT_STAT

Reserved


Programmers Model


SSC_DBGCFG_SET Register

The SSC_DBGCFG_SET Register characteristics are:

Purpose A Secure access only write-only memory-mapped register. It is associated with the SSC_DBGCFG_STAT Register on page 3-36, and when any field is written with a HIGH, the corresponding bit in the SSC_DBGCFG_SET Register is set to HIGH. This register always reads as zero.



Figure 3-13 on page 3-38 shows the bit assignments.

Table 3-9 SSC_DBGCFG_STAT Register bit assignments

Bits Name Description

[31:8] - Reserved. Read as zero.

[7] SPIDEN_SEL_STAT SPIDEN external or internal drive selection:0 External.1 Internal.If you select external mode, an ADP top-level configuration input, SPIDEN_CFG SPIDEN drives SPIDEN_CFG.

[6] SPIDEN_INT_STAT SPIDEN internal drive value.

[5] SPNIDEN_SEL_STAT SPNIDEN external or internal drive selection:0 External.1 Internal.If you select external mode, an ADP top-level configuration input drives SPNIDEN.

[4] SPNIDEN_INT_STAT SPNIDEN internal drive value.

[3] DEVICEEN_SEL_STAT DEVICEEN external or internal drive selection:0 External.1 Internal.If you select external mode, an ADP top-level configuration input drives DEVICEEN.

[2] DEVICEEN_INT_STAT DEVICEEN internal drive value.



Programmers Model

Figure 3-13 SSC_DBGCFG_SET Register bit assignments


SSC_DBGCFG_CLR Register

The SSC_DBGCFG_CLR Register characteristics are:

Purpose A Secure access only write-only memory-mapped register. This register is associated with the SSC_DBGCFG_STAT register, and when any field in this register is set to HIGH, the corresponding bit in the SSC_DBGCFG_STAT Register on page 3-36 is set to LOW. This register always read as zero.




Reserved

31 0

SPIDEN_SEL_SET

3 12

SPIDEN_INT_SETSPNIDEN_SEL_SET

4

SPNIDEN_INT_SET

8 7 6 5

DEVICEEN_SEL_SETDEVICEEN_INT_SET

Reserved

Table 3-10 SSC_DBGCFG_SET Register bit assignments



[7] SPIDEN_SEL_SET Sets SPIDEN external or internal drive selection, SPIDEN_SEL_STAT, to HIGH.

[6] SPIDEN_INT_SET Sets SPIDEN internal drive value, SPIDEN_INT_STAT, to HIGH.

[5] SPNIDEN_SEL_SET Sets SPNIDEN external or internal drive selection, SPNIDEN_SEL_STAT, to HIGH.

[4] SPNIDEN_INT_SET Sets SPNIDEN internal drive value, SPNIDEN_INT_STAT, to HIGH.

[3] DEVICEEN_SEL_SET Sets DEVICEEN external or internal drive selection, DEVICEEN_SEL_STAT, to HIGH.

[2] DEVICEN_INT_SET Sets DEVICEEN internal drive value, DEVICEEN_INT_STAT, to HIGH.



Programmers Model

Figure 3-14 SSC_DBGCFG_CLR Register bit assignments


SSC_AUXDBGCFG Register

The SSC_AUXDBGCFG Register characteristics are:

Purpose Auxiliary Debug Configuration Register. A secure access only read and write register. This register provides override control of the DBGEN and NIDEN debug authentication signals.

Usage constraints Setting any of the bits in this register violates compliance with the ARM Architecture Standard Configurations Platform Design Document, and requires self-hosted debug to always be present. To disable the use of external debuggers, drive DEVICEEN LOW using the SSC_DBGCFG registers instead.

Note ARM strongly recommends not to use this register, and to leave both bits

at their reset values.



Reserved

31 0

SPIDEN_SEL_CLR

3 12

SPIDEN_INT_CLRSPNIDEN_SEL_CLR

4

SPNIDEN_INT_CLR

8 7 6 5

DEVICEEN_SEL_CLRDEVICEEN_INT_CLR

Reserved

Table 3-11 SSC_DBGCFG_CLR Register bit assignments



[7] SPIDEN_SEL_CLR Clears SPIDEN external or internal drive selection, SPIDEN_SEL_STAT, to LOW.

[6] SPIDEN_INT_CLR Clears SPIDEN internal drive value, SPIDEN_INT_STAT, to LOW.

[5] SPNIDEN_SEL_CLR Clears SPNIDEN external or internal drive selection, SPNIDEN_SEL_STAT, to LOW.

[4] SPNIDEN_INT_CLR Clears SPNIDEN internal drive value, SPNIDEN_INT_STAT, to LOW.

[3] DEVICEEN_SEL_CLR Clears DEVICEEN external or internal drive selection, DEVICEEN_SEL_STAT, to LOW.

[2] DEVICEEN_INT_CLR Clears DEVICEEN internal drive value, DEVICEEN_INT_STAT, to LOW.



Programmers Model

Figure 3-15 SSC_AUXDBGCFG Register bit assignments


SSC_SWDHOD Register

The SSC_SWDHOD Register characteristics are:

Purpose A Secure access only read and write register. It drives control signals that enable the Halt On Debug functionality of both the SCP watchdog timer, and the system Secure watchdog.




Figure 3-16 SSC_SWDHOD Register bit assignments

Reserved

31 0

INTERNAL_DEBUG_OVERRIDE

12

Table 3-12 SSC_AUXDBGCFG Register bit assignments


[31:2] - Reserved. RAZ, WI.

[1:0] INTERNAL_DEBUG_OVERRIDE The settings are as follows:b00 Non-secure self-hosted debug is enabled. This is the reset value.b11 or b10 Both invasive and non-invasive Non-secure self-hosted debug are

disabled.b01 Invasive Non-secure self-hosted debug is disabled, but non-invasive

Non-secure self-hosted debug remains enabled. The DBGEN inputs to the applications processors are driven LOW, and the NIDEN inputs to the applications processors are driven HIGH.

Reserved

31 012

SCPWD_HOD_ENSYSWD_HOD_EN


Programmers Model


SSC_GPRETN Register

The SSC_GPRETN Register characteristics are:

Purpose A Secure access only read and write memory-mapped register that provides 16 bits of general storage space for security purposes. The SSC_GPRETN Register only resets only on a system powerup reset.




Figure 3-17 SSC_GPRETN Register bit assignments


SSC_VERSION Register

The SSC_VERSION Register characteristics are:

Purpose A Secure access only read-only memory-mapped register that specifies the version ID for the ADP security feature.




Table 3-13 SSC_SWDHOD Register bit assignments


[31:2] - Reserved. RAZ, WI.

[1] SCPWD_HOD_EN Setting this bit to HIGH enables the Halt On Debug functionality of the watchdog timer in the SCP subsystem. When enabled, the SCP Watchdog can be halted using the cross trigger network.Setting this field to LOW disables Halt on Debug for the SCP watchdog.

[0] SYSWD_HOD_EN Setting this bit to HIGH enables the Halt On Debug functionality of the trusted watchdog in the main subsystem.When enabled, the trusted watchdog can be halted using the cross trigger network.Setting this bit to LOW disables Halt on Debug for the Secure watchdog in the main system.

GPRETNReserved

31 01516

Table 3-14 SSC_GPRETN Register bit assignments



[15:0] GPRETN General purpose register for Secure state storage.


Programmers Model

Figure 3-18 SSC_VERSION Register bit assignments


Peripheral ID Registers

The Peripheral ID Register characteristics are:

Purpose You can conceptually treat these four 8-bit registers as a single register that contains a 32-bit peripheral ID value.

Usage constraints There are no usage constraints.


PID_4 Register


Figure 3-19 SSC_PID_4 Register bit assignments


DESIGNER_ID PART_NUMBER

31 01112

MINOR REVISION

2728 2324 1920

MAJOR REVISIONCONFIGURATION

Table 3-15 SSC_VERSION Register bit assignments


[31:28] CONFIGURATION Set to 0x0 because the ADP is not configurable

[27:24] MAJOR REVISION Set to 0x0

[23:20] MINOR REVISION Set to 0x0

[19:12] DESIGNER_ID ARM product with designer code 0x41

[11:0] PART_NUMBER 0x030 for the Juno ADP

DES_2Reserved SIZE

31 078 34

Table 3-16 SSC_PID_4 Register bit assignments



[7:4] SIZE Indicates the log2 of the number of 4KB blocks that the interface occupies. Set to 0x0.

[3:0] DES_2 JEP106 continuation code that identifies the designer. Set to 0x4 for ARM.


Programmers Model

PID_0 Register




PID_1 Register




PID_2 Register



PART_0Reserved

31 078

Table 3-17 SSC PID_0 Register bit assignments



[7:0] PART_0 Bits [7:0] of the part number. Set to 0x41.

PART_1Reserved DES_0

31 078 34




[7:4] DES_0 Bits [3:0] of the JEP Identity. Set to 0xB for ARM.


DES_1Reserved REVISION

31 078

JEDEC

34 2


Programmers Model


PID_3 Register




COMP_ID Registers

The COMP_ID Registers characteristics are:

Purpose You can conceptually treat these four 8-bit registers as a single register that contains a 32-bit component ID value.



COMP_ID0 Register





[7:4] REVISION Set to 0x0 for r0p0.

[3] JEDEC Set to 0x1.

[2:0] DES_1 Bits [6:4] of Designer field. Set to 0x3 for ARM.

Reserved Reserved

31 078





Table 3-21 SSC COMP_ID0 Register



[7:0] COMP_ID0 Reads as 0x0D.


Programmers Model

COMP_ID1 Register


COMP_ID2 Register


COMP_ID3 Register


3.6.4 Message Handling Unit (MHU)

The Message Handling Unit (MHU) is a memory-mapped peripheral that provides a mechanism to assert interrupt signals to facilitate inter-processor message passing between the SCP and the application processor. The message payload can be deposited into main memory or on-chip memories, and therefore, the MHU is used as a messaging signaling mechanism.

The MHU asserts the following interrupt signals:

• A high-priority Non-secure interrupt and a low-priority Non-secure interrupt in the application processor interrupt map.

• A Secure interrupt in the application processor interrupt map.

• A high-priority Non-secure interrupt and a low priority Non-secure interrupt in the SCP interrupt map.

• A Secure interrupt in the SCP interrupt map.

See Application processor interrupt map on page 3-3 and System Control Processor (SCP) interrupt map on page 3-10.




[7:0] COMP_ID1 Reads as 0xF0.




[7:0] COMP_ID2 Reads as 0x05.




[7:0] COMP_ID3 Reads as 0xB1.


Programmers Model

For each of the six interrupt signals, with a slight difference for the Secure interrupt to the application processor, the MHU drives the signal using a 32-bit register, with all 32 bits logically ORed together. The MHU provides a set of registers to enable software to set, clear, and check the status of each of the bits of this register independently. The use of 32 bits for each interrupt line enables software to provide more information about the source of the interrupt. For example, each bit of the register can be associated with a type of event that can contribute to raising the interrupt.

From these memory-mapped registers, all registers associated with Secure interrupts are mapped as Secure access only, and the rest are accessible to Secure and Non-secure accesses. If Non-secure accesses attempt to access Secure registers, these accesses are RAZ, WI. You can use software to configure the MHU to raise an interrupt to the application processor if such a violation occurs.

This interrupt is merged with the Secure application processor interrupt, and when enabled using the MHU_SCFG register, bit 31 of the SCP_INTR_S_STAT register is also used as the status for this interrupt.

All unmapped, unused areas within the 4KB region that the MHU occupies is reserved and accesses targeting them are RAZ, WI.

Note Software cannot set bit 31 of the MHU SCP_INTR_S register directly regardless of the settings of the MHU_SCFG Register on page 3-101. It is reserved for reporting an access violation. Therefore, writes to bit 31 of the SCP_INTR_S_SET register are ignored.

Because the MHU registers all reside in the same 64Kbyte region, to avoid conflicts with normal world software, avoid secure access to the any Non-Secure MHU interrupt set, clear, and status registers.

Table 3-91 on page 3-98 shows a summary of the register map of the MHU.


Programmers Model

3.7 System Configuration Controller (SCC) registersThis section describes:• Register summary.• Register descriptions on page 3-50.


Table 3-25 shows the System Configuration Controller (SCC) registers.

Table 3-25 SCC Register summary

Offset Name Type Width Description

Peripheral Registers

0x000 FAXICLK Clock Control Register RW 32 Clock Control, FAXICLK, Register on page 3-50

0x004 SAXICLK Clock Control Register RW 32 Clock Control, SAXICLK, Register on page 3-51

0x008 HDLCDCLK Clock Control Register RW 32 Clock Control, HDLCDCLK, Register on page 3-52

0x00C TMIF2XCLK Clock Control Register RW 32 Clock Control, TMIF2XCLK, Register on page 3-52

0x010 TSIF2XCLK Clock Control Register RW 32 Clock Control, TSIF2XCLK, Register on page 3-53

0x014 USBHCLK Clock Control Register RW 32 Clock Control, USBHCLK, Register on page 3-54

0x018 PCIEACLK Clock Control Register RW 32 Clock Control, PCIEACLK, Register on page 3-55

0x01C PCIETLCLK Clock Control Register RW 32 Clock Control, PCIETLCLK, Register on page 3-55

0x020 APBCLK Clock Control Register RW 32 Clock Control, APBCLK, Register on page 3-56

0x024 PXLCLK Clock Control Register RW 32 Clock Control, PXLCLK, Register on page 3-57

0x028 - - - Reserved

0x02C System Clock Enable Register RW 32 System Clock Enable Register on page 3-58

0x030 System Clock Force Register RW 32 System Clock Force Register on page 3-59

0x034 Manual Reset Register, VSYS RW 32 Manual Reset, VSYS, Register on page 3-59

0x038 Master Reset Register, VSYS RW 32 Master Reset, VSYS, Register on page 3-61

0x03C Manual Reset Register, VAON RW 32 Manual Reset, VAON, Register on page 3-61

0x040 SMC Mask Register 0 RW 32 SMC Mask Register 0 on page 3-62



0x04C SMC Mask Register 3 RW 32 SMC Mask Register 3 on page 3-63

0x050 SMC Control Register RW 32 SMC Control Register on page 3-64

0x054 DMA Control Register 0 RW 32 DMA Control Register 0 on page 3-65

0x058 DMA Control Register 1 RW 32 DMA Control Register 1 on page 3-65

0x05C GPU Texture Format Register RW 32 GPU Texture Format Register on page 3-65

0x060 Debug Authentication Register RW 32 Debug Authentication Register on page 3-66


Programmers Model

0x064 USB Strap Signals Register RW 32 USB Strap Signals Register on page 3-67

0x068 HDLCD Pixel Clock Selection Register RW 32 HDLCD Pixel Clock Selection Register on page 3-67

0x06C Test Mux Control Register RW 32 Test Mux Control Register on page 3-68

0x0F0 General Purpose Register 0 RW 32 General Purpose Register 0 on page 3-70

0x0F4 General Purpose Register 1 RW 32 General Purpose Register 1 on page 3-71

0x0F8 Apps Alternative Boot Register RW 32 Apps Alternative Boot Register on page 3-72

0x0FC SCP Alternative Boot Register RW 32 SCP Alternative Boot Register on page 3-72

0x100 Cortex-A57 PLL Control Register 0 RW 32 Cortex-A57 PLL Control Register 0 on page 3-72



0x10C Cortex-A53 PLL Control Register 1 RW 32 Cortex-A53 PLL Control Register 1 on page 3-75

0x110 GPU PLL Control Register 0 RW 32 GPU PLL Control Register 0 on page 3-76

0x114 GPU PLL Control Register 0 RW 32 GPU PLL Control Register 0 on page 3-76

0x118 SYS PLL Control Register 0 RW 32 SYS PLL Control Register 0 on page 3-78

0x11C SYS PLL Control Register 1 RW 32 SYS PLL Control Register 1 on page 3-79

0x120 HDLCD PLL Control Register 0 RW 32 HDLCD PLL Control Register 0 on page 3-80

0x124 HDLCD PLL Control Register 1 RW 32 HDLCD PLL Control Register 1 on page 3-81

0x128 DDR3L PHY0 PLL Config Register RW 32 DDR3L PHY0 PLL Configuration Register on page 3-82

0x12C DDR3L PHY1 PLL Config Register RW 32 DDR3L PHY1 PLL Config Register on page 3-83

EMA Registers

0x180 Cortex-A57 RF1P EMA Register RW 32 Cortex-A57 RF1P EMA Register on page 3-84

0x184 Cortex-A57 SRAM1P EMA Register RW 32 Cortex-A57 SRAM1P EMA Register on page 3-85

0x188 Cortex-A53 RF1P EMA Register RW 32 Cortex-A53 RF1P EMA Register on page 3-85

0x18C Cortex-A53 SRAM1P EMA Register RW 32 Cortex-A53 SRAM1P EMA Register on page 3-86

0x190 PCIe MMU RF1P EMA Register RW 32 PCIe MMU RF1P EMA Register on page 3-87

0x194 Onchip Scratch RAM SRAM1P EMA Register

RW 32 Onchip Scratch RAM SRAM1P EMA Register on page 3-87

0x198 Onchip Secure RAM SRAM1P EMA Register

RW 32 Onchip Secure RAM SRAM1P EMA Register on page 3-88

0x19C Onchip Secure ROM ROM1P EMA Register

RW 32 Onchip Secure ROM ROM1P EMA Register on page 3-88

0x1A0 Onchip Non-secure ROM ROM1P EMA Register

RW 32 Onchip Non-Secure ROM ROM1P EMA Register on page 3-89

0x1A4 GPU RF2P EMA Register RW 32 GPU RF2P EMA Register on page 3-89

Table 3-25 SCC Register summary (continued)



Programmers Model

0x1A8 GPU SRAM1P EMA Register RW 32 GPU SRAM1P EMA Register on page 3-90

0x1AC GPU RF1P EMA Register RW 32 GPU RF1P EMA Register on page 3-91

0x1B0 PCIe RF1P EMA Register RW 32 PCIe RF1P EMA Register on page 3-91

0x1B4 PCIe RF2P EMA Register RW 32 PCIe RF2P EMA Register on page 3-92

0x1B8 HDLCD RF2P EMA Register RW 32 HDLCD RF2P EMA Register on page 3-92

0x1BC DMA RF2P EMA Register RW 32 DMA RF2P EMA Register on page 3-93

0x1C0 HDLCD MMU RF1P EMA Register RW 32 HDLCD MMU RF1P EMA Register on page 3-94

0x1C4 USB MMU RF1P EMA Register RW 32 USB MMU RF1P EMA Register on page 3-94

0x1C8 DMA MMU RF1P EMA Register RW 32 DMA MMU RF1P EMA Register on page 3-95

0x1CC SCP Onchip Secure ROM ROM1P EMA Register

RW 32 SCP Onchip Secure ROM ROM1P EMA Register on page 3-95

0x1D0 SCP Onchip RAM SRAM1P EMA Register

RW 32 SCP Onchip RAM SRAM1P EMA Register on page 3-96

Power Control Registers

0x200-0x210 PCSM Control Registers RW 32 Cortex-A57 core 0


0x400-0x410 PCSM Control Registers RW 32 Cortex-A57 SCU & L2





0x900-0x910 PCSM Control Registers RW 32 Cortex-A53 SCU & L2

0xA00 VSYS Pad Isolate Register RW 32 -

0xA04 DDR3L PHY0 Retention Control Register RW 32 -

0xA08 DDR3L PHY1 Retention Control Register RW 32 -

0xA0C SYSTOP PCSM Retention Delay Register RW 32 -

APB Magic Register

0xE00 APB Control Clear RW 32 Write {0xA50F5, base_offset[11:0]} to this register to revert to serial control on the register at the specified base offset.

Standard APB Slave Registers

0xFD0 Peripheral ID 4 RW 32 0x04

0xFE0 Peripheral ID 0 RW 32 0xAD

0xFE4 Peripheral ID 1 RW 32 0xB0




Programmers Model


This section describes the SCC registers. Table 3-25 on page 3-47 provides cross references to individual registers.

Clock Control, FAXICLK, Register

The Clock Control, FAXICLK, Register characteristics are:

Purpose Controls the settings related to the FAXICLK signal including clock source and divide ratio.




Figure 3-24 Clock Control, FAXICLK, Register bit assignments


0xFE8 Peripheral ID 2 RW 32 0x0B

0xFEC Peripheral ID 3 RW 32 0x00

0xFF0 Component ID 0 RW 32 0x0D

0xFF4 Component ID 1 RW 32 0xF0

0xFF8 Component ID 2 RW 32 0x05

0xFFC Component ID 3 RW 32 0xB1



CLKDIVCRNTCLKLPI ENTRY DELAY CLKSELReserved

31 0412 8 7

CRNTCLKDIV

31516 1124 23

Table 3-26 Clock Control, FAXICLK, Register bit assignments

Bits Name Default Type Description

[31:24] - 0x00 RW Reserved.

[23:16] LPI ENTRY DELAY 0x00 RW Delay between CACTIVE and CSYSREQ for dynamic Low Power Interface (LPI) clock gating.

[15:12] CRNTCLKDIV 0x2 RO Acknowledges the currently active clock divider value. The divider value is the value + 1. For example, setting a value of 0 indicates a divider value of 1.


Programmers Model

Clock Control, SAXICLK, Register

The Clock Control, SAXICLK, Register characteristics are:

Purpose Controls the settings related to the SAXICLK signal including clock source and divide ratio.





[11:8] CRNTCLK 0x0 RO Acknowledges the currently active clock source being used as the input to the clock divider.0000 Output gated.0001 REFCLK.0010 SYSINCLK.

[7:4] CLKDIV 0x2 RW Requests a new clock divider value. The divider value is the value + 1. For example, setting a value of 0 indicates a divider value of 1.

[3:0] CLKSEL 0x1 RW Requests a new clock source to be used as the input to the clock divider.0000 Output gated.0001 AON_REF_CLK.0010 SYSCLK.All other values Reserved.

Table 3-26 Clock Control, FAXICLK, Register bit assignments (continued)


Table 3-27 Clock Control, SAXICLK, Register bit assignments



[23:16] LPI ENTRY DELAY 0x00 RW Delay between CACTIVE and CSYSREQ for dynamic LPI clock gating.


[11:8] CRNTCLK 0x0 RO Acknowledges the currently active clock source being used as the input to the clock divider:0000 Output gated.0001 REFCLK.0010 SYSINCLK.


[3:0] CLKSEL 0x1 RW Requests a new clock source to be used as the input to the clock divider:0000 Output gated.0001 AON_REF_CLK.0010 SYSCLK.All other values Reserved.


Programmers Model

Clock Control, HDLCDCLK, Register

The Clock Control, HDLCDCLK, Register characteristics are:

Purpose Controls the settings related to the HDLCDCLK signal including clock source and divide ratio.





Clock Control, TMIF2XCLK, Register

The Clock Control, TMIF2XCLK, Register characteristics are:

Purpose Controls the settings related to the TMIF2XCLK signal including clock source and divide ratio.




Figure 3-25 Clock Control, TMIF2XCLK, Register bit assignments

Table 3-28 Clock Control, HDLCDCLK, Register bit assignments



[23:16] LPI ENTRY DELAY 0x00 RW Delay between CACTIVE and CSYSREQ for dynamic LPI clock gating.





CLKDIVCRNTCLKReserved CLKSELReserved

31 0412 8 7

CRNTCLKDIV

31516 1124 23


Programmers Model


Clock Control, TSIF2XCLK, Register

The Clock Control, TSIF2XCLK, Register characteristics are:

Purpose Controls the settings related to the TSIF2XCLK signal including clock source and divide ratio.





Table 3-29 Clock Control, TMIF2XCLK, Register bit assignments



[23:16] - 0x00 RW Reserved. LPI is not supported.

[15:12] CRNTCLKDIV 0xC RO Acknowledges the currently active clock divider value. The divider value is the value + 1. For example, setting a value of 0 indicates a divider value of 1.


[7:4] CLKDIV 0xC RW Requests a new clock divider value. The divider value is the value + 1. For example, setting a value of 0 indicates a divider value of 1.


Table 3-30 Clock Control, TSIF2XCLK, Register bit assignments




[15:12] CRNTCLKDIV 0xC RO Acknowledges the currently active clock divider value. The divider value is the value + 1. For example, setting a value of 0 indicates a divider value of 1.


Programmers Model

Clock Control, USBHCLK, Register

The Clock Control, USBHCLK, Register characteristics are:

Purpose Controls the settings related to the USBHCLK signal including clock source and divide ratio.






[7:4] CLKDIV 0xC RW Requests a new clock divider value. The divider value is the value + 1. For example, setting a value of 0 indicates a divider value of 1.


Table 3-30 Clock Control, TSIF2XCLK, Register bit assignments (continued)


Table 3-31 Clock Control, USBHCLK, Register bit assignments






[7:4] CLKDIV 0x9 RW Requests new clock divider value. Divider value is the value + 1. For example, setting 0 indicates divider value of 1.

[3:0] CLKSEL 0x1 RW Requests new clock source to be used as the input to the clock divider:0000 Output gated.0001 AON_REF_CLK.0010 SYSCLK.All other values Reserved.


Programmers Model

Clock Control, PCIEACLK, Register

The Clock Control, PCIEACLK, Register characteristics are:

Purpose Controls the settings related to the PCIEACLK signal including clock source and divide ratio.





Clock Control, PCIETLCLK, Register

The Clock Control, PCIETCLK, Register characteristics are:

Purpose Controls the settings related to the PCIETCLK signal including clock source and divide ratio.




Table 3-32 Clock Control, PCIEACLK, Register bit assignments




[15:12] CRNTCLKDIV 0x2 RO Acknowledges the currently active clock divider value. Divider value is the value + 1. For example, setting of 0 indicates divider value of 1.


[7:4] CLKDIV 0x2 RW Requests new clock divider value. The divider value is the value + 1. For example, setting a value of 0 indicates a divider value of 1.



Programmers Model


Clock Control, APBCLK, Register

The Clock Control, APBCLK, Register characteristics are:

Purpose Controls the divide ratio of the APBCLK signal from the SAXICLK signal.




Figure 3-26 Clock Control, APBCLK, Register bit assignments


Table 3-33 Clock Control, PCIETLCLK, Register bit assignments




[15:12] CRNTCLKDIV 0xB RO Acknowledges the currently active clock divider value. Divider value is the value + 1. For example, setting 0 indicates divider value of 1.


[7:4] CLKDIV 0xB RW Requests a new clock divider value. The divider value is the value + 1. For example, setting a value of 0 indicates a divider value of 1.


CLKDIVReservedReserved ReservedReserved

31 0412 8 7

CRNTCLKDIV

31516 1124 23

Table 3-34 Clock Control, APBCLK, Register bit assignments






Programmers Model

Clock Control, PXLCLK, Register

The Clock Control, PXLCLK, Register characteristics are:

Purpose Controls the settings related to the PXLCLK signal including clock source and divide ratio.




Figure 3-27 Clock Control, PXLCLK, Register bit assignments



[7:4] CLKDIV 0x3 RW Requests new clock divider value. The divider value is the value + 1. For example, setting a value of 0 indicates a divider value of 1.

[3:0] - 0x0 RW Reserved. APBCLK is the divider output of SAXICLK, and therefore, a glitchless mux is not used for APBCLK.

Table 3-34 Clock Control, APBCLK, Register bit assignments (continued)


Reserved ReservedCRNTCLKReserved CLKSELReserved

31 0412 8 7 31516 1124 23

Table 3-35 Clock Control, PXLCLK, Register bit assignments




[15:12] - 0x0 RO Reserved.


[7:4] - 0x0 RW Reserved. PXLCLK is not a divided output of any clock.



Programmers Model

System Clock Enable Register

The System Clock Enable Register characteristics are:

Purpose Setting any bit position in this register to 1 enables the relevant clock. Setting to 0 disables the relevant clock.




Figure 3-28 System Clock Enable Register bit assignments


Reserved

31 048 7

DMCAUXCLKEN

310 9 126 5

APBCLKENPCIETLCLKENPCIEACLKENUSBHCLKEN

TSIF2XCLKENTMIF2XCLKENHDLCDCLKEN

SAXICLKENFAXICLKEN

Table 3-36 System Clock Enable Register bit assignments

Bits Internal signal name Default Type Description

[31:10] - - RW Reserved

[9] DMCAUXCLKEN 0x1 RW DMCAUXCLK enable

[8] APBCLKEN 0x1 RW APBCLK enable

[7] PCIETLCLKEN 0x1 RW PCIETLCLK enable

[6] PCIEACLKEN 0x1 RW PCIEACLK enable

[5] USBHCLKEN 0x1 RW USBHCLK enable

[4] TSIF2XCLKEN 0x1 RW TSIF2XCLK enable

[3] TMIF2XCLKEN 0x1 RW TMIF2XCLK enable

[2] HDLCDCLKEN 0x1 RW HDLCDCLK enable

[1] SAXICLKEN 0x1 RW SAXICLK enable

[0] FAXICLKEN 0x1 RW FAXICLK enable


Programmers Model

System Clock Force Register

The System Clock Force Register characteristics are:

Purpose Setting any bit position in this register to 1 forces the relevant clock ON regardless of any other enable or internal clock gating. Setting to 0 disables the relevant clock force.




Figure 3-29 System Clock Enable Register bit assignments


Manual Reset, VSYS, Register

The Manual Reset, VSYS, Register characteristics are:

Purpose Setting any bit in this register to 1 forces the relevant internal reset.Setting any bit in this register to 0 disables the relevant internal reset.




Reserved

31 0

FORCE_HDLCDCLK

3 12

FORCE_SAXICLKFORCE_FAXICLK

Table 3-37 System Clock Force Register bit assignments



[2] FORCE_HDLCDCLK 0x0 RW HDLCDCLK clock force

[1] FORCE_SAXICLK 0x0 RW SAXICLK clock force

[0] FORCE_FAXICLK 0x0 RW FAXICLK clock force


Programmers Model

Figure 3-30 Manual Reset, VSYS, Register bit assignments


Reserved

31 048 7

FORCE_VSYS_DMCAUX_RST

310 9 126 51317 16 1218 1115 14

FORCE_VSYS_HDLCD_RSTFORCE_VSYS_PCIE_RST

FORCE_VSYS_USB_PHY_RSTFORCE_VSYS_USB_BIU_RSTFORCE_VSYS_TMIF_RX_RSTFORCE_VSYS_TMIF_TX_RSTFORCE_VSYS_TSIF_RX_RSTFORCE_VSYS_TSIF_TX_RST

FORCE_VSYS_FAXI_RSTFORCE_VSYS_SAXI_RSTFORCE_VSYS_APB_RSTFORCE_VSYS_PXL0_RSTFORCE_VSYS_PXL1_RSTFORCE_VSYS_SMC_RSTFORCE_VSYS_I2C_RSTFORCE_VSYS_I2S_RSTFORCE_VSYS_UART_RSTFORCE_VSYS_AONREF_RST

19

Table 3-38 Manual Reset, VSYS, Register bit assignments


[31:19] - 0x0 RW Reserved

[18] FORCE_VSYS_DMCAUX_RST 0x0 RW DDR subsystem logic

[17] FORCE_VSYS_HDLCD_RST 0x0 RW HDLCD AXI interface logic

[16] FORCE_VSYS_PCIE_RST 0x0 RW PCIe macro logic

[15] FORCE_VSYS_USB_PHY_RST 0x0 RW ULPI logic of the USB host controller

[14] FORCE_VSYS_USB_BIU_RST 0x0 RW BIU logic of the USB host controller

[13] FORCE_VSYS_TMIF_RX_RST 0x0 RW ThinLinks based master interface, receive path

[12] FORCE_VSYS_TMIF_TX_RST 0x0 RW ThinLinks based master interface, transmit path

[11] FORCE_VSYS_TSIF_RX_RST 0x0 RW ThinLinks based slave interface, receive path

[10] FORCE_VSYS_TSIF_TX_RST 0x0 RW ThinLinks based slave interface, transmit path

[9] FORCE_VSYS_AONREF_RST 0x0 RW PVT monitors

[8] FORCE_VSYS_UART_RST 0x0 RW UART

[7] FORCE_VSYS_I2S_RST 0x0 RW I2S controller

[6] FORCE_VSYS_I2C_RST 0x0 RW I2C controller

[5] FORCE_VSYS_SMC_RST 0x0 RW SMC interface

[4] FORCE_VSYS_PXL1_RST 0x0 RW HDLCD 1 controller

[3] FORCE_VSYS_PXL0_RST 0x0 RW HDLCD 0 controller

[2] FORCE_VSYS_APB_RST 0x0 RW APB subsystem

[1] FORCE_VSYS_SAXI_RST 0x0 RW Slow AXI subsystem

[0] FORCE_VSYS_FAXI_RST 0x0 RW Fast AXI subsystem


Programmers Model

Master Reset, VSYS, Register

The Master Reset, VSYS, Register characteristics are:





Figure 3-31 Master Reset, VSYS, Register bit assignments


Manual Reset, VAON, Register

The Manual Reset, VAON, Register characteristics are:





Figure 3-32 Manual Reset, VAON, Register bit assignments

Reserved

31 0

FORCE_VSYS_MASTER_RST

1

Table 3-39 Master Reset, VSYS, Register bit assignments



[0] FORCE_VSYS_MASTER_RST 0x0 RW Master reset for all of the VSYS logic

Reserved

31 0

FORCE_VAON_I2C_RST

12

FORCE_VAON_SYSREF_RST


Programmers Model


SMC Mask Register 0

The SMC Mask 0 Register characteristics are:





Figure 3-33 SMC Mask Register 0 bit assignments


SMC Mask Register 1


Purpose Configures the address mask and match values for SMC chip selects 2 and 3.




Table 3-40 Manual Reset, VAON, Register bit assignments



[1] FORCE_VAON_I2C_RST 0x0 RW I2C controller

[0] FORCE_VAON_SYSREF_RST 0x0 RW PVT monitors

SMC_ADDR_MATCH_0 SMC_ADDR_MASK_0SMC_ADDR_MASK_1SMC_ADDR_MATCH_1

31 08 7151624 23

Table 3-41 SMC Mask Register 0 bit assignments


[31:24] SMC_ADDR_MATCH_1 0x14 RW SMC CS1 address match

[23:16] SMC_ADDR_MASK_1 0xFC RW SMC CS1 address mask




Programmers Model



SMC Mask Register 2








SMC Mask Register 3




31 08 7151624 23



[31:24] SMC_ADDR_MATCH_3 0x1C RW SMC CS3 address match





31 08 7151624 23





[15:8] SMC_ADDR_MATCH_4 0x0C RW SMC CS4 address match



Programmers Model






SMC Control Register

The SMC Control Register characteristics are:

Purpose Controls the SMC SRAM interface remap.




Figure 3-37 SMC Control Register bit assignments



31 08 7151624 23



[31:24] SMC_ADDR_MATCH_7 0x06 RW SMC CS7 address match, reserved

[23:16] SMC_ADDR_MASK_7 0xFE RW SMC CS7 address mask, reserved

[15:8] SMC_ADDR_MATCH_6 0x04 RW SMC CS6 address match, reserved

[7:0] SMC_ADDR_MASK_6 0xFE RW SMC CS6 address mask, reserved

Reserved

31 0

SMC_REMAP_1

12

SMC_REMAP_0

Table 3-45 SMC Control Register bit assignments



[1] SMC_REMAP_1 0x0 RW SMC SRAM interface 1 remap

[0] SMC_REMAP_0 0x1 RW SMC SRAM interface 0 remap


Programmers Model

DMA Control Register 0

The DMA Control Register 0 characteristics are:

Purpose Configures the DMA controller.




Figure 3-38 DMA Control Register 0 bit assignments


DMA Control Register 1

The DMA Control Register 1 characteristics are:

Purpose Configures the DMA controller.




GPU Texture Format Register

The GPU Texture Format Register characteristics are:

Purpose Configures the GPU texture format.

DMA_BOOT_IRQ_NSReserved

31 0

DMA_BOOT_PERIPH_NS

10 9 12

DMA_BOOT_MANAGER_NS

18 17

DMA_BOOT_FROM_PC

Table 3-46 DMA Control Register 0 bit assignments



[17:10] DMA_BOOT_IRQ_NS 0x0 RW Security state of interrupt source.

[9:2] DMA_BOOT_PERIPH_NS 0x0 RW Security state of the peripheral request interface.

[1] DMA_BOOT_MANAGER_NS 0x0 RW Security state of the DMA manger thread.

[0] DMA_BOOT_FROM_PC 0x0 RW Controls whether the DMA boots from the specified boot address or wait from an instruction on APB interface.

Table 3-47 DMA Control Register 1 bit assignments


[31:0] DMA_BOOT_ADDR 0x0 RW DMA boot address


Programmers Model




Debug Authentication Register

The Debug Authentication Register characteristics are:

Purpose The CSS debug authentication signals can be driven by either:• Secure control registers mapped internal to the compute sub-system.• SCC Debug Authentication Register mapped externally at the Juno

SoC level.Secure control registers inside the CSS control the selection of the multiplexor.




Figure 3-39 Debug Authentication Register bit assignments


Table 3-48 GPU Texture Format Register bit assignments


[31:0] MALI_TEX_FORMAT 0x0 RW Defines the value of the CONFIG_TEX_COMPRESSED_FORMAT_ENABLE Mali-T624 GPU configuration parameter.Instead of being statically configured, the ADP enables software to control the value of CONFIG_TEX_COMPRESSED_FORMAT_ENABLE.See the Mali™-T600 Series GPU Configuration and Sign-off Guide for information about this configuration parameter.

Reserved

31 0

DBG_SPNIDEN

12

DBG_SPIDENDBG_DEVICEEN

3

Table 3-49 Debug Authentication Register bit assignments



[2] DBG_SPNIDEN 0x1 RW Secure non-invasive debug enable

[1] DBG_SPIDEN 0x1 RW Secure invasive debug enable

[0] DBG_DEVICEEN 0x1 RW Global external debug enable


Programmers Model

USB Strap Signals Register

The USB Strap Signals Register characteristics are:

Purpose Configures the USB host controller settings.




Figure 3-40 USB Strap Signals Register bit assignments


HDLCD Pixel Clock Selection Register

The HDLCD Pixel Clock Selection Register characteristics are:

Purpose Selects the source for the HDLCD pixel clock.



ss_fladj_val_hostReserved

31 0512 8 711

ss_hubsetup_min

14 13 10 9

ss_ena_incrx_alignss_ena_incr4ss_ena_incr8

ss_ena_incr16ss_ehci64bit_enss_ulpi_pp2vbus

ss_autoppd_on_overcur_en

6

Table 3-50 USB Strap Signals Register bit assignments



[13] ss_hubsetup_min 0x0 RW OHCI: Hub setup time control

[12] ss_ena_incrx_align 0x0 RW AHB: AHB burst alignment enable

[11] ss_ena_incr4 0x1 RW AHB: AHB burst type INCR4 enable



[8] ss_ehci64bit_en 0x1 RW AHB: AHB Master 64-bit addressing enable

[7] ss_ulpi_pp2vbus 0x1 RW ULPI: Auto port power disable on overcurrent

[6] ss_autoppd_on_overcur_en 0x1 RW UTMI: Auto port power disable on overcurrent

[5:0] ss_fladj_val_host 0x20 RW Enhanced Host Controller Interface (EHCI): Frame length adjustment


Programmers Model


Figure 3-41 HDLCD Pixel Clock Selection Register bit assignments


Test Mux Control Register

The Test Mux Control Register characteristics are:

Purpose Controls the test MUX logic, the output of which goes through a divider to be routed to the test_out pin. This scopes out internally-generated clocks, and other important signals.




Figure 3-42 Test Mux Control Register bit assignments


Reserved

31 0

HDLCD1_PXLCLK_SEL

12

HDLCD0_PXLCLK_SEL

Table 3-51 HDLCD Pixel Clock Selection Register bit assignments



[1] HDLCD1_PXLCLK_SEL 0x0 RW Selects pixel clock for HDLCD controller 1:0 HDLCD PLL output.1 PXL_REF_CLK directly from input pad.

[0] HDLCD0_PXLCLK_SEL 0x0 RW Selects pixel clock for HDLCD controller 0:0 HDLCD PLL output.1 PXL_REF_CLK directly from input pad.

clksel_testmuxReserved

31 0

clkdiv_testmux

10 8

Reserved

11 7 5 4

Table 3-52 Test Mux Control Register bit assignments




Programmers Model

Note You can bypass the divider if necessary, for example, when the vsurge_diag input is selected, by setting the clkdiv_testmux field to 3’b101.

You can select the PVT sensor output by setting the Sensor Control Register 0.

[10:8] clkdiv_testmux 0x0 RW Clock divider value for test mux output:3’b000 Divide by 2.3’b001 Divide by 4.3’b010 Divide by 8.3’b011 Divide by 16.3’b100 Divide by 32.3’b101 Divider bypassed.3’b110,3’b111 1’b0.


[4:0] clksel_testmux 0x0 RW Select signals for test mux:5’h00 FAXICLK.5’h01 HDLCDCLK.5’h02 SAXICLK.5’h03 PCIEACLK.5’h04 PCIETLCLK.5’h05 USBHCLK.5’h06 TMIF2XCLK.5’h07 TSIF2XCLK.5’h08 APBCLK.5’h09 PXL0CLK.5’h0A PXL1CLK.5’h0B SCPHCLK.5’h0C USBCLK12.5’h0D DMCCLK.5’h0E DMCCLKIN.5’h0F PVT sensor output.5’h10 Vsurge DIAG.5’h11 Cortex-A57 CPUTESTCLK.5’h12 Cortex-A53 CPUTESTCLK.5’h13 GPU CPUTESTCLK.5’h14-5’h15 Reserved.

Table 3-52 Test Mux Control Register bit assignments (continued)



Programmers Model

General Purpose Register 0


Table 3-53 General Purpose Register 0 bit assignments


[31:0] GPR_0 0x0 RO from APB interface.RW from Serial interface.



Programmers Model



Table 3-54 General Purpose Register 1 bit assignments


[31:16] SCC_GPRETN 0x0 RO from APB interface.RW from Serial interface.

The SCP copies this value into GPRETN so that the AP can read it.

[15:12] Primary CPU 0x0 Sets the primary core. This information is passed to the AP during the boot sequence:0 Cortex-A53 core 0.1 Cortex-A53 core 1.2 Cortex-A53 core 2.3 Cortex-A53 core 3.4 Cortex-A57 core 0.5 Cortex-A57 core 1.6 Reserved.7 Reserved.

[11:4] BOOT_MAP:4 Cortex-A53 core 0.5 Cortex-A53 core 1.6 Cortex-A53 core 2.7 Cortex-A53 core 3.8 Cortex-A57 core 0.9 Cortex-A57 core 1.10 Reserved.11 Reserved.

0x0 Selects the cores that the SCP releases during the boot sequence:0 Hold.1 Release.

[3] BOOT_MAP_EN 0x0 Uses the Boot Map. When the Boot Map mechanism is disabled, the SCP releases only the Cortex-A53 core 0 by default:0 Disabled.1 Enabled.

[2] CFGEE 0x0 The SCP copies this value into CFGEE for the Cortex-A57 Cluster Static Configuration Register on page 3-108 and Cortex-A53 Cluster Static Configuration Register on page 3-109.

[1] CFGTE 0x0 The SCP copies this value into CFGTE for the Cortex-A57 Cluster Static Configuration Register on page 3-108 and Cortex-A53 Cluster Static Configuration Register on page 3-109.

[0] CRYPTODISABLE 0x0 The SCP copies this value into CRYPTODISABLE for the Cortex-A57 Cluster Static Configuration Register on page 3-108 and Cortex-A53 Cluster Static Configuration Register on page 3-109:0 Cryptographic extensions are enabled.1 Cryptographic extensions are disabled.


Programmers Model

Apps Alternative Boot Register


SCP Alternative Boot Register


Cortex-A57 PLL Control Register 0

The Cortex-A57 PLL Control Register 0 characteristics are:

Purpose Controls the Cortex-A57 PLL.




Figure 3-43 Cortex-A57 PLL Control Register 0 bit assignments

Table 3-55 Apps Alternative Boot Register bit assignments


[31:0] APP_ALT_BOOT 0x0 RO from APB interface.RW from Serial interface.

Application processor alternative boot register

Table 3-56 SCP Alternative Boot Register bit assignments


[31:0] SCP_ALT_BOOT 0x0 RO from APB interface.RW from Serial interface.

SCP alternative boot register

X_CLKF

31 048 7

Reserved

310 9 125

x_ENSATx_FASTEN

x_TESTx_BYPASSx_PWRDNReserved

x_FORCE_LOCK

x_RST_TIMER_BYPASSx_HARD_BYPASS

30 2829 16 15

x_PLL_RESETReserved

13 12 11

Reserved


Programmers Model


Note After boot up, the PLL is held in reset until this bit is updated.







Table 3-57 Cortex-A57 PLL Control Register 0 bit assignments


[31] x_PLL_RESET 0x1 RW PLL Reset.


[28:16] x_CLKF 0x3BF RW PLL feedback divider settings. Value = CLKF + 1.


[12] x_ENSAT 0x1 RW Controls the biasing of critical analog circuitry. This signal should only be set LOW under very special conditions.

[11] x_FASTEN 0x0 RW Enables fast locking mode.

Note This should not be used before consultation with True Circuits Inc.

[10] x_TEST 0x0 RW Manufacturing test mode to enable all dividers to be driven by the reference clock.

[9] x_BYPASS 0x0 RW Internally bypass the VCO to enable reference clock to pass through to the PLL output.

[8] x_PWRDN 0x0 RW Shutdown all analog circuitry in the PLL.


[4] x_FORCE_LOCK 0x0 RW Causes actual PLL lock signal to be ignored on the global PLL lock output, PLLS_LOCKED.


[1] x_RST_TIMER_BYPASS 0x0 RW An internal timer forces reset on each PLL for the required minimum period of 50µs. This bit bypasses the counter and enables direct control of the reset to the PLL.

[0] x_HARD_BYPASS 0x0 RW Completely multiplexes out the PLL to enable the reference clock to be driven directly into the design.


Programmers Model










x_CLKRx_CLKODx_BWADJReserved

31 08 7

Reserved

530

x_LOCK_STATUS

12 1124 23 6



[31] x_LOCK_STATUS 0x0 RO Current status of PLL lock signal


[23:12] x_BWADJ 0x1DF RW PLL loop bandwidth settings. See the PLL TRM

[11:8] x_CLKOD 0x1 RW PLL output divider settings Valuer = CLKOD + 1


[5:0] x_CLKR 0x17 RW PLL reference clock divider settings Value = CLKR + 1

X_CLKF

31 048 7

Reserved

310 9 125

x_ENSATx_FASTEN


x_FORCE_LOCK


30 2829 16 15

x_PLL_RESETReserved

13 12 11

Reserved


Programmers Model











[31] x_PLL_RESET 0x1 RW PLL reset.


[28:16] x_CLKF 0xFF RW PLL feedback divider settings. Value = CLKF + 1.














Programmers Model



GPU PLL Control Register 0

The GPU PLL Control Register 0 characteristics are:

Purpose Controls the GPU PLL.




Figure 3-47 GPU PLL Control Register 0 bit assignments

x_CLKODx_BWADJ x_CLKRReserved

31 0512 8 711

Reserved

30 24 23

x_LOCK_STATUS

6



[31] x_LOCK_STATUS 0x0 RO Current status of PLL lock signal.


[23:12] x_BWADJ 0x7F RW PLL loop bandwidth settings. See the PLL TRM.

[11:8] x_CLKOD 0x1 RW PLL output divider settings Value = CLKOD + 1.


[5:0] x_CLKR 0x7 RW PLL reference clock divider settings Value = CLKR + 1.

x_CLKF

31 0512 8 711

Reserved

30

Reserved

29 28 16 15 13

x_PLL_RESET

10 9 4 3 2 1

x_ENSATx_FASTEN


x_FORCE_LOCKReserved



Programmers Model



GPU PLL Control Register 1

The GPU PLL control Register 1 characteristics are:

Purpose Controls the GPU PLL.




Table 3-61 GPU PLL Control Register 0 bit assignments


[31] x_PLL_RESET 0x1 RW PLL reset.

[30:29] Reserved 0x0 RW -

[28:16] x_CLKF 0x3BF RW PLL feedback divider settings. Value = CLKF + 1.











[1] x_RST_TIMER_BYPASS 0x0 RW An internal timer forces reset on each PLL for the required minimum period of 50µs This bit bypasses the counter and enables direct control of the reset to the PLL.



Programmers Model

Figure 3-48 GPU PLL Control Register 1 bit assignments


SYS PLL Control Register 0

The SYS PLL Control Register 0 characteristics are:

Purpose Controls the System PLL.




Figure 3-49 SYS PLL Control Register 0 bit assignments


31 0512 8 711

Reserved

30

x_LOCK_STATUS

24 23 6

Table 3-62 GPU PLL Control Register 1 bit assignments




[23:12] x_BWADJ 0x1DF RW PLL loop bandwidth settings. See the PLL TRM.

[11:8] x_CLKOD 0x1 RW PLL output divider settings. Value = CLKOD + 1.


[5:0] x_CLKR 0x13 RW PLL reference clock divider settings. Value = CLKR + 1.

X_CLKF

31 048 7

Reserved

310 9 125

x_ENSATx_FASTEN


x_FORCE_LOCK


30 2829 16 15

x_PLL_RESETReserved

13 12 11

Reserved


Programmers Model



SYS PLL Control Register 1

The SYS PLL Control Register 1 characteristics are:

Purpose Controls the System PLL.




Table 3-63 SYS PLL Control Register 0 bit assignments




[28:16] x_CLKF 0x27F RW PLL feedback divider settings. Value = CLKF + 1.




Note Do not use before consultation with True Circuits Inc.










Programmers Model

Figure 3-50 SYS PLL Control Register 1 bit assignments


HDLCD PLL Control Register 0

The HDLCD PLL Control Register 0 characteristics are:

Purpose Controls the HDLCD PLL.




Figure 3-51 HDLCD PLL Control Register 0 bit assignments


31 0512 8 711

Reserved

30

x_LOCK_STATUS

24 23 6

Table 3-64 SYS PLL Control Register 1 bit assignments


[31] x_LOCK_STATUS 0x0 RO Current status of the PLL lock signal.


[23:12] x_BWADJ 0x13F RW PLL loop bandwidth settings. See the PLL TRM.

[11:8] x_CLKOD 0x1 RW PLL output divider settings. Value = CLKOD + 1.


[5:0] x_CLKR 0x9 RW PLL reference clock divider settingsValue = CLKR + 1.

X_CLKF

31 048 7

Reserved

310 9 125

x_ENSATx_FASTEN


x_FORCE_LOCK


30 2829 16 15

x_PLL_RESETReserved

13 12 11

Reserved


Programmers Model



HDLCD PLL Control Register 1

The HDLCD PLL Control Register 1 characteristics are:

Purpose Controls the HDLCD PLL.




Table 3-65 HDLCD PLL Control Register 0




[28:16] x_CLKF 0xC5 RW PLL feedback divider settings. Value = CLKF + 1.











[1] x_RST_TIMER_BYPASS 0x0 RW An internal timer forces reset on each PLL for the required minimum period of 50µs.This bit bypasses the counter and enables direct control of the reset to the PLL.



Programmers Model

Figure 3-52 HDLCD PLL Control Register 1 bit assignments


DDR3L PHY0 PLL Configuration Register

The DDR PHY0 PLL Configuration Register characteristics are:

Purpose Configures the DDR3L PHY0 PLL.




Figure 3-53 DDR3L PHY0 PLL Configuration Register bit assignments


31 0512 8 711

Reserved

30

x_LOCK_STATUS

24 23 6

Table 3-66 HDLCD PLL Control Register 1




[23:12] x_BWADJ 0x62 RW PLL loop bandwidth settings.See the PLL TRM.

[11:8] x_CLKOD 0x9 RW PLL output divider settings.Value = CLKOD + 1.


[5:0] x_CLKR 0x5 RW PLL reference clock divider settings.Value = CLKR + 1.

ReservedReserved

31 0112 8 711

PLL_RANGE

216 15

PLL_BYPASS_ENPLL_FBK_DIVPLL_REF_DIV


Programmers Model


Note The DMC-400 controls the DDR3L PHY1 PLL reset, i_pll_enable, during the PHY initialization sequence.

DDR3L PHY1 PLL Config Register

The DDR3L PHY1 PLL Configuration Register characteristics are:

Purpose Configures the DDR3L PHY0 PLL.




Figure 3-54 DDR3L PHY1 PLL Configuration Register bit assignments

Table 3-67 DDR3L PHY0 PLL Configuration Register bit assignments



[15:12] PLL_FBK_DIV 0x0 RW Feedback divider, M, selection bits.If M is 0, then it is divided by 16. For all other values of M, it is divided by M.

[11:8] PLL_REF_DIV 0x0 RW Reference divider, N, selection bits.If N is 0, then it is divided by 16. For all other values of N, it is divided by N.


[1] PLL_RANGE 0x1 RW Selects PHY PLL frequency range:0 PLL output clock frequency < 400Mhz.1 PLL output clock frequency >= 400Mhz.

[0] PLL_BYPASS_EN 0x0 RW Logic HIGH enables PHY PLL to operate under BYPASS mode. In this mode, i_pll_bypass_clk drives the PHY directly.

ReservedReserved

31 0112 8 711

PLL_RANGE

216 15

PLL_BYPASS_ENPLL_FBK_DIVPLL_REF_DIV


Programmers Model


Note The DMC-400 controls the DDR PHY1 PLL reset, i_pll_enable, during the PHY initialization sequence.

Cortex-A57 RF1P EMA Register

The Cortex-A57 RF1P EMA Register characteristics are:

Purpose Configures the Extra Margin Adjust (EMA) value of the Cortex-A57 processor cluster RF1P.




Figure 3-55 Cortex-A57 RF1P EMA Register bit assignments


Table 3-68 DDR3L PHY1 PLL Configuration Register bit assignments



[15:12] PLL_FBK_DIV 0x0 RW If N is 0, then it is divided by16. For all other values of N, it is divided by N.

[11:8] PLL_REF_DIV 0x0 RW Reference divider, N, selection bits.


[1] PLL_RANGE 0x1 RW Selects PHY PLL frequency range:0 PLL output clock frequency < 400Mhz.1 PLL output clock frequency >= 400Mhz.

[0] PLL_BYPASS_EN 0x0 RW Logic HIGH enables PHY PLL to operate under BYPASS mode. In this mode PHY is driven by i_pll_bypass_clk directly.

Reserved

31 06 5

EMAS

2

EMAW

34

EMA

Table 3-69 Cortex-A57 RF1P EMA Register bit assignments




Programmers Model

Cortex-A57 SRAM1P EMA Register

The Cortex-A57 SRAM1P EMA Register characteristics are:

Purpose Configures the EMA value of the Cortex-A57 processor cluster SRAM1P.




Figure 3-56 Cortex-A57 SRAM1P EMA Register bit assignments


Cortex-A53 RF1P EMA Register

The Cortex-A53 RF1P EMA Register characteristics are:

Purpose Configures the EMA value of the Cortex-A53 processor cluster RF1P.




[5] EMAS 1’b0 RW Read EMA

[4:3] EMAW 2’b00 RW Write EMA

[2:0] EMA 3’b011 RW Read, write margin adjustment

Table 3-69 Cortex-A57 RF1P EMA Register bit assignments (continued)


Reserved

31 06 5

EMAS

2

EMAW

34

EMA

Table 3-70 Cortex-A57 SRAM1P EMA Register bit assignments







Programmers Model

Figure 3-57 Cortex-A53 RF1P EMA Register bit assignments


Cortex-A53 SRAM1P EMA Register

The Cortex-A53 SRAM1P EMA Register characteristics are:

Purpose Configures the EMA value of the Cortex-A53 processor cluster SRAM1P.




Figure 3-58 Cortex-A53 SRAM1P EMA Register bit assignments


Reserved

31 06 5

EMAS

2

EMAW

34

EMA

Table 3-71 Cortex-A53 RF1P EMA Register bit assignments






Reserved

31 06 5

EMAS

2

EMAW

34

EMA

Table 3-72 Cortex-A53 SRAM1P EMA Register bit assignments







Programmers Model

PCIe MMU RF1P EMA Register

The PCIe MMU RF1P EMA Register characteristics are:

Purpose Configures the EMA value of the PCIe MMU RF1P.




Figure 3-59 PCIe MMU RF1P EMA Register bit assignments


Onchip Scratch RAM SRAM1P EMA Register

The Onchip Scratch RAM SRAM1P EMA Register characteristics are:

Purpose Configures the EMA value of the Onchip Scratch RAM SRAM1P.




Figure 3-60 Onchip Scratch RAM SRAM1P EMA Register bit assignments

Reserved

31 06 5

EMAS

2

EMAW

34

EMA

Table 3-73 PCIe MMU RF1P EMA Register bit assignments






Reserved

31 06 5

EMAS

2

EMAW

34

EMA


Programmers Model


Onchip Secure RAM SRAM1P EMA Register

The Onchip Secure RAM SRAM1P EMA Register characteristics are:

Purpose Configures the EMA value of the Onchip Secure RAM SRAM1P.




Figure 3-61 Onchip Secure RAM SRAM1P EMA Register bit assignments


Onchip Secure ROM ROM1P EMA Register

The Onchip Secure ROM ROM1P EMA Register characteristics are:

Purpose Configures the EMA value of the Onchip Secure ROM ROM1P.




Table 3-74 Onchip Scratch RAM SRAM1P EMA Register bit assignments






Reserved

31 06 5

EMAS

23

EMAWEMA

4

Table 3-75 Onchip Secure RAM SRAM1P EMA Register bit assignments







Programmers Model

Figure 3-62 Onchip Secure ROM ROM1P EMA Register bit assignments


Onchip Non-Secure ROM ROM1P EMA Register

The Onchip Non-Secure ROM ROM1P EMA Register characteristics are:

Purpose Configures the EMA value of the Onchip Non-Secure ROM ROM1P.




Figure 3-63 Onchip Non-Secure ROM ROM1P EMA Register bit assignments


GPU RF2P EMA Register

The GPU RF2P EMA Register characteristics are:

Purpose Configures the EMA value of the GPU RF2P.




Reserved

31 0

EMA

23

Table 3-76 Onchip Secure ROM ROM1P EMA Register bit assignments




Reserved

31 0

EMA

23

Table 3-77 Onchip Non-Secure ROM ROM1P EMA Register bit assignments





Programmers Model

Figure 3-64 GPU RF2P EMA Register bit assignments


GPU SRAM1P EMA Register

The GPU SRAM1P EMA Register characteristics are:

Purpose Configures the EMA value of the GPU SRAM1P.




Figure 3-65 GPU SRAM1P EMA Register bit assignments


Reserved

31 06 5

EMASA

23

EMAB

7

EMAA

Table 3-78 GPU RF2P EMA Register bit assignments



[6] EMASA 1’b0 RW Read EMA, port A

[5:3] EMAB 3’b011 RW Write margin adjustment, port B

[2:0] EMAA 3’b011 RW Read margin adjustment, port A

Reserved

31 06 5

EMAS

23

EMAWEMA

4

Table 3-79 GPU SRAM1P EMA Register bit assignments

Type Internal signal name Default Type Description






Programmers Model

GPU RF1P EMA Register

The GPU RF1P EMA Register characteristics are:

Purpose Configures the EMA value of the GPU RF1P.




Figure 3-66 GPU RF1P EMA Register bit assignments


PCIe RF1P EMA Register

The PCIe RF1P EMA Register characteristics are:

Purpose Configures the EMA value of the PCIe RF1P.




Figure 3-67 PCIe RF1P EMA Register bit assignments

Reserved

31 06 5

EMAS

23

EMAWEMA

4

Table 3-80 GPU RF1P EMA Register bit assignments






Reserved

31 06 5

EMAS

23

EMAWEMA

4


Programmers Model


PCIe RF2P EMA Register

The PCIe RF2P EMA Register characteristics are:

Purpose Configures the EMA value of the PCIe RF2P.




Figure 3-68 PCIe RF2P EMA Register bit assignments


HDLCD RF2P EMA Register

The HDLCD RF2P EMA Register characteristics are:

Purpose Configures the EMA value of the HDLCD RF2P.




Table 3-81 PCIe RF1P EMA Register bit assignments






Reserved

31 06 5

EMASA

23

EMAB

7

EMAA

Table 3-82 PCIe RF2P EMA Register bit assignments







Programmers Model

Figure 3-69 HDLCD RF2P EMA Register bit assignments


DMA RF2P EMA Register

The DMA RF2P EMA Register characteristics are:

Purpose Configures the EMA value of the DMA RF2P.




Figure 3-70 DMA RF2P EMA Register bit assignments


Reserved

31 06 5

EMASA

23

EMAB

7

EMAA

Table 3-83 HDLCD RF2P EMA Register bit assignments






Reserved

31 06 5

EMASA

23

EMAB

7

EMAA

Table 3-84 DMA RF2P EMA Register bit assignments







Programmers Model

HDLCD MMU RF1P EMA Register

The HDLCD MMU RF1P EMA Register characteristics are:

Purpose Configures the EMA value of the HDLCD MMU RF1P.




Figure 3-71 HDLCD MMU RF1P EMA Register bit assignments


USB MMU RF1P EMA Register

The USB MMU RF1P EMA Register characteristics are:

Purpose Configures the EMA value of the USB MMU RF1P.




Figure 3-72 USB MMU RF1P EMA Register bit assignments

Reserved

31 06 5

EMAS

23

EMAWEMA

4

Table 3-85 HDLCD MMU RF1P EMA Register bit assignments

Addr 0x1C0 Internal signal name Default Type Description





Reserved

31 06 5

EMAS

23

EMAWEMA

4


Programmers Model


DMA MMU RF1P EMA Register

The DMA MMU RF1P EMA Register characteristics are:

Purpose Configures the EMA value of the DMA MMU RF1P.




Figure 3-73 DMA MMU RF1P EMA Register bit assignments


SCP Onchip Secure ROM ROM1P EMA Register

The SCP Onchip Secure ROM ROM1P EMA Register characteristics are:

Purpose Configures the EMA value of the SCP Onchip Secure ROM ROM1P.




Table 3-86 USB MMU RF1P EMA Register bit assignments






Reserved

31 06 5

EMAS

23

EMAWEMA

4

Table 3-87 DMA MMU RF1P EMA Register bit assignments







Programmers Model

Figure 3-74 SCP Onchip Secure ROM ROM1P EMA Register bit assignments


SCP Onchip RAM SRAM1P EMA Register

The SCP Onchip RAM SRAM1P EMA Register characteristics are:

Purpose Configures the EMA value of the SCP Onchip RAM SRAM1P.




Figure 3-75 SCP Onchip RAM SRAM1P EMA Register bit assignments


PCSM Control Registers

The ADP has eight power-gated regions, and a separate PCSM controls the power sequencing of each. Five registers in the SCC control each PCSM. Table 3-90 on page 3-97 shows the base address of the PCSM Control registers. The SCC base address is 0xFFFF_F000.

Reserved

31 0

EMA

23

Table 3-88 SCP Onchip Secure ROM ROM1P EMA Register bit assignments




Reserved

31 06 5

EMAS

23

EMAWEMA

4

Table 3-89 SCP Onchip RAM SRAM1P EMA Register bit assignments







Programmers Model

Table 3-90 shows the base addresses of the PCSM control registers.

Note Entry and exit from retention mode can be achieved in a single clock cycle. It is recommended to use a default value of 0.

Table 3-90 Base addresses of PCSM control registers

PCSM base address Description

SCC base address +0x200 Cortex-A57 core 0 PCSM control registers

SCC base address+0x300 Cortex-A57 core 1 PCSM control registers

SCC base address+0x400 Cortex-A57 SCU & L2 PCSM control registers





SCC base address+0x900 Cortex-A53 SCU & L2 PCSM control registers


Programmers Model

3.8 MHU RegistersAddresses are relative to the base address of the MHU that the ADP memory map defines.

Table 3-91 shows the MHU registers in offset order from the base memory address.

Table 3-91 MHU Register summary

Offset Name Secure only Type Reset Description

0x000 SCP_INTR_L_STAT N RO 0x0000_0000 <n>_STAT Register on page 3-99

0x008 SCP_INTR_L_SET N WO - <n>_SET Register on page 3-100

0x010 SCP _INTR_L_CLEAR N WO - <n>_CLEAR Register on page 3-100

0x020 SCP_INTR_H_STAT N RO 0x0000_0000 <n>_STAT Register on page 3-99

0x028 SCP_INTR_H_SET N WO - <n>_SET Register on page 3-100

0x030 SCP _INTR_H_CLEAR N WO - <n>_CLEAR Register on page 3-100

0x100 CPU_INTR_L_STAT N RO 0x0000_0000 <n>_STAT Register on page 3-99

0x108 CPU_INTR_L_SET N WO - <n>_SET Register on page 3-100

0x110 CPU_INTR_L_CLEAR N WO - <n>_CLEAR Register on page 3-100

0x120 CPU_INTR_H_STAT N RO 0x0000_0000 <n>_STAT Register on page 3-99

0x128 CPU_INTR_H_SET N WO - <n>_SET Register on page 3-100

0x130 CPU_INTR_H_CLEAR N WO - <n>_CLEAR Register on page 3-100

0x200 SCP_INTR_S_STAT Y RO 0x0000_0000 <n>_STAT Register on page 3-99

0x208 SCP_INTR_S_SET Y WO - <n>_SET Register on page 3-100

0x210 SCP _INTR_S_CLEAR Y WO - <n>_CLEAR Register on page 3-100

0x300 CPU_INTR_S_STAT Y RO 0x0000_0000 <n>_STAT Register on page 3-99

0x308 CPU_INTR_S_SET Y WO - <n>_SET Register on page 3-100.

0x310 CPU_INTR_S_CLEAR Y WO - <n>_CLEAR Register on page 3-100

0x400 MHU_SCFG Y RW 0x0000_0000 MHU_SCFG Register on page 3-101

0xFD0 PID4 N RO 0x00000004 PID_4 Register on page 3-101

0xFE0 PID0 N RO 0x00000098 PID_0 Register on page 3-103

0xFE4 PID1 N RO 0x000000B0 PID_1 Register on page 3-102

0xFE8 PID2 N RO 0x0000001B PID_2 Register on page 3-102

0xFEC PID3 N RO 0x00000000 PID_3 Register on page 3-103

0xFF0 COMPID0 N RO 0x0000000D COMP_ID0 Register on page 3-103

0xFF4 COMPID1 N RO 0x000000F0 COMP_ID1 Register on page 3-104

0xFF8 COMPID2 N RO 0x00000005 COMP_ID2 Register on page 3-104

0xFFC COMPID3 N RO 0x000000B1 COMP_ID3 Register on page 3-105


Programmers Model

Because each interrupt line contains three similar control and status registers that are associated with it, the following sections describe these three registers together, where <n> is replaced by one of the following for its associated interrupt line:

SCP_INTR_L Low priority Non-secure interrupt from the SCP to the application processor.

SCP_INTR_H High priority Non-secure interrupt from the SCP to the application processor.

CPU_INTR_L Low priority Non-secure interrupt from the application processor to the SCP.

CPU_INTR_H High priority Non-secure interrupt from the application processor to the SCP.

CPU_INTR_S Secure interrupt from the application processor to the SCP.

SCP_INTR_S Secure interrupt from the SCP to the application processor.


This section describes the MHU registers. Table 3-91 on page 3-98 provides cross references to individual registers.

<n>_STAT Register

The <n>_STAT Register characteristics are:

Purpose Low priority Non-secure interrupt status register, from the SCP to the application processor. It shows the status of all 32 bits of the register that drives the associated interrupt line. If any of the bits are set in the register, then the associated interrupt line is asserted.

Note For the SCP_INTR_S_STAT register that controls the Secure interrupt to

the application processor, bit 31 also denotes an access violation when the SVIEN field in the MHU_SCFG register is set HIGH.




Figure 3-76 <n>_STAT Register bit assignments


31 0

n_<stat>

Table 3-92 <n>_STAT Register bit assignments


[31:0] <n>_STAT If any of these bits are set, then the associated interrupt line is asserted


Programmers Model

<n>_SET Register

The <n>_SET Register characteristics are:

Purpose Low priority Non-secure interrupt set register, from the SCP to the application processor. It sets bits in the associated <n>_STAT register. When read, it always returns 0x0000_0000.




Figure 3-77 <n>_SET Register bit assignments


<n>_CLEAR Register

The <n>_CLEAR Register characteristics are:

Purpose Low priority Non-secure interrupt clear register, from the SCP to the application processor. It clears bits in the associated <n>_STAT register. When read, it always returns 0x0000_0000.




Figure 3-78 <n>_CLEAR Register bit assignments


31 0

n_<set>

Table 3-93 <n>_SET Register bit assignments


[31:0] <n>_SET Setting any bit in this 32-bit field HIGH sets the corresponding bit in the associated <n>_STAT register.Setting LOW has no effect.

31 0

n_<clear>

Table 3-94 <n>_CLEAR Register bit assignments


[31:0] <n>_CLEAR You can set these bits as follows:0 No effect.1 Writing a 1 to any bit in this 32-bit field clears the

corresponding bit in the associated <n>_STAT register.


Programmers Model

MHU_SCFG Register

The MHU_SCFG Register characteristics are:

Purpose MHU Secure configuration register that enables or disables the raising of interrupts when access security violations occur. This means that a Non-secure access attempts to access a Secure only access register. When enabled, and an access security violation occurs, bit 31 of the INTR_S_STAT register, that controls the MHU_SCP_ INTR_S Secure interrupt to the application processor, is set HIGH.




Figure 3-79 MHU_SCFG Register bit assignments


PID Registers

The PID Registers characteristics are:




PID_4 Register


Figure 3-80 MHU_PID_4 Register bit assignments

31 0

n_<set>

Table 3-95 MHU_SCFG register bit assignments



[0] SVIEN Secure Violation Interrupt Enable. You can set this bit as follows:0 Disables interrupts.1 Enables an interrupt to be raised by setting bit 31 of the INTR_S_STAT register

when a security violation occurs.

DES_2SIZEReserved

31 08 7 4 3


Programmers Model


PID_1 Register




PID_2 Register




Table 3-96 MHU PID_4 register



[7:4] SIZE Indicates the log2 of the number of 4KB blocks that the interface occupies. Set to 0x0.

[3:0] DES_2 JEP106 continuation code that identifies the designer. Set to 0x4 for ARM.

PART_1DES_0Reserved

31 08 7 4 3

Table 3-97 MHU PID_1 register bit assignments



[7:4] DES_0 Bits [3:0] of the JEP Identity. Set to 0xB for ARM.


REVISIONReserved

31 08 7 4 3

JEDECDES_1

2




[7:4] REVISION Set to 0x1 for r1p0.

[3] JEDEC Set to 0x1

[2:0] DES_1 Bits [6:4] of the Designer field. Set to 0x3 for ARM.


Programmers Model

PID_3 Register




PID_0 Register




COMP_ID Registers





COMP_ID0 Register


ReservedReserved

31 08 7





PART_0Reserved

31 08 7






Programmers Model

Figure 3-85 COMP_ID0 Register bit assignments


COMP_ID1 Register


Figure 3-86 MHU COMP_ID1 Register bit assignments


COMP_ID2 Register




COMP_ID0Reserved

31 08 7

Table 3-101 MHU COMP_ID0 register bit assignments




COMP_ID1Reserved

31 08 7

Table 3-102 MHU COMP_ID1 Register bit assignments




COMP_ID2Reserved

31 08 7






Programmers Model

COMP_ID3 Register




COMP_ID3Reserved

31 08 7




[7:0] COMP_ID3 Reads as 0xB1


Programmers Model

3.9 ADP System Control RegistersThese registers configure the ADP, including clocks and resets. You can only access these registers from the Cortex-M3 SCP. Some components in the system have a set of inputs that must be fixed to 1 or 0 before reset is de-asserted. You have flexibility in configuring these inputs using the SCP firmware, but you must follow any changes by resetting the system.

All unmapped and unused addresses within the 4KB region that the ADP System Control registers occupy are reserved, and accesses targeting them are RAZ, WI.

This section describes:• Register Summary.• Register descriptions on page 3-108.

3.9.1 Register Summary

Table 3-105 shows the registers in offset order from the base memory address.

Table 3-105 System Control Registers summary


0x000 Cortex-A57 cluster Static Configuration - - 32 Cortex-A57 Cluster Static Configuration Register on page 3-108

0x004 Cortex-A53 cluster Static Configuration - - 32 Cortex-A53 Cluster Static Configuration Register on page 3-109

0x008 Mali-T624 Configuration - - 32 Mali-T624 Configuration Register on page 3-110

0x00C System Profiler configuration - - 32 System Profiler Configuration Register on page 3-111

0x010 System Profiler Disable Register - - 32 System Profiler Disable Register on page 3-112

0x014 AArch64 Reset Vector Base Address Register

- - 32 AArch64 Reset Vector Base Address Register on page 3-113

0x100 A57CLK Clock Control Register - - 32 Cluster Clock Control Register on page 3-113

0x104 A53CLK Clock Control Register - - 32

0x108 GPUCLK Clock Control Register - - 32

0x10C DMCCLK Clock Control Register - - 32 DMC-400 Clock Control Register on page 3-115

0x200 ATCLK Clock Control Register - - 32 Internal Clock Control Register on page 3-116

0x204 CCICLK Clock Control Register - - 32

0x208 NICSCPCLK Clock Control Register - - 32

0x20C NICPERCLK Clock Control Register - - 32

0x210 SPCLK Clock Control Register - - 32

0x214 GICCLK Clock Control Register - - 32

0x218 - - - - Reserved

0x21C TRACECLKIN Clock Control Register - - 32 Internal Clock Control Register on page 3-116


Programmers Model

0x220 PCLKDBG Clock Control Register - - 32 PCLKDBG Clock Control Register on page 3-118

0x300 System Clock Enable Status Register - - 32 System Clock Enable Status Register on page 3-119

0x304 System Clock Enable Set Register - - 32 System Clock Enable Set Register on page 3-119

0x308 System Clock Enable Clear Register - - 32 System Clock Enable Clear Register on page 3-119

0x30C System Clock Force Status Register - - 32 System Clock Force Status Register on page 3-121

0x310 System Clock Force Set Register - - 32 System Clock Force Set Register on page 3-121

0x314 System Clock Force Clear Register - - 32 System Clock Force Clear Register on page 3-121

0x318 Clock Stopped Status Register - - 32 Clock Stopped Status Register on page 3-123

0x31C Clock Stopped Set Register - - 32 Clock Stopped Set Register on page 3-122

0x320 Clock Stopped Clear Register - - 32 Clock Stopped Clear Register on page 3-122

0x400 SCP Control Register - - 32 SCP Control Register on page 3-124

0x404 SCP Status Register - - 32 System Status Register on page 3-125

0x408 - - - - Reserved

0x40C Cortex-A57 cluster Snoop Access Control Register

- - 32 Cortex-A57 Snoop Access Control Register on page 3-125

0x410 Cortex-A53 cluster Snoop Access Control Register

- - 32 Cortex-A53 Snoop Access Control Register on page 3-126

0x414 Cortex-A57 cluster L2 Flush Control Register

- - 32 Cortex-A57 L2 Flush Control Register on page 3-126

0x418 Cortex-A53 cluster L2 Flush Control Register

- - 32 Cortex-A53 L2 Flush Control Register on page 3-127

0x500 Reset Syndrome Register - - 32 Reset Syndrome Register, RSR on page 3-128

0x504 System Manual Reset Status Register - - 32 System Manual Reset Status Register on page 3-129

0x508 System Manual Reset Set Register - - 32 System Manual Reset Set Register on page 3-129

0x50C System Manual Reset Clear Register - - 32 System Manual Reset Clear Register on page 3-129

0x510 Cortex-A57 Manual Reset Status Register - - 32 Cortex-A57 Manual Reset Status Register on page 3-130

0x514 Cortex-A57 Manual Reset Set Register - - 32 Cortex-A57 Manual Reset Set Register on page 3-130

Table 3-105 System Control Registers summary (continued)



Programmers Model


This section describes the ADP System Control registers. Table 3-105 on page 3-106 provides cross references to individual registers.

Cortex-A57 Cluster Static Configuration Register

The Cortex-A57 Cluster Static Configuration Register characteristics are:

Purpose Drives configuration inputs to the Cortex-A57 cluster. Under normal circumstances, SCP firmware programs these values prior to power up and reset de-assertion of the cluster.




Figure 3-89 Cortex-A57 Cluster Static Configuration Register bit assignments


0x518 Cortex-A57 cluster Manual Reset Clear Register

- - 32 Cortex-A57 Manual Reset Clear Register on page 3-131

0x51C Cortex-A53 cluster Manual Reset Status Register

- - 32 Cortex-A53 Manual Reset Status Register on page 3-131

0x520 Cortex-A53 cluster Manual Reset Set Register

- - 32 Cortex-A53 Manual Reset Set Register on page 3-132

0x524 Cortex-A53 cluster Manual Reset Clear Register

- - 32 Cortex-A53 Manual Reset Clear Register on page 3-132

Table 3-105 System Control Registers summary (continued)


ReservedReserved

31 0

CFGEND

41213 10 8 7

SYSBARDISABLE

3569141516171819

ReservedVINITHI

CRYPTODISABLEReserved

ReservedCFGTE

Table 3-106 Cortex-A57 Cluster Static Configuration Register bit assignments

Bits Name Type Default Description

[31:19] - RO 0x0 Reserved. Read as zero.

[18] SYSBARDISABLE RW 0x0 Disables ACE barrier requests.



Programmers Model

See the ARM® Cortex®-A57 MPCore Technical Reference Manual.

Cortex-A53 Cluster Static Configuration Register

The Cortex-A53 Cluster Static Configuration Register characteristics are:

Purpose Drives configuration inputs to the Cortex-A53 cluster. Under normal circumstances, the SCP firmware programs these values prior to power up and reset de-assertion of the cluster.




Figure 3-90 Cortex-A53 Cluster Static Configuration Register bit assignments

[15:14] VINITHI RW 0x1 This pin is only sampled during reset.14 Bit 14 controls core 0.15 Bit 15 controls core 1.

[13] CRYPTODISABLE RW 0x0 Disables cryptographic extensions. This pin is only sampled during reset of the processor.


[9:8] CFGTE RW 0x0 Individual processor control of the default exception handling state. It sets the initial value of the TE bit in the CP15 System Control Register, SCTLR.The processor only samples this control during reset.8 Bit 8 controls core 0.9 Bit 9 controls core 1.


[5:4] CFGEND RW 0x0 Individual processor control of the endianness configuration at reset. It sets the initial value of the EE bit in the CP15 System Control Register, SCTLR.The processor only samples this control during reset.4 Bit 4 controls core 0.5 Bit 5 controls core 1.


Table 3-106 Cortex-A57 Cluster Static Configuration Register bit assignments (continued)


ReservedReserved

31 0

CFGEND

41213 8 7

SYSBARDISABLE

314171819

VINITHICRYPTODISABLE

CFGTE

11

Reserved


Programmers Model



Mali-T624 Configuration Register

The Mali-T624 Static Configuration Register characteristics are:

Purpose Describes the configuration values required for the Mali-T624 GPU.




Table 3-107 Cortex-A53 Cluster Static Configuration Register bit assignments



[18] SYSBARDISABLE RW 0x0 Disables ACE barrier requests.

[17:14] VINITHI RW 0x1 Enable high exception vectors when booting in 32-bit state for each Cortex-A53 core. This pin is only sampled during reset:14 Bit 14 controls core 0.15 Bit 15 controls core 1.16 Bit 16 controls core 2.17 Bit 17 controls core 3.

[13] CRYPTODISABLE RW 0x0 Disables cryptographic extensions. This pin is only sampled during reset of the core.

[12] - RO 0x0 Reserved. Read as zero.

[11:8] CFGTE RW 0x0 Individual core control of the default exception handling state. It sets the initial value of the TE bit in the CP15 System Control Register, SCTLR.The core only samples the control during reset:8 Bit 8 controls core 0.9 Bit 9 controls core 1.10 Bit 10 controls core 2.11 Bit 11 controls core 3.

[7:4] CFGEND RW 0x0 Individual core control of the endianness configuration at reset. It sets the initial value of the EE bit in the CP15 System Control Register, SCTLR.The core only samples the control during reset:4 Bit 4 controls core 0.5 Bit 5 controls core 1.6 Bit 6 controls core 2.7 Bit 7 controls core 3.



Programmers Model

Figure 3-91 Mali-T624 Static Configuration Register bit assignments


System Profiler Configuration Register

The System Profiler Configuration Register characteristics are:

Purpose For System Profiler latency measurements, you can configure the start and end points for the read, write, and snoop channels are using inputs to the System Profiler. The System Profiler only samples the bits in this register on a reset of the AXI interface. This corresponds to a reset of the peripheral NIC-400.




Figure 3-92 System Profiler Configuration Register bit assignments

Reserved

31 0

BARRIERDISABLE

1

Table 3-108 Mali-T624 Static Configuration Register



[0] BARRIERDISABLE RW 0x0 Normally, the Mali-T624 issues ACE-Lite barrier requests at the end of cache flush operations. If the system does not support barriers, you can disable them by tying the BARRIERDISABLE input HIGH.The ADP is designed to handle barriers that the Mali-T624 GPU issues. However, if barriers are not required, setting this bit HIGH prevents the Mali-T624 from issuing barriers.

Note This signal must not toggle during GPU operation.

Reserved

31 04

SYSBARDISABLE

356

SPREADSTART

SPWRITESTARTSPWRITEEND

2 1

SPSNOOPEND

SPREADEND


Programmers Model


System Profiler Disable Register

The System Profiler Disable Register characteristics are:

Purpose Disables the entire System Profiler. You can use this when the System Profiler is not required. All logic is clock-gated, and any register access to the System Profiler returns a slave error. The two bits in this register have the same function, but different effectiveness:1. The SOFTMSTRDIS bit only disables the system profiler until the

next reset of the SYSTOP power domain. This occurs when there is a power down of the SYSTOP power domain or the PPU reset conditions that Internal reset generation on page 2-16 describes.

2. The POMSTRDIS bit disables the System Profiler until a power up reset, nPORESET, occurs.




Figure 3-93 System Profiler Disable Register bit assignments

Table 3-109 System Profiler Configuration Register


[31:6] - RO 0x0 Reserved, read as zero.

[5] SPREADSTART RW 0x1 System Profiler Read Start. Sets the condition that the System Profiler uses to detect the start of a read transaction.

[4] SPREADEND RW 0x1 System Profiler Read End. Sets the condition that the System Profiler uses to detect the end of a read transaction.

[3] SPWRITESTART RW 0x1 System Profiler Write Start. Sets the condition that the System Profiler uses to detect the start of a write transaction.

[2] SPWRITEEND RW 0x1 System Profiler Write End. Sets the condition that the System Profiler uses to detect the end of a write transaction.

[1] SPSNOOPSTART RW 0x1 System Profiler Snoop Start. Sets the condition that the System Profiler uses to detect the start of a snoop transaction.

[0] SPSNOOPEND RW 0x1 System Profiler Snoop End. Sets the condition that the System Profiler uses to detect the end of a snoop transaction.

Reserved

31 0

SOFTMSTRDISPOMSTRDIS

2 1


Programmers Model


AArch64 Reset Vector Base Address Register

The AArch64 Reset Vector Base Address Register characteristics are:

Purpose Configures the AArch64 Reset Vector Base Address.




Figure 3-94 AArch64 Reset Vector Base Address Register bit assignments


Cluster Clock Control Register

A separate register exists for each of the cluster clocks as follows:• A57CLK Clock Control Register.• A53CLK Clock Control Register.• GPUCLK Clock Control Register.

Table 3-110 System Profiler Disable Register


[31:2] - RO 0x0 Reserved

[1] SOFTMSTRDIS RW 0x0 Soft System Profiler disable. This is reset on SYSTOP power down or SYSTOP reset.

[0] POMSTRDIS RW 0x0 Power On Reset System Profiler disable. This is only reset when a power up reset, nPORESET, occurs.

RVBAR

31 0

Reserved

2 1

Table 3-111 AArch64 Reset Vector Base Address Register bit assignments


[31:2] RVBAR RW 0x0 Provides bits [31:2] of the reset value of the RVBAR_EL3 register in the Cortex-A57 and Cortex-A53. This value is used as the address that execution starts from when the processor is in 64-bit state. All other bits of RVBAR_EL3 are zero.This value drives bits [31:2] of all of the RVBARADDRx inputs to the Cortex-A57 and Cortex-A53 processors.Where:For Cortex-A57 x is 0 or 1.For Cortex-A53 x is 0, 1, 2, or 3.These pins are only sampled during reset of the processor.



Programmers Model

Each register has the fields that Table 3-112 describes.


Figure 3-95 Cluster Clock Control Register bit assignments


CRNTCLK CLKSELLPI ENTRY DELAY

31 0

CLKDIVSYS

412 11 8 7 3

CLKDIVEXT

24 23 20 19 16 15

CRNTCLKDIVSYSCRNTCLKDIVEXT

Table 3-112 Cluster Clock Control Register bit assignments


[31:24] LPI ENTRY DELAY RW 0x00 Delay between CACTIVE and CSYSREQ for dynamic LPI clock gating of GPU MMU-400 Bus Interface Clock.

Note Only supported for GPUCLK Clock Control Register, field is RESERVED for other clock control registers.

[23:20] CRNTCLKDIVEXT RO 0x0 Acknowledges the currently active clock divider value when xINCLK is the clock source. The divider value is the value of CRNTCLKDIVEXT + 1.For example, setting 0 indicates a divider value of 1.

[19:16] CRNTCLKDIVSYS RO 0x0 Acknowledges the currently active clock divider value when SYSREFCLK or SYSINCLK is the clock source. The divider value is the value of CRNTCLKDIVSYS + 1.For example, setting 0 indicates a divider value of 1.

[15:12] CRNTCLK RO 0x0 Acknowledges the currently active clock source being used as the input to the clock divider:0000 Output-gated.0001 SYSREFCLK.0010 SYSINCLK.0100 Cluster-specific input clock, A57INCLK, A53INCLK, or

GPUINCLK.


Programmers Model

DMC-400 Clock Control Register

The DMC-400 Clock Control Register characteristics are:

Purpose Controls the DMCCLK and DMCAUXCLK frequencies. These clocks are synchronous, but you program them to have a 1:1 or a 1:2 relationship.Set the clock divider, CLKDIV, field for the required DMCCLK frequency. If you require a 1:2 relationship, set the DMCCLKRATIO bit to 1. This specifies that DMCAUXCLK is double the frequency of DMCCLK. Otherwise, both clocks run at the same frequency.In the case that they are the same frequency, do not use DMCAUXCLK, but use DMCCLK externally for DMC synchronous clocking.

Usage constraints You must program DMCCLK to be twice the required DMC-400 clock frequency and you must disable DMCAUXCLK.



Figure 3-96 DMCCLK Clock Control Register bit assignments

[11:8] CLKDIVEXT RW 0xF Requests a new clock divider value when xINCLK is the clock source.The divider value is the value of CLKDIVEXT + 1.For example, setting 0 indicates a divider value of 1.

[7:4] CLKDIVSYS RW 0xF Requests a new clock divider value when SYSREFCLK or SYSINCLK is the clock source.The divider value is the value of CLKDIVSYS + 1.For example, setting 0 indicates a divider value of 1.

[3:0] CLKSEL RW 0x1 Requests a new clock source to be used as the input to the clock divider:0000 Output-gated.0001 SYSREFCLK.0010 SYSINCLK.0100 Cluster-specific input clock, A57INCLK, A53INCLK, or

GPUINCLK.All other values are reserved.

Table 3-112 Cluster Clock Control Register bit assignments (continued)


CLKDIV CLKSELReserved

31 0

DMCAUXCLKEN

48 7 3

DMCCLKRATIO

91020 19 16 15 1112

ReservedCRNTCLK

CRNTCLKDIV


Programmers Model


Internal Clock Control Register

The following clock control registers exist for each of the internal clocks:

ATCLK ATCLK Control Register.

Note ATCLK generates PCLKDBG.

CCICLK CCICLK Control Register.

NICSCPCLK NICSCPCLK Control Register.

NICPERCLK NICPERCLK Control Register.

SPCLK SPCLK Control Register.

Table 3-113 DMCCLK Clock Control Register bit assignments



[19:16] CRNTCLKDIV RW 0xF Acknowledges the currently active divider value.The divider value is CLKDIV + 1.For example, setting 0 indicates a divider value of 1.

[15:12] CRNTCLK RO 0x0 Acknowledges the currently active clock source being used as the input to the clock divider:0000 Output-gated.0001 REFCLK.0010 SYSINCLK.


[9] DMCCLKRATIO RW 0x0 Setting this bit to 1 enables a 1:2 ratio between the DMCCLK and DMCAUXCLK clocks, and the clocks are still synchronous.If you set this, you must set the CLKSEL/DIV settings in this register to provide the frequency for the DMCCLK. DMCAUXCLK is then twice that frequency:0 DMC:AUX Clock Ratio is 1:1.1 DMC:AUX Clock Ratio is 1:2.

[8] DMCAUXCLKEN RW 0x1 This bit enables the DMCAUXCLK clock as follows:0 Disables the DMCAUXCLK clock.1 Enables the DMCAUXCLK clock.

[7:4] CLKDIV RW 0xF Requests a new clock divider value.The divider value is CLKDIV + 1.For example, setting a value of 0 indicates a divider value of 1.

[3:0] CLKSEL RW 0x1 Requests a new clock source to use as the input to the clock divider. You can set these bits as follows:0000 Output-gated.0001 REFCLK.0010 SYSINCLK.All other values are reserved.


Programmers Model

GICCLK GICCLK Control Register.

TRACECLKIN TRACECLKIN Control Register.

Each register has the fields that Table 3-114 shows.

Note ATCLK generates PCLKDBG.

The Internal Clock Control Register characteristics are:

Purpose Configures internal clock control.




Figure 3-97 Internal clock control Register bit assignments


CRNTCLKLPI ENTRY DELAY CLKDIV CLKSELReserved

31 048 7 324 23 16 15 12 11

CRNTCLKDIV

Table 3-114 Internal clock control Register bit assignments



[23:16] LPI ENTRY DELAY RW 0x00 Delay between CACTIVE and CSYSREQ for dynamic LPI clock-gating.

Note Only supported for CCICLK, NICSCPCLK, NICPERCLK, and SPCLK Control Registers. This is reserved for other clock control registers.

[15:12] CRNTCLKDIV RO 0xF Acknowledges the currently active clock divider value.The divider value is the value of CRNTCLKDIV + 1.For example, setting 0 indicates a divider value of 1.


Programmers Model

PCLKDBG Clock Control Register

The PCLKDBG Clock Control Register characteristics are:

Purpose Controls the divide ratio used to generate PCLKDBG from ATCLK.




Figure 3-98 PCLKDBG clock control Register bit assignments


[11:8] CRNTCLK RO 0x0 Acknowledges the currently active clock source being used as the input to the clock divider:0000 Output-gated.0001 REFCLK.0010 SYSINCLK.

[7:4] CLKDIV RW 0xF Requests a new clock divider value.The divider value is the value of CLKDIV + 1.For example, setting a value of 0 indicates a divider value of 1.

[3:0] CLKSEL RW 0x1 Requests a new clock source to use as the input to the clock divider. You can set these bits as follows:0000 Output-gated.0001 REFCLK.0010 SYSINCLK.All other values are reserved.

Table 3-114 Internal clock control Register bit assignments (continued)


Reserved CLKDIV ReservedReserved

31 048 7 316 15 12 11

CRNTCLKDIV

Table 3-115 PCLKDBG clock control Register bit assignments


[31:16] - RO 0x0 Reserved.

[15:12] CRNTCLKDIV RO 0xF Acknowledges the currently active clock divider value.The divider value is the value of CRNTCLKDIV + 1.For example, setting 0 indicates a divider value of 1.


Programmers Model

System Clock Enable Set Register

The System Clock Enable Set Register characteristics are:

Purpose This is a write-only register.Writing a 1 to any bit position in this register enables the relevant clock.Writing a 0 to any position has no effect on the clock enable.If read, this returns all zeros. Bit mappings are the same as the System Clock Enable Status Register. See System Clock Enable Status Register.



System Clock Enable Clear Register

The System Clock Enable Clear Register characteristics are:

Purpose This is a write-only register.Writing a 1 to any bit position in this register disables the relevant clock.Writing a 0 to any position has no effect on the clock enable.If read, this register returns all zeros.Bit mappings are the same as the System Clock Enable Status Register. See System Clock Enable Status Register.



System Clock Enable Status Register

The System Clock Enable Status Register characteristics are:

Purpose This read-only register contains the current status of the clock enables for all the clocks. You can set or clear clock enables individually using the relevant set or clear registers. See:• System Clock Enable Set Register.• System Clock Enable Clear Register.





[7:4] CLKDIV RW 0xF Requests new clock divider value.The divider value is the value of CLKDIV + 1.For example, setting 0 indicates a divider value of 1.


Table 3-115 PCLKDBG clock control Register bit assignments (continued)



Programmers Model

Figure 3-99 System Clock Enable Status Register bit assignments


Note Only enable or access the Juno System Profiler if the CCI-400 and DMC-400 clocks are enabled.

Reserved

31 045 126 3

A57CLKENA53CLKEN

GPUCLKEN

NICSCPCLKEN

ATCLKENCCICLKEN

1011 7812 9

NICPERCLKENDMCCLKEN

ReservedGICCLKEN

TRACECLKINENReserved

13

PCLKDBGEN

Table 3-116 Clock Enable Status Register bit assignments

Bits Name Default Description

[31:13] - 0x0 Reserved. Read as zero, write ignore.

[12] A57CLKEN 0x1 Clock enable status for the Cortex-A57 processor clock.

[11] A53CLKEN 0x1 Clock enable status for the Cortex-A53 processor clock.

[10] GPUCLKEN 0x0 Clock enable status for the GPU clock.

[9] ATCLKEN 0x0 Clock enable status for the AT clock.

[8] CCICLKEN 0x1 Clock enable status for the CCI-400 clock.

[7] NICSCPCLKEN 0x1 Clock enable status for the SCP NIC-400 clock.

[6] NICPERCLKEN 0x0 Clock enable status for the peripheral NIC-400 clock.

[5] DMCCLKEN 0x1 Clock enable status for the DMC-400 clock.

[4] - 0x0 Reserved. Read as zero, write ignore.

[3] GICCLKEN 0x1 Clock enable status for the GIC-400 clock.

[2] - 0x0 Reserved. Read as zero, write ignore.

[1] TRACECLKINEN 0x0 Clock enable status for the TRACECLKIN clock.

[0] PCLKDBGEN 0x0 Clock enable status for the debug clock.


Programmers Model

System Clock Force Set Register

The System Clock Force Set Register characteristics are:

Purpose This is a write-only register. The operation is as follows:• Writing a 1 to any bit position forces the relevant clock on regardless

of any other enable or internal clock control.• Writing a 0 to any position has no effect on the clock force.• If read, it returns all zeros.Bit mappings are the same as System Clock Force Status Register.



System Clock Force Clear Register

The System Clock Force Clear Register characteristics are:

Purpose This is a write-only register. The operation is as follows:• Writing a 1 to any bit position disables the relevant clock force. The

clock behavior depends on other clock control setting and signaling.• Writing a 0 to any position has no effect on the clock force.• If read, this register returns all zeros.Bit mappings are the same as System Clock Force Status Register.



System Clock Force Status Register

The System Clock Force Status Register characteristics are:

Purpose This read-only register contains the current status of all clock forces. You can set or clear clock forces individually using the relevant set and clear registers.

Note Setting the clock force enables the clock regardless of enable bits and other

clock controls in the system.





Programmers Model

Figure 3-100 System Clock Force Status Register bit assignments


Clock Stopped Set Register

The Clock Stopped Set Register characteristics are:

Purpose This is a write-only register. The operation is as follows:• Writing a 1 to any bit position in this register sets the relevant clock

stopped bit in the Clock Stopped Status Register on page 3-123.• Writing a 0 to any position has no effect on the clock stopped bit. • When read, it returns all zeros.Bit mappings and functional description are the same as Clock Stopped Status Register on page 3-123.



Clock Stopped Clear Register

The Clock Stopped Clear Register characteristics are:

Purpose The operation is as follows:• Writing a 1 to any bit position in this register clears the relevant

clock stopped bit in the Clock Stopped Status Register.

Reserved

31 0456 3

NICSCPCLKFORCECCICLKFORCE

789

NICPERCLKFORCEReserved

SPCLKFORCEReserved

10

GPUCLKFORCE

Table 3-117 Clock Force Status Register bit assignments


[31:10] - 0x0 Reserved. Read as zero.

[9] GPUCLKFORCE 0x0 Clock Force Status for GPU MMU-400 Bus Interface Clock

[8] CCICLKFORCE 0x0 Clock force status for the CCI-400 clock.

[7] NICSCPCLKFORCE 0x0 Clock force status for the SCP NIC-400 clock.

[6] NICPERCLKFORCE 0x0 Clock force status for the peripheral NIC-400 clock.

[5] - 0x0 Reserved. Read as zero.

[4] SPCLKFORCE 0x0 Clock force status for the System Profiler clock.



Programmers Model

• Writing a 0 to any position has no effect on the clock enable.• When read, it returns all zeros.Bit mappings and functional description are the same as Clock Stopped Status Register.



Clock Stopped Status Register

The Clock Stopped Status Register characteristics are:

Purpose The clock stopped bits are set when the related clock is not running. This permits clocks that use these inputs as sources to switch while some of the sources are not running.The bits are set to:1 When the related clock is running.0 When the related clock is stopped.This read-only register contains the current status of the clock stopped registers. You can set and clear clock stopped register bits individually using the relevant set and clear registers. See:• Clock Stopped Set Register on page 3-122.• Clock Stopped Clear Register.




Figure 3-101 Clock Stopped Status Register bit assignments


Reserved

31 04 3

A57INCLKSTOPPEDA53INCLKSTOPPED

GPUINCLKSTOPPEDSYSINCLKSTOPPED

2 1

Table 3-118 Clock Stopped Status Register bit assignments


[31:4] - 0x0 Reserved, read as zero

[3] A57INCLKSTOPPED 0x1 Control signal for use in clock-generation. Required to be set when A57INCLK is not running. Never set this bit when the clock is running.


Programmers Model

SCP Control Register

The SCP Control Register characteristics are:

Purpose Contains the SCP controls for peripherals.




Figure 3-102 SCP control Register bit assignments


[2] A53INCLKSTOPPED 0x1 Control signal for use in clock-generation. Required to be set when A53INCLK is not running. Never set this bit when the clock is running.

[1] GPUINCLKSTOPPED 0x1 Control signal for use in clock-generation. Required to be set when GPUINCLK is not running. Never set this bit when the clock is running.

[0] SYSINCLKSTOPPED 0x1 Control signal for use in clock-generation. Required to be set when SYSINCLK is not running. Never set this bit when the clock is running.

Table 3-118 Clock Stopped Status Register bit assignments (continued)


Reserved

31 04

SCPSYSREMAPEN

2 15

REFCLKREQFORCE

6

M3HCLKFORCEReserved

Table 3-119 SCP control Register bit assignments


[31:6] - RO 0x0 Reserved, read as zero

[5] M3HCLKFORCE RW 0x0 Disable automatic clock gating of the HCLK input to the Cortex-M3 processor when the Cortex-M3 processor is in sleep mode. Only set this bit HIGH when you require self-hosted debug of the Cortex-M3 processor.


[1] SCPSYSREMAPEN RW 0x0 Self-managed remap to return an error response for SCP accesses to the application processor memory map. This is intended to be used when SYSTOP region is OFF to help debug potential system hang scenarios. When set to 0x1, any access from the SCP that targets the application processor memory map is blocked, and an error response is generated.

[0] REFCLKREQFORCE RW 0x0 Forces the ADP REFCLKREQ output to be asserted.


Programmers Model

System Status Register

The System Status Register characteristics are:

Purpose Contains status bits for the ADP inputs.




Figure 3-103 System Status Register bit assignments


Cortex-A57 Snoop Access Control Register

The Cortex-A57 Snoop Access Control Register characteristics are:

Purpose Controls the Cortex-A57 processor Snoop Access Control Gate.




Figure 3-104 Cortex-A57 Snoop Access Control Gate Register bit assignments

Reserved

31 04 3

A57INPLLLOCKA53INPLLLOCK

GPUINPLLLOCKSYSINPLLLOCK

2 15

REFCLKACK

Table 3-120 System status Register bit assignments



[4] A57INPLLLOCK RO 0x0 Current status of the A57PLL LOCK input.

[3] A53INPLLLOCK RO 0x0 Current status of the A53PLL LOCK input.

[2] GPUINPLLLOCK RO 0x0 Current status of the GPUPLL LOCK input.

[1] SYSINPLLLOCK RO 0x0 Current status of the SYSINPLL LOCK input.

[0] REFCLKACK RO 0x0 Current status of the REFCLKACK input.

Reserved

31 03

STANDBYWFIL2L2ACCACKL2ACCREQ

2 1


Programmers Model


Cortex-A53 Snoop Access Control Register

The Cortex-A53 Snoop Access Control Register characteristics are:

Purpose Controls the Cortex-A53 processor Snoop Access Control Gate.




Figure 3-105 Cortex-A53 Snoop Access Control Gate Register bit assignments


Cortex-A57 L2 Flush Control Register

The Cortex-A57 L2 Flush Control Register characteristics are:

Purpose Controls the Cortex-A57 processor L2 Flush mechanism. See SCP controlled Level 2 cache maintenance on page 2-5.


Table 3-121 Cortex-A57 Snoop Access Control Gate Register bit assignments



[2] STANDBYWFIL2 RO 0x0 Current status of the Cortex-A57 L2 Cache STANDBYWFI signal, STANDBYWFIL2

[1] L2ACCACK RO 0x0 Current status of A57L2ACCACK from the Cortex-A57 Snoop Access Control Gate

[0] L2ACCREQ RW 0x0 Request to open the Cortex-A57 Snoop Access Control Gate

Reserved

31 03

STANDBYWFIL2L2ACCACKL2ACCREQ

2 1

Table 3-122 Cortex-A53 Snoop Access Control Gate Register bit assignments



[2] STANDBYWFIL2 RO 0x0 Current status of the Cortex-A53 processor L2 Cache STANDBYWFI signal, STANDBYWFIL2.

[1] L2ACCACK RO 0x0 Current status of A53L2ACCACK from the Cortex-A53 processor Snoop Access Control Gate.

[0] L2ACCREQ RW 0x0 Request to open the Cortex-A53 Snoop Access Control Gate.


Programmers Model



Figure 3-106 Cortex-A57 L2 Flush Control Register bit assignments


Cortex-A53 L2 Flush Control Register

The Cortex-A53 L2 Flush Control Register characteristics are:

Purpose Controls the Cortex-A53 processor L2 Flush mechanism. See SCP controlled Level 2 cache maintenance on page 2-5.




Figure 3-107 Cortex-A53 L2 Flush Control Register bit assignments


Reserved

31 0

FLUSHDONEFLUSHREQ

2 1

Table 3-123 Cortex-A57 L2 Flush Control Register bit assignments



[1] FLUSHDONE RO 0x0 Status of the L2FLUSHDONE output from the processor.

[0] FLUSHREQ RW 0x0 Value of L2FLUSHREQ input to the processor.

Reserved

31 0

FLUSHDONEFLUSHREQ

2 1

Table 3-124 Cortex-A53 L2 Flush Control Register



[1] FLUSHDONE RO 0x0 Status of the L2FLUSHDONE output from the processor.

[0] FLUSHREQ RW 0x0 Value of L2FLUSHREQ input to the processor.


Programmers Model

Reset Syndrome Register, RSR

The Reset Syndrome Register, RSR, characteristics are:

Purpose Indicates the reason for the last system reset. This indicates the last reset that reset both the SCP, including the Cortex-M3 processor, and the remainder of the system, including application processors. Default values in this register only apply at powerup reset, nPORESET.




Figure 3-108 Reset Syndrome Register bit assignments


Note The WDOGRESET_SCP and WDOGRESET_SYS bits are only set when the WDOGRESAON reset request output is asserted. Logic external to the ARM Development Platform asserts the nPORESET input, causing the value of the register to become 0x0000_0001. However, the WDOGRESET_SCP and WDOGRESET_SYS bits can be observed if the SCP reads this register after a watchdog has timed out, but before the external logic has asserted nPORESET. Because this is likely to be a very small window, software should treat these bits as Reserved.

Reserved

31 03

SCPM3LOCKUPSYSRESETREQ

WDOGRESET_SYS

2 145

WDOGRESET_SCPnPORESET

Table 3-125 Reset Syndrome Register bit assignments



[4] SCPM3LOCKUP RO 0x0 Indicates that before the last reset, the Cortex-M3 SCP was in the lockup state.

[3] SYSRESETREQ RO 0x0 Indicates that the SYSRESETREQ bit in the AIRCR of the Cortex-M3 SCP caused the last reset.

[2] WDOGRESET_SYS RO 0x0 Indicates that the system trusted watchdog caused the last reset.

[1] WDOGRESET_SCP RO 0x0 Indicates that the SCP watchdog caused the last reset.

[0] nPORESET RO 0x1 Indicates that the nPORESET input signal caused the last reset.


Programmers Model

System Manual Reset Status Register

The System Manual Reset Status Register characteristics are:

Purpose This read-only register contains the current status of system resets, not including those for the application processors. You can set and clear these resets individually using System Manual Reset Set Register on page 3-129 and System Manual Reset Clear Register on page 3-129. See System Manual Reset Status Register.




Figure 3-109 System Manual Reset Status Register bit assignments


System Manual Reset Set Register

The System Manual Reset Set Register characteristics are:

Purpose You can set this write-only register as follows:0 Writing a 0 to any position has no effect on the reset.1 Writing a 1 to any bit position in this register asserts the relevant

reset.When read, this register returns all zeros.Bit mappings are the same as System Manual Reset Status Register on page 3-129.



System Manual Reset Clear Register

The System Manual Reset Clear Register characteristics are:

Purpose You can set this write-only register as follows:0 Writing a 0 to any position has no effect on the reset.

Reserved

31 02 1

DBGSYSRESETReserved

Table 3-126 System Manual Reset Status Register bit assignments



[1] DBGSYSRESET RO 0x0 Manual control of the APB debug reset.

[0] - RO 0x0 Reserved. Read as zero.


Programmers Model

1 Writing a 1 to any bit position in this register de-asserts the relevant reset.

When read, this register returns all zeros.Bit mappings are the same as System Manual Reset Status Register on page 3-129.



Cortex-A57 Manual Reset Status Register

The Cortex-A57 Manual Reset Status Register characteristics are:

Purpose This read-only register contains the current status of all Cortex-A57 cluster resets. You can set and clear these resets individually using the Cortex-A57 Manual Reset Set Register on page 3-130 and the Cortex-A57 Manual Reset Clear Register on page 3-131.




Figure 3-110 Cortex-A57 Manual Reset Status Register bit assignments


Cortex-A57 Manual Reset Set Register

The Cortex-A57 Manual Reset Set Register characteristics are:


reset.When read, this register returns all zeros.

ReservedReserved

31 0

A57nL2RESETA57nPRESETDBG

14 13 12 11

Table 3-127 Cortex-A57 Manual Reset Status Register bit assignments



[13] A57nL2RESET RO 0x0 Manual control of the Cortex-A57 L2 memory system reset.

[12] A57nPRESETDBG RO 0x0 Manual control of the Cortex-A57 cluster debug reset.



Programmers Model

Bit mappings are the same as Cortex-A57 Manual Reset Status Register on page 3-130



Cortex-A57 Manual Reset Clear Register

The Cortex-A57 Manual Reset Clear Register characteristics are:

Purpose You can set this write-only register as follows:0 Writing a 0 to any position has no effect on the reset.1 Writing a 1 to any bit position in this register de-asserts the

relevant reset.When read, this register returns all zeros.Bit mappings are the same as Cortex-A57 Manual Reset Status Register on page 3-130



Cortex-A53 Manual Reset Status Register

The Cortex-A53 Manual Reset Status Register characteristics are:

Purpose This read-only register contains the current status of all Cortex-A53 cluster resets. You can set and clear these resets individually using the Cortex-A53 Manual Reset Set Register on page 3-132 and Cortex-A53 Manual Reset Clear Register on page 3-132.




Figure 3-111 Cortex-A53 Manual Reset Status Register bit assignments


ReservedReserved

31 0

A53nL2RESETA53nPRESETDBG

12 1114 13

Table 3-128 Cortex-A53 Manual Reset Status Register bit assignments




Programmers Model

Cortex-A53 Manual Reset Set Register

The Cortex-A53 Manual Reset Set Register characteristics are:


reset.When read, this register returns all zeros. Bit mappings are the same as Cortex-A53 Manual Reset Status Register on page 3-131.



Cortex-A53 Manual Reset Clear Register

The Cortex-A53 Manual Reset Clear Register characteristics are:

Purpose You can set this write-only register as follows:0 Writing a 0 to any position has no effect on the reset.1 Writing a 1 to any bit position in this register de-asserts the

relevant reset.When read, this register returns all zeros. Bit mappings are as specified in Cortex-A53 Manual Reset Status Register on page 3-131.



[13] A53nL2RESET RO 0x0 Manual control of the Cortex-A53 cluster L2 memory system reset.

[12] A53nPRESETDBG RO 0x0 Manual control of the Cortex-A53 cluster debug reset.


Table 3-128 Cortex-A53 Manual Reset Status Register bit assignments (continued)



Programmers Model

3.10 Debug RegistersThis section describes:• Register summary.• Register descriptions.


Table 3-129 shows the debug registers in offset order from the base memory address.


This section describes the debug registers. Table 3-129 provides cross references to individual registers.

Debug Control Register

The Debug Control Register characteristics are:

Purpose Controls debug acknowledges. For use, see:• System debug reset request on page 2-25.• Debug power requests on page 2-39.


Attributes See Table 3-129.


Figure 3-112 Debug control Register bit assignments

Table 3-129 Debug Registers summary


0x600 Debug Control Register RW 0x0 32 Debug Control Register

0x604 Debug Status Register RO 0x0 32 Debug Status Register on page 3-134

0x608 Application Processor DAP Target ID Register RO 0x07320477 32 Application Processor Debug Access Port Target ID Register on page 3-135

0x60C SCP Debug Access Port Target ID RO 0x07320477 32 SCP Debug Access Port Target ID Register on page 3-135

0x610 Debug Access Port Instance ID RO 0x0 32 Debug Access Port Instance ID Register on page 3-136

Reserved

31 03

CSYSPWRUPACKCDBGPWRUPACK

CDBGRSTACK

2 1


Programmers Model


Debug Status Register

The Debug Status Register characteristics are:

Purpose Monitors the polarity of debug requests. These requests generate interrupts to the Cortex-M3 SCP. For use, see:• System debug reset request on page 2-25.• Debug power requests on page 2-39.




Figure 3-113 Debug status Register bit assignments


Table 3-130 Debug control Register bit assignments



[2] CSYSPWRUPACK RW 0x0 Sets the acknowledge, CSYSPWRUPACK to a debug system power up request, CSYSPWRUPREQ.

[1] CDBGPWRUPACK RW 0x0 Sets the acknowledge, CDBGPWRUPACK, to a debug system power up request, CDBGPWRUPREQ.

[0] CDBGRSTACK RW 0x0 Sets the acknowledge, CDBGRSTACK, to a debug system power up request, CDBGRSTREQ.

Reserved

31 03

A57DBGPWRUPREQ[1:0]A53DBGPWRUPREQ[3:0]

Reserved

47

CSYSPWRUPREQCDBGPWRUPREQ

8 2 1

CDBGRSTREQ

10 9

Table 3-131 Debug status Register bit assignments



[9:8] A57DBGPWRUPREQ[1:0] RO 0x0 Cortex-A57 DBGPWRUPREQ signal status for each processor.

[7:4] A53DBGPWRUPREQ[3:0] RO 0x0 Cortex-A53 DBGPWRUPREQ signal status for each processor.

[3] - RO 0x0 Reserved, read as zero.


Programmers Model

Application Processor Debug Access Port Target ID Register

The Application Processor Debug Access Port Target ID Register characteristics are:

Purpose Controls the Debug Access Port (DAP) target ID tie-off for multi-drop support.




Figure 3-114 Application Processer DAP target ID Register bit assignments


SCP Debug Access Port Target ID Register

The SCP Debug Access Port Target ID Register characteristics are:

Purpose Controls the DAP target ID tie-off for multi-drop support.




Figure 3-115 SCP DAP target ID Register bit assignments

[2] CSYSPWRUPREQ RO 0x0 Status of the CSYSPWRUPREQ signal from the CoreSight system.

[1] CDBGPWRUPREQ RO 0x0 Status of the CDBGPWRUPREQ signal from the CoreSight system.

[0] CDBGRSTREQ RO 0x0 Status of the CDBGRSTREQ signal from the CoreSight system.

Table 3-131 Debug status Register bit assignments (continued)


TARGETID

31 0

Table 3-132 Application Processer DAP target ID Register bit assignments


[31:0] TARGETID RO 0x07310477 Controls the DAP target ID tie-off for multi-drop support.

TARGETID

31 0


Programmers Model


Debug Access Port Instance ID Register

The Debug Access Port Instance ID Register characteristics are:

Purpose Controls the DAP instance ID tie-off for multi-drop support.




Figure 3-116 DAP instance ID Register bit assignments


Table 3-133 SCP DAP target ID Register bit assignments


[31:0] TARGETID RO 0x07320477 Controls the DAP target ID tie-off for multi-drop support.

Reserved

31 03

INSTANCEID

4

Table 3-134 DAP instance ID Register bit assignments



[3:0] INSTANCEID RO 0x0 Controls the DAP instance ID tie-off for multi-drop support. This field is set to 0x00.


Programmers Model

3.11 Identification RegistersThis section describes:• Register summary.• Register descriptions.


Table 3-135 shows the identification registers in offset order from the base memory address.


This section describes the identification registers. Table 3-135 provides cross references to individual registers.


The Peripheral ID Registers characteristics are:

Purpose You can conceptually treat these registers as a single register that contains a 32-bit peripheral ID value.



Peripheral ID Register 0


Figure 3-117 Peripheral ID Register 0 bit assignments

Table 3-135 Identification Registers summary


0xFD0 Peripheral ID Register 4 RO - 32 Peripheral ID Register 4 on page 3-139

0xFE0 Peripheral ID Register 0 RO - 32 Peripheral ID Register 0

0xFE4 Peripheral ID Register 1 RO - 32 Peripheral ID Register 1 on page 3-138

0xFE8 Peripheral ID Register 2 RO - 32 Peripheral ID Register 2 on page 3-138

0xFEC Peripheral ID Register 3 RO - 32 Peripheral ID Register 3 on page 3-139

0xFF0 Component identification Register 0 RO - 32 Component ID Register 0 on page 3-139



0xFFC Component identification Register 3 RO - 32 Component ID Register 3 on page 3-141

31 8 7 0

PART_0Reserved


Programmers Model










Table 3-136 Peripheral ID Register 0 bit assignments



[7:0] PART_0 0x45 Bits [7:0] of part number.

31 8 7 0

PART_1Reserved

4 3

DES_0




[7:4] DES_0 0xB Bits [3:0] of the Designer field. Set to 0xB for ARM.

[3:0] PART_1 0x8 Bits [11:8] of the part number.

31 8 7 0

DES_1Reserved

4 3

REVISION

2

JEDEC




[7:4] REVISION 0x0 Set to 0x0 for r0p0.

[3] JEDEC 0x1 -

[2:0] DES_1 0x3 Bits [6:4] of the Designer field. Set to 0x3 for ARM.


Programmers Model









Component ID Registers





Component ID Register 0


31 8 7 0

Reserved Reserved





31 8 7 0

DES_2Reserved

4 3

SIZE




[7:4] SIZE 0x0 Indicates log2 of the number of 4KB blocks that the interface occupies. Set to 0x0.

[3:0] DES_2 0x4 JEP106 continuation code identifies the designer. Set to 0x4 for ARM.


Programmers Model

Figure 3-122 System Control Component Register 0 bit assignments










COMP_ID0Reserved

31 08 7

Table 3-141 System Control Component Register 0 bit assignments




COMP_ID1Reserved

31 08 7





COMP_ID2Reserved

31 08 7






Programmers Model





COMP_ID3Reserved

31 08 7






Programmers Model

3.12 Power Policy Unit RegistersThese registers provide an interface for power control including interaction with power policy units. These registers are only accessible from the Cortex-M3 SCP.

This section describes:• Register summary.• Register descriptions on page 3-144.


Three registers are assigned to each power policy unit. All unmapped, unused, addresses within the 4KB region, that the power policy unit registers occupy, are reserved, and accesses targeting them RAZ, WI.

Table 3-145 shows the power registers in offset order from the base memory address.

Table 3-145 Power Policy Registers Summary

Offset Name Type Reset Width Domain Description

0x000 Cortex-A57 core 0 Power Policy Register

R/W - 32 A57CPU[0] Power Policy Register on page 3-144

0x004 Cortex-A57 core 0 Power Status Register

RO Power Status Register on page 3-145

0x00C Cortex-A57 core 0 Power Configuration Register

R/W Power Configuration Register on page 3-146







0x080 A57SSTOP Power Policy Register

R/W - 32 A57SSTOP Power Policy Register on page 3-144

0x084 A57SSTOP Power Status Register


0x08C A57SSTOP Power Configuration Register









Programmers Model



















0x180 A53SSTOP Power Policy Register

R/W - 32 A53SSTOP Power Policy Register on page 3-144

0x184 A53SSTOP Power Status Register


0x18C A53SSTOP Power Configuration Register


0x200 GPUTOP Power Policy Register

R/W - 32 GPUTOP Power Policy Register on page 3-144

0x204 GPUTOP Power Status Register


0x20C GPUTOP Power Configuration Register


0x300 SYSTOP Power Policy Register

R/W - 32 SYSTOP Power Policy Register on page 3-144

0x304 SYSTOP Power Status Register


0x30C SYSTOP Power Configuration Register


Table 3-145 Power Policy Registers Summary (continued)



Programmers Model


This section describes the ADP Power Policy Unit registers. Table 3-145 on page 3-142 provides cross references to individual registers.

Power Policy Register

The Power Policy Register characteristics are:

Purpose Enables software to determine the policy for the next power state transition of the domain as follows:• Transitions to higher power states start immediately.• Active controls can delay transitions to lower power states.Therefore, this register does not always reflect the current power state value. The corresponding Power Status Register reflects the current power state of the domain.


0x320 DBGSYS Power Policy Register

R/W - 32 DBGSYS Power Policy Register

0x324 DBGSYS Power Status Register


0x32C DBGSYS Power Configuration Register


0xFD0 Peripheral ID Register 4

RO - 32 - Peripheral ID Register 4 on page 3-149

0xFE0 Peripheral ID Register 0






0xFEC Peripheral ID Register 3


0xFF0 Component ID Register 0

RO - 32 - COMP_ID0 Register on page 3-149





0xFFC Component ID Register 3


0x1000-0x132C

Override registers, reserved

- - - - Override registers on page 3-151

Table 3-145 Power Policy Registers Summary (continued)



Programmers Model



Figure 3-126 Power Policy Register bit assignments


Table 3-147 shows the default and supported power states for each PPU.

Power Status Register

The Power Status Register characteristics are:

Purpose Contains read-only status information for this domain. This includes the current power state of the domain and an indication of the configured optional power policy support.




POLICYReserved

31 045

Table 3-146 Power Policy Register bit assignments



[4:0] POLICY R/W See Table 3-147 These bits enable software to program the policy for the next power state transition. You can set these bits as Table 3-147 shows.

Table 3-147 Power states

PPU Default policy Supported policies

SYSTOP ON ON, MEM_RET, OFF

DBGSYS OFF ON, OFF

A57SSTOP OFF ON, MEM_RET, configurable, OFF


A53SSTOP OFF ON, MEM_RET, configurable, OFF


GPUTOP OFF ON, OFF


Programmers Model

Figure 3-127 Power Status Register bit assignments


Power Configuration Register

The Power Configuration Register characteristics are:

Purpose Controls enabling and disabling of system hardware control inputs to the PPU and configures memory retention support.




Figure 3-128 Power Configuration Register bit assignments

POWSTATReserved

31 0

MRETSPT

5

ReservedEMULATED

489 67

Table 3-148 Power Status Register bit assignments



[8] MRETSPT RO See Table 3-147 on page 3-145 The PPU is configured to support MEM_RET.


[5] EMULATED RO 0x0 A value of 1 indicates that retention and OFF policies are currently emulated for debug purposes.

[4:0] POWSTAT RO See Table 3-147 on page 3-145 These bits enable software to read the policy that is currently active for the domain. See Table 3-147 on page 3-145.

RETEN[3:0]Reserved

31 0

Reserved

3

HWCSYSREQENHWCACTIVEEN

48 7 2 1


Programmers Model



The Peripheral ID Registers characteristics are:






Figure 3-129 Power Registers Peripheral ID Register 0 bit assignments

Table 3-149 Power Configuration Register bit assignments



[7:4] RETEN[3:0] RW 0x0 Enables and disables memory retention for up to four groups of retention memories within this domain. These bits are applied only in the MEM_RET state:0 A bit cleared indicates that retention is disabled.1 A bit set to 1 indicates that retention is enabled.Writes to this field are ignored if the power region is not in the ON state.You can control each group separately. Memory groups are IMPLEMENTATION DEFINED.


[1] HWCSYSREQEN RW 0x1 Enables and disables device handshake control. You can set this bit as follows:0 The request is driven permanently HIGH, and the device

acknowledge is ignored.1 The device request signaling is driven at each power transition,

and the acknowledge response is required.

[0] HWCACTIVEEN RW 0x1 Enables and disables device HWCACTIVE control. You can set this bit as follows:0 HWCACTIVE is ignored.1 HWCACTIVE set delays entry to any lower power state that has

been programmed until the HWACTIVE signal is de-asserted.

PART_0Reserved

31 08 7


Programmers Model










Table 3-150 Power Registers Peripheral ID Register 0 bit assignments



[7:0] PART _0 RO 0x46 Bits [7:0] of part number.

PART_1DES_0Reserved

31 08 7 4 3




[7:4] DES_0 RO 0xB Bits [3:0] of the designer field. Set to 0xB for ARM.

[3:0] PART_1 RO 0x8 Bits [11:8] of the part number.

DES_1REVISIONReserved

31 08 7 4 3 2

JEDEC




[7:4] REVISION RO 0x0 Set to 0x0 for r0p0.

[3] JEDEC RO 0x1 -

[2:0] DES_1 RO 0x3 Bits [6:4] of the designer field. Set to 0x3 for ARM.


Programmers Model









COMP_ID Registers





COMP_ID0 Register


ReservedReserved

31 08 7





DES_2SIZEReserved

31 08 7 4 3




[7:0] SIZE RO 0x0 Indicates the log2 of the number of 4KB blocks that the interface occupies. Set to 0x0.

[3:0] DES_2 RO 0x4 JEP106 continuation code identifies the designer. Set to 0x4 for ARM.


Programmers Model

Figure 3-134 Power Registers COMP_ID0 Register bit assignments


COMP_ID1 Register




COMP_ID2 Register




COMP_ID0Reserved

31 08 7

Table 3-155 Power Registers COMP_ID0 Register bit assignments




COMP_ID1Reserved

31 08 7





COMP_ID2Reserved

31 08 7






Programmers Model

COMP_ID3 Register




Override registers

The address range 0x1000 to 0x132C contains override registers that can manually control the PPUs. You must not use these registers. They only exist for investigation of system bring-up issues and are therefore deprecated. Contact ARM if you require information about these registers.

REFCLK CNTControl

The REFCLK counter is an implementation of the memory-mapped counter as the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile defines. It implements:• The standard CNTControl frame.• The CNTRead frame in the AP memory map.

This counter implements additional registers in the CNTControl frame.

Table 3-159 shows these additional registers in the CNTControl frame in offset order from the base address.

The following sub-sections provide more information about these registers.

COMP_ID3Reserved

31 08 7





Table 3-159 Additional registers in CNTControl frame of REFCLK Generic Counter


0xC0 CNTSCR R/W 0X00 32 CNTControl Counter Synchronization Control Register, CNTSCR on page 3-152

0xC4 CNTSVL RO 0x00 32 CNTControl Synchronized Counter Value Register, CNTSVL on page 3-152

0xC8 CNTSVU RO 0x00 32 CNTControl Synchronized Counter Value Register, CNTSVU on page 3-153


Programmers Model

CNTControl Counter Synchronization Control Register, CNTSCR

The CNTControl Synchronized Counter Value Register, CNTSVR, characteristics are:

Purpose Controls how the enabling and disabling of the REFCLK Generic Counter is performed.




Figure 3-138 REFCLK CNTControl Sync Control, CNTSCR, Register bit assignments


CNTControl Synchronized Counter Value Register, CNTSVL

The CNTControl Synchronized Counter Value Register, CNTSVL, characteristics are:

Purpose Reads back the value of the counter sampled on the rising of edge of S32KCLK. This register returns the lower word CNTSV[31:0].




Figure 3-139 Synchronized Counter Value Lower Word, CNTSVL, Register bit assignments

Reserved

31 01

ENSYNC

Table 3-160 REFCLK CNTControl Sync Control, CNTSCR, Register bit assignments

Bits Type Reset value Name Description

[31:1] RW 0x0 - Reserved. RAZ, WI.

[0] RW 0x0 ENSYNC Controls how the Counter Control Register EN bit operates. You can set this bit as follows:0 The counter is enabled or disabled immediately.1 The enabling or disabling of the counter is delayed until

just after the next rising edge of S32KCLK.

CNTSVL

31 0


Programmers Model


CNTControl Synchronized Counter Value Register, CNTSVU

The CNTControl Synchronized Counter Value Register, CNTSVU, characteristics are:

Purpose Reads back the value of the counter sampled on the rising of edge of S32KCLK. This register returns the upper word CNTSV[63:32].




Figure 3-140 Synchronized Counter Value Upper Word, CNTSVU, Register bit assignments


Table 3-161 Synchronized Counter Value Lower Word, CNTSVL, Register bit assignments


[31:0] RO 0x0 CNTSVL S32KCLK-sampled value of the counter, lower word, CNTSV[31:0]

CNTSVU

31 0

Table 3-162 Synchronized Counter Value Upper Word, CNTSVU, Register bit assignments


[31:0] RO 0x0 CNTSVU S32KCLK-sampled value of the counter, upper word, CNTSV[63:32]


Programmers Model

3.13 SoC peripherals NIC-400 RegistersThis section summarizes the registers that this NIC-400 configuration creates.

This section describes:• Register summary.• Register descriptions.


Table 3-163 shows the NIC-400 SoC registers in offset order from the base memory address.


This section describes the NIC-400 SoC registers. Table 3-163 provides cross references to individual registers.

Address Region Control Registers

Registers not specified are Reserved. RAZ, WI.

Table 3-163 NIC-400 SoC Registers Summary

Address range Description

0x0 0xFFF Address Region Control Registers

0x1000 0x1FFF ID Registers on page 3-155

0x2000 0x2FFF USB_EHCI (AMIB) on page 3-156

0x3000 0x3FFF TLX_MST (AMIB) on page 3-156

0x4000 0x4FFF USB_OHCI (AMIB) on page 3-156

0x5000 0x5FFF PL354_SMC (AMIB) on page 3-157

0x6000 0x6FFF APB4_BRIDGE (AMIB) on page 3-157

0x7000 0x7FFF BOOTSEC_BRIDGE (AMIB) on page 3-158

0x8000 0x8FFF SECURE_BRIDGE (AMIB) on page 3-158

0xB000 0xBFFF CSS_SC (AMIB) on page 3-158

0x42000 0x42FFF CSS_M (ASIB) on page 3-158

0x44000 0x44FFF HDLCD_0 (ASIB) on page 3-159

0x45000 0x45FFF HDLCD_1 (ASIB) on page 3-160

0x46000 0x46FFF PL330_DMA (ASIB) on page 3-162

0x47000 0x47FFF TLX_SLV (ASIB) on page 3-164

0x48000 0x48FFF USB_MST (ASIB) on page 3-165

0xC2000 0xC2FFF IB0 on page 3-167


Programmers Model

Table 3-164 shows the Address Region Control Registers.

ID Registers

Table 3-165 shows the ID Registers.

Table 3-164 Address Region Control Register bit assignments


0x008 security0 WO 0x0 1 usb_ehci.

0x00C security1 WO 0x0 1 tlx_mst.

0x010 security2 WO 0x0 1 usb_ohci.

0x01C security5 WO 0x0 16 bootsec_bridge0 APB group security settings.Bit to APB master mapping:[0] surge_det.[1] pvt_a53.[2] pvt_soc.[3] pvt_mali.[4] pvt_a57.[5] pvt_std_cell.[6] dfi_phy0_cfg.[7] dfi_phy1_cfg.[8] i2s.[9] hdlcd0_cfg.[10] hdlcd1_cfg.[11] uart0.[12] uart1.[13] i2c.[14] pl354_smc_cfg.[15] pl330_dma_nsec.Bit values:0 Secure.1 Non-secure.

Table 3-165 ID Registers


0x000 – 0xFCC - - - - Reserved. RAZ, WI.

0xFD0 Peripheral ID4 RO 0x04 8 4KB count, JEP106 continuation code

0xFD4 Peripheral ID5 RO 0x00 8 Reserved

0xFD8 Peripheral ID6 RO 0x00 8 Reserved

0xFDC Peripheral ID7 RO 0x00 8 Reserved

0xFE0 Peripheral ID0 RO 0x00 8 Part number[7:0]

0xFE4 Peripheral ID1 RO 0xB4 8 JEP106[3:0], part number[11:8]

0xFE8 Peripheral ID2 RO 0x0B 8 Revision, JEP106 code flag, JEP106[6:4]

0xFEC Peripheral ID3 RO 0x00 8 User-configurable in AMBA Designer, set to 0x0


Programmers Model

USB_EHCI (AMIB)


Table 3-166 shows the USB_EHCI (AMIB) Registers.

TLX_MST (AMIB)


Table 3-167 shows the TLX_MST (AMIB) Registers.

USB_OHCI (AMIB)


0xFF0 Component ID0 RO 0x0D 8 Preamble

0xFF4 Component ID1 RO 0xF0 8 Generic IP component class, preamble

0xFF8 Component ID2 RO 0x05 8 Preamble

0xFFC Component ID3 RO 0xB1 8 Preamble

Table 3-165 ID Registers (continued)


Table 3-166 USB_EHCI (AMIB)


0x008 fn_mod_bm_iss RW 0x0 2 Bus matrix issuing functionality modification register.This register sets issuing capability of the preceding switch arbitration scheme to 1:0 Write Issuing, write_iss_override.1 Read Issuing, read_iss_override.

0x024 fn_mod2 RW 0x0 1 Bypass merge.

0x044 ahb_cntl RW 0x0 2 You can configure the register bits as follows.

Table 3-167 TLX_MST (AMIB)


0x108 fn_mod RW 0x0 2 Issuing functionality modification register. These register bits force the write or read issuing capability of the block to be a single transaction when set to 1:0 read_iss_override.1 write_iss_override.


Programmers Model

Table 3-168 shows the USB_OHCI (AMIB) Registers.

PL354_SMC (AMIB)


Table 3-169 shows the PL354_SMC (AMIB) Registers.

APB4_BRIDGE (AMIB)


Table 3-170 shows the APB4_BRIDGE (AMIB) Registers.

Table 3-168 USB_OHCI (AMIB)




0x044 ahb_cntl RW 0x0 2 You can configure the register bits as follows.

Table 3-169 PL354_SMC (AMIB)


0x008 fn_mod_bm_iss RW 0x0 2 Bus matrix issuing functionality modification register.This register sets issuing capability of the preceding switch arbitration scheme to 1.0 Write Issuing, write_iss_override.1 Read Issuing, read_iss_override.


0x108 fn_mod RW 0x0 2 Issuing functionality modification register. These register bits force the write or read issuing capability of the block to be a single transaction when set to 1.0 read_iss_override.1 write_iss_override.

Table 3-170 APB4_BRIDGE (AMIB)





Programmers Model

BOOTSEC_BRIDGE (AMIB)


Table 3-171 shows the BOOTSEC_BRIDGE (AMIB) Registers.

SECURE_BRIDGE (AMIB)


Table 3-172 shows the SECURE_BRIDGE (AMIB) Registers.

CSS_SC (AMIB)


Table 3-173 shows the CSS_SC (AMIB) Registers.

CSS_M (ASIB)


Table 3-171 BOOTSEC_BRIDGE (AMIB)




Table 3-172 SECURE_BRIDGE (AMIB)

Offset Name Type Width Reset Description

0x008 fn_mod_bm_iss RW 2 0x0 Bus matrix issuing functionality modification register.This register sets issuing capability of the preceding switch arbitration scheme to 1:0 Write Issuing, write_iss_override.1 Read Issuing, read_iss_override.

0x024 fn_mod2 RW 1 0x0 Bypass merge.

Table 3-173 CSS_SC (AMIB)




Programmers Model

Table 3-174 shows the CSS_M (ASIB) Registers.

HDLCD_0 (ASIB)

Table 3-175 shows the HDLCD_0 (ASIB) Registers.

Table 3-174 CSS_M (ASIB)



Table 3-175 HDLCD_0 (ASIB) Register


0x000 – 0x0FF - - - - Reserved. RAZ, WI.

0x100 read_qos RW 0x0 4 Read channel QoS value.

0x104 write_qos RW 0x0 4 Write channel QoS value.


0x10C qos_cntl RW 0x0 21 QoS control register.Enable bits for all of the QoS regulators:[31:21] Reserved. RAZ, do not modify.[20] mode_ar_fc.[19:17] Reserved. RAZ, do not modify.[16] mode_aw_fc.[15:8] Reserved. RAZ, do not modify.[7] en_awar_ot.[6] en_ar_ot.[5] en_aw_ot.[4] en_ar_fc.[3] en_aw_fc.[2:0] Reserved. RAZ, do not modify.

0x110 max_ot RW 0x0 30 Maximum number of outstanding transactions register:[31:30] Reserved. RAZ, do not modify.[29:24] ar_max_oti.[23:16] ar_max_otf.[15:14] Reserved. RAZ, do not modify.[13:8] aw_max_oti.[7:0] aw_max_otf.


Programmers Model

HDLCD_1 (ASIB)

Table 3-176 shows the HDLCD_1 (ASIB) Registers.

0x114 max_comb_ot RW - 15 Maximum number of combined transactions register:[31:15] Reserved. RAZ, do not modify.[14:8] awar_max_oti.[7:0] awar_max_otf.

0x118 aw_p RW 0x0 8 AW channel peak rate Register

0x11C aw_b RW 0x0 16 AW channel burstiness allowance Register.

0x120 aw_r RW 0x0 12 AW channel average rate Register.

0x124 ar_p RW 0x0 8 AR channel peak rate Register.

0x128 ar_b RW 0x0 16 AR channel burstiness allowance Register.

0x12C ar_r RW 0x0 12 AR channel average rate Register.

0x130 target_fc RW 0x0 28 Feedback controlled target register:[31:28] Reserved. RAZ, do not modify.[27:16] ar_tgt_latency.[15:12] Reserved. RAZ, do not modify.[11:0] aw_tgt_latency.

0x134 ki_fc RW 0x0 11 Feedback controlled scale register.[31:11] Reserved. RAZ, do not modify.[10:8] ar_ki.[7:3] Reserved. RAZ, do not modify.[2:0] aw_ki.

0x138 qos_range RW 0x0 28 QoS range register.[31:28] Reserved. RAZ, do not modify.[27:24] ar_max_qos.[23:20] Reserved. RAZ, do not modify.[19:16] ar_min_qos.[15:12] Reserved. RAZ, do not modify.[11:8] aw_max_qos.[7:4] Reserved. RAZ, do not modify.[3:0] aw_min_qos

0x13C – 0FFC - - - - Reserved. RAZ, WI.

Table 3-175 HDLCD_0 (ASIB) Register (continued)


Table 3-176 HDLCD_1 Register



0x100 read_qos RW 0x0 4 Read channel QoS value

0x104 write_qos RW 0x0 4 Write channel QoS value


Programmers Model




0x114 max_comb_ot RW 15 Maximum number of combined transactions register:[31:15] Reserved. RAZ, do not modify.[14:8] awar_max_oti.[7:0] awar_max_otf.

0x118 aw_p RW 0x0 8 AW channel peak rate Register.







Table 3-176 HDLCD_1 Register (continued)



Programmers Model

PL330_DMA (ASIB)

Table 3-177 shows the PL330_DMA (ASIB) Registers.

0x134 ki_fc RW 0x0 11 Feedback controlled scale register:[31:11] Reserved. RAZ, do not modify.[10:8] ar_ki.[7:3] Reserved. RAZ, do not modify.[2:0] aw_ki.

0x138 qos_range RW 0x0 28 QoS range register:[31:28] Reserved. RAZ, do not modify.[27:24] ar_max_qos.[23:20] Reserved. RAZ, do not modify.[19:16] ar_min_qos.[15:12] Reserved. RAZ, do not modify.[11:8] aw_max_qos.[7:4] Reserved. RAZ, do not modify.[3:0] aw_min_qos.


Table 3-176 HDLCD_1 Register (continued)


Table 3-177 PL330_DMA (ASIB) Register






0x10C qos_cntl RW 0x0 21 QoS control register.Enable bits for all of the QoS regulators:[31:21] Reserved. RAZ, do not modify.[20] mode_ar_fc.[19:17] Reserved. RAZ, do not modify.[16] mode_aw_fc.[15:8] Reserved. RAZ, do not modify.[7] en_awar_ot.[6] en_ar_ot.[5] en_aw_ot.[4] en_ar_fc.[3] en_aw_fc[2:0] Reserved. RAZ, do not modify.


Programmers Model

0x110 max_ot RW 0x0 30 Maximum number of outstanding transactions register.[31:30] Reserved. RAZ, do not modify.[29:24] ar_max_oti.[23:16] ar_max_otf.[15:14] Reserved. RAZ, do not modify.[13:8] aw_max_oti.[7:0] aw_max_otf.

0x114 max_comb_ot RW - 15 Maximum number of combined transactions register.[31:15] Reserved. RAZ, do not modify.[14:8] awar_max_oti.[7:0] awar_max_otf.







0x130 target_fc RW 0x0 28 Feedback controlled target register.[31:28] Reserved. RAZ, do not modify.[27:16] ar_tgt_latency.[15:12] Reserved. RAZ, do not modify.[11:0] aw_tgt_latency.




Table 3-177 PL330_DMA (ASIB) Register (continued)



Programmers Model

TLX_SLV (ASIB)

Table 3-178 shows the TLX_SLV (ASIB) Registers.

Table 3-178 TLX_SLV (ASIB) Register


0x000 – 0x104 - - - - Reserved. RAZ, WI.


0x10C qos_cntl RW 0x0 21 QoS control register.Enable bits for all of the QoS regulators:[31:21] Reserved. RAZ, do not modify.[20] mode_ar_fc.[19:17] Reserved. RAZ, do not modify[16] mode_aw_fc.[15:8] Reserved. RAZ, do not modify.[7] en_awar_ot.[6] en_ar_ot.[5] en_aw_ot.[4] en_ar_fc.[3] en_aw_fc.[2:0] Reserved. RAZ, do not modify.

0x110 max_ot RW 0x0 30 Maximum number of outstanding transactions register.[31:30] Reserved. RAZ, do not modify.[29:24] ar_max_oti.[23:16] ar_max_otf.[15:14] Reserved. RAZ, do not modify.[13:8] aw_max_oti.[7:0] aw_max_otf.









Programmers Model

USB_MST (ASIB)

Table 3-179 shows the USB_MST (ASIB) Registers.





Table 3-178 TLX_SLV (ASIB) Register (continued)


Table 3-179 USB_MST (ASIB) Register


0x000 – 0x0FC - - - - Reserved. RAZ, WI.





Programmers Model

0x10C qos_cntl RW 0x0 21 QoS control register.Enable bits for all of the QoS regulators.[31:21] Reserved. RAZ, do not modify.[20] mode_ar_fc.[19:17] Reserved. RAZ, do not modify.[16] mode_aw_fc.[15:8] Reserved. RAZ, do not modify.[7] en_awar_ot.[6] en_ar_ot.[5] en_aw_ot.[4] en_ar_fc.[3] en_aw_fc.[2:0] Reserved. RAZ, do not modify.



0x118 aw_p RW 0x0 8 AW channel peak rate Register






0x130 target_fc RW 0x0 28 Feedback controlled target register.[31:28] Reserved. RAZ, do not modify.[27:16] ar_tgt_latency.[15:12] Reserved. RAZ, do not modify.[11:0] aw_tgt_latency.

Table 3-179 USB_MST (ASIB) Register (continued)



Programmers Model

IB0


Table 3-180 shows the IB0 Registers.




Table 3-179 USB_MST (ASIB) Register (continued)


Table 3-180 IB0 Register


0x008 fn_mod_bm_iss RW 0x0 2 Bus matrix issuing functionality modification register.This register sets issuing capability of the preceding switch arbitration scheme to 1.0 Write Issuing, write_iss_override.1 Read Issuing, read_iss_override.

0x024 fn_mod2 RW 0x0 1 Bypass merge

0x02C fn_mod_lb RW 0x0 1 Long burst functionality modification register:0 Long bursts cannot be generated at the output of this IB.1 Long bursts can be generated at the output of this IB.



Programmers Model

3.14 Compute subsystem NIC-400 RegistersThis section contains a summary of the registers that this NIC configuration creates.

This section describes:• Register summary.• Register descriptions.


Table 3-181 shows the NIC-400 registers in offset order from the base memory address.


This section describes the NIC-400 registers. Table 3-181 provides cross references to individual registers.

Address Region Control Registers

Table 3-182 shows the address regions control registers.

Table 3-181 NIC-400 Registers summary

Address range Description

0x0 0xFFF Address Region Control Registers

0x1000 0x1FFF ID Registers on page 3-169

0x2000 0x41FFF Reserved

0x42000 0x42FFF CCISLAVE, ASIB on page 3-169

0x43000 0x43FFF CUST_EXT_SLV, ASIB on page 3-170

0x44000 0x44FFF SCP, ASIB on page 3-171

0x45000 0x45FFF CS_DAP, ASIB on page 3-172

0x46000 0x46FFF CS_ETR, ASIB on page 3-172

0x47000 0xFFFFF Reserved

Table 3-182 Address Region Control Registers

Offset Name Type Reset Width Details


0x028 security8 WO 0x0 3 slave_bootsecure APB group security settings.Bit to APB master mapping:[2] GPU_CFG.[1] DMC_CFG.[0] CS_CFG.Bit values:0 Secure.1 Non-secure.

0x2C – 0xFFF - - - - Reserved. RAZ, WI.


Programmers Model

ID Registers

Table 3-183 shows the ID registers.

CCISLAVE, ASIB

Table 3-184 shows the CCISLAVE, ASIB, registers.

Table 3-183 ID Registers


0x000 – 0xFCC - - - - Reserved. RAZ, WI.

0xFD0 Peripheral ID4 RO 0x04 8 4KB count, JEP106 continuation code

0xFD4 Peripheral ID5 RO 0x00 8 Reserved.

0xFD8 Peripheral ID6 RO 0x00 8 Reserved.

0xFDC Peripheral ID7 RO 0x00 8 Reserved.

0xFE0 Peripheral ID0 RO 0x00 8 Part number[7:0].

0xFE4 Peripheral ID1 RO 0xB4 8 JEP106[3:0], part number[11:8].

0xFE8 Peripheral ID2 RO 0x0B 8 Revision, JEP106 code flag, JEP106[6:4].

0xFEC Peripheral ID3 RO 0x00 8 User configurable in AMBA Designer. Set to 0x0.

0xFF0 Component ID0 RO 0x0D 8 Preamble.

0xFF4 Component ID1 RO 0xF0 8 Generic IP component class, preamble.

0xFF8 Component ID2 RO 0x05 8 Preamble.

0xFFC Component ID3 RO 0xB1 8 Preamble.

Table 3-184 CCISLAVE (ASIB) Register


0x000-0x104 - - - - Reserved. RAZ, WI.

0x108 fn_mod RW 0x0 2 Issuing functionality modification register. These register bits force the write or read issuing capability of the block to be a single transaction when set to 1.[1] write_iss_override.[0] read_iss_override.

0x10C-0xFFC - - - - Reserved. RAZ, WI.


Programmers Model

CUST_EXT_SLV, ASIB

Table 3-185 shows the CUST_EXT_SLV (ASIB) registers.

Table 3-185 CUST_EXT_SLV (ASIB) Register






0x114 max_comb_ot RW - 15 Maximum number of combined transactions register:[31:15] Reserved. RAZ, do not modify.[14:8] awar_max_oti.[7:0] awar_max_otf.

0x118 – 0x12C - - - - Reserved. RAZ, do not modify



Programmers Model

SCP, ASIB

Table 3-186 shows the SCP (ASIB) registers.




Table 3-185 CUST_EXT_SLV (ASIB) Register (continued)


Table 3-186 SCP (ASIB) Register



0x024 fn_mod2 RW 0x0 1 Bypass merge. only if upsizing or downsizing.

0x028 – 0x0FC - - - - Reserved. RAZ, do not modify.




0x10C – 0xFFC - - - - Reserved. RAZ, WI.


Programmers Model

CS_DAP, ASIB

Table 3-187 shows the CS_DAP (ASIB) registers.

CS_ETR, ASIB

Table 3-188 shows the CS_ETR (ASIB) registers.

Table 3-187 CS_DAP (ASIB) Register






0x10C – 0xFFC - - - - Reserved. RAZ, WI.

Table 3-188 CS_ETR (ASIB) Register





0x108 fn_mod RW 0x0 2 Issuing functionality modification register. These register bits force the write or read issuing capability of the block to be a single transaction when set to 1:[1] write_iss_override.[0] read_iss_override.

0x10C qos_cntl RW 0x0 21 QoS control register.Enable bits for all of the QoS regulators.[31:21] Reserved. RAZ, do not modify.[20] mode_ar_fc.[19:17] Reserved. RAZ, do not modify.[16] mode_aw_fc.[15:8] Reserved. RAZ, do not modify.[7] en_awar_ot.[6] en_ar_ot.[5] en_aw_ot.[4] en_ar_fc.[3] en_aw_fc.[2:0] Reserved. RAZ, do not modify.


Programmers Model



0x118 – 0x12C - - - - Reserved. RAZ, do not modify.



0x138 qos_range RW 0x0 28 QoS range register.[31:28] Reserved. RAZ, do not modify.[27:24] ar_max_qos.[23:20] Reserved. RAZ, do not modify.[19:16] ar_min_qos.[15:12] Reserved. RAZ, do not modify.[11:8] aw_max_qos.[7:4] Reserved. RAZ, do not modify.[3:0] aw_min_qos.


Table 3-188 CS_ETR (ASIB) Register (continued)



Programmers Model

3.15 HDLCD RegistersThis section describes the programmers model. It contains the following subsections:• Register summary.• Register descriptions on page 3-175.



Table 3-189 Register summary


0x0000 VERSION RO VERSION 32 Version Register on page 3-175

0x0010 INT_RAWSTAT RW 0x0 32 Interrupt Raw Status Register on page 3-175

0x0014 INT_CLEAR WO N/A 32 Interrupt Clear Register on page 3-176

0x0018 INT_MASK RW 0x0 32 Interrupt Mask Register on page 3-177

0x001C INT_STATUS RO 0x0 32 Interrupt Status Register on page 3-178

0x0100 FB_BASE RW 0x0 32 Frame Buffer Base Address Register on page 3-179

0x0104 FB_LINE_LENGTH RW 0x0 32 Frame Buffer Line Length Register on page 3-179

0x0108 FB_LINE_COUNT RW 0x0 32 Frame Buffer Line Count Register on page 3-180

0x010C FB_LINE_PITCH RW 0x0 32 Frame Buffer Line Pitch Register on page 3-181

0x0110 BUS_OPTIONS RW 0x408 32 Bus Options Register on page 3-181

0x0200 V_SYNC RW 0x0 32 Vertical Synch Width Register on page 3-182

0x0204 V_BACK_PORCH RW 0x0 32 Vertical Back Porch Width Register on page 3-183

0x0208 V_DATA RW 0x0 32 Vertical Data Width Register on page 3-183

0x020C V_FRONT_PORCH RW 0x0 32 Vertical Front Porch Width Register on page 3-184

0x0210 H_SYNC RW 0x0 32 Horizontal Synch Width Register on page 3-184

0x0214 H_BACK_PORCH RW 0x0 32 Horizontal Back Porch Width Register on page 3-185

0x0218 H_DATA RW 0x0 32 Horizontal Data Width Register on page 3-185

0x021C H_FRONT_PORCH RW 0x0 32 Horizontal Front Porch Width Register on page 3-186

0x0220 POLARITIES RW 0x0 32 Polarities Register on page 3-187

0x0230 COMMAND RW 0x0 32 Command Register on page 3-187

0x0240 PIXEL_FORMAT RW 0x0 32 Pixel Format Register on page 3-188

0x0244 RED_SELECT RW 0x0 32 Color Select Registers on page 3-189

0x0248 GREEN_SELECT RW 0x0 32 Color Select Registers on page 3-189

0x024C BLUE_SELECT RW 0x0 32 Color Select Registers on page 3-189


Programmers Model


This section describes the HDLCD controller registers. Table 3-189 on page 3-174 provides cross references to individual registers.

Version Register

The VERSION Register characteristics are:

Purpose Contains a static version number for the LCD controller. Changes to the processor that affect registers and data structures increment the VERSION_MAJOR value and reset the VERSION_MINOR value.Other changes that do not affect the binary compatibility only increment the VERSION_MINOR number.


Configurations Available in all HDLCD configurations.



Figure 3-141 Version Register bit assignments


Interrupt Raw Status Register

The INT_RAWSTAT Register characteristics are:

Purpose Shows the unmasked status of the interrupt sources.Writing a 1 to the bit of an interrupt source forces this bit to be set and generates an interrupt if it is not masked by the corresponding bit in the Interrupt Mask Register on page 3-177.Writing a 0 to the bit of an interrupt source has no effect.Use the Interrupt Clear Register on page 3-176 to clear interrupts.


Configurations Available in all HDLCD controller configurations.

31 16 15 8 7 0

PRODUCT_ID VERSION_MAJOR VERSION_MINOR

Table 3-190 Version Register bit assignments


[31:16] PRODUCT_ID Product ID number 0x1CDC.

[15:8] VERSION_MAJOR These bits provide the major product version information.For release r0p0, the value is 0x00.

[7:0] VERSION_MINOR These bits provide the minor product version information.For release r0p0, the value is 0x00.


Programmers Model



Figure 3-142 Interrupt Raw Status Register bit assignments


Interrupt Clear Register

The INT_CLEAR Register characteristics are:

Purpose Clears interrupt sources. Writing a 1 to the bit of an asserted source clears the interrupt in the Interrupt Raw Status Register on page 3-175, and in the Interrupt Status Register on page 3-178 if it is not masked.





31 4 3 02 1

Reserved

UNDERRUNVSYNC

BUS_ERRORDMA_END

Table 3-191 Interrupt Raw Status Register bit assignments


[31:4] - Reserved. Write as zero, read undefined.

[3] UNDERRUN No data was available to display while DATAEN was active.This interrupt triggers if the controller does not have pixel data available to drive when DATAEN is active. When this occurs, the controller drives the default color for the rest of the screen and attempts to display the next frame correctly.

[2] VSYNC Vertical sync is active.This interrupt triggers at the moment the VSYNC output goes active.

[1] BUS_ERROR The DMA module received a bus error while reading data.This interrupt triggers if any frame buffer read operation ever reports an error.

[0] DMA_END The DMA module has finished reading a frame.This interrupt triggers when the last piece of data for a frame has been read. The DMA immediately continues on the next frame, so this interrupt only ensures that the frame buffer for the previous frame is no longer required.


Programmers Model

Figure 3-143 Interrupt Clear Register bit assignments


Interrupt Mask Register

The INT_MASK Register characteristics are:

Purpose Contains the bit mask that enables an interrupt source if the corresponding mask bit is set to 1.





Figure 3-144 Interrupt Mask Register bit assignments

31 4 3 02 1

Reserved

UNDERRUNVSYNC

BUS_ERRORDMA_END

Table 3-192 Interrupt Clear Register bit assignments


[31:4] - Reserved. Write as zero.





31 4 3 02 1

Reserved

UNDERRUNVSYNC

BUS_ERRORDMA_END


Programmers Model


Interrupt Status Register

The INT_STATUS Register characteristics are:

Purpose This register is the Interrupt Raw Status Register on page 3-175 ANDed with the Interrupt Mask Register on page 3-177 and shows the active and masked interrupt sources. Bits selected by the Interrupt Mask Register on page 3-177 are active in the Interrupt Status Register. These bits show the status of the interrupt sources. Bits not selected by the Interrupt Mask are inactive. If any of the sources are asserted in the Interrupt Status Register, then the external IRQ line is asserted.





Figure 3-145 Interrupt Status Register bit assignments

Table 3-193 Interrupt Mask Register bit assignments







31 4 3 02 1

Reserved

UNDERRUNVSYNC

BUS_ERRORDMA_END


Programmers Model


Frame Buffer Base Address Register

The FB_BASE Register characteristics are:

Purpose Contains the address of the first pixel of the first line in the frame buffer.





Figure 3-146 Frame Buffer Base Address Register bit assignments


Frame Buffer Line Length Register

The FB_LINE_LENGTH Register characteristics are:

Purpose Contains the length of each frame buffer line in bytes.

Table 3-194 Interrupt Status Register bit assignments


[31:4] - Reserved, read undefined.





31 3 02

FB_BASE_ADDR

Reserved

Table 3-195 Frame Buffer Base Address Register bit assignments


[31:3] FB_BASE_ADDR Frame buffer base address.



Programmers Model





Figure 3-147 Frame Buffer Line Length Register bit assignments


Frame Buffer Line Count Register

The FB_LINE_COUNT Register characteristics are:

Purpose Contains the number of lines to read from the frame buffer.





Figure 3-148 Frame Buffer Line Count Register bit assignments


31 3 02

FB_LINE_LENGTH

Reserved

Table 3-196 Frame Buffer Line Length Register bit assignments


[31:3] FB_LINE_LENGTH Frame buffer line length.


31 012

FB_LINE_COUNT

11

Reserved

Table 3-197 Frame Buffer Line Count Register bit assignments



[11:0] FB_LINE_COUNT Frame buffer line count.


Programmers Model

Frame Buffer Line Pitch Register

The FB_LINE_PITCH Register characteristics are:

Purpose Contains the number of bytes between the start of one line in the frame buffer, and the start of the next line. This value is treated as a signed 2’s complement number, enabling negative pitch if required.





Figure 3-149 Frame Buffer Line Count Pitch bit assignments


Bus Options Register

The BUS_OPTIONS Register characteristics are:

Purpose Controls aspects of how the LCD controller accesses the bus. This value can be tuned to better match the characteristics of the memory controller and other units in the system.





31 3 02

FB_LINE_PITCH

Reserved

Table 3-198 Frame Buffer Line Pitch Register bit assignments


[31:3] FB_LINE_PITCH Frame buffer line pitch.



Programmers Model

Figure 3-150 Bus Options Register bit assignments


Note • If the scan line length does not end up at a multiple of the permitted burst lengths, the

controller uses smaller bursts to read the remaining few pixels in each scan line. If no bursts are permitted, this mechanism also triggers, and has the same effect as permitting all bursts.

• Incorrectly configuring this register can degrade the performance of both the LCD controller and the rest of the system.

Vertical Synch Width Register

The V_SYNC Register characteristics are:

Purpose Contains the width of the vertical synch signal, counted in number of horizontal scan lines.



31 12 11 8 7 5 4 3 2 1 0

Reserved

MAX_OUTSTANDINGReserved

BURST_16BURST_8BURST_4BURST_2BURST_1

Table 3-199 Bus Options Register bit assignments



[11:8] MAX_OUTSTANDING Maximum number of outstanding requests the LCD controller is permitted to have on the bus at any time.

Caution A value of zero disables all bus transfers


[4] BURST_16 Permit the use of 16-beat bursts.






Programmers Model



Figure 3-151 Vertical Synch Width Register bit assignments


Vertical Back Porch Width Register

The V_BACK_PORCH Register characteristics are:

Purpose Contains the width of the interval between the vertical sync and the first visible line, counted in number of horizontal scan lines.





Figure 3-152 Vertical Back Porch Width Register bit assignments


Vertical Data Width Register

The V_DATA Register characteristics are:

Purpose Contains the width of the vertical data area, that is, the number of visible lines, counted in the number of horizontal scan lines.


31 12 11 0

Reserved V_SYNC

Table 3-200 Vertical Synch Register bit assignments



[11:0] V_SYNC Vertical synch width -1.

31 12 11 0

Reserved V_BACK_PORCH

Table 3-201 Vertical Back Porch Register bit assignments



[11:0] V_BACK_PORCH Vertical back porch width -1.


Programmers Model




Figure 3-153 Vertical Data Width Register bit assignments


Vertical Front Porch Width Register

The V_FRONT_PORCH Register characteristics are:

Purpose Contains the width of the interval between the last visible line and the next vertical synchronization, counted in number of horizontal scan lines.





Figure 3-154 Vertical Front Porch Width Register bit assignments


Horizontal Synch Width Register

The H_SYNCH Register characteristics are:

Purpose Contains the width of the horizontal synch signal, counted in pixel clocks.


31 12 11 0

Reserved V_DATA

Table 3-202 Vertical Data Width Register bit assignments



[11:0] V_DATA Vertical data width -1.

31 12 11 0

Reserved V_FRONT_PORCH

Table 3-203 Vertical Front Porch Width Register bit assignments



[11:0] V_FRONT_PORCH Vertical front porch width -1.


Programmers Model




Figure 3-155 Horizontal Synch Width Register bit assignments


Horizontal Back Porch Width Register

The H_BACK_PORCH Register characteristics are:

Purpose Contains the width of the interval between the horizontal sync and the first visible column, counted in pixel clocks.





Figure 3-156 Horizontal Back Porch Width Register bit assignments


Horizontal Data Width Register

The H_DATA Register characteristics are:

Purpose Contains the width of the horizontal data area, that is, the number of visible columns counted in pixel clocks.

31 12 11 0

Reserved H_SYNC

Table 3-204 Horizontal Synch Width Register bit assignments



[11:0] H_SYNC Horizontal synch width -1.

31 12 11 0

Reserved H_BACK_PORCH

Table 3-205 Horizontal Back Porch Register bit assignments



[11:0] H_BACK_PORCH Horizontal back porch width -1.


Programmers Model





Figure 3-157 Horizontal Data Width Register bit assignments


Horizontal Front Porch Width Register

The H_FRONT_PORCH Register characteristics are:

Purpose Contains the width of the interval between the last visible column and the next horizontal synchronization, counted in pixel clocks.





Figure 3-158 Horizontal Front Porch Width Register bit assignments


31 12 11 0

Reserved H_DATA

Table 3-206 Horizontal Data Width Register bit assignments



[11:0] H_DATA Horizontal data width -1.

31 12 11 0

Reserved H_FRONT_PORCH

Table 3-207 Horizontal Front Porch Register bit assignments



[11:0] H_FRONT_PORCH Horizontal front porch width -1.


Programmers Model

Polarities Register

The POLARITIES Register characteristics are:

Purpose Controls the polarities of the synchronization signals and PXLCLK that is exported from the CoreTile Express A5×2 daughterboard.





Figure 3-159 Polarities Register bit assignments


Command Register

The COMMAND Register characteristics are:

Purpose Starts and stops the LCD controller.



31 5 4 3 2 1 0

PXLCK_POLARITYDATA_POLARITY

DATAEN_POLARITYHSYNC_POLARITYVSYNC_POLARITY

Reserved

Table 3-208 Polarities Register bit assignments



[4] PXLCLK_POLARITY Contains value of the PXLCLKPOL output. This is intended to be used for controlling the polarity of the pixel clock that is exported from the CoreTile Express A5×2 daughterboard.

Note • PXLCLK_POLARITY=b1;

— PXLCLK, HDLCD, and MMB_IDCLK, export, are the same polarity.• PXLCLK_POLARITY=b0;

— PXLCLK, HDLCD, and MMB_IDCLK, export, are the opposite polarity.

[3] DATA_POLARITY Contains the active level of the DATA output.

[2] DATAEN_POLARITY Contains the active level of the DATAEN output.

[1] HSYNC_POLARITY Contains the active level of the HSYNC output.

[0] VSYNC_POLARITY Contains the active level of the VSYNC output.


Programmers Model



Figure 3-160 Command Register bit assignments


Pixel Format Register

The PIXEL_FORMAT Register characteristics are:

Purpose BYTES_PER_PIXEL plus one bytes are extracted from the internal buffer. The extracted bytes are used to form a 32-bit value. The individual bytes are then optionally reordered if BIG_ENDIAN is set before the color components are extracted.




Figure 3-161 shows the little endian byte layout.

Figure 3-161 Little endian byte layout

Figure 3-162 shows the big endian byte layout.

Figure 3-162 Big endian byte layout

Figure 3-163 on page 3-189 shows the bit assignments for the big endian format.

31 1 0

ENABLE

Reserved

Table 3-209 Command Register bit assignments



[0] ENABLE Enable the LCD controller.

313

02 1 0

Undefined 2 101Undefined0Undefined

24 23 16 15 8 7 0

310

Undefined1 2 3

0 1 20 1 Undefined0 Undefined

24 23 16 15 8 7 0


Programmers Model

Figure 3-163 Pixel Format Register bit assignments

Table 3-210 shows the bit assignments for the big endian format.

Color Select Registers

The RED_SELECT, GREEN_SELECT and BLUE_SELECT Registers characteristics are:

Purpose The bytes extracted from the internal buffer are presented as a 32-bit value. These registers select how many bits at which position are used to extract and use as the red, green, and blue color components. If no bits are extracted or no data is available, the default color is used.





Figure 3-164 Color Select Register bit assignments

Table 3-211 on page 3-190 shows the bit assignments.

31 30 5 4 3 2 0

BIG_ENDIAN

Reserved

BYTES_PER_PIXELReserved

Table 3-210 Pixel Format Register bit assignments


[31] BIG_ENDIAN Use big endian byte order.


[4:3] BYTES_PER_PIXEL Number of bytes to extract from the buffer for each pixel to display, minus one.


31 24 23 16 15 12 11 8 7 5 4 0

OFFSET

Reserved

SIZE

Reserved

DEFAULTReserved


Programmers Model

Table 3-211 Color Select Register bit assignments



[23:16] DEFAULT Default color.This color is used if any of the following occur:• SIZE is zero.• The buffer underruns.• While outside the visible frame area.


[11:8] SIZE Number of bits to extract.If this value is zero, the default color is used.If this value is in the range 1-7, the extracted MSBs are repeated for the LSBs until eight bits are reached.If this value is larger than 8, the behavior is UNDEFINED.


[4:0] OFFSET Index of the lowest bit to extract.If OFFSET + SIZE >= 8 + 8 x BYTES_PER_PIXEL, the behavior is undefined.


Programmers Model

3.16 PCIe Control RegistersThis section describes the PCIe Control Registers. It contains the following subsections:• Register summary.• Register descriptions on page 3-192.


Table 3-212 shows the PCIe Control Registers in offset order from the base memory address.

Note Any memory not allocated is treated as RAZ/WI and does not generated an error.

Table 3-212 PCIe control Registers summary

Address Register name Type Reset Width Description

0x0000-0x00FF PHY internal registers RW - 32 PHY internal registers on page 3-192.

0x0100-0x0FFF - RO 0x0 32 Reserved. RAZ/WI.

0x1000 PLL Config RW 0x0 32 PLL Config Register on page 3-192.

0x1004 PCIe reset control WO 0x0 32 PCIe Reset Control Register on page 3-192.

0x1008 PCIe reset status RO 0x0 32 PCIe Reset Status Register on page 3-193.

0x100C PCIe clock control RW 0x0 32 PCIe Clock Control Register on page 3-194.

0x2004 PMAD_DEBUG RO - 32 PMAD_DEBUG Register on page 3-195.

0x2008 PCS_DEBUG_SEL RW 0x0 32 PCS_DEBUG_SEL Register on page 3-195.

0x200C PCS_DEBUG_OUT RO - 32 PCS_DEBUG_OUT Register on page 3-195.

0x2010 Root Port Test In Lower RW 0x0 32 Root Port Test In Register on page 3-195.

0x2014 Root Port Test In Upper RW 0x0 32

0x2018 Root Port Test Out Lower RO 0x0 32 Root Port Test Out Register on page 3-195.

0x201C Root Port Test Out Upper RO 0x0 32

0x2020 Root Port LTSSM RO 0x0 32 Root Port LTSSM Register on page 3-195.

0x3000 Secure RW 0x2 32 Secure Register on page 3-196.

0xFFD0 Peripheral ID4 RO 0x64 32 PID4 Register on page 3-196.

0xFFE0 Peripheral ID0 RO 0xAC 32 PID0 Register on page 3-197.

0xFFE4 Peripheral ID1 RO 0xB0 32 PID1 Register on page 3-197.

0xFFE8 Peripheral ID2 RO 0x0B 32 PID2 Register on page 3-198.

0xFFEC Peripheral ID3 RO 0x00 32 PID3 Register on page 3-198.

0xFFF0 Component ID0 RO 0x0D 32 ID0 Register on page 3-199.

0xFFF4 Component ID1 RO 0xF0 32 ID1 Register on page 3-199.

0xFFF8 Component ID2 RO 0x05 32 ID2 Register on page 3-200.

0xFFFC Component ID3 RO 0xB1 32 ID3 Register on page 3-200.


Programmers Model


This section describes the PCIe Control registers. Table 3-212 on page 3-191 provides cross references to individual registers.

PHY internal registers

Note These registers are only for debug and DFT purposes. Software must avoid accessing these registers.

PLL Config Register

The PLL Config Register characteristics are:

Purpose Configures the settings of the PLL within the PHY.

Usage constraints Do not modify the values in this register after the PHY_REL bit has been set.



Figure 3-165 PLL Config Register bit assignments


PCIe Reset Control Register

The PCIe Reset Control Register characteristics are:

Purpose Reset control register for the PCIe subsystem.



Reserved

31 0

FD_SEL

1

SSC

2

Table 3-213 PLL Config Register bit assignments


[31:2] - Reserved. RAZ/WI.

[1] FD_SEL Feedback divider input selection for the PHY PLL:0 Integer divider.1 Fractional divider.

[0] SSC PLL Spectrum Spreader Control enable:0 No SSC.1 Enable SSC.


Programmers Model


Figure 3-166 PCIe Reset Control Register bit assignments


Table 3-215 shows the valid combinations of RC_REL and PHY_REL.

PCIe Reset Status Register

The PCIe Reset Status Register characteristics are:

Purpose Reset status register for the PCIe subsystem.


Reserved

31 0

nCLR_STK

1

RC_REL

2

PHY_REL

3

Table 3-214 PCIe Reset Control Register bit assignments



[2] nCLR_STK Select whether on the next reset of the PCIe subsystem, the sticky bits in the PCIe configuration registers inside the Root Port are reset.0 Sticky bits are reset at next reset of PCIe subsystem.1 Sticky bits are not reset at next reset of PCIe subsystem.

Note In the ADP, this feature is not implemented and software is advised to always set this bit to 0.

[1] RC_REL Releases the transaction and PCIe layers of the Root Port.0 Writing a 0 has no effect.1 Writing a 1 to this register releases the transaction and pcie layers from reset when the pcie

subsystem is released from reset.This register changes to 0 when the PCIe subsystem reset occurs.

[0] PHY_REL Releases the PHY’s pipe interface.0 Writing a 0 has no effect.1 Writing a 1 to this register releases the PHY pipe interface when the pcie subsystem is released

from reset.This register will change to 0 when the PCIe subsystem reset occurs

Table 3-215 Valid combinations of RC_REL and PHY_REL

RC_REL PHY_REL Result

x 0 SoC reset condition. The PCIe link is held in reset.

0 1 PHY released from reset.

1 1 Root Port and PHY released from reset.


Programmers Model



Figure 3-167 PCIe Reset Status Register bit assignments


PCIe Clock Control Register

The PCIe Clock Control Register characteristics are:

Purpose Clock control register for the PCIe subsystem.




Figure 3-168 PCIe Clock Control Register bit assignments

Reserved

31 0

CLR_STK_ST

1

RC_ST

2

PHY_ST

34

PLL_ST

Table 3-216 PCIe Reset Status Register bit assignments



[3] CLR_STK_ST Indicates whether on the next reset of the PCIe subsystem, the sticky bits in the PCIe configuration registers are reset.0 Sticky bits are reset at next reset of PCIe subsystem.1 Sticky bits are not reset at next reset of PCIe subsystem.

[2] RC_ST Indicates when the RC is out of reset:0 RC is in reset.1 RC is out of reset.

[1] PHY_ST Indicates when the PHY is out of reset:0 PHY is in reset.1 PHY out of reset.

[0] PLL_ST Indicates when the PHY’s PLL is stable:0 PLL not stable.1 PLL stable.

DELAYReserved

31 0

AXI_FORCE

79 8


Programmers Model


PMAD_DEBUG Register

Note This register is only for debug and DFT purposes. Software must avoid accessing this register.

PCS_DEBUG_SEL Register


PCS_DEBUG_OUT Register


Root Port Test In Register


Root Port Test Out Register


Root Port LTSSM Register


Table 3-217 PCIe Clock Control Register bit assignments



[8] AXI_FORCE AXI clock force:0 The AXI clock clock gates when no transactions are active.1 The AXI clock does not clock gate when no transactions are active.

[7:0] DELAY Selects the number of AXI clock cycles of bus inactivity required to pass before the AXI clock is gated.0 The AXI clock is gated as soon as all transaction have completed.1 The AXI clock is gated one clock cycle after all transaction have completed.


Programmers Model

Secure Register

The Secure Register characteristics are:

Purpose Control of security.




Figure 3-169 Secure Register bit assignments


Note This register is RAZ/WI for non-secure accesses.

PID4 Register

The PID4 Register characteristics are:

Purpose Peripheral identification 4 Register.




Figure 3-170 PID4 Register bit assignments

Reserved

31 0

MS

1

S

2

Table 3-218 Secure Register bit assignments



[1] MS Controls the security of transactions that the PCIe endpoints generate:0 Secure transaction.1 Non secure transaction.

[0] S Control whether non-secure transactions can access the PCIe registers:0 Only secure.1 Non-secure and secure.

4KBReserved

31 0

CONT CODE

348 7


Programmers Model


PID0 Register








PID1 Register







Table 3-219 PID4 Register bit assignments



[7:4] 4KB Number of 4KB blocks used by this component in a power of 2 format. For the PCIe registers, the value is 0x6.

[3:0] CONT CODE The JEP106 continuation code. For ARM Limited, the value is 0x4.

PART NOReserved

31 08 7




[7:0] PART NO Part Number[7:0]. Reads as 0xAC.

PART NOJEP106 IDReserved

31 0348 7


Programmers Model


PID2 Register








PID3 Register









[7:4] JEP106 ID JEP106 Identity code [3:0]. For ARM Limited, the value is 0xB.

[3:0] PART NO Part Number [11:8]. Reads as 0x0.

1REVReserved

31 0348 7 2

JEP106 ID




[7:4] REV Revision number. Incremental value starting at 0x0. For the PCIe registers, the value is 0x0.

[3] 1 Treat as RAO.

[2:0] JEP106 ID JEP106 identity code [6:4]. For ARM Limited, the value is 0x3.


Programmers Model



ID0 Register

The ID0 Register characteristics are:

Purpose Identification 0 Register.




Figure 3-175 ID0 Register bit assignments


ID1 Register






CUST MODREVANDReserved

31 0348 7




[7:4] REVAND Indicates minor errata fixes specific to this design, for example, metal fixes. For the PCIe registers, the value is 0x0.

[3:0] CUST MOD Indicates customer modification to reusable IP. For the PCIe registers, the value is 0x0.

PREAMBLEReserved

31 08 7

Table 3-224 ID0 Register bit assignments



[7:0] PREAMBLE The value is 0x0D.


Programmers Model



ID2 Register








ID3 Register






PREAMBLEReserved

31 08 7 4 3

COMPONENT CLASS




[7:4] COMPONENT CLASS The class of the component. For the PCIe registers, the value is 0xF.

[3:0] PREAMBLE Value is 0x0.

PREAMBLEReserved

31 08 7




[7:0] PREMABLE Value is 0x05.


Programmers Model



PREAMBLEReserved

31 08 7




[7:0] PREAMBLE The value is 0xB1.


Programmers Model

3.17 PCIe Root Port configuration registersThis section describes the PCIe Root Port configuration Registers. It contains the following subsections:• Register summary.• Control and status Registers descriptions on page 3-204.• Interrupt and event Registers descriptions on page 3-221.• Address translation Registers descriptions on page 3-226.


Table 3-228 shows the PCIe Root Port configuration Registers in address order from the base memory address.

Table 3-228 PCIe Root Port configuration Registers summary

Address Register name Type Width Description

Control and status Registers descriptions on page 3-204

0x0000 BRIDGE_VER RO 32 BRIDGE_VER Register on page 3-204

0x0004 BRIDGE_BUS RO 32 BRIDGE_BUS Register on page 3-205

0x0008-0x000F - - - Reserved.

0x0010 PCIE_IF_CONF RO 32 PCIE_IF_CONF Register on page 3-206

0x0014 PCIE_BASIC_CONF RO 32 PCIE_BASIC_CONF Register on page 3-207

0x0018 PCIE_BASIC_STATUS RO 32 PCIE_BASIC_STATUS Register on page 3-208

0x001C-0x007F - - - Reserved.

0x0080 GEN_SETTINGS RO 32 GEN_SETTINGS Register on page 3-209

0x0084-0x008F - - - Reserved.

0x0090 PCIE_VC_CRED_0 RW 32 PCIE_VC_CRED_0 Register on page 3-210

0x0094 PCIE_VC_CRED_1 PCIE_VC_CRED_1 Register on page 3-210

0x0098- PCIE_PCI_IDS_0 RW 32 PCIE_PCI_IDS_0 on page 3-211

0x009C PCIE_PCI_IDS_1 PCIE_PCI_IDS_1 on page 3-211

0x00A0 PCIE_PCI_IDS_2 PCIE_PCI_IDS_2 on page 3-212

0x00A4 PCIE_PCI_LPM RW 32 PCIE_PCI_LPM Register on page 3-212

0x00A8 PCIE_PCI_IRQ_0 RW 32 PCIE_PCI_IRQ_0 Register on page 3-212

0x00AC PCIE_PCI_IRQ_1 PCIE_PCI_IRQ_1 Register on page 3-213

0x00B0 PCIE_PCI_IRQ_2 PCIE_PCI_IRQ_2 Register on page 3-214

0x00B4-0x00BF - - - Reserved.

0x00C0 PCIE_PEX_DEV RW 32 PCIE_PEX_DEV Register on page 3-214

0x00C4 - - - Reserved.

0x00C8 PCIE_PEX_LINK RW 32 PCIE_PEX_LINK Register on page 3-214


Programmers Model

0x00CC-0x00CF - - - Reserved.

0x00D0-0x00D3 - - - Reserved.

0x00D4 PCIE_PEX_SPC RW 32 PCIE_PEX_SPC Register on page 3-215

0x00D8 PCIE_PEX_SPC2 RW 32 PCIE_PEX_SPC2 Register on page 3-215

0x00DC PCIE_PEX_NFTS RW 32 PCIE_PEX_NFTS Register on page 3-216

0x00E0-0x00FB - - - Reserved.

0x00FC PCIE_BAR_WIN RW 32 PCIE_BAR_WIN Register on page 3-216

0x0100 PCIE_EQ_PRESET_LANE_0_1 RW 32 PCIE_EQ_PRESET_LANE_0_1 Register on page 3-217

0x0104 PCIE_EQ_PRESET_LANE_2_3 PCIE_EQ_PRESET_LANE_2_3 Register on page 3-218

0x0108-0x013F - - - Reserved.

0x0140 PCIE_CFGNUM RO 32 PCIE_CFGNUM Register on page 3-218

0x0144-0x0173 - - - Reserved.

0x0174 PM_CONF_0 RW 32 PM_CONF_0 Register on page 3-219

0x0178 PM_CONF_1 PM_CONF_1 Register on page 3-220

0x017C PM_CONF_2 PM_CONF_2 Register on page 3-220

Interrupt and event Registers descriptions on page 3-221

0x0180 IMASK_LOCAL RW 32 IMASK_LOCAL Register on page 3-221

0x0184 ISTATUS_LOCAL RW1C 32 ISTATUS_LOCAL Register on page 3-221

0x0188-0x018F - - - Reserved.

0x0190 IMSI_ADDR RO 32 IMSI_ADDR Register on page 3-222

0x0194 ISTATUS_MSI RW1C 32 ISTATUS_MSI Register on page 3-223

0x0198 ICMD_PM RW 32 ICMD_PM Register on page 3-223

0x019C-0x01D7 - - - Reserved.

0x01D8 ISTATUS_P_ADT_WIN0 RO 32 ISTATUS_P_ADT_WIN0 Register on page 3-224

0x01DC ISTATUS_P_ADT_WIN1 RO 32 ISTATUS_P_ADT_WIN1 Register on page 3-225

0x01E0 ISTATUS_A_ADT_SLV0 RO 32 ISTATUS_A_ADT_SLV0 Register on page 3-226

0x01E4-0x3F03 - - - Reserved.

Address translation Registers descriptions on page 3-226

Table 3-228 PCIe Root Port configuration Registers summary (continued)



Programmers Model

Note Program these registers before the Root Port is released from reset. See the RC_REL bit in PCIe Reset Control Register on page 3-192. Any changes to these registers after reset is released can lead to unpredictable results. The exceptions to this are the following registers:• IMASK_LOCAL Register on page 3-221.• ISTATUS_LOCAL Register on page 3-221.• ISTATUS_MSI Register on page 3-223.• ICMD_PM Register on page 3-223.

3.17.2 Control and status Registers descriptions

This section describes the control and status registers. Table 3-228 on page 3-202 provides cross references to individual registers.

BRIDGE_VER Register

The BRIDGE_VER Register characteristics are:

Purpose Bridge IP version and revision.




Figure 3-179 BRIDGE_VER Register bit assignments


0x0600-0x06FF ATR_PCIE_WIN0 RW 32 PCIe Window 0 address translation tables 0-7.

0x0700-0x07FF ATR_PCIE_WIN1 RW 32 PCIe Window 1 address translation tables 0-7.

0x0800-0x08FF ATR_AXI4_SLV0 RW 32 AXI4 Slave 0 address translation tables 0-7.

Table 3-228 PCIe Root Port configuration Registers summary (continued)


31 28 27 24 23 12 11 0

VERSIONDMA_NUMReserved PRODUCT_ID

Table 3-229 BRIDGE_VER Register bit assignments


[31:28] - Reserved.


Programmers Model

BRIDGE_BUS Register

The BRIDGE_BUS Register characteristics are:

Purpose Bridge internal bus.




Figure 3-180 BRIDGE_BUS Register bit assignments

[27:24] DMA_NUM Indicates the number of DMA engines implemented in the core. Supported values are in the range 4’h0-4’h8.

[23:12] PRODUCT_ID Provides the bridge IP product ID, equal to 12’h511.

[11:0] VERSION Provides the bridge IP core version. For example, 12’h123 indicates version 1.2.3 of the core.

Table 3-229 BRIDGE_VER Register bit assignments (continued)


31 28 27 24 23 12 11 0

VERSION

MAXRREQSIZEMAXPAYLOADWR_OUTREQ_N

20 19 16 15

RD_OUTREQ_NDATAPATH


Programmers Model


PCIE_IF_CONF Register

The PCIE_IF_CONF Register characteristics are:

Purpose PCIe interface configuration.




Figure 3-181 PCIE_IF_CONF Register bit assignments

Table 3-230 BRIDGE_BUS Register bit assignments


[31:28] MAXRREQSIZE Provides the maximum read request size of the bridge internal bus. Supported values are:0 128 bytes.1 256 bytes.2 512 bytes.3 1024 bytes.4 2048 bytes.5 4096 bytes.

[27:24] MAXPAYLOAD Provides the maximum payload size of the bridge internal bus. Supported values are:0 128 bytes.1 256 bytes.2 512 bytes.3 1024 bytes.4 2048 bytes.5 4096 bytes.

[23:20] WR_OUTREQ_N Number of outstanding write requests. Supported values are:8 256 outstanding requests.

[19:16] RD_OUTREQ_N Number of outstanding read requests. Supported values are:8 256 outstanding requests.

[15:12] DATAPATH Indicates the bridge internal bus data path width:5 256-bits

[11:0] VERSION Provides the bridge internal bus version. For example, 12’h123 indicates version 1.2.3 of the Bus.

31 28 27 24 23 12 11 0

VERSION

MAXRREQSIZEMAXPAYLOADP2B_MRD_OUTREQ_N

20 19 16 15

B2P_MRD_OUTREQ_NIF_ID


Programmers Model


PCIE_BASIC_CONF Register

The PCIE_BASIC_CONF Register characteristics are:

Purpose Provides information on the implementation of the PCIe Root Port core.




Table 3-231 PCIE_IF_CONF Register bit assignments


[31:28] MAXRREQSIZE Provides the maximum supported read request size for the PCIe interface. Supported values are:0 128 Bytes.1 256 Bytes.2 512 Bytes.3 1024 Bytes.4 2048 Bytes.5 4096 Bytes.

[27:24] MAXPAYLOAD Provides the maximum supported payload size for the PCIe interface. Supported values are:0 128 Bytes.1 256 Bytes.2 512 Bytes.3 1024 Bytes.4 2048 Bytes.5 4096 Bytes.

[23:20] P2B_MRD_OUTREQ_N Number of outstanding read requests from the PCIe domain that the bridge can handle simultaneously. Supported values are:0 1 outstanding request.1 2 outstanding requests. …7 128 outstanding requests.

[19:16] B2P_MRD_OUTREQ_N Number of outstanding read requests the bridge can issue to the PCIe domain. Supported values are:0 1 outstanding request.1 2 outstanding requests. …7 128 outstanding requests.

[15:12] IF_ID Provides the ID used to target this interface, that is, 0. This ID specifies the TRSL_ID fields of the Address translation Registers descriptions on page 3-226.

[11:0] VERSION Provides the PCI Express Controller core version. For example, 12’h123 indicates version 1.2.3 of the core.


Programmers Model

Figure 3-182 PCIE_BASIC_CONF Register bit assignments


PCIE_BASIC_STATUS Register

The PCIE_BASIC_STATUS Register characteristics are:

Purpose PCIe IP Basic Status.


31 28 27 24 23 8 0

LINK_WIDTHTYPE VC_NUM

20 19 16 15

LINK_SPEED

FUNC_NUM

COMPL

7

Table 3-232 PCIE_BASIC_CONF Register bit assignments


[31:28] TYPE Advertises the PCI Express core type. Supported values are:0x0 Native Endpoint.0x1 Root Port.Other values are reserved.

[27:24] COMPL Advertises the core compliance to PCI Express 3.0 specification. The only supported value is 0x3. Other values are reserved.

[23:20] VC_NUM Advertises the number of virtual channels implemented in the core. The only supported value is 0x1. Other values are reserved.

[19:16] FUNC_NUM Advertises the number of functions implemented in the core. Supported values are between 4'h1 and 4'h8. Other values are reserved.

[15:8] LINK_SPEED Advertises the supported link speed:Bit 0 Supports a 2.5 Gbps link speed.Bit 1 Supports a 5.0 Gbps link speed.Bit 2 Supports a 8.0 Gbps link speed.Bits 7-3 Reserved.

Note Several bits of this field can be asserted at the same time.

[7:0] LINK_WIDTH Advertises the supported link width:Bit 0 Supports x1 configuration. This bit is always asserted.Bit 1 Supports x2 configuration.Bit 2 Supports x4 configuration.Bit 3 Supports x8 configuration.Bit 4 Supports x16 configuration.Bit 5 Supports x32 configuration.Bits 7-6 Reserved.

Note You can assert several bits of this field at the same time.


Programmers Model



Figure 3-183 PCIE_BASIC_STATUS Register bit assignments


GEN_SETTINGS Register

This PCIE_CFGCTRL Register is depreciated. Software must use the PCIe configuration register instead.

31 28 27 24 23 8 0

NEG_LINK_WIDTH

NEG_LINK_SPEED

7

NEG_MAXPAYLOADNEG_MAXRREQSIZE

12 11

Reserved

Table 3-233 PCIE_BASIC_STATUS Register bit assignments


[31:28] NEG_MAXRREQSIZE Reports the negotiated maximum read request size of the PCIe link. Supported values are:0 128 bytes.1 256 bytes.2 512 bytes.3 1024 bytes.4 2048 bytes.5 4096 bytes.

[27:24] NEG_MAXPAYLOAD Reports the negotiated maximum Payload of the PCIe link. Supported values are:0 128 bytes.1 256 bytes.2 512 bytes.3 1024 bytes.4 2048 bytes.5 4096 bytes.


[11:8] NEG_LINK_SPEED Reports the negotiated link speed of the PCIe link. Supported values are:1 2.5 Gbps link speed.2 5.0 Gbps link speed.3 8.0 Gbps link speed.

[7:0] NEG_LINK_WIDTH Reports the negotiated link width of the PCIe link. Supported values are:01 x1 link width.02 x2 link width.04 x4 link width.08 x8 link width.10 x16 link width.


Programmers Model

PCIE_VC_CRED_0 Register

The PCIE_VC_CRED_0 Register characteristics are:

Purpose Enables system firmware to set the initial flow control credit values for Virtual Channel 0.

Usage constraints All fields in this register are set to their maximum legal values at reset. An initial value of 0x0 means infinite flow control credits. A Root Port must advertise infinite credits for completion data and completion headers, so the only legal value for completion credits is 0x0. The minimum legal value for the posted and non-posted credits is 0x1.



Note Software must not rely on the values of this register after reset and is therefore required to program this register with legal values before releasing the Root Port from reset. See the RC_REL bit in the PCIe Reset Control Register on page 3-192.

PCIE_VC_CRED_1 Register

The PCIE_VC_CRED_1 Register characteristics are:

Purpose Enables system firmware to set the initial flow control credit values for Virtual Channel 0.

Usage constraints All fields in this register are set to their maximum legal values at reset. An initial value of 0x0 means infinite flow control credits. A Root Port must advertise infinite credits for completion data and completion headers, so the only legal value for completion credits is 0x0. The minimum legal value for the posted and non-posted credits is 0x1.


Table 3-234 PCIE_VC_CRED_0 Register bit assignments


[31:28] NON_POSTED_DATA_CREDITS Bits [3:0] of Non-Posted data credits. Legal values are 0x01-0x10.

[27:20] NON_POSTED_HEADER_CREDITS Number of Non-Posted Header credits. Legal values are 0x01-0x0F.

[19:8] POSTED_DATA_CREDITS Number of Posted Data credits. Legal values are 0x01-0x0B8.

[7:0] POSTED_HEADER_CREDITS Number of Posted Header credits. Legal values are 0x01-0x18.


Programmers Model


Note Software must not rely on the values of this register after reset and is therefore required to program this register with legal values before releasing the Root Port from reset. See the RC_REL bit in the PCIe Reset Control Register on page 3-192.

PCIE_PCI_IDS_0

The PCIE_PCI_IDS_0 Register characteristics are:

Purpose PCIe PCI Standard Configuration Identification Settings.




PCIE_PCI_IDS_1






Table 3-235 PCIE_VC_CRED_1 Register bit assignments


[63:56] - Reserved.

[55:44] COMPLETION_DATA_CREDITS Number of Completion Data credits. Legal values is 0x0.

[43:36] COMPLETION_HEADER_CREDITS Number of Completion Header credits. Legal values is 0x0.

[35:32] NON_POSTED_DATA_CREDITS Bits [7:4] of Non-Posted Data credits. Legal values are 0x01-0x10.

Table 3-236 PCIE_PCI_IDS_0 Register bit assignments


[31:16] DEVICE_ID Sets the value of the PCIe Device ID for the Root Port.

[15:0] VENDOR_ID Sets the value of the PCIe Vendor ID for the Root Port.



[31:8] CLASS_CODE Sets the value of the PCIe Class code for the Root Port.

[7:0] REVISION_ID Sets the value of the PCIe Revision ID for the Root Port.


Programmers Model

PCIE_PCI_IDS_2






PCIE_PCI_LPM Register

The PCIE_PCI_LPM Register characteristics are:

Purpose Enables system firmware to set the values of the capability fields in the PCI Power Management Capabilities Register.




PCIE_PCI_IRQ_0 Register

The PCIE_PCI_IRQ_0 Register characteristics are:

Purpose PCI Interrupt, MSI, and MSI-X Settings, per function number.





[31:16] SUB_SYSTEM_DEVICE_ID Sets the value of the PCIe Sub-system device ID for the Root Port.

[15:0] SUB_SYSTEM_VENDOR_ID Sets the value of the PCIe Sub-system vendor ID for the Root Port.

Table 3-239 PCIE_PCI_LPM Register bit assignments


[31:27] PME_SUPPORT Enables PME support.

[26] D2_SUPPORT Enables D2 support.

[25] D1_SUPPORT Enables D1 support.

[24:22] AUXILIARY CURRENT_SUPPORT Sets Auxiliary current support.

[21] DSI Enables Device-specific initialization.

[20:0] - Reserved.


Programmers Model


Note The use of MSI and MSI-X generation by the Root Port is deprecated. Software must instead use the GICv2m to generate MSI or MSI-X interrupts.








Table 3-240 PCIE_PCI_IRQ _0 Register bit assignments


[31] MSI_X_ENABLE Enables MSI-X capability.

[30:27] - Reserved.

[26:16] TABLE_SIZE Size of MSI-X table.

[15:7] - Reserved.

[6:4] NUM_MSI Sets the number of MSI messages:000 1.001 2.... ...101 32.

[3] - Reserved.

[2:0] INT_PIN Interrupt Pin:000 None.001 INTA.010 INTB.011 INTC.100 INTD.

Table 3-241 PCIE_PCI_IRQ_1 Register bit assignments


[31:3] TABLE_OFFSET Sets the PCIe MSI-X table offset field.

[2:0] TABLE_BIR Sets the PCIe MSI-X table BIR field.


Programmers Model








PCIE_PEX_DEV Register

The PCIE_PEX_DEV Register characteristics are:

Purpose Enables system firmware to set the values of the capability fields in the PCI Express Device Capabilities Register.




PCIE_PEX_LINK Register

The PCIE_PEX_LINK Register characteristics are:

Purpose Enables system firmware to set the values of the capability fields in the PCI Express Link Capabilities Register.


Table 3-242 PCIE_PCI_IRQ_2 Register bit assignments


[31:3] PBA_OFFSET Sets the PCIe MSI-X PBA offset field.

[2:0] PBA_BIR Sets the PCIe MSI-X PBA BIR field.

Table 3-243 PCIE_PEX_DEV Register bit assignments


[31:12] - Reserved.

[11:9] EP_LAT_L1 Endpoint L1 acceptable latency.

[8:6] EP_LAT_L0S Endpoint L0s acceptable latency.

[5:3] - Reserved.

[2:0] MAX_PAYLOAD_SIZE Maximum payload size.


Programmers Model



PCIE_PEX_SPC Register

The PCIE_PEX_SPC Register characteristics are:

Purpose Enables system firmware to set the values of miscellaneous capability fields in the PCI Configuration Space.




PCIE_PEX_SPC2 Register

The PCIE_PEX_SPC2 Register characteristics are:

Purpose Enables system firmware to set the values of miscellaneous capability fields in the PCI Configuration Space.

Table 3-244 PCIE_PEX_LINK Register bit assignments


[31:24] PORT_NUM Sets the port number.

[23:18] - Reserved.

[17:15] L1_EXIT_LAT Sets the L1 exit latency.

[14:12] L0S_EXIT_LAT Sets the L0s exit latency.

[11] ASPM_L1 Enables ASPM L1 support.

[10] ASPM_L0S Enables ASPM L0s support.

[9:0] - Reserved.

Table 3-245 PCIE_PEX_SPC Register bit assignments


[31] AER_ENABLE Enable Advanced Error Reporting Capability.

[30:21] - Reserved.

[20:16] DEV_NUM_RP Sets the device number of the Root Port.

[15] RP_RCB Sets the Root Port Read Completion Boundary.

[14] LINK_DE_EMPHASIS Sets the initial value of the Selectable de-emphasis field in the Link Control 2 registers.

[13] CLK_CONFIG Sets the Slot Clock Configuration field in the PCIe Link Status Register:0 Independent.1 refclk.

[12] SLOT_REG_IMPL Enables PCIe Slot registers.

[11:0] - Reserved.


Programmers Model




PCIE_PEX_NFTS Register

The PCIE_PEX_NFTS Register characteristics are:

Purpose Number of Fast Training Sequences Settings.




PCIE_BAR_WIN Register

The PCIE_PEX_NFTS Register characteristics are:

Purpose PCIe Windows Settings, per function number.



Table 3-246 PCIE_PEX_SPC2 Register bit assignments


[31:23] - Reserved.

[22:18] ASPM_L1_DLY ASPM L1 entry delay, in steps of 256ns.

[17:13] ASPM_L0_DLY ASPM L0s entry delay, in steps of 256ns.

[12:8] PCIE_MSI_MESSAGE_NUM PCI Express MSI message number.

[7:3] AER_MSI_MESSAGE_NUM AER MSI message number.

[2] ECRC_CHECK_ENABLE Enables the ECRC Check Capable bit in the PCI Express Advanced Error Capabilities and Control Register.

[1] ECRC_GEN_ENABLE Enables the ECRC Generation Capable bit in the PCI Express Advanced Error Capabilities and Control Register.

[0] - Reserved.

Table 3-247 PCIE_PEX_NFTS Register bit assignments


[31:24] - Reserved.

[23:16] FTS_8GBPS Number of fast training sequences at 8.0 Gbps.




Programmers Model


PCIE_EQ_PRESET_LANE_0_1 Register

The PCIE_EQ_PRESET_LANE_0_1 Register characteristics are:

Purpose Sets the values of the Lane Equalization Control Register of the Secondary PCI Express Extend Capability.




Note Transmitter preset and receiver preset values must be set to legal values, as specified in the PCI Express Specification.

Table 3-248 PCIE_BAR_WIN Register bit assignments


[31:4] - Reserved.

[3] PREFETCH_WIN64_ENABLE Prefetchable memory window 64-bit addressing support.

[2] PREFETCH_WIN_ENABLE Prefetchable memory window implemented.

[1] IO_WIN32_ENABLE IO window 32-bit addressing support.

[0] IO_WIN_ENABLE IO window implemented.

Table 3-249 PCIE_EQ_PRESET_LANE_0_1 Register bit assignments


[31] - Reserved.

[30:28] LANE1_UP_RCV_HINT Sets the value of the upstream port receiver preset hint for lane 1.

[27:24] LANE1_UP_TRS_PRES Sets the value of the upstream port transmitter preset for lane 1.

[23] - Reserved.

[22:20] LANE1_DWN_RCV_HINT Sets the value of the downstream port receiver preset hint for lane 1.

[19:16] LANE1_DWN_TRS_HINT Sets the value of the downstream port transmitter preset for lane 1.

[15] - Reserved.


[11:8] LANE0_UP_TRS_PRES Sets the value of the upstream port transmitter preset hint for lane 0.

[7] - Reserved.

[6:4] LANE0_DWN_RCV_HINT Sets the value of the downstream port receiver preset hint or lane 0.

[3:0] LANE0_DWN_TRS_HINT Sets the value of the downstream port transmitter preset hint for lane 0.


Programmers Model

PCIE_EQ_PRESET_LANE_2_3 Register

The PCIE_EQ_PRESET_LANE_2_3 Register characteristics are:

Purpose Sets the values of the Lane Equalization Control Register of the Secondary PCI Express Extend Capability.




PCIE_CFGNUM Register

The PCIE_CFGNUM Register characteristics are:

Purpose Selects the configuration space that the bridge configuration space accesses.

Usage constraints None.


Table 3-250 PCIE_EQ_PRESET_LANE_2_3 register bit assignments


[31] - Reserved.


[27:24] LANE3_UP_TRS_PRES Sets the value of the upstream port transmitter preset for lane 3.

[23] - Reserved.

[22:20] LANE3_DWN_RCV_HINT Sets the value of the downstream port receiver preset hint for lane 3.

[19:16] LANE3_DWN_TRS_HINT Sets the value of the downstream port transmitter preset for lane 3.

[15] - Reserved.


[11:8] LANE2_UP_TRS_PRES Sets the value of the upstream port transmitter preset hint for lane 2.

[7] - Reserved.

[6:4] LANE2_DWN_RCV_HINT Sets the value of the downstream port receiver preset hint or lane 2.

[3:0] LANE2_DWN_TRS_HINT Sets the value of the downstream port transmitter preset hint for lane 2.


Programmers Model


Note This register is deprecated. Software must use the ECAM method of accessing the PCI Configuration Space. See the PCI Express Base Specification Revision 3.0.

PM_CONF_0 Register

The PM_CONF_0 Register characteristics are:

Purpose PCI Power Management Data Register. PCI Power Management Data Register provides the scaling factor and state dependant data related to the power state selected by the Data Select Register in the Power Budgeting Capability.




Table 3-251 PCIE_CFGNUM Register bit assignments


[20] FORCE_BE When asserted, the byte enable of the CFG read or write request is forced to the BYTE_EN field value, regardless of AXI strobes. This might be required, for example, when targeting the R1C register, because there is no read strobe in the AXI protocol.

[19:16] BYTE_EN CFG byte enable.

[15:8] BUS_NUMBER Bus Number.

[7:3] DEVICE_NUMBER Device Number.

[2:0] FUNC_NUMBER Function Number.

Table 3-252 PM_CONF_0 Register bit assignments


[31:30] DATA_SCALE_7 Data scale value returned when the Data Select Register is set to 0x7:0x0 Reserved.0x1 0.1 multiplier.0x2 0.01 multiplier.0x3 0.001 multiplier.

[29:28] DATA_SCALE_6 Data scale value returned when the Data Select Register is set to 0x6.






Programmers Model

Note See the PCI Power Management Specification, v1.2 for a full description of this register.

PM_CONF_1 Register







PM_CONF_2 Register







[15:0] - Reserved.

Table 3-252 PM_CONF_0 Register bit assignments (continued)



Bit Name Description

[31:24] DATA_VALUE_3 Sets the value returned in the Base Power field when the Data Select Register is 0x3.





Programmers Model



3.17.3 Interrupt and event Registers descriptions

This section describes the interrupt and event registers that enable, disable, monitor and clear interrupt sources. Table 3-228 on page 3-202 provides cross references to individual registers.

IMASK_LOCAL Register

The IMASK_LOCAL Register characteristics are:

Purpose Root Port Interrupt Mask. Setting a bit enables the associated interrupt source and clearing a bit masks the interrupt source. See ISTATUS_LOCAL Register for information about the bits of this register.



ISTATUS_LOCAL Register

The ISTATUS_LOCAL Register characteristics are:

Purpose Root Port Interrupt Status.The bits of this register are automatically set when the corresponding interrupt source is activated. Each source is independent and therefore multiple sources might be active simultaneously. Software can monitor and clear status bits:• Writing 1 clears a bit.• Writing 0 has no effect.If one or more ISTATUS_LOCAL interrupt sources are active and not masked by IMASK_LOCAL, an interrupt is asserted as Table 3-3 on page 3-4 shows.










Programmers Model


Note The use of ISTATUS_LOCAL and IMASK_LOCAL for the following interrupts is deprecated:• System error.• PM/Hotplug.• AER.• MSI.• INTx.

Software must use the GIC to control and clear interrupts.

IMSI_ADDR Register

The IMSI_ADDR Register characteristics are:

Purpose Specifies the address that the Root Port uses to trigger an MSI interrupt to the application processor.


Table 3-255 ISTATUS_LOCAL Register bit assignments


[31:24] PM_MSI_INT Reports Power Management, MSI and Interrupts events to the application processor:7 System error signaled, Root Port only, reserved for Endpoint.6 PM/Hotplug event for Root Port, Legacy power management state change for Endpoint.5 AER Event, RP only, reserved for EP.4 MSI received, RP only, reserved for EP.3 Asserted when PCI interrupt line D is asserted, RP only, reserved for EP.2 Asserted when PCI interrupt line C is asserted, RP only, reserved for EP.1 Asserted when PCI interrupt line B is asserted, RP only, reserved for EP.0 Asserted when PCI interrupt line A is asserted, RP only, reserved for EP.When one of these interrupt’s sources is activated, an interrupt asserted as Table 3-3 on page 3-4 shows.

[23:20] P_ATR_EVT Reports PCIe address translation events:3 PCIe Doorbell. Asserted when a PCIe request has successfully targeted an address

translation table.2 PCIe Discard Error. Asserted to signal a completion timeout on a PCIe read request.1 PCIe Fetch Error. Asserted to indicate that an error occurred on a PCIe read request.0 PCIe Post Error. Asserted to indicate that an error occurred on a PCIe write request.

[19:16] A_ATR_EVT Reports AXI address translation events:3 AXI Doorbell. Asserted when an AXI request has successfully targeted an address

translation table.2 AXI Discard Error. Asserted to signal a completion timeout on an AXI read request.1 AXI Fetch Error. Asserted to indicate that an error occurred on an AXI read request.0 AXI Post Error. Asserted to indicate that an error occurred on an AXI write request.

[15:8] DMA_ERROR Reports that an error occurred during a DMA transfer. Bit number i corresponds to DMA Engine number i.

[7:0] DMA_END Reports that a DMA transfer is ended. Bit number i corresponds to DMA Engine number i.


Programmers Model


Note • This address is 64-bit aligned. Bits [2:0] are 000.• This register is deprecated. Software must use the GICv2m for MSI.

ISTATUS_MSI Register

The ISTATUS_MSI Register characteristics are:

Purpose MSI Message. This is a read/write/clear register. Bits [31:0] are asserted when an MSI with message number 31-0 is received. The application processor must monitor and clear these bits:• Writing 1 clears a bit.• Writing 0 has no effect.

Note MSI messages with numbers greater than 31 are ignored and discarded.



Note This register is deprecated. Software must use the GICv2m for MSI.

ICMD_PM Register

The ICMD_PM Register characteristics are:

Purpose Event Command. Enables the application processor to activate and send events to the PCIe bus.




ISTATUS_PM Register

The ISTATUS_PM Register characteristics are:

Purpose PCI Legacy Power Management State. Reports the PCIe power state.

Table 3-256 ICMD_PM Register bit assignments


[31:5] - Reserved.

[4] LINK_OFF The application processor can send a Turn Off Link command to start L2 state entry negotiation. If the Endpoint device is also ready to enter this state, then both devices enter L2 state and this link is turned off. Deasserting this signal forces the core to exit L2 state and wakes the link.

[3:0] - Reserved.


Programmers Model




ISTATUS_P_ADT_WIN0 Register

The ISTATUS_P_ADT_WIN0 Register characteristics are:

Purpose Address Translation Table WIN0 interrupt status.




Table 3-257 ISTATUS_PM Register bit assignments


[31:2] Reserved. Reserved.

[1:0] Specifies the PCI Legacy Power Management state:00 D0.01 D1.10 D211 D3hot or D3cold.It is used when the PCIe is Endpoint.

Note Change in the power management state is reported by an interrupt in the ISTATUS_LOCAL register, bit 6 of PM_MSI_INT Field.

Specifies the PCI Legacy Power Management state:00 D0.01 D1.10 D211 D3hot or D3cold.It is used when the PCIe is Endpoint.

Note Change in the power management state is reported by an interrupt in the ISTATUS_LOCAL register, bit 6 of PM_MSI_INT Field.

Table 3-258 ISTATUS_P_ADT_WIN0 Register bit assignments


[31:28] ATT7 Interrupt status for address translation table 7









Programmers Model

Table 3-259 shows the form of each nibble.

ISTATUS_P_ADT_WIN1 Register

The ISTATUS_P_ADT_WIN1 Register characteristics are:

Purpose Address Translation Table WIN1 interrupt status.





Table 3-259 ISTATUS_P_ADT_WIN0 Register nibble form


[3] DOORBELL PCIe Doorbell interrupt status. Indicates that a successful PCIe request has been translated.

[2] DIS_ERR PCIe Discard Error interrupt status. Indicates a completion timeout on a PCIe read request.

[1] FETCH_ERR PCIe Fetch Error interrupt status. Indicates that an error has occurred with a PCIe read request.

[0] POST_ERR PCIe Post Error interrupt status. Indicates that an error has occurred with a PCIe write request.

Table 3-260 ISTATUS_P_ADT_WIN1 Register bit assignments










Table 3-261 ISTATUS_P_ADT_WIN1 Register nibble form


[3] DOORBELL PCIe Doorbell interrupt status. Indicates that a successful PCIe request has been translated.

[2] DIS_ERR PCIe Discard Error interrupt status. Indicates a completion timeout on a PCIe read request.

[1] FETCH_ERR PCIe Fetch Error interrupt status. Indicates that an error has occurred with a PCIe read request.

[0] POST_ERR PCIe Post Error interrupt status. Indicates that an error has occurred with a PCIe write request.


Programmers Model

ISTATUS_A_ADT_SLV0 Register

The ISTATUS_A_ADT_SLV0 Register characteristics are:

Purpose Address Translation Table AXI Slave0 interrupt status.





Note An AXI transaction is a transaction that the application processor issues to the PCIe system.

3.17.4 Address translation Registers descriptions

This section describes the address translation registers. Table 3-228 on page 3-202 provides cross references to individual registers.

Three sets of Address Translation Tables exist, and each set contains up to eight individual programmable tables.

Two sets of Address Translation Tables translate from the PCIe address space to the application processor address space, one for each BAR implemented by the Root Port.

Table 3-262 ISTATUS_A_ADT_SLV0 Register bit assignments










Table 3-263 ISTATUS_A_ADT_SLV0 Register nibble form


[3] DOORBELL AXI Doorbell interrupt status. Indicates that a successful AXI request has been translated.

[2] DIS_ERR AXI Discard Error interrupt status. Indicates a completion timeout on a AXI read request.

[1] FETCH_ERR AXI Fetch Error interrupt status. Indicates that an error has occurred with a AXI read request.

[0] POST_ERR AXI Post Error interrupt status. Indicates that an error has occurred with a AXI write request.


Programmers Model

The other table performs address translation from the application processor address space to the PCIe address space.

Table 3-264 shows the layout of the individual address translation tables within the set.

Table 3-265 shows the registers within an address translation table.

Note • Table 0 of AXI4 Slave 0 Address Translation Tables is RO and is configured to map the

PCIe configuration space to 0x4000_0000 in the application processor memory map.

• Tables 1-7 are RW and software must use these to map the address translation from the application processor address space to the PCIe address space.

• SRC_ADDR and TRSL_ADDR are aligned to the size of the translation table.

Note If an address translation event occurs, it is reported to the ISTATUS_X_ADT_X registers and ISTATUS_LOCAL Register on page 3-221.

You can enable interrupts by using the IMASK_LOCAL Register on page 3-221 and clear interrupts by using the ISTATUS_LOCAL Register on page 3-221.

Table 3-264 Address translation table register blocks

Address range Name Description

0x00-0x1F TABLE0 Registers for address translation table 0.





0xA0-0xBF TABLE5 Registers for address translation table 5.

0xC0-0xDF TABLE6 Registers for address translation table 6.

0xE0-0xFF TABLE7 Registers for address translation table 7.

Table 3-265 Address translation table Registers


0x00-0x03 SRC_ADDR_LO RW 32 SRC_ADDR_LO Register on page 3-228

0x04-0x07 SRC_ADDR_UP RW 32 SRC_ADDR_UP Register on page 3-228

0x08-0x0B TRSL_ADDR_LO RW 32 TRSL_ADDR_LO Register on page 3-228

0x0C-0x0F TRSL_ADDR_UP RW 32 TRSL_ADDR_UP register on page 3-229

0x10-0x13 TRSL_PARAM RW 32 TRSL_PARAM Register on page 3-229

0x14-0x17 - RO - Reserved

0x18-0x1F TRSL_MASK RO 32 TRSL_MASK Register on page 3-230


Programmers Model

SRC_ADDR_LO Register

The SRC_ADDR_LO Register characteristics are:

Purpose Sets the source address and size of the region of memory that incoming transactions must address for the translation table to be applied.




SRC_ADDR_UP Register

The SRC_ADDR_UP Register characteristics are:

Purpose Sets the upper 32 bits of the source address.




TRSL_ADDR_LO Register

The TRSL_ADDR_LO Register characteristics are:

Purpose Sets bits [31:12] of the translated address.



Table 3-266 SRC_ADDR_LO Register bit assignments


[31:12] SRC_ADDR [31:12] Bits 31 to 12 of the source address.

[11:7] - Reserved.

[6:1] ATR_SIZE Defines the Address Translation Space Size. This space size in bytes is equal to 2(ATR_SIZE +1).Permitted values for this field are from 6’d11 (212 =4 KBytes) to 6’d63 (264 = 16 Exabytes) only.

[0] ATR_IMP When set to 1, indicates that the Translation Address Table is enabled.

Table 3-267 SRC_ADDR_UP Register bit assignments


[31:0] SRC_ADDR[63:32] Bits [63:32] of the source address.


Programmers Model


TRSL_ADDR_UP register

The TRSL_ADDR_UP Register characteristics are:

Purpose Sets bits [63:32] of the translated address.




TRSL_PARAM Register

The TRSL_PARAM Register characteristics are:

Purpose Sets the transaction properties and destination of the transactions that this table translates.



Table 3-268 TRSL_ADDR_LO Register bit assignments


[31:12] TRSL_ADDR[31:12] Bits [31:12] of the translated address.

[11:0] - Reserved.

Table 3-269 TRSL_ADDR[63:32] Register bit assignments


[31:0] TRSL_ADDR[63:32] Bits [63:32] of the translated address.


Programmers Model


TRSL_MASK Register

The TRSL_MASK Register characteristics are:

Purpose Defines the translation table mask address. It is equal to:

264 – Table Size

Where the table size is equal to 2(ATR_SIZE +1). For example, if the table size is fixed to 256 KBytes, TRSL_MASK is equal to:16EB – 256KBytes = 64’hFFFFFFFFFFFC0000.

Table 3-270 TRSL_PARAM Register bit assignments


[31:28] - Reserved.

[27:16] TRSF_PARAM Defines the parameters of the translated transactions:If TRSL_ID is PCIe:[11] Reserved.[10:8] Traffic class.[7] ECRC Forward.[6] EP.[5:4] Attr.[3] Reserved.[2:0] TLP Type, as follows:

3'b000 Memory.3'b001 Memory Locked.3'b010 IO.3'b100 Message.

If TRSL_ID is AXI4 Master:[11:8] AxQOS.[7:5] AxPROT. AxPROT[1] is controlled by the MS bit in the Secure Register on

page 3-196.[4] AxLOCK.[3:0] AxCACHE.

[15:4] - Reserved.

[3:0] TRSL_ID Sets the target for the translated transaction. The permitted values are:4’d0 PCIe Tx/Rx interface.4’d1 PCIe config interface.

Note Table 0 of ATR_AXI_SLV0 is configure to map 0x4000_0000 to the PCIe

configuration space. ARM recommends that software does not map another region of memory to the configuration space.

4’d4 AXI4 Master 0.

Note All other values are reserved.


Programmers Model

This register is automatically updated when ATR_SIZE in the SRC_ADDR_LO Register on page 3-228 is updated.




Programmers Model

3.18 MSI RegistersThis section describes the Message Signaled Interrupt (MSI) Registers. It contains the following subsections:• Register summary.• Register descriptions.


Table 3-271 shows the MSI Registers in offset order from the base memory address.


This section describes the MSI registers. Table 3-271 provides cross references to individual registers.

Table 3-271 MSI Registers summary

Address Register name Type Reset Description

0x0000-0x0004 - - 0x0 Reserved. RAZ/WI

0x0008 MSI_TYPER RO IMPLEMENTATION DEFINED MSI_TYPER Register on page 3-233

0x000C-0x003C - - 0x0 Reserved. RAZ/WI

0x0040 MSI_SETSPI_NSR WO - MSI_SETSPI_NSR Register on page 3-233

0x0044 – 0x0FC8 - - 0x0 Reserved. RAZ/WI

0x0FCC MSI_IIDR RO 0x0AE0043B MSI_IIDR Register on page 3-233

0x0FD0 Peripheral ID4 RO 0x4 Peripheral ID Register 4 on page 3-233

0x0FE0 Peripheral ID0 RO 0xAE Peripheral ID Register 0 on page 3-234

0x0FE4 Peripheral ID1 RO 0xB0 Peripheral ID Register 1 on page 3-234

0x0FE8 Peripheral ID2 RO 0x1B Peripheral ID Register 2 on page 3-235

0x0FEC Peripheral ID3 RO 0x0 Peripheral ID Register 3 on page 3-235

0x0FF0 Component ID0 RO 0xD Component ID Register 0 on page 3-236

0x0FF4 Component ID1 RO 0xF0 Component ID Register 1 on page 3-236

0x0FF8 Component ID2 RO 0x5 Component ID Register 2 on page 3-237

0x0FFC Component ID3 RO 0xB1 Component ID Register 3 on page 3-237

0x1000-0xFFFF - - 0x0 Reserved. RAZ/WI


Programmers Model

MSI_TYPER Register


MSI_SETSPI_NSR Register

See the Server Base System Architecture Platform Design Document, http://infocenter.arm.com/help/topic/com.arm.doc.den0029/index.html.

MSI_IIDR Register




Purpose PID4.




Table 3-272 MSI_TYPER Register bit assignments


[31:26] - Reserved

[25:16] Base SPI number Returns the lowest SPI assigned to the frame. For:Frame 0 Value reads as 224.Frame 1 Value reads as 256.Frame 2 Value reads as 288.Frame 3 Value reads as 320.

[15:10] - Reserved

[9:0] Number of SPIs Number of contiguous SPIs assigned to the frame:0x20 32 contiguous SPIs.All other values Reserved.

Table 3-273 MSI_IIDR Register bit assignments


[31:20] - Product ID.

[19:16] - Architecture Version. 0x0 for GICv2m v0.

[15:12] - Revision.

[11:8] CONT CODE JEP106 continuation code.

[7] - Reserved. RAZ

[6:0] JEP106 ID JEP106 identity code.


Programmers Model





Purpose Peripheral identification 0.












4KBReserved

31 078 34

CONT CODE




[7:4] 4KB Number of 4KB blocks used by this component in a power of 2 format. For the ADP MSI, the value is 0x6.

[3:0] CONT CODE The JEP106 continuation code. For ARM Limited, this field is 0x4.

PART NOReserved

31 078




[7:0] PART NO Part Number[7:0]. Reads as 0xAE.


Programmers Model
















PART NOJEP106 IDReserved

31 078 34




[7:4] JEP106 ID JEP106 Identity code [3:0]. For ARM Limited, the value is 0xB.

[3:0] PART NO Part Number [11:8]. Reads as 0x0.

1ARCH REVReserved

31 078 34

JEP106 ID

2




[7:4] ARCHREV Revision Number. Incremental value starting at 0x0. For the ADP MSI, the value is 0x0.

[3] 1 Treat as RAO.

[2:0] JEP106 ID JEP106 Identity code [6:4]. For ARM Limited, the value is 0x3.


Programmers Model






Purpose Identification 0.












CUST MODREVANDReserved

31 078 34




[7:4] REVAND Indicates minor errata fixes specific to this design, for example, metal fixes. For the ADP MSI, the value is 0x0.

[3:0] CUST MOD Indicates customer modification to reusable IP. For the ADP MSI, the value is 0x0.

PREAMBLEReserved

31 078




[7:0] PREAMBLE 0x0D.


Programmers Model

















PREAMBLEReserved

31 078 34

COMPONENT CLASS




[7:4] COMPONENT CLASS The class of the component. For the CSS MSI, the value is 0xF.

[3:0] PREAMBLE The value is 0x0.

PREAMBLEReserved

31 078




[7:0] PREMABLE The value is 0x05.


Programmers Model



PREAMBLEReserved

31 078




[7:0] PREAMBLE The value is 0xB1.


Programmers Model

3.19 Trusted Entropy Source RegistersThis section describes the Trusted Entropy Source Registers. It describes:• Register summary.• Register descriptions.




This section describes the trusted entropy source registers. Table 3-283 provides cross references to individual registers.

RNG Output, OUTPUT_0, Register

The RNG Output, OUTPUT_0, Register characteristics are:

Purpose Least significant word of the 128-bit random number.



Table 3-283 Trusted Entropy Source Registers summary

Offset Type Reset value Name Description

0x00 RO 0x0 OUTPUT_0 RNG Output, OUTPUT_0, Register

0x04 RO 0x0 OUTPUT_1 RNG Output, OUTPUT_1, Register on page 3-240

0x08 RO 0x0 OUTPUT_2 RNG Output, OUTPUT_2, Register on page 3-240

0x0C RO 0x0 OUTPUT_3 RNG Output, OUTPUT_3, Register on page 3-240

0X10 RW 0x0 STATUS Status, STATUS, Register on page 3-241

0x14 RW 0x0 INTMASK Interrupt Mask, INTMASK, Register on page 3-241

0x18 RW 0x0 OSC_TIME Oscillation Time Register

0X1C WO 0x0 CONTROL Control, CONTROL, Register on page 3-242

0xFD0 RO 0x04 PID4 Peripheral ID Register 4 on page 3-233

0xFE0 RO 0xAA PID0 Peripheral ID Register 0 on page 3-234

0xFE4 RO 0xB0 PID1 Peripheral ID Register 1 on page 3-234

0xFE8 RO 0x2B PID2 Peripheral ID Register 2 on page 3-235

0xFEC RO 0x00 PID3 Peripheral ID Register 3 on page 3-235

0xFF0 RO 0x0D COMPID0 Component ID Register 0 on page 3-236

0xFF4 RO 0xF0 COMPID1 Component ID Register 1 on page 3-236

0xFF8 RO 0x05 COMPID2 Component ID Register 2 on page 3-237

0xFFC RO 0xB1 COMPID3 Component ID Register 3 on page 3-237


Programmers Model




Purpose Second word of the 128-bit random number.






Purpose Third word of the 128-bit random number.






Purpose Most significant word of the 128-bit random number.



Table 3-284 RNG Output Register (OUTPUT_0)


[31:0] Output [31:0] Least significant word of 128-bit word of random data. This is only valid when the Ready bit in the Status, STATUS, Register on page 3-241 is set HIGH.

Table 3-285 RNG Output, OUTPUT_1, Register bit assignments


[31:0] Output [63:32] Second word of 128-bit word of random data. This is only valid when the Ready bit in the Status, STATUS, Register on page 3-241 is set HIGH.



[31:0] Output [95:64] Third word of 128-bit word of random data. This is only valid when the Ready bit in the Status, STATUS, Register on page 3-241 is set HIGH.


Programmers Model


Status, STATUS, Register

The Status, STATUS, Register characteristics are:

Purpose Indicates that a new 128-bit random number is available.




Figure 3-193 Status, STATUS, Register bit assignments


Interrupt Mask, INTMASK, Register

The Interrupt Mask, INTMASK, Register characteristics are:

Purpose The RNG generates an interrupt when the new random number is ready, if the mask register is set.




Figure 3-194 Interrupt Mask, INTMASK, Register bit assignments



[31:0] Output [127:96] Final word of 128-bit word of random data. This is only valid when the Ready bit in the Status, STATUS, Register is set HIGH.

31

Reserved

01

Ready

Table 3-288 Status, STATUS, Register bit assignments


[31:1] - Reserved bits.

[0] Ready If set HIGH, data is available in the OUTPUT_0:3 registers.Acknowledging this state by setting bit [0] of this register HIGH resets the output value, and acknowledges the interrupt, if enabled through the Interrupt Mask, INTMASK, Register.

31

Reserved

01

Ready_mask


Programmers Model


Configuration, CONFIG, Register

The Configuration, CONFIG, Register characteristics are:

Purpose Configures the RNG.




Control, CONTROL, Register

The Control, CONTROL, Register characteristics are:

Purpose Configures the RNG.




Figure 3-195 Control, CONTROL, Register bit assignments

Table 3-289 Interrupt Mask, INTMASK, Register bit assignments


[31:1] - Reserved bits.

[0] Ready_mask If this bit is set HIGH, the interrupt line is asserted when the ready condition is true.

Table 3-290 Configuration, CONFIG, Register bit assignments


[31:0] Sample_clocks This field programs the enable pulse width for the Entropy Source. The pulse width for the Enable control is equal to sample_clocks clock cycles. If you program it LOW, the enable is held asserted for one cycle.The pulse width limits are as follows:Minimum 1 clock cycle.Maximum (232 – 1) = 231 clock cycles.This field can only be written when the enable_trng bit in Control, CONTROL, Register is deasserted.

31

Reserved

012

Abort trngEnable trng


Programmers Model


Note This is a self-clearing register.

Table 3-291 Control, CONTROL, Register bit assignments


[31:2] - Reserved.

[1] Abort_trng Setting the bit to 1 aborts the entropy gathering tasks by de-asserting the “Enable” control and resetting the output value registers. This bit automatically clears to 0.

[0] Enable_trng Setting this bit to 1 starts the TRNG gathering entropy from the entropy source. This bit automatically clears after de-asserting the “Enable” control to the entropy source.


Appendix A Power and Access Control Sequences

This chapter describes the Juno ARM Development Platform (ADP) power and access control sequences. It contains the following section:• About power and access control sequences on page A-2.

ARM DDI 0515A-3b Copyright © 2014. All rights reserved. A-1ID050214 Confidential - Draft

Power and Access Control Sequences

A.1 About power and access control sequencesThis section describes software and system requirements for power region state transitions. It contains the following subsections:• Cortex-A57 power domains, A57SSTOP, A57CPU[n].• Cortex-A53 power domains, A53SSTOP, A53CPU[n] on page A-4.• System power domain, SYSTOP on page A-4.• Mali-T624 power domain, GPUTOP on page A-5.

A.1.1 Cortex-A57 power domains, A57SSTOP, A57CPU[n]

Before you power up any power domains in the Cortex-A57 cluster, you must first power up and configure the SYSTOP power domain. See System power domain, SYSTOP on page A-4.

This section describes:• Enabling A57CLK at system clock-generation level.• Managing powerup transitions for the VA57 power regions.• Managing powerdown transitions for the VA57 power regions on page A-3.• Managing powerdown transitions for the A57SSTOP power domain on page A-3.

Enabling A57CLK at system clock-generation level

Enable A57CLK at the system clock-generation level before you power up any VA57 region as follows:

1. Ensure that the source and divider settings are correct in the A57 Clock Control Register. See Cluster Clock Control Register on page 3-113.

2. Set the A57CLKEN bit in the System Clock Enable Set Register on page 3-119.

3. Set the A57INCLKSTOPPED bit in the Clock Stopped Clear Register on page 3-122, to clear the bit that specifies that the clock is running.

SYSTOP must remain on until all power domains in the Cortex-A57 cluster are powered down.

Note The first VA57 power region to be powered up must be A57SSTOP.

Managing powerup transitions for the VA57 power regions

Manage powerup transitions for the VA57 power regions as follows:

1. Set the POLICY bit in the A57SSTOP PPU Policy Register to ON.

2. Power region powerup is complete when an interrupt is detected from the PPU or the POWSTAT bit in the A57SSTOP PPU Power Status Register indicates this power state.

3. The SCP then powers a core, for example, A57CPU[0], setting the POLICY bit in the A57CPU[x] PPU to ON.

4. Manage snoop slave access control.

5. When one core is available, and the reset is released, it determines, from the SSC_GPRETN Register on page 3-41, the boot type and L2 cache retention status and takes appropriate action.



6. The SCP can power additional cores, using the corresponding PPU, after a message request from the OS.

Managing powerdown transitions for the VA57 power regions

Manage powerdown transitions for the VA57 power regions as follows:

1. To power down a core, the OS sends a message to the SCP to indicate that it is ready to power down, context saved, at the next STANDBYWFI.

2. When saving context, the core must mask interrupts to the core in the GIC-400 to prevent exit from STANDBYWFI before the power down sequence has completed.

3. The SCP programs the POLICY bit in the A57CPU[x] PPU Policy Register to OFF, ensuring that the HWCACTIVEEN bit is set in the Power Configuration Register on page 3-146. See also Power Policy Register on page 3-144.

4. When the processor STANDBYWFI is asserted, the power down sequence completes.

Managing powerdown transitions for the A57SSTOP power domain

Manage powerdown transitions for the A57SSTOP power regions as follows:

1. When powering down the last core, the OS indicates the following in the message format:• Whether A57SSTOP is also to be powered down.• Whether the L2 cache requires flushing using the SCP-controlled L2 cache flush

mechanism. See Cortex-A57 L2 Flush Control Register on page 3-126.

2. Wait until all CPU power down sequences are complete, as the PPU interrupts indicate.

Note You can skip steps a-d if the L2 cache is already flushed.

If you require a SCP-controlled L2 cache flush:a. Set the FLUSHREQ bit in the Cortex-A57 L2 Flush Control Register on

page 3-126.b. Wait for the FLUSHDONE bit to be set.

This can use the A57 L2 Flush Done Interrupt to the SCP.c. Clear the FLUSHREQ bit in the Cortex-A57 L2 Flush Control Register on

page 3-126.d. Wait for the FLUSHDONE bit to be cleared.

This can use the A57 L2 Flush Done Interrupt to the SCP.

3. Program the CCI-400 to remove the Cortex-A57 cluster from coherency.

Note You can skip steps a-b if the cluster is already removed from coherency:

a. Clear the ACCHANNELEN bits, that is, bit 31 and bit 30, in the CCI-400 Snoop Control Register.

b. Poll the change_pending bit in the CCI-400 Status Register.When this bit reads as zero, the change is complete and no additional Snoop or DVM messages are sent.

4. Close snoop slave access control gate.



This sets the ACINACTM input to the cluster and enables STANDBYWFIL2 to be set.

5. Program the PPU policy to OFF. See Power states on page 3-145. Configure the PPU with the HWCACTIVEEN and HWCSYSREQEN bits set in its Power Configuration Register. See Power Configuration Register on page 3-146.The sequence is complete when either:• An interrupt is detected from the PPU.• The POWSTAT bit in the A57SSTOP PPU Power Status Register indicates the new

power state.

A.1.2 Cortex-A53 power domains, A53SSTOP, A53CPU[n]

The power domains in the Cortex-A53 cluster are handled in exactly the same manner as Cortex-A57 power domains, A57SSTOP, A57CPU[n] on page A-2 describes. You can follow the same procedures by substituting power domains in the Cortex-A57 cluster for the equivalent power domain in the Cortex-A53 cluster.

A.1.3 System power domain, SYSTOP

The SYSTOP region in the ADP has the property as the switchable domain that must be first on and last off. This is because no component, apart from the SCP, can perform useful work without this region being available.

The following tasks are required to manage a SYSTOP ON to OFF transition:

ADP power state pre-conditions • All power domains in the Cortex-A57 cluster are Off. This means that the

Cortex-A57 cluster must be in the SLEEP or OFF power state.• All power domains in the Cortex-A53 cluster are Off. This means that the

Cortex-A53 cluster must be in the SLEEP or OFF power state.• The GPUTOP power domain is Off. This means that the GPU must be in

the OFF power state.• The application processor wake-up latency requirements must also permit

the exit latency from the SYSTOP OFF state.

State save The SCP saves any system IP and DMC-400, including PHY, states not already saved.

DMC shutdown The DMC-400 is placed into the low-power state using the APB interface. This ensures that the memory devices are placed into self-refresh. This should also place the PHY into a low-power state using the DFI. Additional PHY shutdown support, prior to clock stopping and power down of the digital domain, is implementation-specific.

Stop PLLs If a PLL shares external logic that remains active, then it can remain running.

SCP remap The SCP enables its self-managed system access remap by setting the SCPSYSREMAPEN bit in the SCP Control Register. This is not mandatory, but prevents system deadlocks that might be difficult to debug.



Power down The SCP sets the POLICY field in the SYSTOP PPU Power Policy Register. Any remaining input clocks to the SYSTOP region, for example, REFCLK, CLK32K, and any running PLLs, are disabled outside the SYSTOP boundary as part of the power control sequence by signals derived from the PPU CLKEN output.

Perform the following tasks to manage a SYSTOP OFF to ON transition:

1. Pre-power up clock configurationBecause the clock configuration registers are in the SCP, their content has not been lost. Therefore, normally there is no specific requirement in this step unless it is required that the configuration after powerup is to be different to that before powerdown.

Note Clocks selected to be dependent on PLLs, unless located in another SoC power region and

already running, are not available until step 4.

2. Power upThe SCP sets the POLICY in the SYSTOP PPU Power Policy Register to ON. See Power states on page 3-145. At completion of the sequence, indicated by PPU interrupt, REFCLK, S32KCLK, and any already running PLL clocks are available.

3. SCP remapThe SCP self-managed remap is unset by clearing the SCPSYSREMAPEN bit in the SCP Control Register.

4. Start PLLsRe-start any required PLLs and wait for lock interrupts.

5. State restoreThe system IP and memory controller states are restored. The DMC-400 is not set to the active state in this step. You can do this in parallel with restarting the PLLs in step 4.

6. Start DMC-400Perform the DDR PHY start-up sequence and then set the DMC-400 to the active state.

A.1.4 Mali-T624 power domain, GPUTOP

Before you can power up the GPUTOP region, you must power up and configure the SYSTOP region. The VGPU must be available and you must enable GPUCLK by setting the GPUCLKEN bit in the SCP System Clock Enable Set Register on page 3-119. These conditions must remain until after GPUTOP is powered down again.

The CLKEN signal from the GPU PPU then handles the enabling of the clock to the domain. Until GPUTOP is powered up, the GPU job manager is inaccessible and no Mali-T624 power regions can be powered up.

The OS must perform both of the following before enabling the driver to attempt to gain access to the Mali-T624 job manager:• Send a message to the SCP to power GPUTOP.• Wait to receive acknowledgement that the resource is available.

When GPUTOP is powered up, the Mali-T624 driver software can manage the Mali-T624 power state transitions using the Mali-T624 job manager registers. GPUTOP can only be powered down if all Mali-T624 power regions are first powered down and the Mali-T624 driver releases the requirement for use of the Mali-T624 device to the OS.


Appendix B Subcomponent Configurations

This chapter describes the IP configurations for the subcomponents of the Juno ARM Development Platform (ADP). It contains the following sections:• Cortex-A57 processor cluster on page B-2.• Cortex-A53 processor cluster on page B-3.• SCP Cortex-M3 processor configuration on page B-4.• Mali-T624 GPU on page B-5.• CoreLink MMU-40x System Memory Management Unit components on page B-6.• CoreLink DMC-400 Dynamic Memory Controller on page B-7.• CoreLink Static Memory Controller (SMC), PL354 on page B-8.• USB host controller on page B-9.• I2S on page B-11.• I2C on page B-12.

ARM DDI 0515A-3b Copyright © 2014. All rights reserved. B-1ID050214 Confidential - Draft

Subcomponent Configurations

B.1 Cortex-A57 processor clusterTable B-1 shows the Cortex-A57 processor cluster configuration options.


Table B-1 Cortex-A57 cluster configuration options

Cortex-A57 cluster feature Value

Number of processor cores 2

Cryptography engine Included

L2 cache size 2MB

L2 logic idle gated clock Included

ECC and parity support ECC in L1 and L2

Vector Floating Point Unit (VFPU) Included



B.2 Cortex-A53 processor clusterTable B-2 shows the Cortex-A53 processor cluster configuration options.


Table B-2 Cortex-A53 cluster configuration options

Cortex-A53 cluster feature Value

Number of processor cores 4

Cryptography engine Included

Advanced SIMD and Floating-point Extension Included

L1 instruction cache size 32KB

L1 data cache size 32KB

L2 cache Included

L2 cache size 1MB



B.3 SCP Cortex-M3 processor configurationTable B-3 shows the Cortex-M3 SCP configuration options.

See the ARM® Cortex®-M3 Technical Reference Manual.

Table B-3 SCP Cortex-M3 processor configuration options

Configuration option Value

NUM_IRQ 105

LVL_WIDTH 3

MPU_PRESENT 1

BB_PRESENT 0

AHB_CONST_CTRL 0

DEBUG_LVL 3

TRACE_LVL 2

RESET_ALL_REGS 0

JTAG_PRESENT 1

CLKGATE_PRESENT 1

OBSERVATION 0

WIC_PRESENT 0

WIC_LINES N/A



B.4 Mali-T624 GPUTable B-4 shows the Mali-T624 GPU configuration options.

See the ARM® Mali™-T600 Series Implementation Guide.

Table B-4 Mali-T624 GPU configuration options

Mali-T624 feature Value

Number of shader cores 4 shader cores in one cluster.

L2 cache size 256KB.

L2 bus width 128.

Supported texture formats Programmable using the GPU Texture Format Register on page 3-65.



B.5 CoreLink MMU-40x System Memory Management Unit componentsThe ADP can contain the SMMUs that Figure 1-1 on page 1-4 shows.

Table B-5 shows the MMU-40x configuration options.

See CoreLink MMU-401 and MMU-400 System Memory Management (SMMU) components on page 2-61.

Table B-5 MMU-40x configuration options

Configuration optionsValue

GPU PCIe ETR DMA USB HDLCD0 HDLCD1

Component MMU-400 MMU-401 MMU-401 MMU-401 MMU-401 MMU-401 MMU-401

APB type APB4 APB4 APB4 APB4 APB4 APB4 APB4

AXI type ACE-Lite+ DVM

ACE-Lite + DVM

AXI3 AXI3 AXI3 AXI3 AXI3

AXI data width 128 bits 128 bits 64 bits 128 bits 128 bits 64 bits 64 bits

Number of contexts 1 4 1 4 1 1 1

Separate interface for PTW No No No No No No No

Security determination, SSD table entries

1 1 1 9 1 1 1

Stream matching registers 2 32 2 8 2 2 2

Stream ID 1 15 1 4 1 1 1

TLB depth 32 32 2 64 64 36 36

Write buffer depth 16 16 0 16 16 0 0



B.6 CoreLink DMC-400 Dynamic Memory ControllerTable B-6 shows the DMC-400 configuration options for DDR3L-1600.

Table B-6 DMC-400 configuration options for DDR3-1600

Configuration option Value Purpose

SYSTEM_INTERFACES 4 Number of system ACE4-Lite interfaces.

SYSTEM_ID_WIDTH 14 ACE interface ID signal width, for each system interface.

SYSTEM_ADDR_WIDTH 40 ACE address signal width, for each system interface.

SYSTEM_DATA_WIDTH 128 ACE data signal width, for each system interface.

SYSTEM_READ_ACCEPTANCE 64a Outstanding read acceptance capability, for each system interface.

SYSTEM_READ_HAZARD_DEPTH 16a Read hazard acceptance capability, for each system interface.

SYSTEM_READ_HAZARD_RAM 1 Read hazard buffer RAM implementation:0 Synthesizable RTL models.1 Custom RAM models.

MEMORY_INTERFACES 2 Number of memory interfaces or channels.

MEMORY_DATA_WIDTH 128 Memory interface width, width of the DFI data buses.

MEMORY_CHIP_SELECTS 2 Number of chip-selects on a memory interface.

WRITE_BUFFER_DEPTH 32a Depth of the write buffer, for each memory interface.

WRITE_BUFFER_RAM 1 Write buffer RAM implementation:0 Synthesizable RTL models.1 Custom RAM models.

READ_QUEUE_DEPTH 32 Depth of the read queue, for each memory interface.

MAX_BURST_LENGTH 8 Maximum memory burst length, in beats.

ECC 0 Single-Error-Correction, Double-Error-Detection, Error-Correcting-Code (SECDED ECC) support:0 Disabled.1 Enabled.

QVN 1 Virtual networks.

a. Buffer and queue depths are specified in terms of the number of memory bursts.



B.7 CoreLink Static Memory Controller (SMC), PL354Table B-7 shows the PL354 configuration options.

Table B-7 PL354 configuration


AXI width 64

MEMIF width 32

MEMIF CS 8

Exclusive monitors 4

CFIFO Depth 8

WFIFO Depth 16

RFIFO Depth 16

AID Width 14

Pipeline True

ECC False



B.8 USB host controllerTable B-8 shows the USB host controller configuration options.

Table B-8 USB host controller configuration options

Configuration option Value Description

EHCI descriptor, data prefetching Yes Descriptor, data prefetch logic is implemented in EHCI. RAM must be integrated external to the host controller for descriptor and data storage.

Number of OHCI controllers 1 -

Number of USB physical ports 1 -

EHCI controller includes port power control Yes Selects port power switches, and the PORTSC.PP bit represents the current switch setting, 0 off, 1 on.

EHCI packet buffer depth range - Not applicable because descriptor, data prefetching has been selected.

System reset is asynchronous No -

Support EHCI extended capabilities pointer range 0 No extended capabilities implemented.

Support EHCI asynchronous schedule park capability Yes -

Support EHCI programmable frame list flag Yes Software can specify and use a smaller frame list than 1024 elements.

Enable 64-bit addressing capability for EHCI Yes -

Support HSIC functionality No ULPI PHY used.

HSIC enable or disable control setting INSNREG08[15:0] register.Port power bit in the PORTSC register.

Not Applicable.

Support heterogeneous interface selection per port No ULPI PHY used.

Add the ULPI interface Yes -

Add 16-bit UTMI support to the ULPI interface No -

Add capability for the UTMI interface to bypass ULPI No The controller only has an ULPI interface and the UTMI interface is not exposed at the top level.

Use UTMI legacy interface No -

Add DDR support to the ULPI interface No ULPI is always used in 8-bit mode.

Support for dedicated AHB interface for EHCI and OHCI Yes Dedicated AHB interface for EHCI and OHCI is used.

Support Link Power Management (LPM) ECN for the EHCI core

No Disables LPM in the host controller.

Add enhanced AHB master INCRX support Yes, No Yes: Enhance AHB Master interface with INCR4, INCR8, and INCR16 burst support utilized.



OCHI configuration parameters

Support OHCI legacy No Does not support keyboard or mouse legacy emulation interface.

PowerOnToPowerGoodTime in 2ms units ‘h02 -

Device connected to each port is non-removable No Device on the port can be removed and connected again.

Implement power switching of ports Yes, No Yes. Port power switching is permitted for OHCI-owned ports.

Global or PerPort PowerSwitching GlobalPowerSwitchin

g is supported. A single power switch controls all OHCI-owned ports.

PortPowerControlMask value for each port 0. Port power control mask value is 0.

-

Table B-8 USB host controller configuration options (continued)

Configuration option Value Description



B.9 I2S

Table B-9 shows the I2S configuration options.

Table B-9 I2S configuration options


General configuration

APB data bus width 32

Receiver block enabled False

Number of receive channels NA

Transmitted block enabled True

Number of transmit channels 4

Is an I2S master True

FIFO depth for receive and transmit channels 16

Master Clk and slave Clk settings

Word select length 24

Serial clock gating No gating

Interrupt settings

Multiple interrupt output ports present False

Polarity of interrupt signals is active-HIGH True

CDC settings

CDC synchronization depth 2

Transmitter channels

Transmitter block DMA enabled True

TX0 maximum audio resolution 24

TX0 FIFO empty threshold trigger level 3









B.10 I2C

Table B-10 shows the I2C configuration options.

Table B-10 I2C configuration options

Configurable parameters Value

System configuration

APB data width 32

Device configuration

Highest speed I2C mode supported Fast

I2C default slave address 0x055

I2C default target slave address 0x055

High speed mode master code 0x1

Is an I2C master True

Disable slave after reset True

Supports 10-bit addressing in slave mode False

Supports 10-bit addressing in master mode False

Depth of transmit buffer is 16

Depth of receive buffer is 16

Transmit buffer threshold value is 0

Receive buffer threshold value is 0

Permit re-start conditions to be sent when acting as a master True

Hardware reset value for IC_SDA_SETUP register 0x64

Hardware reset value for IC_SDA_HOLD register 0x0001

IC_ACK_GENERAL_CALL set to acknowledge I2C general calls on reset True

External configuration

Include DMA handshaking interface signals False

Single interrupt output port present True

Polarity of interrupts is active-HIGH True

Internal configuration

Add encoded parameters True

Specify clock counts directly instead of supplying clock frequency True

Hard code the count values for each mode False

ic_clk has a period of, ns integers only NA

Relationship between pclk and ic_clk is Identical

Standard speed mode configuration based on 50MHz ic_clk SCL frequency generated is 99.21KHz



Std speed SCL high count 0x00e4

Std speed SCL low count 0x010c

Fast speed mode configuration based on 50MHz ic_clk. SCL frequency generated is 396.83KHz

Fast speed SCL high count 0x0022

Fast speed SCL low count 0x0054

High speed mode configuration

Loading in pF NA

High speed SCL high count NA

High speed SCL low count NA

Spike suppression

Maximum length, in ic_clk cycles, of suppressed spikes in SS and FS modes 0x1

Additional features

Permit dynamic updating of the TAR address False

Enable register to generate NACKs for data received by slave False

Hold transfer when Tx FIFO is empty False

Table B-10 I2C configuration options (continued)

Configurable parameters Value


ARM DDI 0515A-3b Copyright © 2014. All rights reserved. C-1ID050214 Confidential - Draft

Appendix C Revisions

This appendix describes the technical changes between released issues of this book.

Table C-1 Issue A

Change Location Affects

First release - -