JP Wang-IEEE Magn Summer School-2015

J. P. Wang, IEEE Magnetic Summer School, June 2015

Spintronics and Promising Applications

Jian-Ping Wang

University of Minnesota

IEEE Magnetic Society 2015 Summer School

June 16, 2015


Early Research on Magnetism

at University of Minnesota

Prof. William Brown started his pioneer research on Magnetic Particles and laid out the foundation of

Micromagnetics Theory at the Electrical and Computer Engineering Department, University of Minnesota.

Prof. Allan Morrish started his pioneer research on high frequency magnetic materials and wrote his

famous magnetic book at the Electrical and Computer Engineering Department, Unviersity of Minnesota.


John Van Vleck with his wife, Abigail,

Prof. Van Vleck was a professor at University of Minnesota.

Prof. Vleck, a Nobel Laureate, has been recognized as the father of modern magnetism.

Representative Lectures in Van Vleck Auditorium

• Albert Fert , Nobel Laureate, "Spintronics: electrons, spins, computers and telephones“ (2009)

• David Gross, Nobel Laureate, "Heterotic String Theory“ (2008)

Early Research on Magnetism

at University of Minnesota


Something Interesting about ECE/UMN & Minnesota

Discovery of Micromagnetic

Theory (Brown)

Early work on perpendicular

magnetic recording (Judy)

Invention of modern

sputtering technique (Werner)

First magnetic memory (IBM)

and GMR based memory

(Honeywell)

First supercomputer (Clay)

Invention of nano-imprinting

technique (Chou)

…

Early and Large Magnetic Industry (3M,

Control Data and Seagate)

Early and Fast Growing Spintronic

Industry (Seagate, NVE, Honeywell,…)

Large Medical Device Industry

(e.g. Medtronics, …)

Mayo Clinic

…



Jian-Ping Wang

University of Minnesota

IEEE Magnetic Society 2015 Summer School

June 16, 2015


Outline

Introduction

Why Spintronics (more on metallic spintronics and its hybrid)

Spintronics Basics (more on metallic spintronics and its hybrid)

Promising Applications and Challenges (selected)

Spin Memory

Spin Logic

Spin Biomedical Diagnostics

Summary and outlook

6


First Invention/Concept of Amplifier of Electric Currents

Lilienfeld's patents[edit]

US 1745175 "Method and apparatus for controlling electric current" first filed in

Canada on 1925-10-22, describing a device similar to a MESFET

US 1900018 "Device for controlling electric current" filed on 1928-03-28, a thin

film MOSFET

US 1877140 "Amplifier for electric currents" filed on 1928-12-08, solid state device

where the current flow is controlled by a porous metal layer, a solid state version

of the vacuum tube

US 2013564 "Electrolytic condenser" filed on 1931-08-29, Electrolytic capacitor

In patent applications to

Canada in 1925 and to the

United States in 1926,

Lilienfeld claimed that his

solid-state amplifier “relates to

a method of and apparatus for

controlling the flow of an

electrical current between two

terminals of an electrically

conducting solid by

establishing a third potential

between said terminals.”

http://worldwide.espacenet.com/textdoc?DB=EPODOC&IDX=US1745175

http://en.wikipedia.org/wiki/MESFET


http://en.wikipedia.org/wiki/MOSFET


http://en.wikipedia.org/wiki/Vacuum_tube


http://en.wikipedia.org/wiki/Electrolytic_capacitor


The First Point

Contact Transistor

First Demonstration of Transistor What Can We Learn?

• A mix of team members:

− Technical manager with strong theory background and vision/passion

− A top-notch theoretical physicist

− A versatile and highly skilled experimentalist

J. P. Wang, IEEE Magnetic Summer School, June 2015 9

•Building block (device): CMOS

•Interconnection: Memory + Logic

•Computing scheme: Boolean logic, Von-

Neumann architecture

CPU Architecture(Image: Intel Core i7) Off chip DRAM memory

(Image: Micron DDR3)

CPU with embedded DRAM memory (Image:

IBM PowerPC)

Challenges of Modern Computing


Challenges of CMOS

10


Why Are We Looking Beyond CMOS

Nikonov / Benchmarking / NVMTS '13

0

50

100

150

200

250

300

0.0 0.3 0.6 0.9

CM

OS

Cir

cuit

De

lay

(p

s)

Supply Voltage (V)

Computation Efficiency needs max. performance at lowest supply (Vdd)

• Switching Energy a CVdd2

• At Vdd ≤ Vth , performance suffers significantly

• Lowest Vth is limited by leakage

For ITRS LG=20nm At 1nW Standby Power


CMOS Device vs. Post-CMOS Devices

With further reducing device dimension, transistor based device will face

high leakage power issue.

Alternative technology (beyond CMOS) is required for future devices.

International Technology Roadmap for Semiconductors,

ITRS 2007, Executive summary

Figure Power consumption trend for CMOS


Spintronics

e- e-


In 1921, Otto Stern and Walter Gerlach performed an experiment which showed the

quantization of electron spin into two orientations. This made a major contribution to the

development of the quantum theory of the atom.

The actual experiment was carried out with a beam of silver atoms from a hot oven because

they could be readily detected using a photographic emulsion. The silver atoms allowed

Stern and Gerlach to study the magnetic properties of a single electron because these

atoms have a single outer electron which moves in the Coulomb potential caused by the 47

protons of the nucleus shielded by the 46 inner electrons. Since this electron has zero orbital

angular momentum (orbital quantum number l=0), one would expect there to be no

interaction with an external magnetic field.

Stern and Gerlach directed the beam of silver atoms into a region of nonuniform magnetic

field (see experiment sketch). A magnetic dipole moment will experience a force proportional

to the field gradient since the two "poles" will be subjected to different fields. Classically one

would expect all possible orientations of the dipoles so that a continuous smear would be

produced on the photographic plate, but they found that the field separated the beam into

two distinct parts, indicating just two possible orientations of the magnetic moment of the

electron.

What is Spin?


Stern-Gerlach Experiment

Stern-Gerlach Experiment



Read sensor

Spin logic Spin transistor e-

e-

MRAM

Quantum

computer

New Biomedical Devices

–Sensing/Energy transfer Spin processor Field

Programmable

Gate Array

(FPGA)


Types of Spin-Based Materials & Devices

e- e-

Metallic Spintronics Semiconductor Spintronics Oxide Spintronics

• Spin-transistor:

still a transistor

• Dilute magnetic

semiconductor:

Fundamental physics limit

Low spin density low

temperature

• MTJ/GMR limit:

no gain

• MTJ/GMR: need

voltage-current

conversion

• Current GMR:

low signal

• Potential limit:

speed

• Engineering limit:

processing temp

and integration with

CMOS

Non-volatility

(RT operation)

Multi-function Low power in theory

(spin current)

Multi-control

H, I, V

• To tackle the key issues for spintronic materials, devices and systems by fully taking advantages of different spintronic materials while being aware of their fundamental limits.

C-SPIN Kickoff Meeting


Memory

Logic

Processor on in

Traditional Architecture

Memory Logic and

New Architecture

• Adding new functionalities is the key for future logic and

memory devices spintronic materials and devices

hold this potential.

Path to Address Challenges of Modern Computing

C-SPIN Kickoff Meeting


Spin vs Magnet Spin

Magnet

Spin Injection

Spin

Channels

GMR Cu & MgO MTJ

e- e-

Charge current

Spin current

Graphene/MoS2 : 1 - 10s micrometer

Metal: 500 nanometer

Domain wall: 10s - 100s micrometer

Photonics channel: 10s millimeter

Interface

Layers of

MTJ/GMR

6/17/2015 C-SPIN Kickoff Meeting 19


Opportunities for Spintronics

• Collective behavior of spin-polarized electrons coupled through different

quantum mechanisms leads to unique advantages for spintronics:

Low operation energy (in theory);

Room and high temperature operation;

Non-volatile (zero leakage power);

Re-programmable; Reconfigurable;


Outline

Introduction




Spin Memory

Spin Logic


Summary and outlook

21


Giant Magnetoresistance (GMR)

Tunnel Magnetoresistance (TMR)

Spin Transfer Torque (STT)

3 Important Discoveries in Spintronics

Grünberg/Fert

*2007 Nobel

GMR (all metals)

Free FM

Reference FM

Cu

Free FM

Reference FM

AlO or MgO

TMR (tunnel junctions)

Lower RA Higher MR

Ideal: High MR with Low RA


Spin Torque: Enabler for Electrons to

Manipulate The Magnet

e-

Spin torque transfer driving device Traditional field driving device

I

H

J. C. Slonczewski, J. Magn. Magn. Mater. L1-L7, 159 (1996)

L. Berger, Phys. Rev. B. 54, 9353 (1996)

eff

0

diss HMMT M

Ga pMMT 0

STM

I

dissT dt

dMSTT MH eff


Two Terminal Spin Electronics

GMR, MTJ, etc


Giant Magnetoresistance

M. Baibich, J.M. Broto, A. Fert, V.D. Nguyen, F. Petroff, P. Etienne, G. Creuzet, A.

Friederich, J. Chazelas, Phys. Rev. Lett. 61, 2472–2475 (1988)


Tunneling Magnetoresistance

Electron tunneling across a ferromagnet/insulator/ferromagnet junction. In (a) the

orientation of the magnetizations is parallel and (b) antiparallel, showing in both cases the

electron density of the split d states. Dashed lines show spin conserved tunneling.

I. Zutic, J. Fabian, S.D. Sarma, Rev. Mod. Phys. 76, 323–410 (2004)


Spin-Dependent tunneling Conductance of

Fe|MgO|Fe Sandwiches

Zhang and Butler, Phys. Rev. B 63, 054416 (2001)

• Energy band for parallel state

Different bloch states at k//=0.

States with symmetry have the slowest decay rate. 1


Spin-Dependent tunneling Conductance of

Fe|MgO|Fe Sandwiches

Zhang and Butler, Phys. Rev. B 63, 054416 (2001)

• Energy Band for Anti-parallel State

electrons decay slowly through MgO, but cannot propagate on top Fe

layer since there is no minority propagating states at the Fermi energy. 1

1


MgO Barrier Magnetic Tunneling Junction

Highly-oriented

MgO (001) structure

Low roughness

Smooth interface

CoFeB > CoFe(002)

High spin polarization

+

+

Band match

Fe/MgO/Fe

> High MR ratio

Barrier (MgO (001))

Free Layer (CoFeB/..)

Fixed Layer (CoFeB/..)

Sputtering Growth:





Parkin, et al, Nature Mater. 2004;

Yuasa, et al, Nature Mater, 2004


Spin Hall Effect: Beyond Two-Terminal Device

M. I. Dyakonov and V. I. Perel,; Perel' (1971). "Possibility of orientating electron spins with current". Sov. Phys.

JETP Lett. 13: 467.

J.E. Hirsch (1999). "Spin Hall Effect" (subscription required). Phys. Rev. Lett. 83 (9) 1834.

Y. Kato; R. C. Myers; A. C. Gossard; D. D. Awschalom (11 November 2004). "Observation of the Spin Hall Effect

in Semiconductors". Science 306 (5703)1910

Luqiao Liu, Chi-Feng Pai, Y. Li, H. W. Tseng, D. C. Ralph, R. A. Buhrman (2012) , Spin-Torque Switching with the

Giant Spin Hall Effect of Tantalum, Science 336 (6081) 555


Liu et al., Science 336 , 55 (2012)

Magnetization Switching by Spin Hall Effect

Spin Hall Effect (SHE)

• Magnetization switching by pure spin

current.

• No charge current runs through the MTJ

stack during writing process.

• No heat generated in MTJ

e.g. Pt, Ta, W


field-like

torque

Oersted

torque anti-damping

torque

Spin-orbit Torques

ˆ ˆˆ ˆ ˆ ˆ ˆ ˆ ˆ ˆ ˆ( )eff AD FL Oe

d d

dt dt a

m mm H m m y m m y m y

ADprecession

term damping

torque

Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation:

FL Oe

Spin-orbit torques


Strain and Electric-Field Assisted Switching

We do need the spin torque no matter what. Strain and electric field can’t

switch the magnet but can assist the switching or lower down the energy.


Metallic Spintronics

Demonstration of Room Temperature

Magnetic Tunnel Junction (MTJ)

Discovery of Giant Magnetoresistance (GMR)

Correlation between magnetic and electric performance

– anisotropic magnetoresistance (AMR)

Discovery of Magnetic Tunnel Junction (MTJ)

Theory of Spin Transfer Torque

Demonstration of Spin Transfer Torque Switching

Theory of Magnetoelectric Effect

Demonstration of Magnetoelectric Effect

Demonstration of Giant Spin Hall Effect

Proposal of MTJ/GMR Logic

Demonstration of MTJ/GMR Logic

Demonstration of Lateral Spin Valve Switching

2010 1990 1970 1900


World Wide Spintronics Research Survey

1996

1998

2000

2002

2004

2006

2008

2010

2012

0 1000 2000 3000 4000

Publication

Ye

ar

Spintronic

1995 1998 2001 2004 2007 20100

200

400

600

800

1000

Public

ation

Year

USA

Japan

Europe

China

Korea

*Europe: Germany, France, UK, and Italy

• Spintronic-related publication analysis (Source: Web of

Science):


A Large Tool Box for Spintronics • A variety of building blocks (not existing before) from spintronics lead to

many new devices and systems concepts and eventually new applications:

nanomagnet Skyrmion

Si ·Sj Si x Sj

Hybrid spin structure 2:

domain wall vs magnetic layer

Hybrid spin structure 1:

metal layer vs. magnetic layer

Memory cell, Logic gate,

Spin injector, RF source

Electron spin

Photon spin

angular

momentum

Spin-optical coupling ME controlled exchange bias ME controlled strain


Opportunities for Spintronics • Low density STT-RAM is in production

• New and specific applications of spintronics are approaching

• Efficiency of prior switching mechanisms and related materials should be

improved greatly before approaching the 40 – 60 kBT target for drop-in

replacement

/ ME EB

Drop-in

replacement

New/Specific

applications

First

application

(STT-RAM)


• Prior existing materials are insufficient for spintronics

• Different combination of those demanding new materials’ functions could

enable and lead to new applications

Beyond “Multifunctional”: Opportunities for Spintronic

Materials and Applications

Demand new heterostructured material systems

Demand new multi-functional materials

• Large perpendicular anisotropy

• 100% spin polarization ratio

• Low damping constant

• Crystalline structure and lattice match

• Bulk/Interfacial magnetism control

• TI; VCM; ME exchange bias; ME

strain


Outline

Introduction




Spin Memory

Spin Logic


Summary and outlook

41


Spin Based Memory and Computing System


MTJ Memory Cell Requirements for STT-RAM application

Readability

(Signal to Noise Ratio, Read Error)

Writability

(Write Voltage,

current and time,

Write Error)

Thermal Stability

(Stand by data

Retention

Thermal Stability

under current)

R, Δ

Hk Other Requirement

• Impedance matching with CMOS circuit

• Sample to sample variation

• Endurance under voltage pressure

• STT switching distribution

e- STT-RAM memory bit


Memory Technology Comparison

Source: Grandis Corporation, 2008


Scaling Analysis Strategy and Simulation Scenario

for STT-RAM

with Jongyeon Kim, Yanfeng Jiang and Chris Kim, DRC 2014


Scaling Challenges and Opportunities for STT-RAM

with Jongyeon Kim, Yanfeng Jiang and Chris Kim, DRC 2014


Field Switching and DC Current Switching

-200 -100 0 100

0.9

1.2

1.5

1.8

2.1

Re

sis

tan

ce

(k

)

H (Oe)

RA=4.3 m2

MR=135%

Hc=48 Oe

-0.4 -0.2 0.0 0.2 0.4

0.9

1.2

1.5

1.8

2.1

-138 A

Re

sis

tance

(k

)

Current (mA)

102 A

Field switching!

DC current

switching!

Seed layer

Capping layer

PtMn 15nm

Co70Fe30 2.5 nm

Ru 0.85 nm

Co40Fe40B20 2.4 nm

MgO 0.85 nm

Co60Fe20B20 1.8 nm

130nm*50 nm

Hui Zhao, et al, J. Appl. Phys. 2011


MTJ with Interface Perpendicular Anisotropy

Seed layer

Capping layer

PtMn 15nm

Co70Fe30 2.5 nm

Ru 0.85 nm

Co40Fe40B20 2.4 nm

MgO 0.85 nm

Co60Fe20B201.8 nm

Seed layer

Capping layer

PtMn 15nm

Co70Fe30 2.5 nm

Ru 0.85 nm

Co40Fe40B20 2.4 nm

MgO 0.85 nm

Co20Fe60B20 1.8 nm

Size: 50nm*130nm

With small perpendicular anisotropy

Co rich free layer

With large perpendicular anisotropy

Fe rich free layer

Size: 50nm*130nm

0 2 2c s kk dJ e M t H H Ha Theory: a is the free layer damping factor, Ms is the saturation magnetization,

Hd is the demagnetization field, Hk is the free layer perpendicular interface anisotropy field corresponding to 2Ki/Mst

48

Reduces switching current by almost a factor of 2x Nz Ms =4πMs


Sub 200ps Ultrafast Switching in MTJ

49

Successfully demonstrated sub 200ps switching using in-plane MTJ sample with interface

perpendicular anisotropy. Writing energy as low as 0.12 pJ (AP-P) and 0.23 pJ (P-AP).

Free layer: Co20Fe60B20 2.0 nm

Size: 50nm*150nm

Thermal Stability: 60

Hui Zhao et al, J. Phys. D., 45,025001 (2012).


3 4 5 6 7 8 9 100.0

0.5

1.0

1.5

2.0

2.5

3.0 25 C

50 C

70 C

10 ns

10 s

Sw

itchin

g P

robabili

ty D

ensity

J (MA/cm2)

x 10-6

100 ms

Temperature Dependence of

Switching Probability Distribution

50 nm×170 nm

In this particular temperature range, the switching current density variation was found be

less sensitive to the environmental temperature compared to the switching time. Hui Zhao, et al, IEEE Magn. Lett. 3, 3000304, (2012)


Read Disturb Rate and Write Error Rate

Hui Zhao et al, IEEE Trans. Magn., (2012).


Switching Probability Density Function Asymmetry

0 0 0

0 0

( )exp 1

exp , exp 1

p

c c

p U

Bc

tVp

V V V

t K V

k TV V

2

2

2

1 1, , 1

22 2

xx

x xf x

xwhere x e x x dt erf

a

Thermal activated switching model Skew normal distribution

Hui Zhao et al, IEEE Trans. Magn., (2012).


Perpendicular STT-MRAM

Why perpendicular anisotropy?

• 1st reason Kin-plane ~ 106 erg/cm3

Kperpendicular ~ 107 erg/cm3

• 2nd reason

0

2 ( 4 )s k sc

e M V H H MI

a

0

2 ( 2 )s k s

c

e M V H H MI

a

In-plane

Perpendicular


Perpendicular Spin Transfer Torque Demonstration

Electrode

Free

Cu

Fixed

Electrode

e-

Free layer: [CoFe2.5Å/Pt15Å]5 /CoFe5 Å

Space layer: Cu 30 Å

Fixed layer: [CoFe4.5 Å /Pt23 Å]7

100 nm in diameter

H. Meng and J. P. Wang, Appl. Phys. Lett., 88 (2006) 172506;


MTJ with Interface Perpendicular anisotropy

Perpendicular MgO MTJ fabricated by ultrathin CoFeB layer

(<1.4 nm) as a result of perpendicular interface anisotropy in

CoFeB/MgO interface.

S. Ikeda et al Nature Mater. 9, 721 (2010)

TMR 120%, Jc0 = 3.9 x 106 A/cm2


Fe16N2

< 1.5 nm CoFeB, Interface anisotropy

How to support sub-10 nm MTJ thermally stable while

keeping high MR and low damping constant?

GMR Cu & MgO MTJ



• To search for materials that satisfy: high PMA, high spin polarization, low damping constant and good match with tunnel barriers, graphene and other spin channels



Multi-bit STT-MRAM Concept

Four Resistance states

[1] T. Ishigaki, T. Kawahara, R. Takemura, et al., VLSI Technology Symposium, pp. 47-48, 2010 [2] Y. Zhang X. Yao and J. P. Wang, INTERMAG, GD-04, Spain, May, 2008

Four Resistance states

Fixed Layer

Free Layer 1

Fixed Layer

Free Layer 2

Free Layer 2

Free Layer 1

Fixed Layer

Multi-MTJ Multi-free layer

58


Y. Zhang and J. P. Wang, Intermag 2008.

T. Ishigaki et al., Hitachi & Tohoku Univ. @ Symp. on VLSI Technology 2010

• Series Stacked MTJs

– The same film configuration provides the same JC.

– Area ratio of 2 of the two MTJs makes the IC and ΔR ratios 2 and ½.

It is difficulty to use interface anisotropy to achieve this!

Multi-bit STT-MRAM Concept


Perpendicular Multi-bit MTJ Stacks

Perpendicular multi-bit MTJ stacks with: • [Co/Pd]n multilayer as the bottom electrode and the top electrode • MgO/CoFeB/Ta/CoFeB/MgO as the middle free layer

• In film stack, magnetizations of all the three layers are perpendicular. • Coercivity of the three magnetic layers are well separated.

Seed layer Ta/Pd

Bottom fixed layer

[Co/Pd]n/CFB

MgO barrier 1

Middle free layer

CoFeB/Ta/CoFeB

MgO barrier 2

Top free layer

CFB/[Co/Pd]n

Capping layer

X. Li, J. Chen, H. Li and J. P. Wang, unpublished


2. E-beam or photo-

lithography to define

the nanopillar.

1. Bottom electrode

definition.

Bottom electrode

5. Via open (RIE)

Bottom electrode

6. Deposit electrodes

Current flow

MTJ MTJ SiO2 SiO2

3. SiO2 deposition (PECVD).

4. Lift off

wafer wafer

SiO2 MTJ

Bottom electrode

wafer

140nm×100nm

E-beam pillar

wafer

Bottom electrode

MTJ stack

EB resist

Bottom electrode

MTJ

wafer wafer

Bottom electrode

MTJ

EB resist

SiO2

Nanoscale Multi-Bit MTJ Fabrication


Outline

Introduction




Spin Memory

Spin Logic


Summary and outlook

62


Datta-Das Spin Transistor

Datta-Das spin transistor (1990), a device concept that has triggered the early work

on magnetic semiconductor. Non-volatility was there for the first time.

“Idealized” interfaces are not available;

Physics simply not supporting large gain; Nonlinear behavior for spin

processing is different from nonlinear behavior of electron transport;


Adding New Functionalities is the Key for Designing and Building New Spin Logic Devices

Memory

Logic

Processor on in

Traditional Architecture

Memory Logic and

New Architecture (with Non-volatile components)

J.P Wang and X. F. Yao, “Programmable Spintronic Logic Devices for Reconfigurable Computation and

Beyond- History and outlook”, JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS 3, 12 (2008)


Spin (Low Voltage) vs Magnet (Non-Volatile) Spin Magnet

Spin Injection

Spin

Channels

GMR Cu & MgO MTJ

e- e-

Charge current

Spin current

Graphene/MoS2 : 1 - 10s micrometer

Metal: 500 nanometer

Domain wall: 10s - 100s micrometer

Photonics channel: 10s millimeter

Interface

Layers of MTJ/GMR

Collective behavior of

coupled spins

(60 kBT vs 1000 kBT)

www.cspin.umn.edu; C-SPIN: STARnet center

http://www.cspin.umn.edu/


“Communication Between Magnetic Tunnel Junctions

Using Spin-Polarized Current for Logic Applications”, A.

Lyle, et al, IEEE TRANSACTIONS ON MAGNETICS, 46:

2216 (2010),

X. Yao, et al, “Magnetic Tunnel Junction-Based Spintronic

Logic Units Operated by Spin Transfer Torque“, IEEE Trans.

Nanotechnology (2012);

H. Meng, et al “A Spintronics Full Adder for Magnetic CPU”,

IEEE Electron Dev. Lett., 26 (2005) 360;


MTJ

Input C

Input

B

Input

A I(-)

I(+)

IC

Outp

ut

A. Imre, et al.

Magnetic Cellular Automata Domain wall logic MTJ/GMR logic

D.A. Allwood, et al., H. Meng, et al

Spintronic Logic Building Blocks


Comparison of Spintronic Logic Devices

CMOS

logic MQCA

Domain wall

logic MTJ/GMR logic

Element Transistor Magnetic

dot/pillar Magnetic wire MTJ/GMR

Binary states Voltage Magnetization

direction

Domain wall

(head to head;

tail to tail)

Resistance

(high, low)

Driving force Voltage Magn. field Rotating magn.

field

Magn.

Field

Pulse

current

Programmable

Reconfigurable Yes No No Yes Yes

Speed <ns <ns ns under large field < ns < ns

Density medium low low low high

Reliability high low high high high

power high high high high low


H. Meng, J.G. Wang and J-P Wang, “A Spintronics Full Adder for Magnetic CPU”, IEEE Electron Dev. Lett., 26 (2005) 360

Spintronic Full Adder for Magnetic Processor

Circuit design for magnetic Full Adder based on SEVEN MTJs.

Circuit inside the dash line: the sum output (S) logic functions.

A B C 0

A B C 0

I sens

I sens

I sens

I sens

Sense

Amp

Sense

Amp

R ref 0

R ref 1 R ref 2 R ref 3

R 1 R 2 R 3

V+

V-

V+

V-

+

C1

-

-

+

S

A B C 0

C 0 C 0 C 0 A B C 0

I sens I sens

I sens I sens

I sens


H. Meng, J.G. Wang and J-P Wang, “A Spintronics

Full Adder for Magnetic CPU”, IEEE Electron Dev.

Lett., 26 (2005) 360

Spintronic Full Adder for Magnetic Processor

Circuit design for magnetic Full Adder.

Circuit inside the dash line: the sum

output (S) logic functions.

Seven MTJs only

-150-100 -50 0 50 100 150

6.2

6.4

6.6

6.8

7.0

7.2

7.4

(c)

C:1

A:1

B:1

C:1

A:0

B:0

pinned layer pinned layer

Line A: 0.9Oe/mA

R(

)I (mA)


Output Element Dimensions: ~238 nm x 357 nm (Aspect ratio 1.4)

Input Element Dimensions: ~190 nm x 380 nm (Aspect ratio 2)

~162 nm x 405 nm (Aspect ratio 2.5)

~142 nm x 426 nm (Aspect ratio 3)

Note: Same area for all MTJs

Si/SiO2/Ta 3/CuN 40/Ta 3/CuN 40/Ta 3/Ru 10/Ta 5/PtMn 20/CoFe30 2.4/Ru 0.85/Co60Fe20B20 2.4/MgO

1.05/Co60Fe20B20 1.6/Ta 5/Cu 10/Ru 7/Ta 10/Au 100 (nm)

Annealed at 300°C for 1 hr with field applied to set fixed layer direction

A. Lyle, J. Harms, S. Patil, X. Yao, D. Lilja, and J. P. Wang, “Direct Communication Between Magnetic Tunnel

Junctions for Non-Volatile Logic Fan-Out Architecture,” Appl. Phys. Lett., 97, 152504 (2010).

Voltage Controlled MTJ Logic


-200 -150 -100 -50 0 50 100 150 200

220

240

260

280

300

320

340

360

Re

sis

tan

ce

(O

hm

s)

Applied Field (Oe)

Input

-1.9 -1.8 -1.7 -1.6 -1.5 -1.4 -1.3 -1.2

1250

1300

1350

1400

1450

1500

1550

1600

1650

Resis

tan

ce (

Oh

ms)

Applied Voltage (Volts)

111

011

001111

011

001

Voltage Controlled MTJ Logic


Learning from Nanomagnet Logic

73

• First demonstration of MTJ based MQCA arrays • A. Lyle, et al., Appl. Phys. Lett., 98, 092502 (2011).

Device Type CMOS

(60nm)

MQCA

Switching energy (aJ) 216 10.1

Clock Frequency

(GHz)

4 2

Non-volatile No Yes

Throughput

(Mops/cm2/ns)

269 556

Top Contacts

Transmission

line

Coupled MTJ

Nanomagnets

• First proposal and demonstration of MQCA and logic operations • R. P. Cowburn and M. E. Welland, Science, vol. 287, pp. 1466-1468, 2000.

• A. Imre, et al., Science, vol. 311, pp. 205-208, 2006.

http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2

009_ERD.pdf


Experimental Details

• 50 nm x 80 nm and 70 nm x 100 nm MTJ pillars • Si / SiO2 (100 nm) / bottom lead / PtMn (20 nm) / Co70Fe30 (2.4 nm) / Ru (0.85

nm) / Co40Fe40B20 (2.4 nm) / MgO (0.9 nm) / Co60Fe20B20 (1.8 nm) / top lead

100 nm

7.5 kV WD 2.8 mm 80,000 X

Hx, Clock

100 nm

Hy, Set, Bias 100 nm

70 nm

10 nm

• Edge to edge spacing: 0 to 30 nm

• One dimensional arrays with 2 to 20 pillars that are AF coupled


STT Programming: No Clocking Field

75

-100 -75 -50 -25 0 25 50 75 100

1300

1400

1500

1600

1700

1800

Re

sis

tan

ce (

Oh

ms)

HY (Oe)

Field Switching

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5

1300

1400

1500

1600

1700

1800

Re

sis

tan

ce (

Oh

ms)

Current (mA)

STT w/o Clock

• STT programming without clocking field analogous to STT-RAM

writing

• Demonstrates one of the worst case scenarios for programming

since no clocking field is lowering energy barrier

Hy X

I+

Iinput

1 2 3 Time

X

Hy X

I+ X


5 10 15 20 25 300

200

400

600

800

1000

Nanomagnet Spacing

Cu

rren

t (

Spacing (nm)

Effect of Nanomagnet Configurations

76

0 2 4 6 8 10 12 14 16 18 20

200

300

400

500

600

# Elements in array

Cu

rren

t (

# Elements in Array

100 nm

100 nm

Spacing

# Elements

50 nm x 80 nm pillar with 10-15 nm spacing

50 nm x 80 nm pillar


All Spin Logic Based on Lateral Spin Valve

CuFePtInput

magnetOutputmagnet

GND

Isolation

Contact

Channel

VSSIDC

IS

S. Datta, Nature nanotech 2010, Y. Otani, Nature physics 2008

Vsupply

Icharge, Ispin

Output magnet

spin direction

Input magnet

spin direction

Icharge

Ispin

Vsupply

77


Spin Device Wish List (ASL Example)

78

Nanomagnet: High thermal stability

(must be stronger than thermal noise),

low switching energy, high polarization

Icharge Icharge

Ispin

Spin channel:

Minimal signal

attenuation

Interface:

High spin injection

efficiency (=Ispin/Icharge)

Icharge driver circuit (not shown):

Low power consumption, small

voltage drop

Isolation:

Good separation

between devices

Ground terminal:

Good

directionality

C. Kim, et al, Proceedings of IEEE, 2015


ASL Energy Calculation

79

Major energy dissipation is the charge current for generating the spin current

Target device: Py+Cu ASL (i.e. Py magnet and Cu channel)

Vsupply

(CLK)

Ic, Is

tsw

System specification

m: Device count

t: Retention time

System frequency

Thermal stability

Chip failure rate

Energy barrier height

Operating temperature

Magnet material

Ms: Magnetization

α: Damping factor

P: Polarization factor

Switching energy

E=Vsupply·Q total

=Vsupply·Ic,critical·tsw

=Vsupply·Is,critical·(Ic/Is)·tsw

Magnet design

Magnetic anisotropy

Magnet dimension

Is,critical by solving LLG

Channel design

Device dimensions

Spin injection ratio (Is/Ic)

Supply voltage

Channel material

λ: Spin diffusion length

ρ: Resistivity

Impedance matching

Vsupply

IcIs

Is,critical

[1] Y. Otani, Nature physics 2008

[1]



Test Vehicle and Thermal Stability

Channel length

Transistor count

Die size

Power

Parameter

Architecture

Characteristic

Power supply

Cache

# of cores

32nm

1 billion

216mm2

95W @ 3.4GHz

Sandy Bridge

0.7 ~ 1.15V

64KB L1 cache per core

256KB L2 cache per core

8MB L3 shared cache

4 cores

Intel Core i7 2600K processor as the

test vehicle for our system level studies

Device count for ASL system was

estimated as 0.27 billion (logic only, half

the device count of CMOS)

1. Comparison target

2. Thermal stability requirements

Eb = 69kBT at 0.01% failure rate (1FIT)

1 FIT =1 failure in 109 device-hours of operation

m(capacity): 0.27billion, t(retention time): 10yrs,

t0(attempt period): 10ns

)/exp(1

0 TkEf Bb

Relaxation time:

Thermal switching probability:

Chip failure rate:

Failure criteria:

)/exp(1)( ttP

)exp(exp10 Tk

EtmF

B

bchip

[1] S. Zhang, PRB 2004

[2] R. Takemura, JSSC 2010

[1]

[2]

FIThrhryear

110

110

2436510

0001.0

10

%01.09

9

1E-08

1E-06

1E-04

1E-02

1E+00

1E+02

55 60 65 70 75 80 8555 60 65 80

102

100

10-2

10-4

10-6

10-8

1FIT 69kBT

Thermal stability Eb/kBT

Ch

ip f

ailu

re r

ate

(%

)

70 75 85


0

10

20

30

40

50

60

70

1 2 3 4 5 6

C0

sta

te p

ow

er

(W)

Interconnect power

Core logic power

30

50

70

20

0

60

40

10

0

5

10

15

20

1 2 3 4 5 6

C1

sta

te p

ow

er

(W)

10

15

20

5

032nm

CMOS

ASL,

λ: 2μm

Py+Cu

ASL

ASL,

λ: 2μm,

Hybrid

intercon.

ASL,

λ: 2μm,

Hybrid

intercon.,

P: 0.8

ASL,

λ: 2μm,

Hybrid

intercon.,

P: 0.8,

1μs retention

Interconnect power

Core logic power

4 cores active

1 core active, 3 cores idle

Active Power Comparison:

ASL vs. CMOS (Intel Core i7, 25MHz)



Spin Hall Effect: Beyond Two-Terminal Device

M. I. Dyakonov and V. I. Perel,; Perel' (1971). "Possibility of orientating electron spins with current". Sov. Phys.

JETP Lett. 13: 467.

J.E. Hirsch (1999). "Spin Hall Effect" (subscription required). Phys. Rev. Lett. 83 (9) 1834.

Y. Kato; R. C. Myers; A. C. Gossard; D. D. Awschalom (11 November 2004). "Observation of the Spin Hall Effect

in Semiconductors". Science 306 (5703)1910

Luqiao Liu, Chi-Feng Pai, Y. Li, H. W. Tseng, D. C. Ralph, R. A. Buhrman (2012) , Spin-Torque Switching with the

Giant Spin Hall Effect of Tantalum, Science 336 (6081) 555



• Prior spintronic materials and devices are insufficient:

State-of-art for Spintronic Materials and Devices

S. Manipatruni, et al,, arXiv preprint arXiv:1301.5374

(2013).

Energy-delay trajectory for GSHE switching with PMA nanomagnet

switching

Energy-

Delay

Power

Nikonov and Young, NCN summer school, 2014

2nd phase spin logic benchmarking (through NRI centers) Perpendicular magnetic materials; thermal stability vs damping constant

Scaling

Gated magnetization switching (VCMA, Exchange Bias, Strain, etc)

Example: Strain induced/assisted magnetization switching

Gated

Energy

0 5 10 15 20 25 30

0

200

400

600

800

1000

1200

Northeasten U, NiCo/PZN-PT

NiFe(10nm)/BaTiO3

Lanzhou U, CoFeB/PMN-PT

Tsinghua U, CoFeB/PMN-PT

Northeasten U, CoFeB/PZN-PT

Nanjing U, FePd/PMN-PT

UCLA

Walther-Meibner-Institut, Ni/PZT

Str

ain

-in

du

ced

eff

ective

fie

ld (

Oe

)

E (kV/cm)

Gated

Energy


Outline

Introduction




Spin Memory

Spin Logic


Summary and outlook

85


Economic Burden on Health Care

SOURCES: Centers For Medicare and Medicaid Services,

Office of Management and Budget, Kaiser Family

Foundation, Alliance for Health Reform, Organization for

Economic Co-operation and Development, Senate Finance

Committee, Commonwealth Fund


Demand for New Biosensing Technology

-Poor sensitivity

-High background noise: optical or electrical/chemical background

-Limited Multiplex

-High cost per test

-Low speed

Existing Technologies Not Ready For this Challenge


GMR + Magnetic Particles Based Sensing Scheme

A) GMR sensor + capture antibodies,

biomarkers above

B) GMR sensor after specific reaction

with biomarkers

C) GMR sensor during specific

reaction with detection antibodies +

magnetic nanoparticles (MNPs)

B Other

proteins do

not react

with capture

antibodies

C

MNPs will

change the

GMR signal

after binding

A

GMR Free layer

GMR Fixed Layer


Breakthrough

First publication on GMR biosensing by Naval Research Lab in 1998

• GMR sensors + Micro beads + Microfluidic channel

• No quantification

Many labs around world were unable to commercialize Naval Lab’s invention

High magnetic moment particles enabled efficient Brownian motion and low limit of detection

Unique Features for

magnetic biosensing:

1.Ultra high sensitivity

2.Ultra low background noise

(matrix-in-sensitive)

3.Multiplex (10 ~ 1000)


Magnetic Tag Based Sensing Scheme

Unique Features:

1.Ultra high sensitivity

(ultra low background noise)

2.Matrix in-sensitive

3.Fast (<10 minutes)

4.Low cost (<$1.0)

5.Multiplex (10 ~ 100)

6.Low volume detection (4µL – 100 µL)

C

High resistance

No external

magnetic field

Low resistance

an external

magnetic field

C

A BPost-CMOS Technology:

Electronics > Spintronics

Nobel Prize in physics in 2007

Profs. Fert and Grunberg

Capture

antibody

Antigen (Target Molecule)

Detection antibody

+ biotin

MNP + Streptavidin

APTES-coated Sensor


Magnetic Tag Based Sensing Scheme


Biological testing

Integration and Computer

Control

Electrical and

Electronic system

Magnetic Field Generator and

Control

Mechanical system

Nanoparticles Functionalization

Antibody &

Antigen

Local Printing

Validation of antibody and

antigen working condition

Assay schemes

(calibration and optimization)

GMR sensor functionalization

Prototyped Handheld GMR Molecule Diagnostic System

Nanoparticles Fabrication Chemicals Local

Printing System (0.1 nanoliter)

GMR Sensor Wafer Fabrication

GMR Chip Fabrication (patterning & reaction well)


Unprocessed Human Serum Quantification

NS1-5: Normal human serum sample 1-5; CS1-5: Cancer patient serum sample 1-5

[IL-6] fM NS1 NS2 NS3 NS4 NS5 CS1 CS2 CS3 CS4 CS5

ELISA 219 N/A[a] N/A[a] N/A[a] N/A[a] 192140[b] 552 742 3928 757

GMR 248 122 56 203 112 195981 567 597 3681 627

[a] N/A – Not detectable by ELISA; [b] After 80-fold dilution

Li, Y.; Srinivasan, B.; Jing, Y.; Yao, X.; Hugger, M. A.; Xing, C.; Wang, J.-P. J. Am. Chem. Soc., 2010, 132 (12), 4388–4392


Z-Lab 1.0 Z-Lab 2.0

Specifications:

Power: 3.2W

Bluetooth

29 – 225 sensors per chip

4 uL sample size minimum

Specifications: Power: 0.02W

Bluetooth

29 – 225 sensors per chip

4 uL sample size minimum

www.magneticbiosensing.umn.edu

Share the Nokia

Sensing X-

Challenging

Distinguished

Winner Award with

StanfordTeam

(Shan Wang) and

other three teams


To Enable Remote Healthcare System

- Personalized Medicine

Device/System/Network

Develop a disposable biochip that costs less than $1 and could test more than 100

diseases within 10 minutes.


Next “Hard Disk Drive” Type

Technology in Life Science Biology

+ Magnetism

Hard Disk Drive Magnetic Biosensing

The world 2nd most difficult and

complicated engineering product;

Only three players in the world;

Minnesota is one of the places to start

this industry;

Difficult and complicated engineering

product ;

Minnesota is one of the places to start

this industry;

One of three pillars for information technologies: Processor; Display; Hard Disk Drive

Potentially one of the key technologies for disease early detection

The landscape changer for human life:

social- life internet enabler (Google,

Facebook, etc)

The landscape changer for life science

and disease early detection


Magnetic Sensors Technology Comparison


Outline

Introduction




Spin Memory

Spin Logic


Summary and outlook

98


Opportunities for Spintronics • Low density STT-RAM is in production

• New and specific applications of spintronics are approaching

• Efficiency of prior switching mechanisms and related materials should be

improved greatly before approaching the 40 – 60 kBT target for drop-in

replacement

/ ME EB

Drop-in

replacement

New/Specific

applications

First

application

(STT-RAM)


• Prior existing materials are insufficient for spintronics

• Different combination of those demanding new materials’ functions could

enable and lead to new applications

Beyond “Multifunctional”: Opportunities for

Spintronic Materials and Applications

Demand new heterostructured material systems

Demand new multi-functional materials

• Large perpendicular anisotropy

• 100% spin polarization ratio

• Low damping constant

• Crystalline structure and lattice match

• Bulk/Interfacial magnetism control

• TI; VCM; ME exchange bias; ME

strain


C-SPIN

www.cspin.umn.edu


Overview of C-SPIN

• The vision of C-SPIN is to bring together multi-disciplinary leaders in the

areas of spintronic materials, devices, circuits and architectures to create

the fundamental building blocks that allow novel spin-based multi-

functional, scalable memory and computational architectures to be

realized.


C-SPIN

www.cspin.umn.edu


C-SPIN PIs

CSPIN students & postdoc

Students: 121

Postdoc: 21


Coordinated Effort to Go Beyond CMOS

We are excited to announce the upcoming workshop, “Heusler Alloys for Spintronic

Devices” to be held at the University of Minnesota in Minneapolis, Minnesota, July 30 – 31,

2015. The workshop will be organized by The Center for Spintronic Materials, Interfaces,

and Novel Architectures (C-SPIN).

Materials with 100% spin polarization and high perpendicular magneto crystalline anisotropy

have been the ideal for next generation spintronic memory and logic devices. Heusler alloys

are a candidate for such materials and have been extensively studied over the past decade.

There have been some promising results, but many roadblocks remain. This workshop will

candidly discuss these promises and challenges by bringing together leading experts

working in this field. To this end we expect to have around 10-15 talks over 1.5 days along

with time dedicated to discussions.

C-SPIN

PIs

C-SPIN

Students

SAB feedback and industry associates Leverage with domestic and

international collaboration





Through human history, technology has

driven the advance of civilization

Recent Examples:

Car, Airplane, Space shuttle;

Computer; Internet

Processor; Hard disk drive;

Recent Nobel Prizes in Physics:

Integrated Circuits (IC)

CCD/Optical Fiber

I believe you will see more

-National Academy of Engineering

Grant Challenges White Paper


Minneapolis – St. Paul Twin City

Documents

JP Wang-IEEE Magn Summer School-2015