January 14, 2008

IEEE P1800: SystemVerilog

• Verilog currently consists of two ratified standards– IEEE 1800-2005: SystemVerilog– IEEE 1364-2005: Verilog

• Both have had significant implementation in commercial simulators and are in active use by hardware design teams.– ASICs and Full Custom flows

• Useful features include– Testbenches: assertions, constrained random,

coverage– Design: structures, always_comb, always_ff

January 14, 2008

Current P1800 Efforts

• Merging P1364 and P1800 into one standard is complete– Draft released for purchase

• http://standards.ieee.org/announcements/PR_SYSTEMVERILOGstds.html

• Enhancement of assertion features• Clarification of the scheduling algorithm, naming,

and other complex issues• Initial balloting expected in July of 2008

– Current draft in the process of freezing

January 14, 2008

SV Contacts

• Working Group website– http://www.eda.org/sv-ieee1800/

• Technical committee websites– SV-AC (Assertions)

• http://www.eda.org/sv-ac/

– SV-BC (Design)• http://www.eda.org/sv-bc/

– SV-CC (VPI)• http://www.eda.org/sv-cc/

– SV-EC (Testbench)• http://www.eda.org/sv-ec/

– SV-XC (Cross HDL)• http://www.eda.org/sv-xc/