ITRS 2009 1

Metrology RoadmapMetrology Roadmap20102010

EuropeEurope Adrian Kiermasz (Metryx)Adrian Kiermasz (Metryx)Carlos Beitia (Carlos Beitia (CEA LETI MINATECCEA LETI MINATEC))Philippe Maillot (ST)Philippe Maillot (ST)Delphine Le Cunff (ST)Delphine Le Cunff (ST)

JapanJapan Yuichiro Yamazaki (Toshiba)Yuichiro Yamazaki (Toshiba)Masahiko Ikeno (Hitachi High-Tech)Masahiko Ikeno (Hitachi High-Tech)

KoreaKoreaTaiwanTaiwan

North AmericaNorth America Yaw Obeng (NIST)Yaw Obeng (NIST)George Orji (NIST)George Orji (NIST)Jack Martinez (NIST)Jack Martinez (NIST)Dave Seiler (NIST)Dave Seiler (NIST) Ben Bunday (ISMI)Ben Bunday (ISMI)Vic Vartanian (ISMI)Vic Vartanian (ISMI)Alain Diebold (CNSE – Univ. Albany)Alain Diebold (CNSE – Univ. Albany)

ITRS 2009 2

Metrology Timing Model w/Technology Cycle Timing

Source: 2009 ITRS - Executive Summary Fig 2b

Months

Development Production

Vol

ume

(Waf

ers/

Mon

th)

2

20

200

2K

20K

200KResearch

-72 0 24-48 -24-96

First Tech. Conf.

Device PapersUp to ~12yrs

Prior to Product

20192017201520132011 2021

1st 2 Co’s

Reach

Product

First Tech. Conf.

Circuits PapersUp to ~ 5yrs

Prior to Product

New for 2010

Process

Research

Tool

Alpha

Tool

Beta

Tool

Product

Tool

Metrology/Char.

Research

Tool

Metrology

Alpha Tool

Metrology

Product Tool

w/prec. & Uncert.

Metrology

Beta Tool

w/precision

ITRS 2009 3

Metrology Materials and Test Structure Timing Model w/Technology Cycle Timing

Source: 2009 ITRS - Executive Summary Fig 2b

Months

Development Production

Vol

ume

(Waf

ers/

Mon

th)

2

20

200

2K

20K

200KResearch

-72 0 24-48 -24-96

First Tech. Conf.

Device PapersUp to ~12yrs

Prior to Product

20192017201520132011 2021

1st 2 Co’s

Reach

Product

First Tech. Conf.

Circuits PapersUp to ~ 5yrs

Prior to Product

New for 2010

Metrology

Research

Tool

Metrology

Alpha Tool

Metrology

Product Tool

w/prec. & Uncert.

Metrology

Research

Samples

Metrology Test Structure

Samples @ Man. Design Rules

Metrology

Beta Tool

w/precision

ITRS 2009 4

2010 Metrology Roadmap2010 2013 2016 2019

Flash 1/2 pitch (nm) 32 22 16 11

DRAM ½ Pitch (nm) 45 32 22 16MPU Printed Gate Length (nm) 41 28 20 14.0MPU Physical Gate Length (nm) 27 20 15.0 12.0Wafer Overlay Control (nm) - 20% DRAM 9.0 6.0 5.0 3.0Wafer Overlay Control Double Patterning (nm) 6 4 2 1Lithography MetrologyPhysical CD Control (nm)Allowed Litho Variance = 3/4 Total Variance

2.8 2.1 1.6 1.2

Wafer CD metrology tool uncertainty (3s, nm) at P/T = 0.2 0.55 0.42 0.31 0.25

Etched Gate Line Width Roughness (nm) <8% of CD 2.1 1.6 1.2 1.0

Printed CD Control (nm)Allowed Litho Variance = 3/4 Total Variance

3.3 2.3 1.7 1.1

Wafer CD metrology tool uncertainty (3s, nm) at P/T = 0.2 0.7 0.5 0.4 0.3

Double Patterning Overlay Metrology

Double Exposure and Etch - Process Range (nm) 6.4 5.1 4.0 3.2

Double Exposure and Etch - Uncertainty (nm) 1.3 1.0 0.8 0.6

Spacer PEE process

First pass CD control (after etch) - Process Variation (nm) 3.0 2.4 1.9 1.6

First pass CD control (after etch) - Uncertainty (nm) 0.6 0.5 0.4 0.3

Front End Processes Metrology

High Performance Logic EOTequivalent oxide thickness (EOT), nm

0.65 0.5 0.5 0.5

Logic Dielectric EOT Precision 3s, nm 0.0026 0.002 0.002 0.002

Interconnect MetrologyBarrier layer thick (nm) 3.3 2.4 1.7 1.3Void Size for 1% Voiding in Cu Lines 4.5 3.2 2.2 1.6Detection of Killer Pores at (nm) size 4.5 3.2 2.2 1.6

Gat

eD

ense

L

ines

ITRS 2009 5

Litho Metrology

CD Metrology Extendibility

Dual PatterningLER

Litho Metrology for 3D Devices

MuGFETMuCFET

CD-SAXSSpacersSpacers

Pitch

LinewidthCurvature & Area of Missing Pattern

Line End Shortening

Contour vs. GDS2

Contour vs DesignContour vs Designpolarizer

analyzermonochromator

p

s

E(t)

Polarizationafter sample

p

s

p

s

Si

Light source(Xe, D2, lasers)

Si(100)

a-Si

HfSixOy

(a)

30 ÅSi(100)

a-Si

HfSixOy

(a)

30 Å

Muller Matrix Ellipsometry

ITRS 2009 6

Metrology for FEPMetrology for Generation II and III

High K stacksEOT & Defects for

Alternate Channel Materials

Nano-topography & Local Stress measurements

New Memory Materials Phase Change Memory

FDSOI

MuGFETMuCFET

+ III/V High µAlternative

Channel Mat’ls

Sidewall Metrology for 3D Devices

ITRS 2009 7

Metrology for ERM/ERDHigh carrier mobility and structural robustness have driven a

considerable effort in Graphene research

Measurement of Bi-layer

misorientation

Aberration corrected TEM

How many Layers? Raman and LEEM

Quantum Hall Effect observes the Berry Phase

ITRS 2009 8

Metrology for 3D Interconnect

X-Ray MicroscopyOverlay – IR Microscopy

Stress MetrologyRaman Microscopy

Bonding Defects - SAM

ITRS 2009 9

Metrology Summary• FEP-Interconnect-Litho

– PC and SST RAM - New materials for Metrology– Dual Patterning– 3D Metrology – Confirm Geometry Requirements

e.g. film thickness & properties on sidewall– Reference Methods for 3D– Composition & Stress – e.g. buried channels– EUV metrology requirements

• ERD-ERM– III-V & Ge Transition to FEP & PIDS– STT RAM Transition to FEP & PIDS

• Tunnel Dielectric• Magnetic layers and interfaces

– Redox RAM• Local characterization of oxygen vacancies • Real device dimensions and structures

– Deterministic Doping• Characterize dopants in 3D

– Dopant vacancies and interstitials– Directed Self Assembly

• Defect detection• Structure variations

– Graphene• Defects in CVD Graphene• Mobility & Substrate Interactions• Bandgap Measurement (Strain, etc.)

3D Metrology for Advanced Memory

Graphene – C. Kisielowski