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ISLAMIC UNIVERSITY OF GAZA Faculty of Engineering Computer Engineering Department. EELE3321: Digital Electronics Course Asst. Prof. Mohammed Alhanjouri Lecture 1 : Properties and Definitions of Digital ICs Spring 2009-2010. - PowerPoint PPT Presentation
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ISLAMIC UNIVERSITY OF GAZA
Faculty of Engineering
Computer Engineering Department
EELE3321: Digital Electronics CourseAsst. Prof. Mohammed Alhanjouri
Lecture 1: Properties and Definitions of Digital ICs
Spring 2009-2010
Digital electronics circuits are represented by five basic logic operations:
NOT (Inverter)
AND
OR
NAND
NOR
NOT (inverter)
input Output
1 00 1
ANDInput Outputa b y0 0 00 1 01 0 01 1 1
ORInput Outputa b y0 0 00 1 11 0 11 1 1
NANDInput Outputa b y0 0 10 1 11 0 11 1 0
NORInput Outputa b y0 0 10 1 01 0 01 1 0
The truth table is a table to represent the relation between the input and the output
Inverting and Non-Inverting (Buffer)
IDEAL LOGIC ELEMENTS
Ideal Inverter
One power supply (Vcc) typical operating voltage of many logic families is 5VIcc is zero (ideal)Pcc is zero (ideal) – power dissipated
Vin < Vcc/2 Vout is logical 1 (Vcc)Vin > Vcc/2 Vout is logical 0Vin = Vcc/2 Unpredictable results (Should be avoided)CMOS logic family is the nearest to ideal
Voltage Transfer Characteristic
Transient Response
Ideal input and output Gate Impedances
Model of the input and the output impedance of a logic inverter
For multiple output (referred to as Fan-out) the logic gates is directly dependent upon the gate’s input and output impedances
Static driving of Multiple (Identical) Inverters
Iout = N Íin
For very large input resistance, the input current is zero, and the driving capabilities are maximized.Ideally, the infinite input resistance is desired because given infinite driving capability.
But for cascaded inverters with infinite input resistance the input capacitance of load gates must be charged through the output resistance of driving inverter
For small output resistance the charging current is large and faster switching time Zero output resistance, for ideally For small capacitance, faster switching when fewer gates
Inverting Voltage transfer characteristics
VOH= Output High VoltageVm= Midpoint VoltageVOL= Output Low VoltageVIH= Input High VoltageVIL= Input Low VoltageVTW= Transition Width = VIH – VIL
VLS= Logic Swing Voltage = VOH – VOL
At Vm Vin = Vout
Noise in Digital CircuitsNoise Margins: High noise Margin VNMH =VOH – VIH
Low noise Margin VNML =VIL – VOL
Noise Sensitivities: High noise Sensitivity VNSH =VOH – Vm
Low noise Sensitivity VNSL =Vm – VOL
Noise Immunities: Is the ability of a gate to reject the noiseHigh noise Immunity VNIH = VNSH /(VOH – VOL)
Low noise Immunity VNIL = VNSL /(VOH – VOL)
(VOH – VOL)= VLS
VOH VIH
Undefined Region
VIL VOL
“1”
“0”
Fan-In and Fan-OutThe maximum Fan-out possible during the driving gate’s logical “1” output state is
The maximum Fan-out possible during the driving gate’s logical “0” output state is
The maximum Fan-out possible is the smallest value. The maximum Fan-out possible is an Integer number. If the Maximum Fan-out is not integer, should be use Integer number less than the actual value.
)(
)(
highin
highouthigh I
IN
)(
)(
lowin
lowoutlow I
IN
Transient CharacteristicsDigital logic circuits have finite switching speeds
Propagation delayWhen the input voltage changes from one level to another, the output voltage response is delayed in time
VOH < Vcc
td = delay timetr = rise timets = storage timetf= fall timetON= td+tr = turn on timetOFF= ts+tf
= turn off time tr and tf are associated with charging and discharging load capacitancetd and ts are associated with stored charge of PN Junction
Switching Speed Definitions
Propagation Delay Times
tPLH = low to high propagation delay timetPHL = high to low propagation delay timetp (ave.) = (tPLH + tPHL) / 2
Power DissipationWe have two power dissipated valuesPcc(OH) output highPcc(OL) output lowThe average power dissipation
But for some logic circuit as shown, the power equations as:
EEEEEE
CCCCCC
diss
EECCdiss
EEEEEE
CCCCCC
CCCCCC
CC
CCCC
VOLIOHIVOLIOHIaveP
avePavePavePVIPVIP
VOLIOHIaveP
OLPOHP
*2
)()(*2
)()()(
)()()(**
*2
)()()(
2)()(
Power-delay product
For faster propagation delay times, the power dissipation will be increase, while the lower power dissipation results in longer propagation delay times.
Power-delay product = Speed-power product
PD = PDiss(ave)*tP(ave) (Joules)
Homework of Ch.1From chapter 1 problems, try to solve the following problems
1.3, 1.12, 1.18, 1.26
Then submit your solutions for course discussion teacher.