IS41C16100C IS41LV16100C - ISSI Integrated Silicon Solution, Inc. — — 1-800-379-4774 Rev. C 02/16/2012 IS41C16100C IS41LV16100C TRUTH TABLE(5) Function RAS LCAS UCAS WE OE Address

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1Rev. C 02/16/2012

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IS41C16100CIS41LV16100C

FEATURES

• TTLcompatibleinputsandoutputs;tristateI/O

• RefreshInterval:

— AutorefreshMode:1,024cycles/16ms

— RAS-Only,CAS-before-RAS(CBR),andHidden

— SelfrefreshMode:1,024cycles/128ms

• JEDECstandardpinout

• Singlepowersupply:5V±10%(IS41C16100C)3.3V±10%(IS41LV16100C)

• ByteWriteandByteReadoperationviatwoCAS

• IndustrialTemperatureRange:-40oCto+85oC

DESCRIPTION

TheISSIIS41C16100CandIS41LV16100Care1,048,576x16-bithigh-performanceCMOSDynamicRandomAc-cessMemories.ThesedevicesofferacycleaccesscalledExtendedDataOut(EDO)PageMode.EDOPageModeallows1,024randomaccesseswithinasinglerowwithaccesscycletimeasshortas30nsper16-bitword.Itisasynchronous,asitdoesnotrequireaclocksignalinputtosynchronizecommandsandI/O.

ThesefeaturesmaketheIS41C/41LV16100Cideallysuitedforhigh-bandwidthgraphics,digitalsignalprocessing,high-performance computing systems, and peripheralapplicationsthatrunwithoutaclocktosynchronizewiththeDRAM.

TheIS41C/41LV16100Cispackagedina42-pin400-milSOJand400-mil50/44pinTSOP(TypeII).

1Mx16 16Mb DRAM WITH EDO PAGE MODE

KEY TIMING PARAMETERS

Parameter -50 Unit

Max.RASAccessTime(trac) 50 ns

Max.CASAccessTime(tcac) 14 ns

Max.ColumnAddressAccessTime(taa) 25 ns

Min.EDOPageModeCycleTime(tpc) 30 ns

Min.Read/WriteCycleTime(trc) 85 ns

FEBRUARY 2012

2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C

02/16/2012

IS41C16100CIS41LV16100C

PIN CONFIGURATIONS

50(44)-Pin TSOP (Type II)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

VDD

I/O0

I/O1

I/O2

I/O3

VDD

I/O4

I/O5

I/O6

I/O7

NC

NC

WE

RAS

NC

NC

A0

A1

A2

A3

VDD

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

NC

LCAS

UCAS

OE

A9

A8

A7

A6

A5

A4

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

VDD

I/O0

I/O1

I/O2

I/O3

VDD

I/O4

I/O5

I/O6

I/O7

NC

NC

NC

WE

RAS

NC

NC

A0

A1

A2

A3

VDD

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

NC

NC

LCAS

UCAS

OE

A9

A8

A7

A6

A5

A4

GND

PIN DESCRIPTIONS

A0-A9 AddressInputs

I/O0-15 DataInputs/Outputs

WE WriteEnable

OE OutputEnable

RAS RowAddressStrobe

UCAS UpperColumnAddressStrobe

LCAS LowerColumnAddressStrobe

Vdd Power

GND Ground

NC NoConnection

42-Pin SOJ

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3Rev. C02/16/2012

IS41C16100CIS41LV16100C

FUNCTIONAL BLOCK DIAGRAM

OE

WE

LCAS

UCASCAS WE

OE

DATA I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

MEMORY ARRAY1,048,576 x 16

RO

W D

EC

OD

ER DA

TA

I/O

BU

FF

ER

S

CAS CLOCK

GENERATOR

WECONTROLLOGICS

OE CONTROL

LOGIC

I/O0-I/O15

RAS RA

S

A0-A9

RAS CLOCK

GENERATOR

REFRESH COUNTER

ADDRESSBUFFERS


02/16/2012

IS41C16100CIS41LV16100C

TRUTH TABLE(5)

Function RAS LCAS UCAS WE OE Address tR/tC I/O

Standby H X X X X X High-ZRead:Word L L L H L ROW/COL Dout

Read:LowerByte L L H H L ROW/COL LowerByte,Dout

UpperByte,High-ZRead:UpperByte L H L H L ROW/COL LowerByte,High-Z UpperByte,Dout

Write:Word(EarlyWrite) L L L L X ROW/COL Din

Write:LowerByte(EarlyWrite) L L H L X ROW/COL LowerByte,Din UpperByte,High-ZWrite:UpperByte(EarlyWrite) L H L L X ROW/COL LowerByte,High-Z UpperByte,Din

Read-Write(1,2) L L L H→L L→H ROW/COL Dout,Din

EDOPage-ModeRead(2) 1stCycle: L H→L H→L H L ROW/COL Dout

2ndCycle: L H→L H→L H L NA/COL Dout

AnyCycle: L L→H L→H H L NA/NA Dout

EDOPage-ModeWrite(1) 1stCycle: L H→L H→L L X ROW/COL Din

2ndCycle: L H→L H→L L X NA/COL Din

EDOPage-Mode(1,2) 1stCycle: L H→L H→L H→L L→H ROW/COL Dout,Din

Read-Write 2ndCycle: L H→L H→L H→L L→H NA/COL Dout,Din

HiddenRefresh Read(2) L→H→L L L H L ROW/COL Dout

Write(1,3) L→H→L L L L X ROW/COL Dout

RAS-OnlyRefresh L H H X X ROW/NA High-ZCBRRefresh(4) H→L L L H X X High-Z

Notes:1. TheseWRITEcyclesmayalsobeBYTEWRITEcycles(eitherLCASorUCASactive).2. TheseREADcyclesmayalsobeBYTEREADcycles(eitherLCASorUCASactive).3. EARLYWRITEonly.4. AtleastoneofthetwoCASsignalsmustbeactive(LCASorUCAS).5.Commandsvalidonlyafterproperinitialization.


IS41C16100CIS41LV16100CFunctional Description

The IS41C/41LV16100C is a CMOS DRAM optimizedforhigh-speedbandwidth,lowpowerapplications.DuringREADorWRITEcycles,eachbitisuniquelyaddressedthroughthe16addressbits.Theseareenteredtenbits(A0-A9)attime.TherowaddressislatchedbytheRowAddressStrobe(RAS).ThecolumnaddressislatchedbytheColumnAddressStrobe(CAS).RAS isusedtolatchthefirstninebitsandCASisusedtolatchthelatterninebits.

TheIS41C/41LV16100ChastwoCAScontrols,LCASandUCAS.TheLCASandUCAS inputs internallygeneratesaCASsignal functioning inan identicalmanner to thesingleCASinputontheother1Mx16DRAMs.ThekeydifferenceisthateachCAScontrolsitscorrespondingI/Otristatelogic(inconjunctionwithOEandWEandRAS).LCAScontrolsI/O0throughI/O7andUCAScontrolsI/O8throughI/O15.

TheIS41C/41LV16100CCASfunctionisdeterminedbythefirstCAS(LCASorUCAS)transitioningLOWandthelasttransitioningbackHIGH.ThetwoCAScontrolsgivetheIS41C16100CandIS41LV16100CbothBYTEREADandBYTEWRITEcyclecapabilities.

Memory Cycle

AmemorycycleisinitiatedbybringRASLOWanditisterminated by returning both RAS and CAS HIGH.Toensuresproperdeviceoperationanddata integrityanymemorycycle,onceinitiated,mustnotbeendedorabortedbeforetheminimumtrastimehasexpired.Anewcyclemustnotbe initiateduntil theminimumprecharge timetrp,tcphaselapsed.

Read Cycle

AreadcycleisinitiatedbythefallingedgeofCASorOE,whicheveroccurslast,whileholdingWEHIGH.Thecolumnaddressmustbeheldforaminimumtimespecifiedbytar.DataOutbecomesvalidonlywhentrac,taa,tcacandtoeaareallsatisfied.Asaresult,theaccesstimeisdependentonthetimingrelationshipsbetweentheseparameters.

Write Cycle

AwritecycleisinitiatedbythefallingedgeofCASandWE,whicheveroccurslast.TheinputdatamustbevalidatorbeforethefallingedgeofCASorWE,whicheveroccursfirst.

Auto Refresh Cycle

Toretaindata,1,024refreshcyclesarerequiredineach16msperiod.Therearetwowaystorefreshthememory.

1. Byclockingeachofthe1,024rowaddresses(A0throughA9)withRASatleastonceeverytrefmax.Anyread,write,read-modify-writeorRAS-onlycyclerefreshestheaddressedrow.

2. UsingaCAS-before-RASrefreshcycle.CAS-before-RASrefreshisactivatedbythefallingedgeofRAS,whileholdingCASLOW.InCAS-before-RASrefreshcycle,

an internal9-bitcounterprovidestherowaddressesandtheexternaladdressinputsareignored.

CAS-before-RAS is a refresh-only mode and no dataaccessordeviceselection isallowed.Thus, theoutputremainsintheHigh-Zstateduringthecycle.

Self Refresh Cycle

TheSelfRefreshallowstheuseradynamicrefresh,dataretentionmodeattheextendedrefreshperiodof128ms.i.e.,125µsperrowwhenusingdistributedCBRrefreshes.Thefeaturealsoallowstheuserthechoiceofafullystatic,lowpowerdataretentionmode.TheoptionalSelfRefreshfeatureisinitiatedbyperformingaCBRRefreshcycleandholdingRASLOWforthespecifiedtRAS.

The Self Refresh mode is terminated by driving RASHIGHforaminimumtimeoftRP.ThisdelayallowsforthecompletionofanyinternalrefreshcyclesthatmaybeinprocessatthetimeoftheRASLOW-to-HIGHtransition.IftheDRAMcontrollerusesadistributedrefreshsequence,aburstrefreshisnotrequireduponexitingSelfRefresh.

However,iftheDRAMcontrollerutilizesaRAS-onlyorburstrefreshsequence,all1,024rowsmustberefreshedwithintheaverageinternalrefreshrate,priortotheresumptionofnormaloperation.

Extended Data Out Page Mode

EDO page mode operation permits all 1,024 columnswithinaselectedrowtoberandomlyaccessedatahighdatarate.

InEDOpagemodereadcycle,thedata-outisheldtothenextCAScycle’sfallingedge,insteadoftherisingedge.Forthisreason,thevaliddataoutputtimeinEDOpagemodeisextendedcomparedwiththefastpagemode.Inthefastpagemode,thevaliddataoutputtimebecomesshorterastheCAScycletimebecomesshorter.There-fore,inEDOpagemode,thetimingmargininreadcycleislargerthanthatofthefastpagemodeeveniftheCAScycletimebecomesshorter.

InEDOpagemode,duetotheextendeddatafunction,theCAScycletimecanbeshorterthaninthefastpagemodeifthetimingmarginisthesame.

TheEDOpagemodeallowsbothreadandwriteoperationsduringoneRAScycle,buttheperformanceisequivalenttothatofthefastpagemodeinthatcase.

Power-On

During Power-On, RAS, UCAS, LCAS, and WE mustall track with Vdd (HIGH) to avoid current surges,and allow initialization to continue. An initial pause of200µsisrequiredfollowedbyaminimumofeightinitial-ization cycles (any combination of cycles containing aRASsignal).


02/16/2012

IS41C16100CIS41LV16100C

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameters Rating Unit

Vt VoltageonAnyPinRelativetoGND 5V –1.0to+7.0 V 3.3V –0.5to+4.6 Vdd SupplyVoltage 5V –1.0to+7.0 V 3.3V –0.5to+4.6 Iout OutputCurrent 50 mA Pd PowerDissipation 1 W Ta IndustrialOperationTemperature -40to+85 °C Tstg StorageTemperature –55to+125 °CNote:1. Stressgreater than those listedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdam-

agetothedevice.Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.

RECOMMENDED OPERATING CONDITIONS (AtTa=-40°Cto+85°CforIndustrialgrade.VoltagesarereferencedtoGND.)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Vdd SupplyVoltage 5V 4.5 5.0 5.5 V 3.3V 3.0 3.3 3.6 Vih InputHighVoltage 5V 2.4 — Vdd+1.0 V 3.3V 2.0 — Vdd+0.3 Vil InputLowVoltage 5V –1.0 — 0.8 V 3.3V –0.3 — 0.8 iil InputLeakageCurrent Anyinput0V≤Vin≤Vdd –5 5 µA Otherinputsnotundertest=0V

iio OutputLeakageCurrent Outputisdisabled(Hi-Z) –5 5 µA 0V≤Vout≤Vdd

Voh OutputHighVoltageLevel ioh=–5.0mA 5V 2.4 — V ioh=–2.0mA 3.3V 2.4 —

Vol OutputLowVoltageLevel iol=4.2mA 5V — 0.4 V iol=2.0mA 3.3V — 0.4

CAPACITANCE(1,2)

Symbol Parameter Max. Unit

Cin1 InputCapacitance:A0-A9 5 pF Cin2 InputCapacitance:RAS,UCAS,LCAS,WE,OE 7 pF Cio DataInput/OutputCapacitance:I/O0-I/O15 7 pFNotes:1. Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.2. Testconditions:Ta=25°C,f=1MHz.


IS41C16100CIS41LV16100C

ELECTRICAL CHARACTERISTICS(1)

(RecommendedOperatingConditionsunlessotherwisenoted.)

Symbol Parameter Test Condition VDD Min. Max. Unit

idd1 StandbyCurrent:TTL RAS,LCAS,UCAS≥Vih 5V — 2 mA 3.3V — 2 mA

idd2 StandbyCurrent:CMOS RAS,LCAS,UCAS≥Vdd–0.2V 5V — 1 mA 3.3V — 1 mA

idd3 OperatingCurrent: RAS,LCAS, UCAS, 5V — 90 mA RandomRead/Write(2,3,4) AddressCycling,trc=trc(min.) 3.3V — 90 AveragePowerSupplyCurrent

idd4 OperatingCurrent: RAS=Vil,LCAS,UCAS, 5V — 30 mA EDOPageMode(2,3,4) Cyclingtpc=tpc(min.) 3.3V — 30 AveragePowerSupplyCurrent

idd5 RefreshCurrent: RASCycling,LCAS,UCAS≥Vih 5V — 60 mA RAS-Only(2,3) trc=trc(min.) 3.3V — 60 AveragePowerSupplyCurrent

idd6 RefreshCurrent: RAS,LCAS,UCASCycling 5V — 60 mA CBR(2,3,5) trc=trc(min.) 3.3V — 60 AveragePowerSupplyCurrent Notes:1. Aninitialpauseof200µsisrequiredafterpower-upfollowedbyeightRASrefreshcycles(RAS-OnlyorCBR)beforeproperdevice

operationisassured.TheeightRAScycleswake-upshouldberepeatedanytimethetrefrefreshrequirementisexceeded.2. Dependentoncyclerates.3. Specifiedvaluesareobtainedwithminimumcycletimeandtheoutputopen.4. Column-addressischangedonceeachEDOpagecycle.5. Enableson-chiprefreshandaddresscounters.


02/16/2012

IS41C16100CIS41LV16100C

AC CHARACTERISTICS(1,2,3,4,5,6)


-50 -60 Symbol Parameter Min. Max. Min. Max. Units

trc RandomREADorWRITECycleTime 85 — 110 — ns

trac AccessTimefromRAS(6,7) — 50 — 60 ns

tcac AccessTimefromCAS(6,8,15) — 14 — 15 ns

taa AccessTimefromColumn-Address(6) — 25 — 30 ns

tras RASPulseWidth 50 10K 60 10K ns

trp RASPrechargeTime 30 — 40 — ns

tcas CASPulseWidth(26) 8 10K 10 10K ns

tcp CASPrechargeTime(9,25) 9 — 10 — ns

tcsh CASHoldTime(21) 50 — 60 — ns

trcd RAStoCASDelayTime(10,20) 12 37 20 45 ns

tasr Row-AddressSetupTime 0 — 0 — ns

trah Row-AddressHoldTime 8 — 10 — ns

tasc Column-AddressSetupTime(20) 0 — 0 — ns

tcah Column-AddressHoldTime(20) 8 — 10 — ns

tar Column-AddressHoldTime 30 — 40 — ns (referencedtoRAS)

trad RAStoColumn-AddressDelayTime(11) 14 25 15 30 ns

tral Column-AddresstoRASLeadTime 25 — 30 — ns

trpc RAStoCASPrechargeTime 5 — 5 — ns

trsh RASHoldTime(27) 14 — 15 — ns

trhcp RASHoldTimefromCASPrecharge 37 — 37 — ns

tclz CAStoOutputinLow-Z(15,29) 0 — 0 — ns

tcrp CAStoRASPrechargeTime(21) 5 — 5 — ns

tod OutputDisableTime(19,28,29) 3 12 3 12 ns

toe/toea OutputEnableTime(15,16) — 14 — 15 ns

toehc OEHIGHHoldTimefromCASHIGH 15 — 15 — ns

toep OEHIGHPulseWidth 10 — 10 — ns

toes OELOWtoCASHIGHSetupTime 5 — 5 — ns

trcs ReadCommandSetupTime(17,20) 0 — 0 — ns

trrh ReadCommandHoldTime 0 — 0 — ns (referencedtoRAS)(12)

trch ReadCommandHoldTime 0 — 0 — ns (referencedtoCAS)(12,17,21)

twch WriteCommandHoldTime(17,27) 8 — 10 — ns

twcr WriteCommandHoldTime 40 — 50 — ns (referencedtoRAS)(17)


IS41C16100CIS41LV16100C

AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)


-50 -60 Symbol Parameter Min. Max. Min. Max. Units

twp WriteCommandPulseWidth(17) 8 — 10 — ns

twpz WEPulseWidthstoDisableOutputs 10 — 10 — ns

trwl WriteCommandtoRASLeadTime(17) 13 — 15 — ns

tcwl WriteCommandtoCASLeadTime(17,21) 8 — 15 — ns

twcs WriteCommandSetupTime(14,17,20) 0 — 0 — ns

tdhr Data-inHoldTime(referencedtoRAS) 39 — 40 — ns

tach Column-AddressSetupTimetoCASprecharge 15 — 15 — ns duringWRITEcycle

toeh OEHoldTimefromWEduring 14 — 15 — ns READ-MODIFY-WRITEcycle(18)

tds Data-InSetupTime(15,22) 0 — 0 — ns

tdh Data-InHoldTime(15,22) 8 — 15 — ns

trwc READ-MODIFY-WRITECycleTime 110 — 155 — ns

trwd RAStoWEDelayTimeduring 65 — 85 — ns READ-MODIFY-WRITECycle(14)

tcwd CAStoWEDelayTime(14,20) 26 — 40 — ns

tawd Column-AddresstoWEDelayTime(14) 40 — 55 — ns

tpc EDOPageModeREADorWRITE 30 — 40 — ns CycleTime(24)

trasp RASPulseWidthinEDOPageMode 50 100K 60 100K ns

tcpa AccessTimefromCASPrecharge(15) — 30 — 35 ns

tprwc EDOPageModeREAD-WRITE 56 — 56 — ns CycleTime(24)

tcoh DataOutputHoldafterCASLOW 5 — 5 — ns

toff OutputBufferTurn-OffDelayfrom 3 12 3 15 ns CASorRAS(13,15,19,29)

twhz OutputDisableDelayfromWE 3 10 3 15 ns

tclch LastCASgoingLOWtoFirstCAS 10 — 10 — ns returningHIGH(23)

tcsr CASSetupTime(CBRREFRESH)(30,20) 5 — 5 — ns

tchr CASHoldTime(CBRREFRESH)(30,21) 8 — 10 — ns

tord OESetupTimepriortoRASduring 0 — 0 — ns HIDDENREFRESHCycle

twrp WESetupTime(CBRRefresh) 5 — 5 — ns

twrh WEHoldTime(CBRRefresh) 8 — 10 — ns

tref AutoRefreshPeriod(1,024Cycles) — 16 — 16 ms

tref SelfRefreshPeriod(1,024Cycles) — 128 — 128 ms

tt TransitionTime(RiseorFall)(2,3) 1 50 1 50 ns

Note:The-60timingparametersareshownforreferenceonly.The-50speedoptionsupports50nsand60nstimingspecifications.


02/16/2012

IS41C16100CIS41LV16100C

Notes: 1.Aninitialpauseof200µsisrequiredafterpower-upfollowedbyeightRASrefreshcycle(RAS-OnlyorCBR)beforeproperdevice

operationisassured.TheeightRAScycleswake-upshouldberepeatedanytimethetrefrefreshrequirementisexceeded. 2.Vih(MIN)andVil(MAX)arereferencelevelsformeasuringtimingofinputsignals.Transitiontimes,aremeasuredbetweenVih

andVil(orbetweenVilandVih)andassumetobe1nsforallinputs. 3.Inadditiontomeetingthetransitionratespecification,allinputsignalsmusttransitbetweenVihandVil(orbetweenVilandVih)

inamonotonicmanner. 4.IfCASandRAS=Vih,dataoutputisHigh-Z. 5.IfCAS=Vil,dataoutputmaycontaindatafromthelastvalidREADcycle. 6.MeasuredwithaloadequivalenttooneTTLgateand50pF. 7.Assumesthattrcd≤ trcd(MAX).Iftrcdisgreaterthanthemaximumrecommendedvalueshowninthistable,tracwillincrease

bytheamountthattrcdexceedsthevalueshown. 8.Assumesthattrcd≤trcd(MAX). 9.IfCASisLOWatthefallingedgeofRAS,dataoutwillbemaintainedfromthepreviouscycle.Toinitiateanewcycleandclearthe

dataoutputbuffer,CASandRASmustbepulsedfortcp.10.Operationwiththetrcd(MAX)limitensuresthattrac(MAX)canbemet.trcd(MAX)isspecifiedasareferencepointonly;iftrcd

isgreaterthanthespecifiedtrcd(MAX)limit,accesstimeiscontrolledexclusivelybytcac.11.Operationwithinthetrad(MAX)limitensuresthattrcd(MAX)canbemet.trad(MAX)isspecifiedasareferencepointonly;iftrad

isgreaterthanthespecifiedtrad(MAX)limit,accesstimeiscontrolledexclusivelybytaa.12.EithertrchortrrhmustbesatisfiedforaREADcycle.13.toff(MAX)definesthetimeatwhichtheoutputachievestheopencircuitcondition;itisnotareferencetoVohorVol.14.twcs,trwd,tawdandtcwdarerestrictiveoperatingparametersinLATEWRITEandREAD-MODIFY-WRITEcycleonly.Iftwcs≤

twcs(MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.Iftrwd≤ trwd(MIN),tawd≤ tawd(MIN)andtcwd≤ tcwd(MIN),thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindatareadfromtheselectedcell.Ifneitheroftheaboveconditionsismet,thestateofI/O(ataccesstimeanduntilCASandRASorOEgobacktoVih)isindeterminate.OEheldHIGHandWEtakenLOWafterCASgoesLOWresultinaLATEWRITE(OE-controlled)cycle.

15.Outputparameter(I/O)isreferencedtocorrespondingCASinput,I/O0-I/O7byLCASandI/O8-I/O15byUCAS.16.DuringaREADcycle,ifOEisLOWthentakenHIGHbeforeCASgoesHIGH,I/Ogoesopen.IfOEistiedpermanentlyLOW,a

LATEWRITEorREAD-MODIFY-WRITEisnotpossible.17.WritecommandisdefinedasWEgoinglow.18.LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothtodandtoehmet(OEHIGHduringWRITEcycle)inorderto

ensurethattheoutputbufferswillbeopenduringtheWRITEcycle.TheI/OswillprovidethepreviouslywrittendataifCASremainsLOWandOEistakenbacktoLOWaftertoehismet.

19.TheI/OsareinopenduringREADcyclesoncetodortoffoccur.20.ThefirstχCASedgetotransitionLOW.21.ThelastχCASedgetotransitionHIGH.22.TheseparametersarereferencedtoCASleadingedgeinEARLYWRITEcyclesandWEleadingedgeinLATEWRITEorREAD-

MODIFY-WRITEcycles.23.LastfallingχCASedgetofirstrisingχCASedge.24.LastrisingχCASedgetonextcycle’slastrisingχCASedge.25.LastrisingχCASedgetofirstfallingχCASedge.26.EachχCASmustmeetminimumpulsewidth.27.LastχCAStogoLOW.28.I/Oscontrolled,regardlessUCASandLCAS.29.The3nsminimumisaparameterguaranteedbydesign.30.Enableson-chiprefreshandaddresscounters.

AC TEST CONDITIONSOutput load: Two TTL Loads and 100 pF (Vdd = 5.0V ±10%) One TTL Load and 50 pF (Vdd = 3.3V ±10%)

Input timing reference levels: Vih = 2.4V, Vil = 0.8V (Vdd = 5.0V ±10%); Vih = 2.0V, Vil = 0.8V (Vdd = 3.3V ±10%)

Output timing reference levels: Voh = 2.4V, Vol = 0.4V (Vdd = 5V ±10%, 3.3V ±10%)


IS41C16100CIS41LV16100C

READ CYCLE

Note:1. toffisreferencedfromrisingedgeofRASorCAS,whicheveroccurslast.

tRAS

tRC

tRP

tAR

tCAHtASC

tRAD tRAL

OE

I/O

WE

ADDRESS

UCAS/LCAS

RAS

Row Column Row

Open OpenValid Data

tCSH

tCAS

tRSH

tCRP tCLCHtRCD

tRAHtASR

tRRH

tRCHtRCS

tAA

tCAC tOFF(1)

tRAC

tCLC

tOES

tOE tOD

Don’tCare

Undefined


02/16/2012

IS41C16100CIS41LV16100C

EARLY WRITE CYCLE (OE=DON'TCARE)

tRAS

tRC

tRP

tAR

tCAHtASC

tRAD tRAL

tACH

I/O

WE

ADDRESS

UCAS/LCAS

RAS

Row Column Row

tCSH

tCAS

tRSH

tCRP tCLCHtRCD

tRAHtASR

tCWL

tWCR

tWCH

tRWL

tWP

tWCS

tDHtDS

tDHR

Valid Data

Don’tCare


IS41C16100CIS41LV16100C

READ WRITE CYCLE (LATEWRITEandREAD-MODIFY-WRITECycles)

tRAS

tRWC

tRP

tAR

tCAHtASC

tRAD tRAL

tACH

WE

OE

ADDRESS

UCAS/LCAS

RAS

Row Column Row

tCSH

tCAS

tRSH

tCRP tCLCHtRCD

tRAHtASR

tRWD tCWL

tCWD tRWL

tAWD tWP

tRCS

tCAC

tCLZ tDS tDH

tOEHtODtOE

tRAC

tAA

I/O Open OpenValid DOUT Valid DIN

Don’tCare

Undefined


02/16/2012

IS41C16100CIS41LV16100C

EDO-PAGE-MODE READ CYCLE

Note:1. tpccanbemeasuredfromfallingedgeofCAStofallingedgeofCAS,orfromrisingedgeofCAStorisingedgeofCAS.Both

measurementsmustmeetthetpcspecifications.

tRASP tRP

ADDRESS

UCAS/LCAS

RAS

Row Row

tCAS, tCLCH

tCRP tRCD

tCSH

tCP tCAS, tCLCH

tCAH

tCAS, tCLCH

tRAL

tRSH

tCPtCP

tPC(1)

tASR

tRAH

tRAD

tAR

Column Column

tCAHtCAH

Column

tASCtASC

OE

I/O

WE

Open OpenValid Data

tAA tAA

tCPA

tCAC tCAC

tRAC

tCOHtCLZ

tOEP

tOE

tOES tOES tOD

tOEtOEHC

Valid Data

tRCH

tRRH

tAA

tCPA

tCAC

tOFFtCLZ

Valid Data

tOD

tASC

tRCS

Don’tCare

Undefined


IS41C16100CIS41LV16100C

EDO-PAGE-MODE EARLY-WRITE CYCLE

tRASP tRP

ADDRESS

UCAS/LCAS

RAS

Row Row

tCAS, tCLCH

tCRP tRCD

tCSH

tCP tCAS, tCLCH

tCAH

tCAS, tCLCH

tRAL

tRSH

tCPtCP

tPC

tASR

tRAH

tRAD

tAR tACH

Column Column

tACHtACH

tCAHtCAH

Column

tASCtASC

OE

I/O

WE

Valid Data

tASC

tWCS

tWCH

tCWL

tWP

tRHCP

tWCS

tWCH

tCWL

tWP

tDS

tDH

tDHR

tWCR

tWCS

tWCH

tCWL

tWP

Valid Data

tDS

tDH

Valid Data

tDS

tRWL

tDH

Don’tCare


02/16/2012

IS41C16100CIS41LV16100C

EDO-PAGE-MODE READ-WRITE CYCLE(LATEWRITEandREAD-MODIFYWRITECycles)

Note:1. tpccanbemeasuredfromfallingedgeofCAStofallingedgeofCAS,orfromrisingedgeofCAStorisingedgeofCAS.Both

measurementsmustmeetthetpcspecifications.

Don’tCare

Undefined

tRASP tRP

ADDRESS

UCAS/LCAS

RAS

Row Row

tCRP tRCD

tCSH

tCP

tCAH

tCAS, tCLCH

tRAL

tRSH

tCPtCP

tRAH

tRAD

tAR

tASR

Column Column

tCAHtCAH

Column

tASCtASC

tCAS, tCLCHtCAS, tCLCH

OE

I/O

WE

tASC

tRWDtRCS tCWL

tWPtAWD

tCWD

tDHtDS

tCACtCLZ

tAWDtCWD

tCWLtWP

tAWDtCWD

tCWLtRWL

tWP

Open OpenDINDOUT

tOE tOE tOE tOD

tOEH

tOD tOD

tDHtDS

tCPAtAA

tCACtCLZ

DINDOUT

tDHtDS

tCACtCLZ

DINDOUT

tCPAtAA

tRACtAA

tPC / tPRWC(1)


IS41C16100CIS41LV16100C

EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (PseudoREAD-MODIFYWRITE)

tRASP tRP

ADDRESS

UCAS/LCAS

RAS

Row Row

tCRP tRCD

tPC

tCSH

tCP

tCAH

tCAS

tRAL

tRSH

tCPtCP

tACH

tRAH

tRAD

tAR

tASR

Column (A) Column (N)

tCAHtCAH

Column (B)

tASCtASC

tCAS tCAS

OE

I/O

WE

tASC

tCAC

tRCH

tDH

Open OpenValid Data (A)

tOE

tWCS

tCACtCOH

DIN

tCPA

tWCH

tRACtAA

tPC

Valid Data (B)

tWHZ

tDS

tRCS

tAA

Don’tCare


02/16/2012

IS41C16100CIS41LV16100C

AC WAVEFORMS

READ CYCLE (WithWE-ControlledDisable)

RAS-ONLY REFRESH CYCLE (OE,WE=DON'TCARE)

tAR

tCAH tASCtASC

tRAD

OE

I/O

WE

ADDRESS

UCAS/LCAS

RAS

Row Column

Open OpenValid Data

tCSH

tCAStCRP tRCD tCP

tRAHtASR

tRCH tRCStWPZ

tRCS

tAA

tCAC

tWHZ

tRAC

tCLZtCLZ

tOE tOD

Column

tRAS

tRC

tRP

I/O

ADDRESS

UCAS/LCAS

RAS

Row Row

Open

tCRP

tRAHtASR

tRPC

Don’tCare

Undefined

Don’tCare


IS41C16100CIS41LV16100C

HIDDEN REFRESH CYCLE(1) (WE=HIGH;OE=LOW)

CBR REFRESH CYCLE (Addresses;OE=DON'TCARE)

Notes:1. AHiddenRefreshmayalsobeperformedafteraWriteCycle.Inthiscase,WE=LOWandOE=HIGH.2. toffisreferencedfromrisingedgeofRASorCAS,whicheveroccurslast.

tRAS tRAStRP tRP

I/O

UCAS/LCAS

RAS

WE

Open

tCPtRPC

tCSRtCHR tRPC

tCSRtCHR

tWRP tWRPtWRH tWRH

tRAS tRAStRP

UCAS/LCAS

RAS

tCRP tRCD tRSH tCHR

tAR

tASC

tRAD

ADDRESS Row Column

tRAHtASR

tRAL

tCAH

I/O Open OpenValid Data

tAA

tCAC

tRAC

tCLZ

tOFF(2)

OE

tOE

tORD

tOD

Don’tCare

Undefined


02/16/2012

IS41C16100CIS41LV16100C

ORDERING INFORMATION : 3.3V

Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Package

50 IS41LV16100C-50KI 400-milSOJ IS41LV16100C-50KLI 400-milSOJ,Lead-free IS41LV16100C-50TI 400-milTSOP(TypeII) IS41LV16100C-50TLI 400-milTSOP(TypeII),Lead-free

ORDERING INFORMATION : 5V

Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Package

50 IS41C16100C-50KI 400-milSOJ IS41C16100C-50KLI 400-milSOJ,Lead-free IS41C16100C-50TI 400-milTSOP(TypeII) IS41C16100C-50TLI 400-milTSOP(TypeII),Lead-free

Note:The-50speedoptionsupports50nsand60nstimingspecifications.


IS41C16100CIS41LV16100C


02/16/2012

IS41C16100CIS41LV16100C

Documents

IS41C16100C IS41LV16100C - ISSI Integrated Silicon Solution, Inc. — — 1-800-379-4774 Rev. C 02/16/2012 IS41C16100C IS41LV16100C TRUTH TABLE(5) Function RAS LCAS UCAS WE OE Address