IRF7821PbF

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www.irf.com 105/23/07

IRF7821PbFHEXFET® Power MOSFET

Notes through are on page 10

Benefits

l Very Low RDS(on) at 4.5V VGS

l Low Gate Chargel Fully Characterized Avalanche Voltage

and Current

Applications

l High Frequency Point-of-Load

Synchronous Buck Converter for

Applications in Networking &

Computing Systems.

Top View

81

2

3

4 5

6

7

D

D

D

DG

S

A

S

S

A

SO-8

VDSS RDS(on) max Qg(typ.)

30V 9.1mW@VGS= 10V 9.3nC

Absolute Maximum RatingsParameter Units

VDS Drain-to-Source Voltage V

VGS Gate-to-Source Voltage

ID @ TA = 25°C Continuous Drain Current, VGS @ 10V

ID @ TA = 70°C Continuous Drain Current, VGS @ 10V A

IDMPulsed Drain Current c

PD @TA = 25°C Power Dissipation f W

PD @TA = 70°C Power Dissipation f

Linear Derating Factor W/°C

TJ Operating Junction and °C

TSTG Storage Temperature Range

Thermal ResistanceParameter Typ. Max. Units

RθJLJunction-to-Drain Lead g

––– 20 °C/WRθJA

Junction-to-Ambient f g ––– 50

-55 to + 155

2.5

0.02

1.6

Max.

13.6

11

100

± 20

30

PD - 95213A

l Lead-Free



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Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. UnitsBVDSS Drain-to-Source Breakdown Voltage 30 ––– ––– V

∆ΒVDSS / ∆TJ Breakdown Voltage Temp. Coefficient ––– 0.025 ––– V/°C

RDS(on) Static Drain-to-Source On-Resistance ––– 7.0 9.1 mΩ––– 9.5 12.5

VGS(th) Gate Threshold Voltage 1.0 ––– ––– V

∆VGS(th) Gate Threshold Voltage Coefficient ––– - 4.9 ––– mV/°C

IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA

––– ––– 150

IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

gfs Forward Transconductance 22 ––– ––– S

Qg Total Gate Charge ––– 9.3 14

Qgs1 Pre-Vth Gate-to-Source Charge ––– 2.5 –––

Qgs2 Post-Vth Gate-to-Source Charge ––– 0.8 ––– nC

Qgd Gate-to-Drain Charge ––– 2.9 –––

Qgodr Gate Charge Overdrive ––– 3.1 ––– See Fig. 16

Qsw Switch Charge (Qgs2 + Qgd) ––– 3.7 –––

Qoss Output Charge ––– 6.1 ––– nC

td(on) Turn-On Delay Time ––– 6.3 –––

tr Rise Time ––– 2.7 –––

td(off) Turn-Off Delay Time ––– 9.7 ––– ns

tf Fall Time ––– 7.3 –––

Ciss Input Capacitance ––– 1010 –––Coss Output Capacitance ––– 360 ––– pF

Crss Reverse Transfer Capacitance ––– 110 –––

Avalanche CharacteristicsParameter Units

EAS Single Pulse Avalanche Energy d h mJ

IAR Avalanche Current A

Diode CharacteristicsParameter Min. Typ. Max. Units

IS Continuous Source Current ––– ––– 3.1

(Body Diode) AISM Pulsed Source Current ––– ––– 100

(Body Diode) Ã h

VSD Diode Forward Voltage ––– ––– 1.0 V

trr Reverse Recovery Time ––– 28 42 ns

Qrr Reverse Recovery Charge ––– 23 35 nC

–––

ID = 10A

VGS = 0VVDS = 15V

VGS = 4.5V, ID = 10A e

VGS = 4.5V

Typ.

–––

VDS = VGS, ID = 250µA

Clamped Inductive Load

VDS = 15V, ID = 10A

VDS = 24V, VGS = 0V, TJ = 125°C

TJ = 25°C, IF = 10A, VDD = 20V

di/dt = 100A/µs e

TJ = 25°C, IS = 10A, VGS = 0V e

showing the

integral reverse

p-n junction diode.

MOSFET symbol

VDS = 10V, VGS = 0V

VDD = 15V, VGS = 4.5V e

ID = 10A

VDS = 15V

VGS = 20V

VGS = -20V

VDS = 24V, VGS = 0V

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, ID = 1mA

VGS = 10V, ID = 13A e

Conditions

Max.

44

10

ƒ = 1.0MHz



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Fig 4. Normalized On-ResistanceVs. Temperature

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

2.0 3.0 4.0 5.0 6.0

VGS, Gate-to-Source Voltage (V)

0.1

1.0

10.0

100.0

I D ,

D r a i n - t o - S o u r c e C u r r e n t ( Α )

TJ = 25°C

TJ = 150°C

VDS = 15V

20µs PULSE WIDTH

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

R D S ( o n ) ,

D r a i n - t o - S o u r c e O n R e s i s t a n c e

( N o r m a l i z e d )

ID = 13AVGS = 10V

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

0.1

1

10

100

I D ,

D r a i n - t o - S o u r c e C u r r e n t ( A )

2.5V

20µs PULSE WIDTH

Tj = 25°C

VGSTOP 10V

4.5V3.7V3.5V3.3V3.0V2.7V

BOTTOM 2.5V

0.1 1 10 100


1

10

100

I D ,


2.5V

20µs PULSE WIDTH

Tj = 150°C

VGSTOP 10V

4.5V3.7V3.5V3.3V3.0V2.7V

BOTTOM 2.5V



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Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.

Gate-to-Source VoltageFig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain DiodeForward Voltage

1 10 100


10

100

1000

10000

C ,

C a p a c i t a n c e ( p F )

Coss

Crss

Ciss

VGS = 0V, f = 1 MHZ

Ciss = Cgs + Cgd, Cds SHORTED

Crss = CgdCoss = Cds + Cgd

0 5 10 15 20

QG Total Gate Charge (nC)

0

2

4

6

8

10

12

V G S ,

G a t e - t o - S o u r c e V o l t a g e ( V )

VDS= 24V

VDS= 15V

ID= 10A

0.0 0.5 1.0 1.5

VSD, Source-toDrain Voltage (V)

0.1

1.0

10.0

100.0

I S D ,

R e v e r s e D r a i n C u r r e n t ( A )

TJ = 25°C

TJ = 150°C

VGS = 0V

0.1 1.0 10.0 100.0 1000.0

VDS , Drain-toSource Voltage (V)

0.1

1

10

100

1000

I D ,


Tc = 25°CTj = 150°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREALIMITED BY R DS(on)

100µsec



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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

Fig 9. Maximum Drain Current Vs.

Case Temperature

Fig 10. Threshold Voltage Vs. Temperature

-75 -50 -25 0 25 50 75 100 125 150

TJ , Temperature ( °C )

1.0

1.4

1.8

2.2

2.6

V G S ( t h )

G a t e t h r e s h o l d V o l t a g e ( V )

ID = 250µA

1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100

t1 , Rectangular Pulse Duration (sec)

0.01

0.1

1

10

100

T h e r m a l R e s p o n s e ( Z

t h J A

)

0.20

0.10

D = 0.50

0.020.01

0.05

SINGLE PULSE( THERMAL RESPONSE )

25 50 75 100 125 150

TJ , Junction Temperature (°C)

0

2

4

6

8

10

12

14

I D

, D r a i n C u r r e n t ( A )



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Fig 13b. Unclamped Inductive Waveforms

Fig 13a. Unclamped Inductive Test Circuit

tp

V(BR)DSS

IAS

Fig 13c. Maximum Avalanche EnergyVs. Drain Current

RG

IAS

0.01Ωtp

D.U.T

LVDS

+

-VDD

DRIVER

A

15V

20V

VGS

25 50 75 100 125 150

Starting TJ, Junction Temperature (°C)

0

20

40

60

80

100

E A S ,

S i n g l e P u l s e A v a l a n c h e E n e r g y ( m J ) I D

TOP 4.5A8.0A

BOTTOM 10A

Fig 14a. Switching Time Test Circuit

Fig 14b. Switching Time Waveforms

VGS

VDS

90%

10%

td(on) td(off)tf tr

VGS

Pulse Width < 1µs

Duty Factor < 0.1%

VDD

VDS

LD

D.U.T

Fig 12. On-Resistance Vs. Gate Voltage

2.0 4.0 6.0 8.0 10.0

VGS, Gate-to-Source Voltage (V)

0

5

10

15

20

25

30

R D S

( o n ) , D r a i n - t o - S o u r c e O n R e s i s t a n c e ( m Ω )

TJ = 25°C

TJ = 125°C

ID = 13A



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D.U.T.VDS

IDIG

3mA

VGS

.3µF

50KΩ

.2µF12V

Current Regulator

Same Type as D.U.T.

Current Sampl ing Resis tors

+

-

Fig 16. Gate Charge Test Circuit

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W.Period

di/dt

Diode Recoverydv/dt

Ripple ≤ 5%

Body Diode Forward Drop

Re-AppliedVoltage

ReverseRecoveryCurrent

Body Diode ForwardCurrent

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D =P.W.

Period

* VGS = 5V for Logic Level Devices

*

+

-

+

+

+-

-

-

RGVDD• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T

Fig 17. Gate Charge Waveform

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr



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Control FET

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the Rds(on)

of the

MOSFET, but these conduction losses are only about

one half of the total losses.

Power losses in the control switch Q1 are given

by;

Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput

This can be expanded and approximated by;

Ploss= I rms

2 × Rds(on)( )

+ I ×Qgd

ig

× V in × f ⎛

⎝⎜

⎞

⎠⎟ + I ×

Qgs2

ig× V in × f

⎛

⎝⎜

⎞

⎠⎟

+ Qg × V g × f ( ) + Qoss

2×V in × f

⎛⎝

⎞ ⎠

This simplified loss equation includes the terms Qgs2

and Qoss

which are new to Power MOSFET data sheets.

Qgs2

is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Qgs1

and Qgs2

, can be seen from

Fig 16.

Qgs2

indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to Idmax

at which time the drain voltage be-

gins to change. Minimizing Qgs2

is a critical factor in

reducing switching losses in Q1.

Qoss

is the charge that must be supplied to the out-put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Qoss

is formed by the

parallel combination of the voltage dependant (non-

linear) capacitances Cds

and Cdg

when multiplied by

the power supply input buss voltage.

Synchronous FET

The power loss equation for Q2 is approximatedby;

Ploss

= Pconduction

+ Pdrive

+ Poutput

*

Ploss = I rms

2× Rds(on)( )

+ Qg × V g × f ( ) + Qoss

2×V in × f ⎛⎝⎜ ⎞ ⎠ +

Qrr × V in × f ( )*dissipated primarily in Q1.

For the synchronous MOSFET Q2, Rds(on)

is an im-

portant characteristic; however, once again the im-portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-trol IC so the gate drive losses become much more

significant. Secondly, the output charge Qoss

and re-verse recovery charge Q

rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact theMOSFETs’ susceptibility to Cdv/dt turn on.

The drain of Q2 is connected to the switching nodeof the converter and therefore sees transitions be-

tween ground and Vin. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turnthe MOSFET on, resulting in shoot-through current .

The ratio of Qgd /Q

gs1must be minimized to reduce the

potential for Cdv/dt turn on.

Power MOSFET Selection for Non-Isolated DC/DC Converters

Figure A: Qoss

Characteristic



IRF7821PbF

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SO-8 Package Details

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Dimensions are shown in milimeters (inches)



IRF7821PbF

10 www.irf.com

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information .05/2007

330.00(12.992)MAX.

14.40 ( .566 )

12.40 ( .488 )

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.2. OUTLINE CONFORMS TO EIA-481 & EIA-541.

FEED DIRECTION

TERMINAL NUMBER 1

12.3 ( .484 )

11.7 ( .461 )

8.1 ( .318 )

7.9 ( .312 )

NOTES:1. CONTROLLING DIMENSION : MILLIMETER .2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES ).3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

SO-8 Tape and ReelDimensions are shown in milimeters (inches)

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html

Notes:

Repetitive rating; pulse width limited by

max. junction temperature.

Starting TJ = 25°C, L = 0.87mH

RG = 25Ω, IAS = 10A.

Pulse width ≤ 400µs; duty cycle ≤ 2%.

When mounted on 1 inch square copper board

Rθ is measured at TJ approximately 90°C

Documents

IRF7821PbF