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Investigation on the RRAM Overshoot Current Suppression with Circuit Simulation

SuyunBang" SungjunKiml , Min-HwiKim" Tae-HyeonKiml , Dong KeunLee l , and Byung-GookParkl 'Inter-university Semiconductor Research Center (ISRC) and Departmmt of Electrical Engineering and Computer

Engin_ing, Seoul National University, South Korea Email: bgpark@snu.ac.kr

A.bstract-In this paper, we have simulated how the overshoot current in the Resistive-switching Random Access Memory (RRAM) cell is generated and whether the integrated transistor can effectively suppress the overshoot current that can cause degradation oCeeli endurance. We propose a CMOS-friendly 1 Tt R fahrication process and proceed with circuit simulation using the process parameters. The simulation shows that the internal transistor effectively prevent RRAM overshoot current and be capable of controlling the compliance current.

1. INTRODUCTION

RRAM (Resistive-switching Random Access Memory) has been widely studied as a device to overcome the limitations of existing nonvoiatile memory. Advantages of RRAM include fast switching speed, high scalability, and simple structure [I], [2]. On the other hand, low reliability due to randomness and endurance problems need to be overcome, and so far, many studies have been done [3]-[5].

In this study, we point the overshoot current problem that could cause degradation in RRAM endurance [6]. We have designed an RRAM fabrication process and modeled the simulation circuit based on the parameters used in the designed process. We investigate the effect of internal transistor on overshoot current by comparing I TlR and single RRAM (Fig. I).

II. SIMULATION RESULTS AND DISCUSSION

Transient simulation using 5 V square pulse was performed. When the voltage ramping proceeds 80 % of a rising time, SET transition from I MO to I kG occurs exponentially during 50 ns.

When SET transition occurs in single RRAM cell, voltage across the RRAM cell drops suddeuly and discharging occurs in the cell capacitor and the external parasitic capacitor (Fig. 2a). The current due to this discharging flows instantaneously into the RRAM cell and causes current overshoot. Since the internal currents are offset from each other, the overshoot current above the compliance current cannot be detected by measuring equipment (Fig. 2b).

When SET transition occurs in I TlR structure, voltage across the RRAM cell drops suddeuly. However, in this case, supply voltage of the transistor connected in series with the RRAM is rapidly increased, whicb completely compensates the sudden voltage drop. Consequently the node voltage of external parasitic capacitor maintains (Fig. 3a).

Inside the RRAM, the transistor current and the discharging current of the internal capacitor flow. Externally measured current is the sum of the displacement current due to the external parasitic capacitor and the transistor current. RRAM cell is independent to the displacement current and ouly tra.nsistor current is actually acting on the RRAM cell (Fig. 3b, Fig. 3c).

By adjusting the gate voltage, transistor can act as a very finely controlled internal compliance current source in I TlR structure (Fig. 4).

m. SUMMARY We have simulated circuit models of a I Tl R

structure and a single RRAM structure. The simulation sbows that IT I R structure is effective enough to overcome the overshoot problem of the conventional single RRAM structure with external compliance current source.

ACKNOWLEDGEMENT

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSlP) (2015RIA2AIAOI007307).

REFERENCES

[I]H. Li et al., IEEE Electron Device Letters, vol. 36, no. 11, p. 1142, November 2015.

[2]C.-T. Chou et al., Microelectronics Reliability, vol. 55, no. II, p. 2220, November 2015.

[3]Y.-T. Su et aI., Jpn. J Appl. Phys., Vol. 56, No. I, p. 010303-1, January 2017.

[4] Y. Y. Chen et al., IEEE Transactions on Electron Devices, Vol. 60, No.3, p. 1114, March 2013.

[5]Y.-S. Chen et at., Solid-State Electronics, Vol. 94, p. 1, April 2014.

[6]B. Chen et aI., International Electron Devices Meeting, p. 12.3.1, December 20 II.

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(a) pad metal

Gate N-channel MOSFET

BE(

RRAM cell ---- TE(Drain)

(b)

~ r -=- Cp 1 -L

Ctj

Ct Q Rt W, L, Tax' VT R j C j Ry

(c)

~ JLe r -=- Cp 1 C

R j C j Ry Ct Q Rt

Fig. 1. Schematic top view of (a) proposed RRAM structure and (b) modeled circuit, (c) single RRAM circuit structure.

(a)

5

4

~ 3 Q)

S g 2

0

0

(b)

3.0x10"

2.0x10"

~ 1.0x10" c: ~ 0.0 ::;,

-1.0x10"

-2.0x10" 0

-Vpu1se

- vRe - Yep - VRRAM

SET transition

5 10 15 20 Time [us]

Overshoot current

-IRRAM

- ICi

- Iep

- IRe

Compliance current

5 10 15 20 Time [us]

Fig. 2. Transient characteristics of single RRAM circuit. (a) Voltage changes in critical elements, (b) Current changes in critical elements

(a)

5

4

o o

(b)

8.0x10"

6.0x10"

~ 4.0x10" 'E ~ :::J 2.0x10" t.l

0.0

-2.0x10" o

SET transiti n

5 10 Time [us]

15

-v", .. - Yep - VRRAM

- v"

@V=2V 9

20

Internal overshoot ,.,. (~

.t1.

5 10 Time [us]

EJ ITr ICI @Vg=2V

15 20

(c) Displacement current + Transistor current ~

2.0x10"

1.0x10"

~( a -I Cp - I Tr ~ @Vg=2V c: 0.0 ~ ::;,

-1.0x10" ~

~ -2.0x10" o 5 10 15 20

Time [us]

Fig. 3. Transient characteristics of 1 TIR circuit. (a) Voltage changes in critical elements, (b) Current changes in internal elements, (c) Externally observed current.

2.0x10-4

~ 'E 1.0x10-4 ~ ::::J t)

0.0

o

Vginc O.SV st

5 10 Time [us]

--IR RAM

ease wit h ~p

15 20

Fig. 4. Compliance current control with V g adjusting.

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