Upload
others
View
4
Download
0
Embed Size (px)
Citation preview
Investigation of Monolithic
Transconductor-Capacitor Video-Filters
Frank Dudek
A thesis submitted in partial fullment of the requirements of
Staordshire University for the Degree of Doctor of Philosophy
School of Engineering and Advanced Technology
Staffordshire University
May 1999
3
Abstract
This thesis presents a detailed investigation into the analysis and design of monolithic
transconductor-capacitor video-lters including amplitude and group-delay equalisa-
tion based on the voltage-mode and the current-mode approaches.
Numerous design techniques and CMOS operational transconductance ampliers
(OTAs) are investigated and an ecient voltage-mode design methodology for the
realisation of ladder-based video-lters is identied. The requirement of amplitude
equalisation is addressed and two novel voltage-mode equaliser structures are proposed.
The high-frequency performance of these equalisers is studied in detail and OTA non-
ideal eects are compensated using a new set of design equations as well as independent
electronic tuning of equaliser parameters. To investigate the practical performance of
voltage-mode lters, a fully-balanced monolithic elliptic lter and amplitude equaliser
is implemented using a commercial 0.8m n-well CMOS process.
In addition to voltage-mode based lters, this thesis investigates the current-mode
approach in the design of transconductor-capacitor video-lters and presents two new
digitally programmable biquadratic lter structures. The rst biquad is capable of
producing lowpass and highpass-notch responses without changing the lter topology
and is used in the design of tunable elliptic lters. The second biquad is a universal
lter structure capable of generating all commonly known lter transfer functions. The
problem of group-delay equalisation is also considered and solved using two approaches,
cascaded biquad and ladder-based. The thesis introduces new allpass structures for the
design of cascaded group-delay equalisers and demonstrates the eciency of the ladder-
based approach with reference to a new group-delay equaliser structure. The synthesis
of the group-delay equalisers is achieved using an optimisation algorithm and is veried
using simulation and practical implementation.
4
Acknowledgements
I would like to express my sincere gratitude to my supervisor Dr. Bashir Al-Hashimi
for his guidance, advice and encouragement throughout the course of this research.
Thanks are also due to Dr. Mansour Moniri who has been involved in the supervision
of this project. Special thanks go to Faraday Technology Ltd., and particularly to Dr.
Bernhard Lovatt, who provided the nancial resources and testing facilities for this
project and also for his enthusiasm and support for analogue signal processing.
Thanks are also due to Dr. Tom Ruxton, Dean of the School of Engineering and
Advanced Technology and to Prof. Rolando Carrasco, Associate Dean for Research, for
their continuing support and encouragement during the course of this project. Many
thanks to all members of sta at Staordshire University, who contributed to the
reported work with the provision of technical support and advice, and especially to
Mr. Don Strong for his advice and friendship during the completion of this project. I
am also grateful for the friendship of my research colleagues, with whom I shared in
many discussions interesting aspects of our work.
Finally, I owe much thanks to my family in Germany for the support and encour-
agement they have given me over the years. Also, many thanks are due to my family
in Britain for their care and support, and the warm welcome I have received into my
new family. Most of all, special thanks go to my wonderful wife Nina for her continuing
inspiration, her never ending support and her unconditional love.
Contents
1 Introduction 17
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1.1 Video-Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1.2 Voltage-Mode versus Current-Mode . . . . . . . . . . . . . . . 22
1.2 Structure of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3 General Statement of Originality . . . . . . . . . . . . . . . . . . . . . 26
2 Voltage-Mode OTA-C Filters 28
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2 LC Simulation Design Approach . . . . . . . . . . . . . . . . . . . . . 30
2.2.1 Component Simulation Design Method . . . . . . . . . . . . . . 31
2.2.2 Operational Simulation Design Method . . . . . . . . . . . . . 32
2.2.3 Filter Design Methods Comparison . . . . . . . . . . . . . . . . 34
2.3 OTA-C Sinc(x) Amplitude Equalisers . . . . . . . . . . . . . . . . . . 37
2.3.1 Sinc(x)-Equaliser 1 Conguration . . . . . . . . . . . . . . . . . 38
2.3.2 Sinc(x)-Equaliser 2 Conguration . . . . . . . . . . . . . . . . 49
2.4 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3 Comparative Study of CMOS OTAs 60
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.2 Comparison Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.3 Noise Performance of CMOS transistors . . . . . . . . . . . . . . . . . 64
3.3.1 Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5
CONTENTS 6
3.3.2 1/f noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.4 Single-Ended OTAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.4.1 Simple CMOS OTA . . . . . . . . . . . . . . . . . . . . . . . . 67
3.4.2 Linear CMOS OTA . . . . . . . . . . . . . . . . . . . . . . . . 69
3.4.3 Widely Tunable CMOS OTA . . . . . . . . . . . . . . . . . . . 71
3.5 Multiple-Output OTAs . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.5.1 Simple Fully-Balanced CMOS OTA . . . . . . . . . . . . . . . 75
3.5.2 Linear Fully-Balanced CMOS OTA . . . . . . . . . . . . . . . . 77
3.5.3 Tunable Fully-Balanced CMOS OTA . . . . . . . . . . . . . . . 78
3.5.4 Multiple-Output CMOS OTA . . . . . . . . . . . . . . . . . . . 80
3.6 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4 Voltage-Mode CMOS OTA-C Video-Filter 83
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.2 Video-Filter Design Specications . . . . . . . . . . . . . . . . . . . . 84
4.2.1 Elliptic Filter Design . . . . . . . . . . . . . . . . . . . . . . . . 84
4.2.2 Sinc(x)-Equaliser Design . . . . . . . . . . . . . . . . . . . . . . 89
4.2.3 Video-Filter Design Summary . . . . . . . . . . . . . . . . . . . 91
4.3 Video-Filter Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.3.1 Design Approach . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.3.2 Integrated Circuit Physical Design . . . . . . . . . . . . . . . . 94
4.3.3 Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.3.4 Design Rule Check . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.4 Video-Filter Implementation and Testing . . . . . . . . . . . . . . . . 100
4.4.1 Test Environment . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.4.2 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.5 Integrated Circuit Tuning . . . . . . . . . . . . . . . . . . . . . . . . 106
4.6 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5 Current-Mode OTA-C Filters 110
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
CONTENTS 7
5.2 Current-Mode Building Blocks . . . . . . . . . . . . . . . . . . . . . . 113
5.3 Ladder-Based Elliptic Filter Design . . . . . . . . . . . . . . . . . . . . 115
5.3.1 Ladder Filter Structure Generation . . . . . . . . . . . . . . . . 116
5.4 Tunable Elliptic Filter Design Based on Cascaded Biquads . . . . . . . 118
5.4.1 Tunable Filter Conguration . . . . . . . . . . . . . . . . . . . . 120
5.4.2 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 125
5.4.4 High-Frequency Analysis of the Filter Structure . . . . . . . . . 129
5.5 Universal Biquad for Oversampling Applications . . . . . . . . . . . . 132
5.5.1 Universal Biquad Conguration . . . . . . . . . . . . . . . . . . 134
5.5.2 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.5.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 140
5.6 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6 Current-Mode Group-Delay Equalisers 145
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.2 Cascaded Group-Delay Equalisers . . . . . . . . . . . . . . . . . . . . 147
6.2.1 First-order Equaliser Sections . . . . . . . . . . . . . . . . . . . 148
6.2.2 Second-order Equaliser Sections . . . . . . . . . . . . . . . . . . 150
6.2.3 Cascaded Group-Delay Equaliser Design . . . . . . . . . . . . . 153
6.3 Ladder-Based Group-Delay Equalisers . . . . . . . . . . . . . . . . . . 154
6.3.1 Current-Mode Ladder-Based Group-Delay Equalisers . . . . . . 154
6.3.2 MO-OTA Ladder-Based Group-Delay Equalisers . . . . . . . . 156
6.3.3 Ladder-Based Group-Delay Equaliser Design . . . . . . . . . . 163
6.4 Design Examples and Comparison . . . . . . . . . . . . . . . . . . . . 165
6.4.1 Group-Delay Equaliser Example 1 . . . . . . . . . . . . . . . . 166
6.4.2 Group-Delay Equaliser Example 2 . . . . . . . . . . . . . . . . 167
6.4.3 Group-Delay Equaliser Performance Comparison . . . . . . . . 170
6.5 Discrete Equaliser Implementation . . . . . . . . . . . . . . . . . . . . 174
6.6 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
CONTENTS 8
7 Conclusions and Areas of Further Research 177
7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
7.2 Areas of Further Research . . . . . . . . . . . . . . . . . . . . . . . . . 180
A Sensitivity Comparison 194
A.1 Sensitivity Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
B Optimisation Source Code Listings 200
B.1 Sinc(x)-Equaliser 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
B.2 Sinc(x)-Equaliser 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
B.3 6th-order Ladder-Based Group-Delay Equaliser . . . . . . . . . . . . . . 206
List of Figures
1.1 Block-diagram of a video-lter . . . . . . . . . . . . . . . . . . . . . . . 21
2.1 Conceptual overview of OTA-C lter design methodologies . . . . . . . 29
2.2 5th-order lowpass all-pole ladder lter prototype . . . . . . . . . . . . . 30
2.3 Floating inductor simulation based on OTAs . . . . . . . . . . . . . . . 31
2.4 Direct impedance simulation based 5th-order lowpass ladder lter . . . 32
2.5 FDNR simulation based 5th-order lowpass ladder lter . . . . . . . . . 33
2.6 Voltage-mode ladder lter: (a) signal- ow graph (b) realisation using
dierential input integrators . . . . . . . . . . . . . . . . . . . . . . . . 34
2.7 Operational simulation based 5th-order lowpass ladder lter . . . . . . . 35
2.8 Sinc(x)-equaliser 1 structure . . . . . . . . . . . . . . . . . . . . . . . . 38
2.9 Video-frequency OTA model . . . . . . . . . . . . . . . . . . . . . . . . 42
2.10 Ideal frequency response simulation of equaliser 1 and the equaliser in
[104] when combined with 13.5MHz sinc(x)-distortion . . . . . . . . . 45
2.11 Transistor-level frequency response simulation of equaliser 1 and the
equaliser in [104] when combined with 13.5MHz sinc(x)-distortion . . . 46
2.12 Simulated frequency response of ideal and uncompensated CMOS equaliser
1 when combined with 27MHz D/A converter sinc(x)-distortion . . . . 47
2.13 Simulated frequency response of ideal and compensated CMOS equaliser
1 when combined with 27MHz sinc(x)-distortion using the proposed
equaliser design equations . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.14 Sinc(x)-equaliser 2 structure . . . . . . . . . . . . . . . . . . . . . . . . 50
9
LIST OF FIGURES 10
2.15 Simulated frequency response of ideal and uncompensated equaliser 2
and equaliser 1 when cascaded with 27MHz sinc(x)-distortion . . . . . 54
2.16 Simulated frequency response of ideal and compensated equaliser 2 and
equaliser 1 when cascaded with 27MHz sinc(x)-distortion . . . . . . . . 55
2.17 Sinc(x)-equaliser 2 discrete implementation . . . . . . . . . . . . . . . . 56
2.18 Sinc(x)-equaliser 2 Q-tuning example . . . . . . . . . . . . . . . . . . . 57
2.19 Sinc(x)-equaliser 2 frequency-tuning example . . . . . . . . . . . . . . . 57
3.1 Circuit diagram of (a) CMOS inverter [62] and (b) simple OTA . . . . 68
3.2 Circuit diagram of linear OTA [65] . . . . . . . . . . . . . . . . . . . . 70
3.3 Circuit diagram of widely tunable OTA [89] . . . . . . . . . . . . . . . 72
3.4 Combining two single-ended OTAs into one MO-OTA . . . . . . . . . . 74
3.5 Circuit diagram of high-frequency OTA [58] . . . . . . . . . . . . . . . 76
3.6 Circuit diagram of low-power OTA [41] . . . . . . . . . . . . . . . . . 78
3.7 Circuit diagram of tunable OTA [53] . . . . . . . . . . . . . . . . . . . 79
3.8 Circuit diagram of triple-output OTA [69] . . . . . . . . . . . . . . . . 81
4.1 Video-lter circuit diagram (a) passive prototype, (b) single-ended de-
sign and (c) fully-balanced design . . . . . . . . . . . . . . . . . . . . . 86
4.2 Simulated frequency response of video-lter (a) passive prototype and
(b) fully-balanced active . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.3 Video sinc(x)-equaliser circuit diagram . . . . . . . . . . . . . . . . . . 89
4.4 Simulated frequency response of video sinc(x)-equaliser (a) block-diagram
and (b) transistor-level . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.5 Video-lter transistor-level circuit diagram (a) lter section and (b)
sinc(x)-equaliser section . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.6 Bottom-up design approach . . . . . . . . . . . . . . . . . . . . . . . . 94
4.7 n-channel MOSFET layout (a) cross-section view and (b) top-view . . . 95
4.8 p-channel MOSFET layout (a) cross-section view and (b) top-view . . . 96
4.9 Layout of capacitors as multiples of unit capacitance having capacitor
ratio 4 : 7 : 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
LIST OF FIGURES 11
4.10 Video-lter microchip oorplan . . . . . . . . . . . . . . . . . . . . . . 99
4.11 Chip microphotograph . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.12 Microchip test jig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.13 Sinc(x)-equaliser frequency response . . . . . . . . . . . . . . . . . . . . 104
4.14 Test-jig frequency response . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.15 Simulated Monte Carlo analysis of the video sinc(x)-equaliser . . . . . . 106
4.16 Filter frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.17 Block diagram of an automatic tuning scheme . . . . . . . . . . . . . . 108
5.1 Multiple-output OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.2 (a) Basic MO-OTA building block, (b) Current-mode integrator, (c)
Current buer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3 Current-mode ladder-based lter (a) SFG and (b) Realisation using dif-
ferential output integrators . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.4 Current-mode 5th-order elliptic lowpass ladder lter . . . . . . . . . . . 118
5.5 Proposed current-mode lowpass and highpass notch lter structure . . . 121
5.6 4th-order tunable elliptic lowpass lter . . . . . . . . . . . . . . . . . . 126
5.7 4th-order tunable elliptic highpass lter . . . . . . . . . . . . . . . . . 127
5.8 Discrete implementation of 4th-order elliptic lter with V-I and I-V con-
verters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.9 Measured frequency response of 4th-order elliptic lowpass lter with tun-
able frequency range of 0.65MHz to 1.3MHz . . . . . . . . . . . . . . . 128
5.10 High-frequency model of MO-OTA . . . . . . . . . . . . . . . . . . . . 129
5.11 Simulated frequency response of ideal and CMOS 10MHz 4th-order el-
liptic lowpass lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.12 Proposed universal biquad . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.13 Proposed universal biquad based on MO-OTAs . . . . . . . . . . . . . 136
5.14 Simulated lowpass tunable lter (1-4MHz) . . . . . . . . . . . . . . . . 138
5.15 Simulated bandpass tunable lter (Q = 5) . . . . . . . . . . . . . . . . 139
5.16 Discrete Implementation of universal biquad with V-I and I-V conversion
(C1 = C2 = 10pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
LIST OF FIGURES 12
5.17 Universal biquad lowpass frequency response (1-2MHz) . . . . . . . . . 141
5.18 Universal biquad bandpass frequency response (1-2MHz) . . . . . . . . 142
6.1 1st-order delay equaliser . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.2 1st-order delay equaliser with simulation of R1 . . . . . . . . . . . . . . 149
6.3 Normalised 1st-order group-delay graph . . . . . . . . . . . . . . . . . . 150
6.4 2nd-order delay equaliser . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.5 2nd-order delay equaliser with impedance simulation of R1 and reduction
of OTA device count . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.6 Normalised 2nd-order group-delay graph . . . . . . . . . . . . . . . . . 152
6.7 Current-mode realisation of all-pass functions . . . . . . . . . . . . . . 155
6.8 Signal ow graph representation of ladder-based allpass function . . . . 156
6.9 Current-mode ladder-based group-delay equaliser block diagram . . . . 156
6.10 nth-order current-mode ladder-based group-delay equaliser structure . . 157
6.11 Normalised 6th-order ladder-based group-delay graph . . . . . . . . . . 162
6.12 Optimisation algorithm ow chart . . . . . . . . . . . . . . . . . . . . 165
6.13 6th-order current-mode group delay equaliser . . . . . . . . . . . . . . . 166
6.14 Pole-zero plot of 6th-order ladder-based group-delay equaliser . . . . . . 167
6.15 Simulated group-delay response of the lter, the ladder-based equaliser
and the combined response . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.16 6th-order cascaded biquad group-delay equaliser . . . . . . . . . . . . . 169
6.17 Pole-zero plot of 6th-order cascaded biquad equaliser . . . . . . . . . . . 170
6.18 Group delay response of the lter, the cascaded biquad equaliser and
the combined response . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.19 Simulated step response of the lter only and combined with the ladder-
based equaliser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.20 Simulated step response of the lter only and combined with the cas-
caded biquad equaliser . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.21 Discrete implementation of 6th-order ladder-based group-delay equaliser 174
6.22 Comparison of simulated and measured group-delay of 6th-order ladder-
based group-delay equaliser . . . . . . . . . . . . . . . . . . . . . . . . 175
LIST OF FIGURES 13
A.1 Phase sensitivity of 6th-order cascaded biquad group-delay equaliser . . 198
A.2 Phase sensitivity of 6th-order ladder-based group-delay equaliser . . . . 199
List of Tables
2.1 Comparison of LC lowpass lter simulation design approaches in terms of
component count (n denotes the lter order and mod2(n) is the modulo
remainder of n divided by 2) . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2 !0 and Q sensitivities for the equaliser 1 . . . . . . . . . . . . . . . . . 39
2.3 Normalised component values of equaliser 1 for dierent sampling ratios 41
2.4 Component values of equaliser 1 and equaliser in [104] ( generated using
the design procedure in section 2.3.1.1) . . . . . . . . . . . . . . . . . . 44
2.5 Normalised pole-zero locations for equaliser 1 and the equaliser in [104]
with = 2:7 : 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.6 W/L ratios of the transconductance ampliers (LN = LP = 1.2m) . . 46
2.7 Non-ideal equaliser 1 polynomial coecients for = 2:7 : 1 . . . . . . . 48
2.8 Non-ideal equaliser 1 pole-zero locations for = 2:7 : 1 . . . . . . . . . 48
2.9 Ideal and compensated equaliser 1 component values for = 2:7 : 1 . . 48
2.10 Ideal and compensated equaliser 1 W/L ratios (LN = LP = 1.2m) . . 48
2.11 !0 and Q sensitivities for equaliser 2 . . . . . . . . . . . . . . . . . . . 52
2.12 Normalised component values of equaliser 2 (changing Qz via gm5) . . . 53
2.13 Ideal and compensated component values for equaliser 2 and equaliser 1 54
3.1 CMOS process parameters for the AMS 0.8m double-metal double-poly
n-well process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.2 Performance parameters of simple OTA [62] with VG1 = VG4 = 4V . . 69
3.3 Performance parameters of linear OTA [65] with Ib = 100A . . . . . . 71
3.4 Performance parameters of widely tunable OTA [89] with Vb = -1V . . 73
14
LIST OF TABLES 15
3.5 Performance parameters of high-frequency OTA [58] . . . . . . . . . . 76
3.6 Performance parameters of low-power OTA [41] with Vb1 = Vb2 = 4V 78
3.7 Performance parameters of tunable OTA [53] with Vb = 4V . . . . . . . 80
3.8 Performance parameters of triple-output OTA [69] with Vb = 4V . . . 81
4.1 Video-lter specications [98] . . . . . . . . . . . . . . . . . . . . . . . 85
4.2 Video-lter transistor dimensions . . . . . . . . . . . . . . . . . . . . . 87
4.3 Video sinc(x)-equaliser transistor dimensions . . . . . . . . . . . . . . . 90
4.4 Video-lter simulation results summary . . . . . . . . . . . . . . . . . . 91
4.5 Video-lter capacitor areas . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.6 Video sinc(x)-equaliser capacitor areas . . . . . . . . . . . . . . . . . . 97
4.7 AMS 0.8m n-well CMOS process design rules . . . . . . . . . . . . . . 101
5.1 Dierent ltering functions of the proposed lter structure . . . . . . . 122
5.2 Filter design equations in terms of elliptic lter polynomial coecients 122
5.3 4th-order elliptic polynomial coecients (Ap = 26dB, 1dB passband ripple)124
5.4 Transistor dimensions of the MO-OTA based on 0.8m CMOS process 125
5.5 Transconductance values of 4th-order tunable elliptic lowpass lter, as-
suming all capacitors = 10pF . . . . . . . . . . . . . . . . . . . . . . . 126
5.6 Pole-zero positions of ideal and CMOS 10MHz 4th-order elliptic lowpass
lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.7 Transfer functions available from the universal biquad . . . . . . . . . . 136
5.8 Transistor dimensions of the MO-OTA based on 0.8m CMOS process 138
6.1 Optimised component values for 6th-order ladder-based group-delay equaliser166
6.2 6th-order cascaded biquad group-delay equaliser !0 and Q parameters . 168
6.3 Optimised component values for 6th-order cascaded biquad group-delay
equaliser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.4 Component count comparison of cascaded biquad and ladder-based group
delay equalisers (where n is the equaliser order and mod2(n) is the mod-
ulo remainder of n divided by 2) . . . . . . . . . . . . . . . . . . . . . . 172
Abbreviations
A/D Analogue-to-Digital
ASIC Application Specic Integrated Circuit
BiCMOS Bipolar and Complementary Metal Oxide Semiconductor
BW Bandwidth
CAD Computer Aided Design
CCIR Comite Consultatif International en Radiodiusion
CMOS Complementary Metal Oxide Semiconductor
D/A Digital-to-Analogue
DC Direct Current
DIL Dual In-Line
DRC Design Rule Check
FDNR Frequency Dependent Negative Resistor
I-V Current-to-Voltage
ITU International Telecommunication Union
LVS Layout Versus Schematics
MESFET MEtal on Semiconductor Field Eect Transistor
MO-OTA Multiple-Output Operational Transconductance Amplier
MOSFET Metal Oxide Semiconductor Field Eect Transistor
OTA Operational Transconductance Amplier
PD Power Dissipation
PLL Phase-Locked Loop
SFG Signal Flow Graph
SPICE Simulation Program with Integrated Circuit Emphasis
THD Total Harmonic Distortion
TR Tuning Range
VCO Voltage Controlled Oscillator
V-I Voltage-to-Current
VLSI Very Large Scale Integration
Chapter 1
Introduction
1.1 Introduction
With the recent advancements in integrated circuit design it has been forecast that
there soon would be little demand for analogue circuits and systems, because the
world would rely entirely on digital realisations. However, although many applications
have indeed replaced much analogue circuitry with their digital counterparts (such as
digital audio and video), the very nature of VLSI (Very Large Scale Integration) digital
system design renders good analogue circuits increasingly important and three reasons
can be identied, why the need for such design expertise will remain strong.
Firstly, the natural world is analogue. Thus analogue systems are always needed
in information acquisition systems in order to prepare analogue information
for conversion to digital format. For example, when digitising physical sig-
nals, analogue-to-digital and digital-to-analogue converters are necessary, to-
gether with the associated antialiasing and reconstruction lters.
Secondly, many important applications are best addressed by mixed analogue
/ digital VLSI systems. That is, analogue and digital VLSI circuits co-exist
on the same semiconductor die. Although the analogue components may often
constitute only a small portion of the total chip area, they are the limiting factor
on overall system performance and the most dicult part of the IC to design.
CHAPTER 1. INTRODUCTION 18
And thirdly, on a very physical design level, demanding digital systems exhibit
many analogue circuit qualities. Thus, a good understanding of analogue de-
sign techniques is a valuable asset in the design and debugging of digital high-
performance systems.
Among the analogue components in an integrated signal-processing system, continuous-
time lter functions are the most important, especially in applications where the lters
interface with the outside world, i.e. where the input and output signals take on
continuous values as a function of the continuous variable time. Although digital or
sampled-data lter implementations oer the advantage of being able to attain very
high accuracy and little parameter drift, they entail a number of peripheral problems
connected with sample-and-hold, switching, anti-aliasing and reconstruction circuitry.
For example, the clock feedthrough problem in switched-capacitor lters escalates at
high speeds [96] and digital lters may exhibit excessive power supply requirements.
For the past 15 years, the operational transconductance amplier (OTA) has re-
ceived much attention as the active device in continuous-time lter design [27, 28],
especially for high frequency applications. Over the years, various terminologies have
been suggested to dene the design of continuous-time lters based on OTAs. The
most widely accepted term is transconductor-capacitor approach, since the only active
devices in continuous-time lters are transconductors and capacitors. More speci-
cally, the transconductors are OTAs and the lter design method is then referred to
as OTA-C approach. Sometimes, the same method is termed gm-C approach, because
it is the gm (i.e. the transconductance parameter) of the OTA which denes the lter
operation.
Today, the transconductor-capacitor approach has been identied as the preferred
design approach for high-frequency continuous-time applications. Its main advantages
are superior high-frequency performance and structural simplicity when compared to
MOSFET-C topologies [95] (consisting of op-amps and MOSFETs operating in the
linear region) and CCII topologies [82] (consisting of second-generation current con-
veyors) for two reasons: Firstly, OTAs possess superior high-frequency performance
due to their single-stage designs and secondly, the OTA-C approach does not rely on
CHAPTER 1. INTRODUCTION 19
the OTAs capability of driving resistive loads, unlike op-amps in MOSFET-C struc-
tures and current conveyors in CCII structures. Their design can hence be simpler,
which also leads to increased high-frequency performance and reduces silicon area re-
quirements. For these reasons, the transconductor-capacitor approach will be adopted
throughout this thesis for the design of analogue video-lters.
A number of attempts at integrating continuous-time lters based on OTAs have
been reported [16, 41, 42, 43, 44, 48, 63, 73, 102, 107], some with emphasis on very
high-frequency operation [85, 86, 103], some with focus on low voltage operation [33,
41, 72, 73], others designed for specic applications such as disk drive read channels
[53, 99].
Despite their obvious advantages at high frequencies however, one of the main limi-
tations of continuous-time lters is their small signal-to-noise ratio, caused by the non-
linearities of the voltage-to-current converter. In order to maximise the dynamic range
of the OTA and to minimise OTA non-linearities, fully dierential circuit structures
have been preferred [42, 44, 58, 85]. Also, linearisation methods have been employed
in OTA-C lters to reduce OTA non-linearities [42, 44, 64, 83].
Semiconductor technology has always been a limiting factor in integrated analogue
circuit design. This has been caused by the fact that most technologies are optimised
for digital performance, which prevents the manufacture of certain passive components
such as good quality capacitors. Today, there are four viable integrated technologies
for analogue circuit design. These are bipolar, CMOS, GaAs and BiCMOS processes.
A very distinctive design criterion for these technologies is system bandwidth. GaAs
(Gallium Arsenide), a III-V semiconductor material providing MESFETs (MEtal on
Semiconductor Field Eect Transistors), is most commonly used in the Gigahertz re-
gion, where it outperforms all other semiconductor technologies. Bipolar and CMOS
(Complementary Metal Oxide Semiconductor) implementations overlap in their oper-
ating frequencies which cover the kilohertz and megahertz regions. Bipolar circuits,
however, can operate at slightly higher frequencies than CMOS circuits. This makes
a strong case for BiCMOS processes, which combine the best aspects of both bipolar
and CMOS technologies. A second important design criterion for the realisation of
CHAPTER 1. INTRODUCTION 20
fully integrated systems, is process versatility. CMOS technology has become domi-
nant in analogue integrated circuit design primarily owing to the fact that it dissipates
only low power, supports the design of high-quality analogue switches and allows the
realisation of comparatively large capacitors, whose values can be well matched. In
contrast, capacitors in bipolar technology can only be realised as junction capacitors
which, in standard processes, are not of high quality [94]. Furthermore, CMOS pro-
cesses have become widely available because of their popularity in digital circuit design.
For these reasons, and the low cost manufacturing aspect that is associated with wide
availability, this thesis focuses on CMOS implementations and employs a commercial
sub-micron CMOS process provided by the AMS foundry [1] for the circuit realisations
throughout this thesis.
1.1.1 Video-Filters
In general, an electrical lter is a two-port network designed to process the magnitude
and/or phase characteristics of a source signal in a pre-dened way. The output of a
lter is hence a selected subset of the input. In electrical ltering the objective is to
perform frequency-selective transmission. Elementary signal theory states [76], that
any periodic wave of period 2=! can be represented by its Fourier-series expansion,
i.e. as the sum of an innite number of cosine and sine-waves with frequencies k!
and varying magnitudes ak and bk. When a harmonically rich signal is applied to a
lter, the ltering process will serve to alter the magnitude of the coecients ak and
bk, for example some coecients may be greatly attenuated, thus dening a stopband.
Others may be transmitted unchanged, thus representing a lter passband. There are
many well dened techniques which help the designer to nd the appropriate transfer
function that a lter must realise to satisfy the required behaviour [78, 108, 76]. Once
the lter transfer function is obtained, implementation methods must be found which
are compatible with the technology selected for the design of the complete system.
An electrical lter for use with video applications must exhibit very stringent trans-
mission characteristics, such as low passband ripple, sharp transition band, high stop-
band attenuation and linear phase or at group delay response. To achieve these
CHAPTER 1. INTRODUCTION 21
characteristics, three separate blocks of circuitry are needed, as shown in Fig.1.1.
Amplitudeequaliser sectionFilter section
AnalogueInput
AnalogueOutput
Group delayequaliser section
Figure 1.1: Block-diagram of a video-lter
A typical application of the video-lter in Fig.1.1 is the use as antialiasing or recon-
struction lter for digital video systems. If the lter is used for antialiasing in front of
an A/D-converter, it has lowpass response in order to limit the spectrum of the input
signal to less than half the sampling frequency of the A/D-converter. If the lter is used
for signal reconstruction after the D/A-converter, it also has lowpass response in order
to remove the higher harmonics, which were added in the sampling process. Generally,
a high-order lter is required to meet the stringent attenuation characteristics. In or-
der to achieve narrow transition band, the most popular lter response is the Cauer
response based on the solution of elliptic polynomials. Because Cauer lters generally
exhibit a non-linear phase response, a group-delay equaliser will be used to provide
a at group-delay response. In order to meet the passband ripple specications, an
amplitude equaliser is required, especially if the amplitude distortion originates from a
D/A-converter which is being used with the reconstruction lter. D/A-converters are
commonly are realised as zero-order holds and generate a characteristic staircase shape
waveform at their output. In the frequency domain, the holding action of the D/A-
converter introduces a distinctive distortion into the signal which is being converted.
The frequency response of this distortion follows the mathematical sinc(x)-function
and is especially signicant, if the ratio between D/A-converter sampling frequency
and the lter passband edge frequency is low. For example, the sinc(x)-function falls
to about -4dB at half the sampling frequency (FS=2) giving an average error of about
36%. In this case, the amplitude equaliser is referred to as sinc(x)-equaliser.
CHAPTER 1. INTRODUCTION 22
1.1.2 Voltage-Mode versus Current-Mode
The design of analogue integrated lters based on the transconductor-capacitor ap-
proach has traditionally been viewed as a voltage dominated form of signal processing
[12, 27, 29, 76, 90, 91]. This means, circuit intermediate signals and overall lter
transfer functions have usually been expressed as voltage ratios which neglects their
capability of processing current signals. This was despite the fact that their respective
implementations use a current-mode device, i.e. the OTA, which provides current-
output as a linear function of a dierential input voltage. In contrast, current-mode
operation implies that all signals in the circuit are current signals and the transfer
function is expressed as a current ratio. Over the last ve years, current-mode sig-
nal processing has emerged as an important class of analogue circuitry, for example
in biquadratic all-pole lters [2, 3, 70], elliptic lters [21, 56, 69] and group-delay
equalisers [4]. Recent advantages in integrated circuit technologies have meant, that
state-of-the-art analogue IC design is now able to fully exploit the advantages oered
by current-mode analogue signal processing. One of the primary motivations behind
the increased importance of current-mode signal processing has been the shrinking fea-
ture size of digital CMOS devices, which implies a degradation of their voltage-mode
performance for analogue circuits because it necessitates a reduction of supply volt-
ages. 3.3V have now become the accepted industrial standard and because processes
are optimised for digital performance, using current as the signal variable has oered
signicant advantages for the analogue designer such as the existence of devices with
'virtual ground' low impedance nodes or the reduction in circuit complexity due to sim-
plied signal summing and scaling using circuit nodes and current mirrors. In addition
to OTA voltage-mode operation, this thesis will also focus on the newly developed
current-mode transconductor-capacitor technique.
1.2 Structure of the Thesis
The primary aim of this thesis is the detailed investigation into the analysis and de-
sign of transconductor-capacitor based structures for analogue video-lters including
CHAPTER 1. INTRODUCTION 23
group-delay and amplitude equalisation. While the design of lter sections has been
extensively described in the literature, OTA-C structures for amplitude and group-
delay equalisation and their design have received only very little attention in the past.
The work contained in this thesis focuses on the analysis, design and implementation
of complete video-lters (see Fig.1.1.1), in both voltage-mode and current-mode.
Chapter 2 will introduce methods for the realisation of voltage-mode high-performance
video lters based on the OTA-C approach. It will identify a suitable lter design
methodology to implement a high-performance video-lter on a silicon chip. While
the realisation of voltage-mode lters is well documented (examples are [50, 53, 73]),
the implementation of sinc(x)-equalisers has received only very little attention in the
past [77]. Section 2.3 will present two new ecient OTA-C amplitude equalisers for
correcting sinc(x)-distortion of video D/A converters [18, 20]. The equaliser synthesis
process will be based on numerical optimisation with a curve-matching algorithm.
In addition, this chapter will include detailed analysis and minimisation of OTA
non-ideal eects in the performance of one of these equalisers operating at video-
frequencies [19]. To compensate these eects, a set of high-frequency design equations
is derived, which facilitates the equaliser synthesis process.
To facilitate video-frequency equaliser design, section 2.3.2 will focus on the capa-
bilities of a biquadratic tunable OTA-C amplitude equaliser structure for correcting
sinc(x)-distortion of video D/A converters [20]. It realises independent electronic con-
trol of !0 and Q by means of gm tuning, allowing simple compensation for active device
non-ideal eects. Simulation and measured results will demonstrate the tunability and
superior equaliser performance when compared with other structures.
In chapter 3, a comprehensive selection of CMOS OTA transistor designs that have
been reported in the literature will be investigated in detail and a suitable design will be
identied for the experimental implementation of an analogue integrated lter based on
the methods introduced in chapter 2. A comparison of performance criteria including
bandwidth, power consumption, harmonic distortion and tuning range will be applied
to single-ended and multiple-output OTAs.
Chapter 4 will report on the design and implementation of a voltage-mode analogue
CHAPTER 1. INTRODUCTION 24
system integrated in 0.8m CMOS technology. The design of a 5th-order elliptic lter
for oversampling digital video based on the operational simulation of a passive ladder
lter will be demonstrated, together with a biquadratic sinc(x)-equaliser based on the
OTA-C structure reported in section 2.3.2. In order to increase the dynamic range of
the system, the lter will be based on fully-balanced topology. After extensive sim-
ulations, the design ow of this full custom microchip will include considerations for
oor-planning of individual system components and the denition of the layout mask
geometries. This chapter will conclude the work on voltage-mode circuits with the test-
ing of the manufactured chip prototype and a discussion of its measured performance.
In chapter 5, methods and structures for the realisation of current-mode lters based
on the OTA-C approach will be presented. Two design methodologies will be investi-
gated, ladder-based topologies and cascaded biquad structures. It will be shown, that
one of the drawbacks of ladder-based elliptic lter design, the lack of tuneability, can be
overcome by the realisation of elliptic lters based on coupled or cascaded biquads. A
novel function-programmable current-mode lter structure based on multiple-output
OTAs will be presented, capable of realising cascaded elliptic responses. Further-
more, a new universal current-mode biquad will be introduced which uses digitally
programmable zero positions to realise any transfer function.
Furthermore, section 5.4 will introduce a methodology to obtain tunable elliptic fre-
quency response characteristics by cascading lowpass or highpass-notch biquads. This
is achieved by introducing a novel programmable current-mode lter structure capable
of generating lowpass-notch and highpass-notch responses without changing the lter
topology by using a symmetrical current switching technique controlled by a 2-bit digi-
tal word. Simulation and measured results will be presented, including an investigation
into multiple-output OTA high-frequency non-ideal eects on the performance of this
lter structure.
Because the focus in current-mode lter design in many modern mixed-signal appli-
cations has changed from high-order circuits with narrow transition bands to simpler
and more versatile all-pole structures used as oversampling lters at the front end
of data converters, section 5.5 will develop and investigate a universal digitally pro-
CHAPTER 1. INTRODUCTION 25
grammable biquadratic current-mode lter structure, capable of realising various lter
responses as well as signal conditioning functions such as allpass response and sinc(x)-
equalisation capability. This novel current-mode biquad based only on multiple-output
OTAs and grounded capacitors has the major benet of achieving maximum exibility
without the need to modify the circuit topology.
This work on current-mode structures will be extended in chapter 6, which is ded-
icated to the current-mode realisation of group-delay equaliser structures. Two design
methodologies will be investigated, ladder-based topologies and cascaded biquad struc-
tures. In the cascade approach, 1st and 2nd-order allpass sections are combined to yield
a high-order group-delay function. Section 6.2 will introduce a 1st-order current-mode
allpass section and present its design equations. Furthermore, it will investigate the
eectiveness of the universal biquad introduced in section 5.5 for the compensation of
delay distortion and propose a specic 2nd-order current-mode allpass section based on
multiple-output OTAs and grounded capacitors, including techniques for minimisation
of the equaliser active device count. In addition, a design strategy for high-order group-
delay functions will be presented and the numerical optimisation of circuit parameters
will be discussed.
In the ladder-based approach, the shapes of high-order group-delay functions are
approximated directly without the typical high-Q peaks of cascaded realisations, which
results in superior correction accuracy. Section 6.3 will introduce a novel current-mode
ladder-based group delay equaliser structure. The ladder-based group-delay equaliser
synthesis process will be based on optimisation using a curve-matching algorithm. To
complete the discussion, two 6th-order group-delay equalisers will be designed in section
6.4, in order to compare the performance of the two design methodologies in terms of
component count, component spread and sensitivity.
Finally, in chapter 7 the main conclusions of the presented investigation are sum-
marised based on the results obtained in the previous chapters and a number of chal-
lenging areas for further research are suggested.
CHAPTER 1. INTRODUCTION 26
1.3 General Statement of Originality
The contribution of the work described in this thesis can be summarised as follows:
1. The problem of correcting D/A converter sinc(x)-distortion in video-frequency
analogue systems has been addressed and solved by the introduction and CMOS
realisation of a new ecient biquadratic amplitude equaliser structure [18].
2. Compensation of OTA non-ideal eects in the performance of this sinc(x)-equaliser
has been achieved by deriving a set of high-frequency design equations expressed
in terms of the active devices input capacitance, output resistance and the poly-
nomial coecients used to correct the sinc(x)-distortion. This analysis and min-
imisation of the active devices non-ideal characteristics greatly facilitates the
equaliser synthesis process [19].
3. Alternatively, compensation of OTA high-frequency non-ideal characteristics can
be achieved by using a novel tunable biquadratic OTA-C amplitude equaliser
structure. The structure realises independent electronic control of !0 and Q by
means of gm tuning, allowing simple compensation for active device non-ideal
eects [20].
4. The advantages of current-mode signal processing using multiple-output transcon-
ductance ampliers have been demonstrated with the development of a new
current-mode universal biquad conguration, capable of generating various lter
functions using digitally programmable zeros. The biquad zeros may be indepen-
dently programmed using four switches, hence removing the need to change the
biquad topology [3].
5. In order to combine the narrow transition band properties of elliptic lters with
the tunability advantage of biquad lter topologies, a programmable biquadratic
current-mode elliptic lter structure based on multiple-outputOTAs and grounded
capacitors is described and implemented [21]. The lter is capable of producing
lowpass- and highpass notch responses without changing the lter structure. This
CHAPTER 1. INTRODUCTION 27
is achieved using a symmetrical current switching technique based on two switches
controlled by a 2-bit digital word.
6. The necessity to provide constant group-delay in video lters with current as
the signal variable has resulted in two new current-mode allpass sections based
on multiple-output OTAs and grounded capacitors [4]. The presented design
method also includes techniques to minimise the equaliser active device count
and to eciently simulate grounded resistors.
7. In order to exploit the advantages of ladder topologies over biquadratic structures
including smaller component sensitivities, a methodology to design current-mode
ladder-based group-delay equalisers has been described based on only multiple-
output OTAs and grounded capacitors. Using this direct equalisation method,
the group delay function is curve-matched over the whole frequency range and
not realised as a product of high-Q second-order sections, which leads to superior
correction accuracy [22].
Chapter 2
Voltage-Mode OTA-C Filters
2.1 Introduction
Chapter 1 has outlined, that the operational transconductance amplier-capacitor ap-
proach (OTA-C approach) has been established as the preferred method in the design
of continuous-time integrated lters, primarily because of its inherent structural sim-
plicity, the potential to operate at high frequencies and its compatibility with standard
CMOS processes [27, 28, 48, 73].
Based on extensive investigations of OTA-C design methodologies suitable for mono-
lithic implementation [75, 76, 90], which have traditionally been regarded as voltage-
mode signal processing, this chapter will present two techniques to derive realisations
of voltage-mode high-order lter transfer functions.
The rst technique is the cascade approach, where high-order functions are realised
as products of 1st and 2nd-order lter sections. Each biquadratic function is then
realised in a separate block using an appropriate OTA based biquad. One of the main
advantages of cascade lters is their ease of tunability, since each biquad realises only
one pole pair. The major drawback of this technique is the relatively high sensitivity
to passive component tolerances, especially in high-order lters (order n > 8). For this
reason, the cascade approach is not preferred to realise monolithic high-performance
high-order analogue lters.
The second technique is the LC simulation approach, which is based on the simula-
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 29
tion of passive LC ladder network prototypes. The low sensitivity properties of equally
terminated passive ladder lters [61] provide a strong motivation for developing inte-
gration techniques based on them. Two design methods based on LC simulation have
been established and both will be discussed and compared in the following sections:
The conceptually simplest LC simulation approach is component simulation, in
which the structure of a prototype inductor is replaced either by active simulation
(direct impedance simulation) or, after Bruton transformation of the prototype,
with frequency-dependent negative resistor (FDNR) simulation.
A more ecient approach to simulate LC ladders is the operational simulation,
which simulates the signal- ow-graph (SFG) behaviour of the lter.
To give a comprehensive overview of OTA-C lter design approaches, these cate-
gories are summarised in Fig.2.1.
componentsimulation
operationalsimulation
simulatedFDNR
cascade LC simulation
direct impedancesimulation
OTA-C filterdesign appraoches
Figure 2.1: Conceptual overview of OTA-C lter design methodologies
This chapter aims to investigate the design of OTA-C high-performance analogue
lters based on the LC simulation approach. Section 2.2 will rst discuss the LC
simulation methods for the realisation of high-order voltage-mode OTA-C lters, which
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 30
are well documented (examples are [50, 53, 73]). Furthermore, it will compare the
eciency of these design methods with respect to OTA and capacitor component count.
In addition, this chapter will introduce two new OTA-C amplitude equalisers for
correcting sinc(x)-distortion of video D/A converters. Their design and high-frequency
performance will be analysed and compared with respect to their sinc(x)-correction
accuracy.
2.2 LC Simulation Design Approach
The following methods for designing monolithic voltage-mode OTA-C ladder lters are
based on the simulation of passive LC ladder prototypes. In particular, LC simulation
benets from the direct correspondence between active lter parameters and passive
prototype components, oering three distinct design advantages:
Firstly, the sensitivity to changes in inductor and capacitor values at the frequen-
cies of minimum loss is low throughout the passband in LC lters [29]. Active LC
simulations will retain the low sensitivity properties of their passive prototypes [44].
Secondly, a circuit capacitor is generally present at all circuit nodes in the LC ladder
prototype which permits the pre-absorption of parasitic implementation eects [15].
And thirdly, the lter design parameters can be obtained directly from standard tables
for passive LC lters [108].
The eciency of the presented design methods will be compared in section 2.2.3 with
reference to a 5th-order lowpass all-pole ladder lter prototype in minimum-inductor
conguration [108] as a common example (see Fig.2.2).
Vin C1
V1L2
I2
C3
V3L4
I4
RLC5
V5
I5Iin
RS
Figure 2.2: 5th-order lowpass all-pole ladder lter prototype
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 31
2.2.1 Component Simulation Design Method
This design method involves replacing any inductor in the LC prototype with an active
equivalent circuit. This is achieved either with OTA-C simulations of inductors (direct
impedance simulation) or with OTA-C simulations of FDNRs after Bruton transfor-
mation of the lter. The remainder of the prototype topology remains unchanged with
this method.
2.2.1.1 Direct Impedance Simulation
Starting from a passive ladder network (e.g. the ladder lter in Fig.2.2), the rst step
is to simulate every inductor with a OTA-C combination. Fig.2.3 shows a OTA-C
implementation of a oating inductor based on an integrator (gm1), where the input
current Iin is proportional to the integrated voltage.
Figure 2.3: Floating inductor simulation based on OTAs
Assuming gm1 = gm2 = gm3 = gm , it can easily be shown [76], that this circuit has
an electronically variable inductance (via gm) of:
L =C
g2m(2.1)
Now consider the direct impedance simulation of the 5th-order lowpass all-pole lad-
der prototype in Fig.2.2 based on replacing the two oating inductors with OTA-C
simulations as shown in Fig.2.4. Note that the termination resistors are also imple-
mented using OTA devices. The realisation of grounded and oating resistors with
OTAs is well documented [27, 76, 91].
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 32
C5C3
C1
gm
gm gm
gm
gm gm
C1
gm
gm gm
C1
Vin Vout
Figure 2.4: Direct impedance simulation based 5th-order lowpass ladder lter
2.2.1.2 Simulated FDNR
A dierent method to simulate inductors in LC ladder networks is based on the Bru-
ton transformation and the use of frequency-dependent negative resistors (FDNRs).
This approach is especially useful for LC prototypes which have only grounded capac-
itors. Therefore, the passive prototype lter of Fig.2.2 will be utilised in its minimum-
capacitor complementary conguration [108]. Bruton transformation [11] subjects the
passive prototype lter to special impedance scaling by a factor 1=(j!) (! is the inde-
pendent frequency variable). Note, that impedance scaling does not alter the dimen-
sionless transfer function of the circuit. Through this transformation, resistors become
capacitors, inductors become resistors and capacitors are transformed into FDNRs, as
indicated in Eqn.2.2.
ZC(j!) =1
j!C! ZC(j!) = ZC(j!)
1
j!=
1
!2C(2.2)
Two complete grounded FDNR circuits (D2 and D4) based on only OTAs and
grounded capacitors are shown in Fig.2.5, where they are inserted into the 5th-order
all-pole lowpass ladder prototype after Bruton transformation. Because the FDNR
element is inherently grounded, this method is particularly useful for prototypes with
only grounded capacitors.
2.2.2 Operational Simulation Design Method
A more ecient approach to simulate LC ladders is operational simulation. It is based
on voltage-mode signal- ow-graph (SFG) representations of the state variable equa-
tions to simulate the behaviour of the lter network. In an LC ladder prototype, the
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 33
R3R1 R5
R2 R4
CS CL
D2
C2
C1
gm
gmgm
gm
gm
D4
C2
C1
gm
gm gm
gm
gm
VoutVin
Figure 2.5: FDNR simulation based 5th-order lowpass ladder lter
circuit branches consist of series and parallel combinations of inductors, capacitors and
possibly resistors. Therefore, the circuit driving-point function is mathematically in
the form of a continuous fraction [91]. For the 5th-order all-pole lowpass lter example
of Fig.2.2, the state variable equations are:
V1 =1
sC1(I2 Iin)
I2 =1
sL2(V1 V3)
V3 =1
sC3(I4 I2)
I4 =1
sL4(V5 V3)
V5 =1
sC5(I5 I4) (2.3)
The state variable equations can be translated into a SFG description of the ladder
lter as shown in Fig.2.6a. The branch weights in the SFG are either +1 or -1 unity
branches or are of the form 1=sTi, where Ti is value of an inductor or capacitor in the
LC network and s is the complex frequency variable.
The active circuit will hence consist of integrators of the form 1=sTi, which simulate
the operation of inductors and capacitors and summers, which simulate the Kirchho
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 34
V1 V3 V5
I2 I4
sC1
1sL2
1sC3
1sL2
1sC5
1
+1-1 +1-1 +1-1
+1 -1 +1 -1 +1 -1
-
1/sT1 1/sT2 1/sT3 1/sT4 1/sT5
+
-+
-+
-+
-+
∫ ∫ ∫ ∫ ∫
(a)
(b)
Figure 2.6: Voltage-mode ladder lter: (a) signal- ow graph (b) realisation using dif-
ferential input integrators
loop and node equations of the LC ladder (Eqn.2.3). In order to realise a voltage-
mode implementation based on single-output OTAs, the +1 and -1 branches, which
occur in pairs, are combined at the at the inputs of the 1=s type integrators, yielding
a realisation in terms of dierential input devices as shown in Fig.2.6b.
Combining the appropriate integrators with simulations of termination resistors
results in the OTA-C implementation of the 5th-order all-pole lowpass ladder in Fig.2.7.
2.2.3 Filter Design Methods Comparison
In integrated active lter design, minimumcomponent count is a major design criterion,
since additional components will lead to increased power consumption and silicon area
requirements, which can be serious limits on the lter performance. Table 2.1 compares
the three LC simulation lter design methods with respect to design eciency by
providing general formulae for the OTA and capacitor component count.
Note, that Table 2.1 is still valid for elliptic lowpass lter design, as will be discussed
in chapter 4. In this case, the number of capacitors for each approach will increase by
nmod2(n)2 .
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 35
gm
C1
gm
gm gm
gm gm gm
CL2
C3
CL4
C5
V1 V3
VL2 VL4
VoutVin
VL1
Figure 2.7: Operational simulation based 5th-order lowpass ladder lter
Direct impedance Simulated Operational
simulation FDNR simulation
No. of capacitors n 2 + 2n mod2(n)
2 n
No. of OTAs 3 + 3nmod2(n)
2 5n mod2(n)
2 n+2
Table 2.1: Comparison of LC lowpass lter simulation design approaches in terms of
component count (n denotes the lter order and mod2(n) is the modulo remainder of
n divided by 2)
For example, the implementation of a 3rd-order lter requires 3 capacitors and 6
OTAs using direct impedance simulation and 4 capacitors and 5 OTAs using FDNR
simulation, but only 3 capacitors and 5 OTAs using operational simulation. This saving
on components increases with the lter order. A 7th-order lter requires 7 capacitors
and 12 OTAs using direct impedance simulation, 8 capacitors and 15 OTAs using
FDNR simulation but only 7 capacitors and 9 OTAs using operational simulation.
These examples clearly show, that the simulated FDNR approach is already the
least component ecient lter design method, even though the above expressions do
not account for resistors introduced by Bruton transformation or the active simulation
of these resistors with OTAs.
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 36
In addition to its component count ineciency, the simulated FDNR design method
presents a further practical diculty: Since the entire prototype ladder structure must
be transformed, the active circuit no longer contains source and load resistors. If these
components are pre-described and have to be maintained in the active implementation,
buers have to be included in the design at the input and output which clearly increase
the circuit complexity. In addition, the circuit now contains a number of resistors which
are dicult to implement accurately and area-eciently on silicon. Hence the FDNR
simulation approach is not favoured for the realisation of monolithic high-performance
lters.
Table 2.1 clearly demonstrates that the operational simulation is the most ecient
design method to simulate the behaviour of passive LC ladder prototypes. In addition
to this comparison, it has been shown in [76] that the operational simulation approach
is canonical, hence requiring the least number of devices for any given lter order.
This is especially signicant with respect to VLSI implementation, since OTAs occupy
relatively large area, consume power and are sources of noise as will be explained in
chapter 3. The operational simulation approach will hence be utilised in chapter 4 to
design and implement a 5th-order elliptic lowpass video-lter.
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 37
2.3 OTA-C Sinc(x) Amplitude Equalisers
So far, the emphasis of this chapter has been on signal ltering. However, in high-
performance video lters, signal equalisation is equally important (see chapter 1). The
most signicant amplitude distortion in video-lters for digital broadcasting is sinc(x)-
distortion, which is being introduced into the spectrum of the converted signal by
D/A converters which are commonly are realised as zero-order holds to generate the
characteristic staircase shape waveform at their output. As explained in section 1.1.1,
the holding action of the D/A-converter introduces the distinctive sinc(x)-distortion
into the signal which is being converted. This distortion is especially signicant for low
sampling-to-signal frequency ratios (for example, a 2.1dB loss is introduced in the lter
passband of a 5MHz PAL digital video signal with the standard sampling rate FS =
13.5MHz). The amount of distortion is a function of the sampling ratio , dened as the
ratio between D/A-converter sampling frequency !S and post lter cut-o frequency
!C , according to = !S : !C .
An eective method to correct this distortion is to cascade an amplitude equaliser
with the lter in order to produce gain boost in the lter passband of opposite shape
to the sinc(x)-distortion. Most equaliser circuits are based on passive components or
op-amps, for example [81]. Recently, some OTA-based equalisers have been reported
in literature [52, 104]. In [52], a 2nd-order canonical amplitude equaliser with 4 OTAs
and 2 oating capacitors was described. For IC implementation, grounded capacitors
are preferred, since they are not only easier to integrate and less aected by parasitic
errors than oating capacitors, but they are also advantageous in mixed-signal designs
since cost-eective single-poly CMOS processes are normally employed. In [104], a
2nd-order amplitude equaliser having 5 OTAs and 2 grounded capacitors was proposed.
However, its correction accuracy is limited since it only realises real transmission zeros.
To overcome this limit in correction accuracy, this section introduces two new and
more ecient OTA-C amplitude equalisers for correcting sinc(x)-distortion of video
D/A converters [18, 20]. It compares their design capabilities with respect to cor-
rection accuracy and analyses OTA non-ideal eects in the performance of these new
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 38
equalisers operating at video-frequencies [19]. In order to simplify referencing to these
two equaliser structures, they will be referred to in the following sections as equaliser
1 and equaliser 2.
2.3.1 Sinc(x)-Equaliser 1 Conguration
The rst new equaliser is based on 5 OTAs and 2 grounded capacitors. Its circuit
diagram is shown in Fig.2.8.
C2
gm
C1
gm2
gm3gm5
Vin
Vout
gm4
gm1
Figure 2.8: Sinc(x)-equaliser 1 structure
Assuming ideal transconductance ampliers yields:
H(s) =VoutVin
=
gm5gm2
s2 + gm1C2
s+ gm1gm4gm5gm2C1C2
s2 + gm3C2
s+ gm3gm4gm5gm2C1C2
(2.4)
The main dierence between the equaliser in Fig.2.8 and that in [104] is, that the
transfer function of the new equaliser has a pair of complex transmission zeros, whilst
the one in [104] has two real transmission zeros. Complex zeros allow more exibility
in shaping the equaliser gain boost and hence better correction accuracy is obtained
as demonstrated section 2.3.1.3.
The presented equaliser circuit has low !0 and Q sensitivities for both zeros (z) and
poles (p) as shown in Table 2.2.
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 39
C1 C2 gm1 gm2 gm3 gm4 gm5
!0z 12 1
212 0 0 1
2 0
!0p 12 1
2 0 0 12
12 0
Qz 12
12
12
12
0 12
12
Qp 12
12
0 12
12
12
12
Table 2.2: !0 and Q sensitivities for the equaliser 1
2.3.1.1 Design Procedure
To ensure the equaliser has unity DC gain and to simplify the design of the equaliser,
assume gm1 = gm2 = gm3 = gm4 = gm, which yields:
HE(s) =VoutVin
=
gm5gm s2 + gm
C2s+ gmgm5
C1C2
s2 + gmC2
s+ gmgm5C1C2
=2s
2 + 1s+ 0s2 + 1s+ 0
(2.5)
where
gm =012
C1 gm5 =01C1 C2 =
0212
C1 (2.6)
The equaliser design for correcting a particular sinc(x)-distortion is based on curve-
matching optimisation and involves ensuring that the equaliser magnitude response is
the inverse of the sinc(x)-distortion. The sinc(x)-transfer function is:
(!) =sin(!T=2)
!T=2ej!T=2 (2.7)
where T = 1=FS . The curve-matching algorithm is required to match a 2nd-order
polynomial (Eqn.2.5) to the inverse of Eqn.2.7 over the entire post lter bandwidth
(!max = !C) and return the polynomial coecients i. The equaliser component values
are easily determined by means of coecient matching with Eqn.2.6. The general
sinc(x)-equaliser design process is based on the following steps:
1. An initial guess solution is generated for the coecients i of the 2nd-order
equaliser function with the amplitude HE(!; k) for the rst iteration (k = 1)
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 40
2. The error criterion E(!; k) for the kth iteration, dened as the maximum error
between the magnitude of the equaliser transfer function, HE(s), and the mag-
nitude of 1/sinc(x), is obtained by Eqn.2.8 within the desired frequency band of
the entire post lter bandwidth (!max = !C) for the kth iteration.
E(!; k) = max
(HE(!; k)1
(!; k)
)
(2.8)
3. The polynomial coecients 0, 1 and 2 are found by evaluating the error
criterion of Eqn.2.8.
Eqn.2.8 is optimised numerically using Matlab c optimisation toolbox [36]. The
input le listing for the Matlab c optimisation can be found in appendix B, section B.1.
To simplify the design process, Table 2.3 summarises normalised equaliser component
values for a range of sampling ratios . Note that ratios 2:2 are uncommon, since
D/A-converters are not usually operated very close to the Nyquist-frequency.
2.3.1.2 OTA Non-Ideal Eects
At video frequencies, the performance of equaliser 1 is limited by the non-ideal char-
acteristics of the active devices. While in general, a complete OTA frequency model
consists of input capacitance Cin, input conductance gin, output capacitance Cout and
output conductance gout, previous work has shown that in the case of CMOS OTAs, gin
and Cout are very small and may hence be neglected [5] and that input capacitance and
output resistance of a CMOS OTA form the signicant parasitics in OTA-C circuits
[76].
With respect to parasitic input capacitance, it has been suggested in the literature
to consider only the dierential capacitance between the input terminals V + and V for
Cin [97, 46]. However, in CMOS circuits with dierential common-source input stages,
this capacitance is very small compared to the parasitic gate-source capacitances of the
input transistors which are given with respect to ground. In order to re ect this fact
and simplify the circuit analysis, this thesis assumes, that Cin is the common-mode
capacitance between each input terminal and ground potential [76] as shown in Fig.2.9.
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 41
C1 (F) C2 (F) gm (S) gm5(S) error (%)
2.3 1.0 48.016 42.916 3.3565 0.052.4 1.0 21.465 20.365 3.1620 0.052.5 1.0 13.665 13.550 3.0255 0.052.6 1.0 10.030 10.285 2.9239 0.062.7 1.0 7.8501 8.2965 2.8229 0.062.8 1.0 6.5647 7.0733 2.7602 0.052.9 1.0 5.7710 6.3665 2.7194 0.053.0 1.0 4.8247 5.2573 2.6083 0.063.1 1.0 4.5182 5.0552 2.6063 0.063.2 1.0 4.2578 4.9015 2.6060 0.053.3 1.0 3.8042 4.2497 2.5123 0.063.4 1.0 3.5693 3.9631 2.4743 0.063.5 1.0 3.5093 4.1540 2.5341 0.053.6 1.0 3.3382 3.9817 2.5151 0.043.7 1.0 3.1380 3.4965 2.4161 0.063.8 1.0 3.0702 3.7076 2.4842 0.043.9 1.0 2.9631 3.5970 2.4712 0.044.0 1.0 2.8688 3.4957 2.4581 0.044.1 1.0 2.7915 3.4169 2.4509 0.044.2 1.0 2.7168 3.3262 2.4364 0.044.3 1.0 2.6496 3.2702 2.4306 0.044.4 1.0 2.6160 3.2230 2.4350 0.044.5 1.0 2.5713 3.0231 2.3707 0.044.6 1.0 2.4932 3.1000 2.4074 0.034.7 1.0 2.4532 3.0528 2.4013 0.034.8 1.0 2.4107 3.0170 2.3971 0.034.9 1.0 2.3752 2.9790 2.3919 0.035.0 1.0 2.3441 2.9450 2.3879 0.035.1 1.0 2.3131 2.9122 2.3828 0.035.2 1.0 2.3010 2.8913 2.3873 0.035.3 1.0 2.2594 2.8546 2.3745 0.035.4 1.0 2.2357 2.8290 2.3708 0.035.5 1.0 2.2137 2.8052 2.3674 0.035.6 1.0 2.1931 2.7830 2.3641 0.025.7 1.0 2.2247 2.7933 2.3892 0.035.8 1.0 2.1574 2.7420 2.3580 0.025.9 1.0 2.1430 2.7249 2.3564 0.026.0 1.0 2.1925 2.7500 2.3918 0.02
Table 2.3: Normalised component values of equaliser 1 for dierent sampling ratios
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 42
This assumption is widely supported by commercial datasheets (e.g. [14]), where input
capacitance is commonly dened in this way.
An appropriate video-frequency OTA model is shown in Fig.2.9, where Cin is the
common-mode input capacitance and gout is the output conductance.
gm gout
V-
Cin
V+
Cin
Iout
Figure 2.9: Video-frequency OTA model
Using this model for all the equaliser OTAs and assuming that gm1 = gm2 = gm3 =
gm4 = gm, circuit analysis yields the following transfer function:
H(s) =6s
2 + 5s+ 43s3 + 2s2 + 1s+ 0
(2.9)
where
6 = gm5(Cin(2Cin + 2C1 + C2) + C1C2)
5 = goutgm5(4Cin + 2C1 + C2) + g2m(Cin + C1)
4 = g2m(gout + gm5) + 2gm5g2out
3 = 2Cin(Cin(2Cin + 2C1 + C2) + C1C2)
2 = C1C2(2gout + gm) + Cin(4gout + gm)(2C1 + C2) + 2C2in(6gout + gm)
1 = gout(2gout + gm)(4Cin + 2C1 + C2) + g2m(C1 + Cin) + 4g2outCin
0 = 4g3out + 2gmg2out + g2m(gout + gm5)
This shows, that the eect of the OTA non-ideal parameters on the ideal equaliser
1 not only modies the complex pair of pole-zero positions by altering every transfer
function coecient, but also introduces an extra real pole when compared with the
ideal case (Eqn.2.5).
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 43
Note, in analysing the non-ideal equaliser performance, it has been assumed that
all the equaliser OTAs have the same Cin and gout. This assumption is valid, since 4
of the 5 OTAs in the circuit have identical transconductance values (gm). Although
the remaining OTA has a dierent gm, simulations have shown that the OTA input
capacitance and output conductance values do not vary signicantly, provided the OTA
operates in the linear region.
In order to absorb the OTA parasitics into the equaliser components and hence
minimise their eects, the equaliser components should be expressed in terms of the
polynomial coecients used to correct the sinc(x)-distortion, as well as the input ca-
pacitance and output conductance of the OTA devices. Manipulating Eqn.2.9 results
in the following equaliser design equations, which take into account the OTA non-ideal
parameters. The parameters Cin and gout are usually known depending on the OTA
chosen for implementation:
gm5 =2Cin63
(2.10)
gm =2g2out(gm5 2gout) + 0 4
2g2out(2.11)
C1 =5(gm + 2gout) + g2mCin(gm5 2gout gm) + gm5(4g2outCin 1)
g2m(2gout + gm gm5)(2.12)
C2 =2gm5 6(gm + 2gout) 4goutgm5Cin(2Cin + C1)
2goutgm5Cin(2.13)
2.3.1.3 Design Examples
The previous two sections have rstly presented the low-frequency design procedure for
the equaliser 1 structure and secondly introduced a compensation method for its OTA
non-ideal eects at high frequencies. To illustrate these design methods, this section
will consider two examples:
1. Example 1 will compare the performance of equaliser 1 with the equaliser reported
in [104], with reference to correcting sinc(x)-distortion of a D/A converter with
standard sampling rate of 13.5MHz to within 0.1dB over the entire bandwidth
of the 5MHz luminance channel lter in a PAL video system.
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 44
2. Example 2 will conrm the theoretical analysis of the non-ideal equaliser 1 design
equations, with reference to correcting the sinc(x)-distortion of a D/A converter
which employs two times oversampling now having sampling rate of 27MHz over
10MHz PAL video lter bandwidth.
2.3.1.4 Example 1
First, consider correcting sinc(x)-distortion of a 13.5MHz D/A converter to within
0.1dB over the entire bandwidth of the 5MHz luminance channel lter in a PAL
video system. Using Table 2.3 for equaliser 1 with = 2:7 : 1, Table 2.4 gives the
denormalised equaliser component values (assuming C1 = 2pF) and the optimisation
error function values.
C1 (pF) C2 (pF) gm (S) gm5 (S) E(%)
Equaliser 1 2 16 529.7 178.4 0.06
Equaliser [104] 10 1.3 159.7 506.8 0.08
Table 2.4: Component values of equaliser 1 and equaliser in [104] ( generated using
the design procedure in section 2.3.1.1)
Based on these values, the ideal frequency response simulation of the equaliser 1 and
the equaliser in [104] when cascaded with D/A sinc(x)-distortion is shown in Fig.2.10.
This shows that the new equaliser has correction error of approximately 0.01dB, whilst
the error is approximately 0.09dB for the equaliser in [104]. Equaliser 1 has better
correction capability because it has complex transmission zeros unlike the equaliser in
[104], which has two real zeros as indicated in Table 2.5.
Fig.2.11 shows frequency response simulation of equaliser 1 and the equaliser in
[104] when cascaded with 13.5MHz D/A sinc(x)-distortion based on CMOS transcon-
ductance ampliers (Fig.3.5 in chapter 3). The amplier W/L ratios of both equalisers
are given in Table 2.6. The simulation is based on 0.8m AMS double-poly CMOS
technology and level 6 SPICE transistor models.
The correction error of equaliser 1 is approximately 0.02dB up to 5MHz, unlike the
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 45
100kHz 300kHz 1MHz 3MHzFrequency
0.06
0.04
0.02
0
-0.02
-0.04
-0.065MHz
dB
Equaliser 1
Equaliser [104]
Figure 2.10: Ideal frequency response simulation of equaliser 1 and the equaliser in
[104] when combined with 13.5MHz sinc(x)-distortion
Poles Zeros
Equaliser 1 0:5284 j1:6495 1:5689 j2:5390
Equaliser [104] 3:3941 0:7999
-0.5980
Table 2.5: Normalised pole-zero locations for equaliser 1 and the equaliser in [104] with
= 2:7 : 1
equaliser in [104] which has correction error of approximately 0.22dB. This variation
in correction error from the ideal case is attributed to the amplier non-ideal charac-
teristics. Fig.2.11 shows, that equaliser 1 is less aected by non-ideal characteristics
compared to the equaliser in [104], which conrms its excellent correction performance.
Note, that this result is not re ected in the error function values of Table 2.4, where
both ideal equalisers exhibit similarly low curve-matching errors.
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 46
100kHz 300kHz 1MHz 3MHzFrequency
0.3
0.2
0.1
0
-0.15MHz
dB
Equaliser 1
Equaliser [104]
Figure 2.11: Transistor-level frequency response simulation of equaliser 1 and the
equaliser in [104] when combined with 13.5MHz sinc(x)-distortion
gm gm5
WN WP WN WP
Equaliser 1 29.1m 84.0m 12.6m 36.4m
Equaliser [104] 20.9m 60.3m 37.8m 109.1m
Table 2.6: W/L ratios of the transconductance ampliers (LN = LP = 1.2m)
2.3.1.5 Example 2
Fig.2.11 has conrmed that equaliser 1 exhibits superior correction accuracy over the
equaliser in [104] at frequencies of 5MHz. This example considers the equalisation
of sinc(x)-distortion introduced by a 27MHz D/A-converter over 10MHz post lter
bandwidth. Using Table 2.3 and impedance and frequency scaling, the denormalised
ideal equaliser component values are given in Table 2.9.
Based on ideal OTAs, the equaliser frequency response simulation is shown in
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 47
100kHz 1.0MHz 10MHzFrequency
0.8
0.6
0.4
0.2
0
-0.2
dB
non-ideal CMOS equaliser 1combined with sinc(x)-distortion
ideal equaliser 1combined with sinc(x)-distortion
Figure 2.12: Simulated frequency response of ideal and uncompensated CMOS
equaliser 1 when combined with 27MHz D/A converter sinc(x)-distortion
Fig.2.12. The correction accuracy of the ideal equaliser when combined with 27MHz
sinc(x)-distortion is <0.01dB. While the sampling ratio = 2:7 : 1 is maintained com-
pared to the previous example, the performance of the transistor-level circuit is now
limited by the OTA non-ideal eects, as indicated in Fig.2.12.
As can be seen, the circuits transistor-level response, based on the same CMOS
process as before, is signicantly dierent from the ideal response, now resulting in an
equaliser sinc(x)-correction accuracy of <0.8dB, which is clearly not acceptable in video
applications. In this case, the OTA non-ideal eects must be compensated for using
the high-frequency design equations (Eqn.2.13) introduced in section 2.3.1.2. With the
design procedure outlined in section 2.3.1.1, the polynomial coecients (0, 1, . . . ,
6) of the non-ideal equaliser 1 can easily be determined and are given in Table 2.7.
Extensive simulation of the CMOS OTA (Fig.3.5 in chapter 3) with dierent values
of gms have shown that the OTA has Cin = 1.6pF and gout = 62.5S. Using these
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 48
6 5 4 3 2 1 0
non-ideal equaliser 0.1511 0.4439 0.9769 0.0977 0.4587 0.6177 1.0000
Table 2.7: Non-ideal equaliser 1 polynomial coecients for = 2:7 : 1
Poles Zeros
non-ideal equaliser 1 0:4795 1:5841 1:4692 2:0755
3:7365
Table 2.8: Non-ideal equaliser 1 pole-zero locations for = 2:7 : 1
values, Table 2.7 and Eqns.2.13, the compensated equaliser values are given in Table
2.9. The corresponding transistor W/L dimensions are given in Table 2.10.
C1 (pF) C2 (pF) gm (S) gm5 (S) Cin (pF) gout (S)
ideal equaliser 2.0 16.0 1059.4 356.8 0.0 0.0
compensated equaliser 0.5 7.0 656.7 301.2 1.6 62.5
Table 2.9: Ideal and compensated equaliser 1 component values for = 2:7 : 1
gm gm5
Equaliser 1 WN WP WN WP
ideal 81.6m 235.6m 16.8m 48.3m
compensated 50.6m 146.1m 14.1m 40.7m
Table 2.10: Ideal and compensated equaliser 1 W/L ratios (LN = LP = 1.2m)
Fig.2.13 shows the simulated response of the compensated equaliser where the cor-
rection accuracy is <0.05dB, which compares favourably with the correction achieved
by the ideal equaliser. This conrms the eectiveness of the proposed equaliser design
equations.
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 49
100kHz 1.0MHz 10MHzFrequency
0.02
0.01
0
-0.01
-0.02
-0.03
compensated CMOS equaliser 1combined with sinc(x)-distortion
ideal equaliser 1combined with sinc(x)-distortion
dB
Figure 2.13: Simulated frequency response of ideal and compensated CMOS equaliser
1 when combined with 27MHz sinc(x)-distortion using the proposed equaliser design
equations
2.3.2 Sinc(x)-Equaliser 2 Conguration
Although equaliser 1 is eective in correcting sinc(x)-distortion, is the necessary to
compensate for high-frequency non-ideal eects using a new set of design equations
which modies all component values (see Table 2.9). This clearly complicates the
design process. A better solution is to develop an equaliser, which has the ability to
tune !0 and Q parameters electronically, hence allowing simple compensation of OTA
non-ideal characteristics. This section introduces a tunable OTA-C equaliser structure,
which is based on 6 OTAs and two grounded capacitors (see Fig.2.14).
The main structural addition to equaliser 2 is the transconductor gm5 (box in
Fig.2.14), which injects current directly into C2, introducing a linear s-term into the
numerator of the transfer function. Assuming ideal transconductance ampliers, circuit
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 50
C2
C1
gm2
gm6
VinVout
gm1
gm5
gm3
gm4
Vb6
Vb1
Vb2
Vb3
Vb4
Vb5
Figure 2.14: Sinc(x)-equaliser 2 structure
analysis yields the following transfer function:
H(s) =VoutVin
=
gm6gm4
s2 + gm3gm5gm4C2
s+ gm1gm2gm3gm4C1C2
s2 + gm2gm3gm4C2
s+ gm1gm2gm3gm4C1C2
(2.14)
2.3.2.1 Design Procedure
There are two important dierences in the transfer function between equaliser 2 and
equaliser 1:
Firstly, the numerator s2-term in Eqn.2.14 is independently controlled by gm6,
unlike with equaliser 1, where the numerator s2-term is linked to the numerator
and denominator constant terms. This introduces an additional degree of freedom
to the shaping of the sinc(x)-equaliser transfer function.
Secondly, the numerator s-term in Eqn.2.14 is only controlled by gm5, unlike in
equaliser 1, where, under the assumptions made, the linear terms in numerator
and denominator are equal. This implies that the zero Q-position can be placed
independently by varying gm5, unlike equaliser 1, which has identical zero and
pole Q-positions.
This independence of coecient control is achieved because the transconductor
gm6 injects current into the respective inverting inputs of the two OTA-C integrators
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 51
(gm1 C1 and gm2 C2) which causes the constant and linear term to appear in the
transfer function denominator.
Thus, the circuit oers two design methodologies to achieve sinc(x)-equalisation.
The rst method relies on controlling the position of the s2-term zero position elec-
tronically via gm6. In this case, assume all gms identical, excluding gm6, which yields
the following transfer function:
H(s) =
gm6gm
s2 + gmC2
s+g2mC1C2
s2 + gmC2
s+g2mC1C2
=2s
2 + 1s+ 0s2 + 1s + 0
(2.15)
where
gm = 1C2 gm6 = 12C2 C1 =210C2 (2.16)
This set of design equations (Eqns. 2.16) corresponds to those derived in section
2.3, because the equaliser presented there relies on the same design method. For this
reason, this design concept will not be investigated further in this section.
The second method achieves equalisation by altering the numerator Q-factors elec-
tronically via gm5. In this case, assume all gms identical, excluding gm5, which yields:
H(s) =s2 + gm5
C2s+
g2mC1C2
s2 + gmC2
s+g2mC1C2
=s2 + 2s+ 0s2 + 1s+ 0
(2.17)
where
gm = 1C2 gm6 = 2C2 C1 = 21 0C2 (2.18)
In section 2.3.2.2, this method will be used to design a tunable video-frequency
sinc(x)-equaliser. The polynomial values 0, 1 and 2 are again found by evaluating
the curve-matching design procedure described in section 2.3. The input le listing for
the Matlab c optimisation can be found in appendix B, section B.2. Equaliser 2 has
low !0 and Q sensitivities for both zeros and poles as shown in Table 2.11.
As before, the equaliser component values are functions of the sampling ratio .
Table 2.12 summarises the normalised equaliser 2 component values.
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 52
C1 C2 gm1 gm2 gm3 gm4 gm5 gm6
!0 12 1
212
12 0 1
2 0 0
Qz 12
12
12
12 1
212 0 -1
Qp 12
12
12
12
12
12
0 0
Table 2.11: !0 and Q sensitivities for equaliser 2
2.3.2.2 Design Example
The design procedure for correcting a particular sinc(x)-distortion has already been
described in section 2.3.1.1. To compare the performance of equaliser 2 to that of
equaliser 1, consider correcting the sinc(x)-distortion of a D/A converter which employs
twice oversampling and hence has sampling rate of 27MHz to within <0.1dB over the
entire bandwidth of a 10MHz PAL digital video system (example 2 in section 2.3.1.3).
Using the design equations (Eqn.2.18), the ideal component values for equaliser 2 are
given in Table 2.13 ( = 2.7). The ideal component values of equaliser 1 are repeated
here for convenience.
Note, that the capacitor spread of equaliser 2 is 80% lower than that of equaliser 1,
while the active transconductance spread is reduced by 40%. Low component spread
is generally preferable in monolithic implementations since it will result in improved
accuracy during production [7].
With these values and ideal OTAs, SPICE simulation reveals correction accuracy
of < 0.01dB for both equalisers when combined with 27MHz sinc(x)-distortion, which
compares favourably with the requirements of the design example.
At video-frequencies however, the active device non-ideal characteristics (i.e. OTA
input capacitance Cin and output conductance gout) limit the performance of the
equaliser monolithic implementation. Section 2.3.1.3 has shown that the CMOS OTA
used for simulation (Fig.3.5 in chapter 3) has Cin = 1.6pF and gout = 62.5S. Using
these parasitics values and Table 2.13, Fig.2.15 shows the uncompensated responses
of CMOS equaliser 2 in Fig.2.14 and CMOS equaliser 1 in comparison to the ideal
equaliser 2 response.
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 53
C1 C2 gm gm5 error
2.3 1.0 0.4922 1.2886 2.9232 0.092.4 1.0 0.5724 1.3901 2.8725 0.092.5 1.0 0.6379 1.4740 2.8447 0.082.6 1.0 0.6775 1.5556 2.9077 0.072.7 1.0 0.7490 1.6180 2.8210 0.072.8 1.0 0.8135 1.6698 2.7485 0.072.9 1.0 0.8629 1.7159 2.7097 0.073.0 1.0 0.9036 1.7696 2.7157 0.063.1 1.0 0.9435 1.8125 2.7012 0.063.2 1.0 0.9621 1.8277 2.6547 0.083.3 1.0 1.0131 1.8891 2.6814 0.053.4 1.0 1.0391 1.9429 2.7223 0.043.5 1.0 1.0861 1.9038 2.5503 0.053.6 1.0 1.1430 1.9178 2.4947 0.073.7 1.0 1.1348 1.9119 2.4588 0.053.8 1.0 1.1564 1.9374 2.4609 0.053.9 1.0 1.1757 1.9552 2.4528 0.044.0 1.0 1.1949 1.9709 2.4430 0.044.1 1.0 1.2122 1.9801 2.4255 0.044.2 1.0 1.2289 2.0014 2.4302 0.044.3 1.0 1.2440 2.0109 2.4180 0.044.4 1.0 1.2586 2.0237 2.4126 0.034.5 1.0 1.2702 2.0185 2.3822 0.034.6 1.0 1.2837 2.0419 2.3961 0.034.7 1.0 1.3002 2.0805 2.4320 0.034.8 1.0 1.3091 2.0763 2.4077 0.034.9 1.0 1.3201 2.0893 2.4090 0.035.0 1.0 1.3275 2.0796 2.3799 0.035.1 1.0 1.3379 2.0926 2.3830 0.025.2 1.0 1.3467 2.1068 2.3890 0.025.3 1.0 1.3596 2.1362 2.4149 0.025.4 1.0 1.3633 2.1136 2.3727 0.025.5 1.0 1.3498 2.1079 2.3588 0.035.6 1.0 1.3781 2.1370 2.3817 0.025.7 1.0 1.3846 2.1310 2.3635 0.025.8 1.0 1.3935 2.1506 2.3791 0.025.9 1.0 1.4668 2.1595 2.3662 0.036.0 1.0 1.4015 2.1387 2.3468 0.02
Table 2.12: Normalised component values of equaliser 2 (changing Qz via gm5)
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 54
Equaliser 2 Equaliser 1
ideal comp. ideal comp.
C1 (pF) 3.8 3.8 2.0 0.5
C2 (pF) 5.0 5.0 16 7.0
gm (pF) 505.8 890.0 1059.4 656.7
gm5 (pF) 868.5 1735.0 356.8 301.2
Cin (pF) 0.0 1.6 0.0 1.6
gout (pF) 0.0 62.5 0.0 62.5
Table 2.13: Ideal and compensated component values for equaliser 2 and equaliser 1
100kHz 1.0MHz 10MHzFrequency
4.0
3.0
2.0
1.0
0
-1.0
dB
non-ideal CMOS equaliser 2combined with sinc(x)-distortion
non-ideal CMOS equaliser 1combined with sinc(x)-distortion
ideal equaliser 2combined with sinc(x)-distortion
Figure 2.15: Simulated frequency response of ideal and uncompensated equaliser 2 and
equaliser 1 when cascaded with 27MHz sinc(x)-distortion
As can be seen, the responses are signicantly dierent from the ideal behaviour,
now resulting in an equaliser correction accuracy of <0.8dB for equaliser 1 and <3.2dB
for equaliser 2. These deviations clearly are not acceptable in video applications. Note
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 55
that although the frequency response amplitude ripple of the uncompensated equaliser
2 is bigger than the ripple of equaliser 1, its compensated response ripple is signicantly
smaller, as will be shown later.
100kHz 1.0MHz 10MHzFrequency
0.02
0.01
0
-0.01
-0.02
-0.03
dB compensated CMOS equaliser 1combined with sinc(x)-distortion
compensated CMOS equaliser 2combined with sinc(x)-distortion
ideal equaliser 2combined with sinc(x)-distortion
Figure 2.16: Simulated frequency response of ideal and compensated equaliser 2 and
equaliser 1 when cascaded with 27MHz sinc(x)-distortion
To compensate for the eects of these non-ideal characteristics, a new set of high-
frequency equaliser 1 design equations was required in section 2.3.1.2, which resulted in
all equaliser 1 component values being changed from their ideal case (see Table 2.13).
Compensation has been achieved to within <0.05dB which compares favourably to the
ideal equaliser (see Fig.2.16).
The need to change every circuit component in the high-frequency design clearly
complicates the design process. Equaliser 2 allows to compensate for these non-ideal
characteristics by adjusting the values of gm and gm5 electronically, as demonstrated in
Fig.2.16. Note in particular, that the ideal capacitor values are maintained, which has
clear advantages in monolithic implementations. Fig.2.16 shows that the equaliser 2
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 56
structure has correction error of approximately<0.01dB up to 10MHz, which compares
favourably with the ideal equaliser results.
2.3.2.3 Discrete Sinc(x)-Equaliser Implementation
In order to verify the functionality and the design of the sinc(x)-equaliser 2 structure,
a discrete implementation of the circuit was produced (Fig.2.17).
C1 C2
Vin
Q3 Q5 Q7 Q8Q2 Q4 Q6Q1
LT1228LT1228 LT1228 LT1228LT1228 LT1228
Vout
VSS
VbVb5
VSS
Figure 2.17: Sinc(x)-equaliser 2 discrete implementation
It is based on Linear Technology LT1228 single-output OTAs [14], passive compo-
nents with 1% tolerances and 5V supplies. The transconductances were dened by
a set of bipolar current sources realised using MPQ7093 transistor arrays [34]. This
section addresses the functionality of the circuit with respect to a proof of concept,
not as a video-frequency sinc(x)-equaliser. To account for the limitations of discrete
realisations and to reduce parasitic eects, the lter capacitor values considered in the
example in section 2.3.2.2 were scaled up from 5pF to 130pF and from 3.8pF to 100pF
respectively. Fig.2.18 shows the measured frequency response of the sinc(x)-equaliser
in Fig.2.14.
Generally there is a good agreement between theoretical and measured results in
terms of the overall equaliser shape. As can be seen, the amplitude boost is vari-
able electronically between 7dB and 10dB by varying the bias voltage on the gm5-
transconductance amplier (Vb5). Note that there is a -6dB drop in the equaliser fre-
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 57
Figure 2.18: Sinc(x)-equaliser 2 Q-tuning example
Figure 2.19: Sinc(x)-equaliser 2 frequency-tuning example
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 58
quency response owing to the equally terminated measurement set-up. Fig.2.19 shows
the same design using unchanged measurement set-up and component values. However,
gm5 is kept constant, while gm is varied by varying the bias voltage of the remaining
OTAs (Vb). The equaliser exhibits tunable frequency response characteristics between
750kHz and 880kHz, independent of the amplitude gain.
2.4 Concluding Remarks
This chapter has investigated in detail the design of high-order voltage-mode ladder
lters based on the OTA-C approach. While it has been noted that the cascade ap-
proach is a simple, straight-forward and well established technique to realise high-order
transfer functions in discrete implementations, it is unsuitable for monolithic realisa-
tions of high-performance lters due to the increased sensitivity to passive component
variations.
It has been shown, that silicon implementations of high-order lters should start
from the simulation of passive ladder networks. The main advantage of simulation
methods is that the active circuits maintain the low sensitivity properties of their
passive prototypes. Three methods to derive OTA-C lters from passive ladder pro-
totypes have been demonstrated: Direct impedance simulation, FDNR simulation and
operational simulation.
Section 2.2.3 has proven, that operational simulation based on signal- ow graphs
is the most accurate and exible approach to simulate the behaviour of a passive
ladder prototype. Since it uses only OTA based integrators as basic building blocks,
it is canonical, hence requiring the least number of active devices for any given lter
order. This design methodology is adapted throughout this thesis for the design of
high-performance ladder lters.
Furthermore, this chapter has demonstrated clearly the design and CMOS imple-
mentation of two new OTA-C equalisers for correcting sinc(x)-distortion of video D/A
converters.
Equaliser 1 is based on 5 single-output OTAs and exhibits superior correction ac-
CHAPTER 2. VOLTAGE-MODE OTA-C FILTERS 59
curacy and better performance when compared with a recently introduced equaliser.
A detailed analysis and minimisation of OTA non-ideal eects in sinc(x)-equaliser 1
operating at video-frequencies has also been presented. The compensation has been
achieved by deriving a set of design equations incorporating the OTA input capaci-
tance and output resistance and the polynomial coecients used to correct the sinc(x)-
distortion.
Equaliser 2 is based on 6 single-output OTAs and has enhanced compensation
features owing to independent electronic control of biquad !0 and Q parameters by
means of gm tuning, allowing simple compensation for active device non-ideal eects.
This is also advantageous in monolithic implementations, since it allows automatic
adjustment for fabrication tolerances using traditional OTA-C tuning schemes based
on phase-locked loops [75]. Measured results conrm the excellent circuit properties,
making the two new equalisers a valuable addition to the building blocks of monolithic
continuous-time video lters.
Chapter 3
Comparative Study of CMOS OTAs
3.1 Introduction
In addition to an ecient lter design method, which has been introduced in chapter
2, the second major performance criterion for analogue lters is the transistor-level
behaviour of the active device. This chapter presents a comprehensive review of dif-
ferent CMOS OTA architectures, which have been proposed over the last fteen years.
While BiCMOS OTAs are receiving some attention in the literature [6, 17, 68, 71, 73],
this chapter focuses on CMOS architectures [41, 53, 58, 63, 65, 69, 89], since CMOS
technology has become dominant in analogue integrated circuit design, primarily for
its low power dissipation and popularity in digital circuits (see in chapter 1). Further-
more, this chapter aims to identify suitable OTA structures for the implementation of
the lter structures presented in this thesis.
Mainly, two types of OTAs can be identied: OTAs with one current output (single-
ended OTAs) and OTAs with more than one current output (multiple-output OTAs
- MO-OTAs). Single-ended OTAs are commonly associated with the voltage-mode
approach, while MO-OTAs are necessary in current-mode lters, because one or more
outputs are utilised for current signal feedback.
Section 3.2 will outline a number of important parameters which allow performance
comparison between several OTA topologies. After brief denitions of these param-
eters, section 3.4 will focus on comparing single-ended OTAs, while section 3.5 will
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 61
introduce multiple-output OTAs.
3.2 Comparison Criteria
Because every OTA structure reported in the literature has been proposed to t a
specic application, it is dicult to identify one single performance parameter which
allows comprehensive comparison between several OTAs. To attempt meaningful clas-
sication, the OTAs are compared according to a number of criteria, which are often
considered important in the evaluation of OTA-based lters [76, 83, 84]. These include:
1. Bandwidth
2. Power consumption
3. THD
4. Tuning Range
These performance criteria will be obtained from SPICE simulations [54], based on
sinusoidal input signals of 100mV amplitude and 1MHz frequency. This input voltage
is commonly accepted as reasonable to guarantee linear CMOS OTA operation [27, 76],
while linear operation at 1MHz is a minimum requirement for video-frequency OTAs.
Another important requirement of CMOS OTAs is their capability of driving capacitive
loads. A typical value for capacitive loads in video-frequency applications is 1pF, which
will be applied throughout the comparison.
To maintain consistency among the compared OTAs, all simulations are based on
BSIM3 transistor models [31] (i.e. SPICE level 6) and model parameters of the 0.8m
double-metal double-poly CMOS n-well process provided by the AMS foundry [1].
For completeness, the model parameters of this process are listed in Table 3.1. More
detailed information on these parameters and the operation CMOS transistors can be
found in [54]. Note, that the reported transistor W=L ratios for each OTA have been
adapted to achieve matching between the n-channel and p-channel devices according
to the model parameters in Table 3.1.
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 62
Parameter NMOS PMOS Dimension
LEVEL 6 6 CGSO 0:350 1009 0:350 1009 F=mCGDO 0:350 1009 0:350 1009 F=mCGBO 0:150 1009 0:150 1009 F=mCJ 0:360 1003 0:440 1003 F=m2
MJ 0:430 0:530 CJSW 0:250 1009 0:220 1009 F=mMJSW 0:190 0:200 JS 0:010 1003 0:020 1003 A=m2
RSH 23:00 40:00 =squareTOX 15:50 1009 15:50 1009 mXJ 0:080 1006 0:087 1006 mLD 0.000 0:076 1006 mWD 0:580 1006 0:331 1006 mVTO 0:830 0:820 VNFS 0:835 10+12 0:483 10+12 1=cm2
NSUB 63:80 10+15 32:80 10+15 1=cm3
NEFF 10:00 2:570 UO 462:0 160:0 cm2=V sUCRIT 37:70 10+04 30:80 10+04 V=cmVMAX 61:90 10+03 61:30 10+03 m=sDELTA 0:237 0:9490 KF 0:276 1025 0:466 1026 AF 1:530 1:610
Table 3.1: CMOS process parameters for the AMS 0.8m double-metal double-poly
n-well process
Before carrying out the comparison, it is necessary to introduce brief denitions of
the performance parameters listed above.
1. Bandwidth (BW): One of the most important aspects of transistor-level active
lter design is the bandwidth of the OTA, dened as the frequency range between
DC and the -3dB point of the OTA frequency response. This is best illustrated
by considering the OTA-C integrator (see section 2.2.2), which is characterised
by its phase shift at the unity-gain frequency. Excess phase shift (< 90) can be
attributed to parasitic poles of the OTA-C circuit [76]. Because this excess phase
will degrade the lter response, the integrator is required to have parasitic poles
located much higher (typically ten times higher) than the lter cut-o frequency
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 63
to keep its phase at 90. For lter operation in the video-frequency range up
to 10MHz this means, the OTA must provide bandwidth of at least >100MHz.
2. Power Dissipation (PD): One of the motivations for integrating analogue lters is
their prospective use in portable system applications where low power dissipation
is a major design consideration. In addition, the increased feature density of
modern CMOS technologies leads to higher power dissipation per area, which can
cause reliability problems [13]. Power dissipation of less than 100mW is desirable
for CMOS OTAs. PD is dened as the product of supply voltage dierence
(VDD VSS ) and total current owing through the supply terminals.
3. Total Harmonic Distortion (THD): In general, the output signal y(t) of a time-
invariant electrical network can be expressed in terms of its input x(t) by a Taylor
series expansion:
y(t) = a1x(t) + a2x2(t) + a3x
3(t) + : : : (3.1)
where the coecient a1 represents the desired linear gain of the network and
coecients a2, a3, : : : represent its distortion. In practice, the output signal y(t)
of a transistor-level OTA will be distorted and its maximum signal level will be
dictated by the non-linear eect of practical amplier saturation characteristics
[10]. If for example a sine wave is applied to the input of an OTA, then harmonic
distortion is dened as the root-mean-square (rms) value of the ratio of all the
harmonics an to the 1st harmonic a1. While at low frequencies the coecients ai
can be assumed constant, at video frequencies the reactive components in the cir-
cuit introduce a frequency dependence into the coecients ai of Eqn.3.1. Hence,
the calculation of harmonic distortion involves solving a set of non-linear equa-
tions separately for every harmonic ai. In software simulation, it is not possible
to include all harmonics into this solution. SPICE restricts the calculation to the
9th harmonic (nine times the fundamental frequency) and refers to the result as
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 64
total harmonic distortion (THD), which is usually expressed in dB:
THD(dB) = 20 log
0@vuut 9X
n=2
ana1
21A (3.2)
For the implementation of high-performance lters, it is necessary that the active
devices exhibit low THD, typically <-50dB.
4. Tuning Range (TR): In almost every OTA reported in the literature, the transcon-
ductance gain gm is proportional to an external DC bias voltage or current. The
ability to tune the gm of the OTA is one of the main advantages of OTA-C lter
design, since it enables external control of lter parameters including !0 and Q.
A wide tuning range is advantageous in active integrated lter design, especially
for tuning the cut-o frequency of the OTA-C lter. The tuning range will be ex-
pressed in terms of the minimum and maximum gm value, which can be achieved
within the possible bias voltage or current range. The typical range of gm values
for lters operating at video-frequencies is 10S to 1mS.
3.3 Noise Performance of CMOS transistors
Before transistor-level OTA structures can be examined, some consideration must be
given to the noise performance of CMOS transistors. The term noise in electronic
circuits can be dened either as an unwanted signal, tending to interfere with a required
signal (interference) or as a random uctuation in voltage or current originating from
random motion of charge carriers (intrinsic noise) [25]. In the rst category, the noise
source is external to the circuit under consideration, while in the second category, the
noise is generated within the circuit elements. In video-frequency IC design, external
interference can be suciently suppressed by shielding either on the circuit board or
on the die packaging level. Also, well dened procedures exist to accomplish shielding
of high frequency signals on the semiconductor die itself. It is hence more important
to focus on the eect of intrinsic noise for the design of CMOS transconductance
ampliers.
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 65
Intrinsic noise is a signal with random amplitude versus time and is generated by
all active and passive circuit devices. Its average value over a certain period of time
is zero and therefore its power is measured by the noise voltage vN squared to v2n and
averaged over that time period. In the frequency domain, it is commonly accepted to
take an elementary small frequency band df and denote the noise power in this band
by dv2N which allows more accurate calculation of noise gures [46].
In order to simplify the analysis and obtain meaningful results, only two important
intrinsic noise sources will be considered: Thermal noise and 1/f or icker noise [46].
It is well known that at low frequencies, 1/f noise is the dominant source of noise in
MOSFET circuits [40]. Noise signals are generally small and can hence be added to
the small signal model of a MOSFET in the saturation region.
3.3.1 Thermal Noise
As the name suggests, thermal noise is a function of temperature but it is independent
of current ow. In general, a resistance R generates thermal noise given by:
dv2R = 4kTRdf (3.3)
where k is Boltzman's constant (1:381023J=K) and T is the absolute temperature.
In MOSFETS, the nite drain-source conductance generates thermal noise di2DS.
It is given by:
di2DS =8kT
3df (3.4)
In order to be able to compare the noise generated by the MOSFET to the input
signal applied, the noise is referred to the input. It is then called equivalent input noise
voltage and is represented by dv2ieq. Its value is obtained by division of di2DS of Eqn.3.4
by 2.
For example using the 0.8m AMS CMOS process, an n-channel MOSFET with
typical transistor dimension ratio W : L = 10 (conductance = 1:162 103A=V )
switched over a frequency band B of 10MHz at a temperature of 27C (300K) will have
an rms equivalent input noise voltage Vieq of:
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 66
Vieq =
vuutdv2ieqdf
=
s8kTB
3
1
(3.5)
Vieq =
vuut8 1:38 1023J=K 300K 10 106Hz
3 1:162 103A=V= 9:75V
which is small for the input voltages considered (Vin 100mV ).
3.3.2 1/f noise
1/f noise is most noticeable at low frequencies and describes the quality of the conduc-
tive medium. The more homogeneous the material, the lower the 1/f noise. For planar
devices, icker noise is always inversely proportional to the size of the device. The 1/f
noise does not depend on temperature but rather is proportional to the current and
has to be added to the thermal noise expression of Eqn.3.4. Referred to the input, the
equivalent input noise voltage due to icker noise is given by:
dv2ieqf =KF
WLC2ox
df
f(3.6)
where W and L are the MOSFET channel width and length parameters, Cox is
the gate oxide capacitance and KF is an empirical constant which depends on the
MOSFET used. It has been shown [46] that typical values are:
PMOS KF 1032 C2=cm2
NMOS KF 4 1031 C2=cm2
Compared to the thermal noise gure in the example above, the rms equivalent input
noise voltage Vieqf of an n-channel MOSFET with transistor dimensions W = 20m
and L = 2m at a frequency f of 100Hz is given by:
Vieqf =
vuutdv2ieqfdf
=
sKF
WLC2ox
1
f(3.7)
Vieqf =
vuut 4 1031C2=cm2
20m 2m 6:331 106F 2=m4 100Hz= 0:39V
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 67
In the SPICE MOSFET model, two parameters are added to characterise 1/f noise.
They are KF and AF (see Table 3.1). The expression used includes the in uence of
the gate area and is given by [46]:
dv2ieqf = KFIAF
2df
f(3.8)
Equating Eqn.3.6 and Eqn.3.8 shows the relation between the technological constant
KF and the parameter KF:
KF =4KP
nL2C2ox
KF (3.9)
While it is generally accepted that active lters suer from higher noise levels than
passive realisations, the advantages of OTA-C lters outlined in chapter 1 make a
strong case for the OTA-C approach. Its viability is supported by the above low noise
gures for CMOS transistors using the AMS process [1] and because the SPICE MOS
model accounts for 1/f noise eects, no further investigation related to noise will be
included this thesis.
3.4 Single-Ended OTAs
In this section, three single-ended OTAs have been chosen out of the numerous reported
topologies [63, 65, 89] to carry out the comparison, because each one oers a distinct
design advantage:
1. Simplicity
2. Linearity
3. Tunability
3.4.1 Simple CMOS OTA
One of the simplest CMOS OTAs has been described in [62]. It consists of four lin-
ear tunable voltage-to-current converters based on the CMOS inverter, each having a
pair of composite n-channel and p-channel devices (Fig.3.1a). The following equations
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 68
demonstrate, that the OTA is gm tunable with two bias voltages VG1 = VG4 = VG.
Assuming matching between M1 M3 and M2 M4 and all transistors operating in
saturation, the output current Iout of one inverter section is given by:
Iout = 2keff (2VG X
VT )Vi = gmVi (3.10)
wherePVT is the sum of the threshold voltages of the n-channel and p-channel
devices and keff is the eective transistor gain:
keff =knkpq
(kn) +q(kp)
2 (3.11)
Eqn.3.10 shows that the transconductance gm can be tuned linearly by varying the
bias voltage VG.
As indicated in Fig.3.1b, an OTA with dierential input and single-ended out-
put [62] can be obtained by combining four of these voltage-to-current converters of
Fig.3.1a.
VG1
Vss
VDD
VG4
Vin Iout
Vin+
Vin-
Iout
M1
M2
M3
M4
(a) (b)
Figure 3.1: Circuit diagram of (a) CMOS inverter [62] and (b) simple OTA
Based on the assumptions made regarding SPICE simulation, with VDD = -VSS =
5V and with bias voltages VG1 = VG4 = 4V , the performance parameters for the
simple CMOS OTA in Fig.3.1b are shown in Table 3.2.
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 69
Parameter Value Unit Transistor W L
(m) (m)
BW 169 MHz M1 20 2
PD 55 mW M2 58 2
THD -45 dB M3 20 2
TR 460-550 S M4 58 2
CL 1 pF VDD = 5V and VSS = -5V
Table 3.2: Performance parameters of simple OTA [62] with VG1 = VG4 = 4V
The above results demonstrate, that the simple OTA is suited for video-frequency
operation, since its bandwidth of 169MHz allows a viable lter frequency range of
17MHz. The OTA is tunable by varying the bias voltages VG1 and VG4 between 1V
and 5V, but its transconductance range is very limited (460S to 550S). A serious
drawback of this OTA is, that it requires two voltages for the biasing of the n-channel
and p-channel devices. Furthermore, the OTA in Fig.3.1b suers from considerable
non-linearity distortion (THD=-45dB), which limits the dynamic range of ensuing OTA
lter topologies, unless the dierential input voltage is restricted to very low levels (for
example, this OTA has been found to exhibit better THD of -54dB with 10mV input
voltage).
3.4.2 Linear CMOS OTA
It is well known, that OTA non-linearities are the main limitation on the dynamic range
of continuous-time lters. The OTA shown in Fig.3.2 improves the conventional source-
coupled dierential input stage by using source degradation, which takes advantage of
the drain-source conductance of CMOS transistors biased in the linear region. This
will generate an extra zero position, which is used to compensate the excess phase lag
introduced by the OTA parasitic poles. This technique developed by [65] has been
extended in the topology proposed by [44], which represents a source degeneration for
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 70
small signals and an additional internal feedback for large signals to increase the gm.
The output current of a simple source-coupled dierential pair is given by
Iout = (Vin+ Vin)
s2WIbL
(3.12)
It has been shown [65], that Eqn.3.12 can be approximated linearly for dierential
input voltages (Vin+ Vin) of 100mV amplitude.
By adding active loads as source degradation resistors, the portion of the input
signal that appears at the input transistors is reduced, thus improving linearity and
the dierential input swing.
Vin+ Vin-
VSS
VDD
Iout
M12 M13
M1
M4
M17 M18 M19 M21
M15
M14
M10
M3M5
M11
M16
M20
M2
M6 - M7 M8 - M9
Ib
Figure 3.2: Circuit diagram of linear OTA [65]
Based on the assumptions made regarding SPICE simulation, with VDD = -VSS
= 5V and with bias current Ib of 100A, the performance parameters for the linear
CMOS OTA in Fig.3.2 are shown in Table 3.3.
The results of Table 3.3 show that the bandwidth of the linear OTA has increased
greatly compared to the OTA in section 3.4.1. Also, the non-linearity distortion is
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 71
Parameter Value Unit Transistor W L
(m) (m)
BW 975 MHz M1,M2 100 2
PD 135 mW M3 M9 10 5
THD -55 dB M10, M15, M16 50 2
TR 125-243 S M12, M13 82 3
CL 1 pF M14 5 10
M11 4 10
M15 M21 10 2 VDD = 5V and VSS = -5V
Table 3.3: Performance parameters of linear OTA [65] with Ib = 100A
signicantly reduced, now exhibiting THD of -55dB with the same 100mV dierential
input voltage. However, the more complicated OTA structure requires higher power
dissipation of 135mW, compared to 55mW in the case of the simple OTA. Note that
the OTA is tunable, but its gm range is still very limited, having 125S gm 243S
with bias current Ib ranging from 10A to 100A.
In addition to source degeneration, a number of techniques have been proposed to
improve the linearity of the OTA without being sensitive to transistor mismatches.
For example, in [59, 79] matched non-symmetrical dierential pairs have been used to
generate additional current for the biasing of the normal dierential pair. Also, in [93]
improved linearity was achieved through a series of dierential pairs, such that the
input voltage is split in sections.
3.4.3 Widely Tunable CMOS OTA
As discussed earlier in this chapter, OTAs, unlike op-amps, are usually employed in
open loop congurations, requiring the amplier gain to be controlled internally rather
than by external circuitry. Hence, a wide gm tuning range is important for the external
control of lter parameters. The OTA shown in Fig.3.3 is a good example of a wide
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 72
bandwidth versatile voltage tunable OTA. In addition to its tuning capability, the
circuit exhibits improved linear operation originating from a cross-coupled dierential
input stage. (Fig.3.3).
It can readily be shown [89], that the output current Iout is dened by
Iout = 2kn(Vb VSS)(Vin+ Vin) = gm(Vin+ Vin) (3.13)
Note that gm goes to zero for Vb approaching VSS . Thus, this cross-coupled congu-
ration exhibits a perfectly linear transconductance of value gm = 2kn(Vb VSS), which
is tunable by varying the voltage V b. Linearity is maintained, as long as all devices
remain on, i.e. the linear dierential input range of the OTA in Fig.3.3 is limited by
jVin+ Vinj < 2 jVB + VTnj or jVin+ Vinj < 2 jVSS + VTnj (3.14)
whichever is smaller.
Vin+ Vin- Iout
VSS
VDD
Vb
M6
M5
M8
M7
M9
M10
M11
M12
M1 M3 M4 M2
M16
M15M13
M14
Figure 3.3: Circuit diagram of widely tunable OTA [89]
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 73
Based on the assumptions made regarding SPICE simulation, with VDD = -VSS =
5V and with bias voltage Vb = -1V, the performance parameters for the widely tunable
CMOS OTA in Fig.3.3 are shown in Table 3.4.
Parameter Value Unit Transistor W L
(m) (m)
BW 2.5 GHz M1 M4 40 2
PD 260 mW M5 M8 30 4
THD -50 dB M9 M12 30 2
TR 10-420 S M13 M16 28 2
CL 1 pF VDD = 5V and VSS = -5V
Table 3.4: Performance parameters of widely tunable OTA [89] with Vb = -1V
The results in Table 3.4 clearly show the improvement in bandwidth obtained from
the cross-coupled topology of the input stage. Although the bandwidth of 2.5GHz
favourably compares with high-frequency ltering applications, the high power dissi-
pation of the OTA limits its suitability for monolithic high-performance lters. The
OTA is gm tunable over a wide range between 10S gm 420S, if the bias voltage
Vb is varied between -4V and 0V.
Note, the large supply voltage requirements of the presented single-ended OTAs
(VDD = 5V and VSS = -5V) severely limit their use in portable system applications. For
those applications, the consideration of low-voltage OTAs is receiving increased atten-
tion. In [8], a folded-cascode operational transconductance amplier is described, which
operates from a 1V supply having 1MHz bandwidth while consuming only 120mW. The
circuit achieves low power operation by using a bulk-driven dierential input pair whilst
providing high output resistance with a bulk-driven current-mirror. Another OTA ca-
pable of operating from voltages as low as 1V is presented in [101]. It uses partial
positive feedback to enhance the overall output gain of the OTA.
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 74
3.5 Multiple-Output OTAs
So far, this chapter has discussed only single-ended OTAs. In many applications how-
ever, OTAs with more than one current output (MO-OTAs) are required. A simple
way of obtaining MO-OTA structures is to combine the dierential inputs of two or
more single-ended OTAs such that their outputs realise the desired current directions
(see Fig.3.4).
Vb
Vin
gm Io1
gm Io2
Vb
Figure 3.4: Combining two single-ended OTAs into one MO-OTA
This technique, which was rst introduced by [69, 85] requires, that the transistors
inside each OTA are perfectly matched. However, such realisations generally lead
to non-symmetrical layout and very poor common-mode rejection. For monolithic
implementations, it is hence advantageous to develop OTAs which inherently provide
multiple current outputs.
As mentioned in the introduction, MO-OTAs are commonly associated with the
current-mode approach to OTA-C lter design (for more information, see chapter 5).
The term MO-OTA encompasses a range of possible OTA topologies, including dual-
output OTAs with two current outputs and triple-output OTAs with three current
outputs [3, 4]. Note, that this classication does not relate to the direction of the
output currents, which may ow either into the active device (i.e. current direction
designated negative) or out of the active device (i.e. current direction designated
positive), depending on the requirement of the lter topology. The number of output
current replicas obtainable from a device is generally not limited. The generation of
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 75
current replicas in integrated circuits is relatively inexpensive since it is based on the
utilisation of multiple output current mirrors and typically requires only two to four
additional transistors [69].
However, a special variety of MO-OTAs are used in integrated voltage-mode l-
ter design, where lter topologies are implemented as fully-balanced structures to re-
duce common-mode noise coupling and improve the dynamic range of the lter (see
chapter 4). These MO-OTAs are characterised by their completely symmetrical ar-
chitecture and their two dierential output currents and are commonly referred to as
fully-balanced OTAs.
In this section, four MO-OTAs have been chosen out of the numerous reported
topologies [41, 53, 58, 69], each one focusing on one distinct design advantage:
1. Simplicity
2. Linearity
3. Tunability
4. Multiple Outputs
3.5.1 Simple Fully-Balanced CMOS OTA
An OTA implementation combining design simplicity and very wide bandwidth has
been described in [57, 58]. It is based on the well known CMOS inverter, operates from
a single supply and due to its lack of internal nodes it realises a linear fully-balanced
OTA having >1GHz bandwidth. It utilises the square law principle but has no internal
nodes, resulting in good linearity and very large bandwidth. The circuit diagram of
this OTA is shown in Fig.3.5.
Assuming all transistors operate in saturation, the dierential output current can
be written as [57]:
Iout = gm(Vin+ Vin) = (VDD VTn VTp)qnp(Vin+ Vin) (3.15)
Hence, the dierential transconductance gm is linear, even with non-linear inverters,
i.e. n 6= p. Furthermore ,the gm is voltage tunable with the supply voltage VDD.
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 76
VDD VDD VDD VDD
VDD
VDD
Vin+
Vin-
Iout-
Iout+
M8
M1
M2
M3
M4
M5 - M7
M6 - M8
M9 - M10
M11 - M12
Figure 3.5: Circuit diagram of high-frequency OTA [58]
Based on the assumptions for SPICE simulation and with VDD = 3.3V, the perfor-
mance parameters for the simple CMOS OTA in Fig.3.5 are shown in Table 3.5.
Parameter Value Unit Transistor W L
(m) (m)
BW 1.4 GHz M1, M3 58 1.2
power 28 mW M2, M4 20 1.2
THD -53 dB M5, M7 58 1.2
TR 50-350 S M6, M8 20 1.2
CL 1 pF M9, M11 58 1.2
M10, M12 20 1.2 VDD = 3.3V
Table 3.5: Performance parameters of high-frequency OTA [58]
This fully-balanced OTA oers a number of attractive properties for high-performance
integrated lter design. Firstly, it exhibits very wide bandwidth of 1.4GHz. Secondly,
its low power consumption of 28mW and low supply voltage of 3.3V make this OTA
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 77
ideally suited for portable system applications. Furthermore, its low THD enables ap-
plication in high-performance ltering implementations. However, a serious drawback
of the OTA in Fig.3.5 is its limited tuning capability. Due to its simple and repeti-
tive structure, this OTA is tunable only by varying the supply voltage VDD. In some
applications, it may not be possible to alter the supply voltage over a wide range,
although the above simulations show that gms between 50S and 350S are possible,
if the supply voltage is varied between 1.5V and 3.3V.
3.5.2 Linear Fully-Balanced CMOS OTA
The schematic of a very linear fully-balanced OTA is shown in Fig.3.6. Transistor M2
is operated in the linear region (i.e. it is used as a voltage-controlled resistor) and
hence degenerates the input dierential pairM1AM1B, which will linearise the OTA,
as explained in section 3.4.2. Symmetrical bias currents are provided by the transistors
M3A and M3B. The dierential output is taken directly on the drains of M1A M1B.
This limits the maximum dierential output amplitude to about jVTpj, but allows the
use of just two current branches per OTA and hence reduces power consumption. The
output common-mode voltage is regulated by a common-mode feedback loop formed
by M4A, M4B, M5A and M5B.
Based on the assumptions made regarding SPICE simulation, with VDD = 5V and
with bias voltages Vb1 = Vb2 = 4V and VC = -2V, the performance parameters for
the linear CMOS OTA in Fig.3.6 are shown in Table 3.6.
The above results clearly show the very low THD of -58dB, which make the fully-
balanced OTA in Fig.3.6 desirable in high-performance applications. The OTA has
low power consumption of 30mW, which is comparable to the OTA in section 3.5.1.
Together with its single supply voltage requirement, this makes the OTA in Fig.3.6
suited for portable system applications. The OTA is gm tunable over a small range
between 650S gm 675S, if the bias voltages Vb1 = Vb2 are varied between
1V and 5V. As with the single-ended OTA in Fig.3.1, a serious drawback of this OTA
is, that it requires two bias voltages, Vb1 and Vb2 for the biasing of the n-channel
and p-channel devices, which clearly increases the complexity of the additional biasing
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 78
Vin+ Vin-
gnd
Vb2
VDD
Iout+Iout-
Vc
Vb1
M3A M3B
M2
M1BM1A
M4BM4A
M5BM5A
Figure 3.6: Circuit diagram of low-power OTA [41]
Parameter Value Unit Transistor W L
(m) (m)
BW 926 MHz M1A, M1B 175 2
PD 30 mW M2 200 2
THD -58 dB M3A, M3B 175 2
TR 650-675 S M4A, M4B 60 2
CL 1 pF M5A, M5B 60 2 VDD = 5V
Table 3.6: Performance parameters of low-power OTA [41] with Vb1 = Vb2 = 4V
circuitry.
3.5.3 Tunable Fully-Balanced CMOS OTA
A more recent design of an fully-balanced OTA is shown in Fig.3.7. It is based on
the triode region MOSFET technique presented in [44] and was rst introduced in
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 79
[53]. The OTA operates o a single +5V supply, it is voltage-tuneable over a wide
transconductance range and has a bandwidth of >100MHz.
The input devicesM1 andM2 translate the dierential input voltage toM7 andM8
which are biased in the triode region. These devices determine the gm value and are
designed to have a signicant size for improved matching of VT and kn. The current
through M7 and M8 is dierentially mirrored through M3, M9 and M4, M10.
The overall transconductance of the OTA can be expressed as [53]:
gm = k0Cox
WL
7;8
2(Vcon VCM VTn) (3.16)
where Vcon is the control voltage, VCM is the common-mode voltage level and VTn
is the n-channel threshold voltage.
Vin+ Vin-
Iout+
VDD
Vcm
Iout-Vcon
Vb VbM11 M7
M1
M6M5
M9 M3 M4 M10
M12
M2M8
gnd
M15 M16
M13 M14
M17 M18
Figure 3.7: Circuit diagram of tunable OTA [53]
Based on the assumptions made regarding SPICE simulation and with VDD = 5V,
Vb = 4V, VCM = 2.5V and Vcon = 4V, the performance parameters for the tunable
CMOS OTA in Fig.3.7 are shown in Table 3.7.
The fully-balanced OTA in Fig.3.7 oers wide gm tuning range between 140S and
360S, if the bias voltage Vb is varied between 1V and 5V. Although its gm range is
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 80
Parameter Value Unit Transistor W L
(m) (m)
BW 1.2 GHz M1 M2 48 1.2
PD 85 mW M3 M4, M9 M10 12 1.2
THD -48 dB M5 M6 120 1.2
TR 140-360 S M7 M8 20 3
CL 1 pF M11 M12 72 1.2
M13 M16 70 1.2
M17 M18 24 1.2 VDD = 5V
Table 3.7: Performance parameters of tunable OTA [53] with Vb = 4V
only slightly wider than that of the OTA in Fig.3.5, the OTA in Fig.3.7 achieves its
tunability by varying an external bias voltage rather than the supply voltage. However,
the circuit has increased power consumption of 85mW compared to 30mW of the OTA
in Fig.3.6 and it has worse THD of -48dB compared to -58dB of the OTA in Fig.3.6.
3.5.4 Multiple-Output CMOS OTA
A voltage-tunable CMOS multiple-output OTA is show in Fig.3.8. It is based on
the topology given in [69]. It consists of a source-coupled dierential input pair with
identical MOS devices (M1-M2) operating in the saturation region, where the output
current is replicated using current-mirrors. The biasing of the input stage is controlled
by the gate voltage of transistor M3. The gm of the OTA is tunable by an external bias
voltage. Note, that while in Fig.3.8, three output current mirrors have been allocated
to the MO-OTA structure, no limit exists for the number of current replicas obtainable
from this OTA. Also note, that the current replicas of the OTA can be either negative
or positive, depending upon which side of the amplier load the replica is taken.
Based on the assumptions made regarding SPICE simulation, with VDD = 5V and
VSS = -5V and Vb = 4V, the performance parameters for the tunable CMOS OTA in
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 81
Vin+ Vin-
Iout1 Iout2Iout3
Vb
gnd
VDD
M4 M5 M7M11M10M8
M1 M2
M3
M14
M13
M12
M15
M16
M17
M6 M9
Figure 3.8: Circuit diagram of triple-output OTA [69]
Fig.3.8 are shown in Table 3.8.
Parameter Value Unit Transistor W L
(m) (m)
BW 96 MHz M1-M3 64 2
PD 175 mW M4-M11 188 2
THD -63 dB M12-M17 64 2
TR 130-220 S
CL 1 pF VDD = 5V and VSS = -5V
Table 3.8: Performance parameters of triple-output OTA [69] with Vb = 4V
These results show, that the OTA in Fig.3.8 achieves good THD of -63dB and wide
gm tuning range of 130S to 220S if Vb is varied between -3V and +5V. However, the
OTA bandwidth of 96MHz is very limited and allows video-frequency lter operation
CHAPTER 3. COMPARATIVE STUDY OF CMOS OTAS 82
only up to 9.6MHz. This limited bandwidth could be improved, e.g. using cascoded
current-mirrors. The main advantage of this topology is its versatility and exibility
regarding the number and the direction of output currents.
3.6 Concluding Remarks
Numerous designs of OTAs have been investigated and compared with respect to perfor-
mance criteria including bandwidth, THD, power consumption and tunability. Based
on the simulation results, this comparison allows to identify single-ended and multiple-
output OTAs for given ltering tasks in this thesis:
Firstly, for the realisation of voltage-mode monolithic lters, fully-balanced OTAs
are required. Evaluating the above comparison, the OTA shown in Fig.3.5 is the
most suitable active device for the implementation of high-performance lters because
it exhibits a number of attractive features including very wide bandwidth, low power
dissipation and single low-voltage supply operation. This device will be utilised further
in chapter 4.
Secondly, in the area of current-mode signal processing, OTAs with more than two
current outputs are required to provide feedback. The MO-OTA shown in Fig.3.8 repre-
sents a versatile structure to obtain multiple current outputs combined with structural
simplicity. This MO-OTA operates from 5V supply, exhibits good linearity and has
the advantage that it allows easy conguration of the transistor-level topology with
respect to the number and direction of output currents. It will be utilised later in this
thesis (chapters 5 and 6).
Chapter 4
Voltage-Mode CMOS OTA-C
Video-Filter
4.1 Introduction
In chapter 2, analytical aspects to the design of voltage-mode lters and sinc(x)-
equalisers have been discussed. Operational simulation has been identied as the most
ecient approach to design ladder-based OTA-C lters. Also, in chapter 3, transistor-
level OTA structures have been investigated and a linear device has been specied (see
Fig.3.5), suitable for silicon implementation of an analogue lter system.
The aim of this chapter is to examine, how continuous-time video-lters based on
the OTA-C approach operate in practice. This will be demonstrated with respect to
a monolithic analogue video-lter system comprising a 5th-order elliptic lter and a
biquadratic sinc(x)-equaliser. Furthermore, the chapter will focus on the translation of
simulation results into physical design, i.e. a transistor layout description of the system.
It will be fabricated using the 0.8m double-metal double-poly n-well CMOS process
provided by the AMS foundry [1]. Section 4.2 will present the transistor-level design of
the video-lter including a full system specication and simulated results. Also, section
4.3 will introduce the layout design ow with respect to CMOS implementation of the
video-lter, while section 4.4 will focus on the testing of the fabricated device and
discuss the measured results.
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 84
4.2 Video-Filter Design Specications
The requirements of a typical video-lter are best re ected in the specications of
the CCIR 601 lter, which are dened by the ITU (International Telecommunication
Union) [98]. The lter is commonly used as reconstruction lter in the luminance chan-
nel of digital PAL (phase-alternating line) video systems. This application requires,
that the lter has bandwidth of 5.75MHz and achieves stopband attenuation of 40dB
at 21.5MHz. In addition, it requires passband ripple of 0.1dB and low group-delay
variation of 5ns [74]. In order to meet this group-delay characteristic without the need
for group-delay equalisers which will signicantly increase the system complexity, it is
possible to increase the lter bandwidth to 10MHz without compromising its perfor-
mance as reconstruction lter. In this application, it is primarily important that the
stopband specication is met.
The use in digital video applications demands, that the analogue video signal is sam-
pled at four times the subcarrier frequency of 3.375MHz, making the standard D/A
converter sampling frequency FS = 13.5MHz. With the advancement in high-resolution
D/A converters, it is becoming increasingly cost-eective to sample the analogue sig-
nal at integer multiples of 13.5MHz and hence improve the system performance by
reducing the D/A converter quantisation error. Modern digital systems employ FS of
27MHz, which will also be assumed in this chapter. Because the ratio between D/A
converter sampling frequency and lter passband edge is small, sinc(x)-correction has
to be included with the system. The complete specication of the analogue video-lter
system is given in Table 4.1.
4.2.1 Elliptic Filter Design
Chapter 2, section 2.2.2 has shown that operational simulation is the most ecient
approach to design ladder-based OTA-C all-pole lters. However, it is well known
that high-performance video lters require elliptic lter structures. It is not dicult to
modify ladder all-pole characteristics into an elliptic lter response, since oating ca-
pacitors can be included at the inputs of integrators which correspond to the prototype
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 85
Filter DC gain 0dB 2%
End of passband 10.0MHz 1%
Start of stopband 21.5MHz 1%
Stopband attenuation 40dB 2%
Passband ripple 0.1dB 2%
Group-delay ripple 5ns 1%
Equaliser DC gain 0dB 2%
D/A converter sampling rate 27MHz
Maximum amplitude boost 2.5dB 1%
Table 4.1: Video-lter specications [98]
inductors, as demonstrated in [76]. For comparison between all-pole ladder lters and
elliptic ladder lters refer to Fig.2.2 and Fig.4.1a respectively. Once the topology is
established, standard tables exist to determine the appropriate lter order [76]. These
tables indicate, that a 5th-order elliptic lter will satisfy the attenuation requirements
in Table 4.1. The circuit diagram of a 5th-order elliptic lter prototype with component
values to meet the above specications is shown in Fig.4.1a.
So far, the design methods have generated only single-ended lter topologies (i.e.
having one signal input and one signal output with respect to ground). Based on the
Fig.2.7 in section 2.2.2, Fig.4.1b shows the corresponding single-ended elliptic OTA-C
lter, now having two additional oating inductors (C6 and C7). However, monolithic
implementations based on the OTA-C approach suer from low dynamic range and
power supply rejection ratio and hence require fully-balanced topology (i.e. a positive
and negative signal path having completely symmetrical layout with respect to ground),
such that any noise or parasitic signals will couple equally into both signal paths as
common-mode signals [44, 85, 91].
Well dened procedures exist to derive a fully-balanced circuit implementation from
single-ended designs [91]. They are based on the duplication of the circuit structure
into its mirror image with respect to ground. Corresponding transconductances can
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 86
be combined, if their signal paths are crossed. This technique will generally lead to a
fully-balanced topology with only few more OTAs then its single-ended counterpart.
Fig.4.1c shows the block-diagram of a fully-balanced 5th-order elliptic lowpass lter
based on the lter in Fig.4.1b. It is based on 13 dierential-input, dierential-output
OTAs, all having equal transconductance value.
3.0pFC71.0pFC6
Vin
Vout1.3mS
C2 13.3pF
1.3mS 1.3mS 1.3mS 1.3mS 1.3mS 1.3mS
C1 5.9pF C5 4.3pFC4 10.8pFC3 15.2pF
(a)
(b)
(c)
Vin RL
RS
L2
C6
L4
C7C1 C3 C5125.2pF
18.8pF
1.2µH
248.7pF
55.7pF
0.9µH
96.9pF
75Ω 75Ω
Vout1.3mS
C1a
C1b
C2a
C2b
C3a
C3b
C4a
C4b
C5a
C5b
2 3 4 5 6 7 8 9 10 11 12 13
5.9pF
5.9pF
13.3pF
13.3pF
15.2pF
15.2pF
10.8pF
10.8pF
4.3pF
4.3pF
3.0pF
3.0pF
C7a
C7b
1.0pF
1.0pFC6b
C6a
1.3mS 1.3mS 1.3mS 1.3mS 1.3mS 1.3mS 1.3mS1.3mS1.3mS 1.3mS 1.3mSVin 1.3mS
1
Figure 4.1: Video-lter circuit diagram (a) passive prototype, (b) single-ended design
and (c) fully-balanced design
All capacitor values are obtained from standard lter tables [108] and have been
denormalised to FC = 10MHz such that the smallest capacitor equals 1pF. This value
was chosen in order to keep the lter capacitors at least one order of magnitude bigger
than any parasitic capacitances that are to be expected from the CMOS process. Under
this assumption, the denormalisation requires gm of 1.3mS for all 13 lter OTAs.
Because Fig.4.1c is a direct equivalent of the equally terminated passive ladder lter
in Fig.4.1a, it has insertion loss of 6dB. However, the specication requires that the
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 87
video-lter has insertion loss of 0dB. A simple method to compensate for this insertion
loss is to increase the transconductance value of OTA1 such that it has twice the gm
of the lter OTAs [76], which will provide additional 6dB DC gain.
Each of the fully-balanced block-diagram OTAs are implemented with the OTA
topology identied in chapter 3 section 3.5.1, which was rst introduced by [58]. In
addition to its wide-bandwidth capability, the OTA has low power dissipation and
operates from a single 3.3V supply, making it ideally suited for monolithic implemen-
tations. A complete transistor-level circuit diagram of the 5th-order elliptic lter section
is shown in Fig.4.5a at the end of this section.
The transconductance of the fully-balanced OTA in section 3.5.1 is a function of
the CMOS transistor W over L ratio, which is dened by the following equation:
gm = (VDD VTn VTp)qnp = (VDD VTn VTp)
"0"rtox
snWn
Ln
pWp
Lp(4.1)
where n = 0:058m2=V s and p = 0:02m2=V s are the mobilities of the charge
carriers in the n and p material, "0 = 8:854 112F=m is the permittivity of free space
and "r = 3:9F=m is the relative permittivity of silicon dioxide.
Utilising the transistor model parameters of Table 3.1 for the 0.8m AMS CMOS
process, it is found that the threshold voltages are VTn = 0:83V and VTp = 0:82V
and that the thickness of the gate oxide tox equals 15:5 109m. Under the assumption
that the n-channel and p-channel transistors are perfectly matched (i.e. n = p), it is
seen that Wp = 2:9Wn. Eqn.4.1 can be solved for gm = 1.3mS to give Wn=Ln = 34.
Based on a minimum channel length parameter L of 1.2m, the lter transistor
dimensions are summarised in Table 4.2.
NMOS PMOS
gm W L W L
OTAs 1.3mS 40.8m 1.2m 117.2m 1.2m
Table 4.2: Video-lter transistor dimensions
Using the capacitor values of Fig.4.1c and the transistor dimensions of Table 4.2,
Fig.4.2 shows a comparison between the frequency response simulation of the passive
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 88
ladder prototype lter of Fig.4.1a and the transistor-level frequency response simulation
of the 5th-order fully-balanced active operational simulation of Fig.4.5.
10.0MHz 20.0MHz 30.0MHz 40.0MHz 50.0MHz 60.0MHz0.1MHz
Frequency
-0
-20
-40
-60
-80
-100
-120
dB
(b)
(a)
Figure 4.2: Simulated frequency response of video-lter (a) passive prototype and (b)
fully-balanced active
This simulation clearly shows, that both realisations meet the video-lter speci-
cations of Table 4.1. However, the lter notch positions are shifted from 21.8MHz and
33.4MHz in the case of the passive video-lter to 22.8MHz and 35.8MHz respectively in
the case of the active simulation. Also, the initial -6dB insertion loss is now reduced to
-5dB. These deviations in the frequency response can be attributed to the in uence of
transistor-level parasitics, especially the OTA input capacitance. In order to attempt
an estimation of the behaviour of the fabricated system, worst case analysis was carried
out on SPICE. Assuming typical values for the CMOS process [1] with 20% variation in
the capacitor values Ci, worst case analysis shows that the video-lter is little aected
by these variations, resulting in a shift of the notch positions of only 5%.
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 89
4.2.2 Sinc(x)-Equaliser Design
Section 4.1 has shown, that a sinc(x)-equaliser has to be included with the lter section
in order to meet the amplitude response specication in Table 4.1. Chapter 2, section
2.3 has introduced two novel sinc(x)-equaliser structures and it has been shown that
equaliser 2 is preferred in monolithic implementations, because its !0 and Q parameters
can be easily and independently tuned.
The ltering system discussed here will be used to reconstruct video signals which
have been sampled at 27MHz, making the sampling ratio = 2.7 as indicated in Table
4.1. Based on the equaliser 2 structure, the video sinc(x)-equaliser is realised as fully-
balanced topology, following the same synthesis procedure as the lter section. The
fully-balanced circuit diagram of the video sinc(x)-equaliser is shown in Fig.4.3.
C2a
C2b
Vout
C1a
C1b
1.3mSVin
16.5pF
16.5pF
12.4pF
12.4pF
1.3mS 1.3mS 1.3mS 1.3mS 1.3mS 1.3mS2.3mS
gm5
Figure 4.3: Video sinc(x)-equaliser circuit diagram
As with the lter section, each of the fully-balanced block-diagram OTAs are im-
plemented with the OTA presented in section 3.5.1. A complete transistor-level circuit
diagram of the biquadratic sinc(x)-equaliser section is shown in Fig.4.5b at the end of
this section.
The normalised sinc(x)-equaliser component values are found from Table 2.12 for
= 2.7. These values are denormalised such that the gm of the equaliser OTAs are
equal to the lter gm, hence facilitating the layout stage through use of repetitive cells.
Following the design procedure for the transconductance values outlined in the previous
section, the sinc(x)-equaliser W over L ratio of the remaining OTA5 is also given in
Table 4.3.
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 90
NMOS PMOS
gm W L W L
OTA5 2.3mS 92.6m 1.2m 267.7m 1.2m
OTAs 1.3mS 40.8m 1.2m 117.2m 1.2m
Table 4.3: Video sinc(x)-equaliser transistor dimensions
Using these values, the block diagram and transistor-level frequency response sim-
ulation of the video sinc(x)-equaliser are shown in Fig.4.4.
20MHz 40MHz 60MHz 80MHz 100MHz100kHz
Frequency
10
0
-10
-20
-30
-40
dB
(b)
(a)
Figure 4.4: Simulated frequency response of video sinc(x)-equaliser (a) block-diagram
and (b) transistor-level
This simulation clearly shows that the transistor-level sinc(x)-equaliser exhibits gain
peaking of 4.5dB at the same frequency of 19MHz as the theoretical block-diagram de-
sign. As with the lter section, an estimation of the behaviour of the fabricated system
was attempted by applying worst case analysis to the sinc(x)-equaliser in SPICE. As-
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 91
suming typical values for the CMOS process [1] with 20% variation in the capacitor
values Ci this analysis shows, that the sinc(x)-equaliser is not seriously aected by
variations in the capacitor values, resulting in a frequency shift of the gain peak of
only 30% which can be compensated for by circuit tuning.
4.2.3 Video-Filter Design Summary
While the specications in Table 4.1 have focused on a behavioural description of the
system, the following table will summarise the transistor-level characterisation and
simulation results of the video-lter system.
Filter SPICE models and technology level 6, 0.8m AMS
Capacitor range 1.0pF to 15.2pF
Number of transconductance ampliers 13
Transistor count per OTA 12
Total transistor count 156
Transistor dimension range Lmin = 1.2m / Wmax = 117.2m
Supply voltage 3.3V - 0V
Power consumption 95mW
Equaliser SPICE models and technology level 6, 0.8m AMS
Capacitor range 12.4pF to 16.5pF
Number of transconductance ampliers 8
Transistor count per OTA 12
Total transistor count 96
Transistor dimension range Lmin = 1.2m / Wmax = 267.7m
Supply voltage 3.3V - 0V
Power consumption 58mW
Table 4.4: Video-lter simulation results summary
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 92
p a dp a d
C 3 a C 3 b
C 4 a C 4 b
C 5 a C 5 b
C 7 a C 7 b
p a dp a d
C 1 a C 1 b
C 2 a C 2 b
C 6 a C 6 b
p a dp a d
p a dp a d
p a dp a d
C 1 bC 1 a
C 2 a C 2 b
O T A 5
(a ) (b )
Figure 4.5: Video-lter transistor-level circuit diagram (a) lter section and (b) sinc(x)-
equaliser section
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 93
4.3 Video-Filter Layout
After successful simulation of the video-lter system, the next step is its IC layout.
Layout deals with the realisation of a given circuit topology on the surface of a semicon-
ductor die. It links the electrical properties of a network to the physical characteristics
of the patterned layers created during the fabrication process. This involves translating
the circuit schematic into physical design in the form of dierent layers representing
the various steps of the photolithographic fabrication process. Photolithography is a
technique in which selected portions of a silicon wafer can be masked out, so that the
next processing step is only applied to the remaining areas.
Every material layer in an integrated circuit is described by a set of geometrical
objects of specied shape and size. These objects are dened with respect to each
other on the same layer and also with reference to geometrical objects that lie on other
layers both above and below. It is therefore possible to say that that a layout drawing
represents the top view of the chip itself.
4.3.1 Design Approach
The design approach most commonly adopted in analogue IC implementations is re-
ferred to as full-custom bottom-up design. The name implies, that full-custom design
does not rely on the use of pre-fabricated standard cells, but determines the system
functionality by the setting of transistor ratios at the bottom level of the design.
As Fig.4.6 indicates, after successful SPICE simulation of the system, the transistor
channel width (W) and channel length (L) dimensions are available from the netlist
(see Tables 4.2 and 4.3. These dimensions are the starting point for the full-custom
layout of the system. They are used to geometrically dene the n-channel and p-
channel transistors, which will be explained in sections 4.3.2.1 and 4.3.2.2. The design
ow progresses to combine the transistors into OTA cells according to their circuit
diagrams (see Fig.3.5) using metal interconnects. The OTA building blocks can then
be connected on a system level to realise the lter and sinc(x)-equaliser functionality
according to Fig.4.5a and b respectively.
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 94
system cells
OTA cells
transistor cellssimulation
core cellperipheral
cells
top-levelchip layout
CMOSfoundry
design rulecheck
layout versusschematic
CMOSdesign rules
transistor W/Lspecifications
Figure 4.6: Bottom-up design approach
Based on the oorplan (see section 4.3.3), the system cells are then combined to
form the IC core. On the top level of the design, the core is nally combined with pre-
designed peripheral cells which include the input and output pads and process specic
information is added, such as layer test patterns, tuning forks and the scribe-line border
to shorten the metal-layers to the substrate.
4.3.2 Integrated Circuit Physical Design
The technological advantages of CMOS design over other semiconductor processes have
already been claried in chapter 1. When designing OTA-C lters in CMOS technology,
the most important structures to be dened during the layout process are the n-channel
and p-channel MOSFET transistors and the capacitors. The following sections will give
a brief overview of their denitions in the 0.8m AMS CMOS process.
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 95
4.3.2.1 n-channel MOSFET
The basic features of an n-channel MOSFET are the gate, drain and source terminals
together with the heavily doped n-implant. As indicated in the cross section of Fig.4.7a,
the layout of n-channel MOSFET comprises the following layers:
1. DIFF active area denition
2. NPLUS drain and source implants
3. POLY1 polycrystal silicon gate area
4. MET1 drain and source contacts
5. CONT contacts between MET1 and NPLUS
This well understood cross-section view of an n-channel MOSFET has to be trans-
lated into a top-view of the transistor, which identies all the necessary production
masks.
L
W
MET1
CONT
DIFF
POLY1
NPLUS
NPLUS
CONT POLY1
DIFF
P - SUBSTRATE
MET1
(a) (b)
Figure 4.7: n-channel MOSFET layout (a) cross-section view and (b) top-view
Note, in all layout drawings the oxide layers which separate the denition layers and
the substrate are implied. The presence of oxide is acknowledged only by including a
contact cut which allows theMET1 to be electrically connected to the NPLUS implants.
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 96
4.3.2.2 p-channel MOSFET
A p-channel MOSFET has the same geometrical structure as an n-channel device,
but with reversed polarities. In CMOS technology with p-type substrate, this means
that n-type regions for the bulk of the p-channel MOSFET must be provided. This is
accomplished by creating n-well sections in the substrate. Due to the smaller mobility
of charge carriers in a p-channel MOSFET, they usually occupy bigger silicon areas.
As indicated in the cross-section view of Fig.4.8a, the layout of n-channel MOSFET
hence comprises the following layers:
1. NTUB denition of the well
2. DIFF active area denition
3. PPLUS drain and source implants
4. POLY1 polycrystal silicon gate area
5. MET1 drain and source contacts
6. CONT contacts between MET1 and PPLUS
(a) (b)
L
W
MET1
CONT
DIFF
POLY1
PPLUS
NTUB
PPLUS
CONT POLY1
DIFF P - SUBSTRATE
MET1
NTUB
Figure 4.8: p-channel MOSFET layout (a) cross-section view and (b) top-view
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 97
4.3.2.3 CMOS Capacitors
In addition to n-channel and p-channel transistors, the third important aspect in full-
custom CMOS design is the layout of capacitors for the realisation of OTA-C lters.
In modern CMOS technology, capacitances are achieved by using polysilicon as plates
and silicon dioxide as dielectric. The structures correspond to a parallel-plate element
with capacitance given by:
C = "0"rA
tox(4.2)
where "0 is the permittivity of free space, "r is the relative permittivity of silicon
dioxide (3.9), A is the area of the plates and tox is the thickness of the silicon dioxide.
Using Eqn.4.2, the necessary capacitor areas for the 5th-order elliptic lter and the
sinc(x)-equaliser can be calculated, based on process oxide thickness of 15.5nm. The
resulting areas are given in Table 4.5 and Table 4.6 respectively.
C1 C2 C3 C4 C5 C6 C7
value 5.9pF 13.3pF 15.2pF 10.8pF 4.3pF 1.0pF 3.0pF
area 8389m2 19016m2 21774m2 15390m2 6130m2 552m2 1680m2
Table 4.5: Video-lter capacitor areas
C1 C2
value 16.5pF 12.4pF
area 23498.1m2 17675.6m2
Table 4.6: Video sinc(x)-equaliser capacitor areas
The capacitor values are subject to fabrication inaccuracies mainly due to errors in
the oxide thickness. With the CMOS process used [1], absolute accuracy of 6% for
tox is possible. In most cases, this error corresponds to a thickness gradient and its
rst-order eect can be cancelled by matched elements that are arranged in a common
centroid fashion [26]. Also, to minimise undercut eects, it is paramount to keep the
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 98
CONT
POLY1
MET1
CAPACITOR 1 CAPACITOR 2 CAPACITOR 3
Figure 4.9: Layout of capacitors as multiples of unit capacitance having capacitor ratio
4 : 7 : 3
area-to-perimeter ratio of the matched capacitor plates constant. For these reasons, it
is commonly accepted to lay out capacitors as (rational) multiples of a unit capacitance,
which can be duplicated and connected in parallel to realise a given circuit capacitance.
This is illustrated in Fig.4.9, where three capacitors are realised having a ratio of 4 : 7 : 3
between them.
4.3.3 Floorplanning
The term oorplanning entails the description of the two-dimensional arrangement of
circuit components on the semiconductor die. While oorplanning is a major consid-
eration in complex digital and mixed-signal designs, it is a comparatively simple issue
in this analogue design. Mainly, three considerations have to be taken into account:
Firstly, arranging the system component such that the total silicon area is minimised.
Secondly, providing sucient external access to the system components for testing of
the system functionality. And thirdly, to allow easy routing of core connections to the
pad ring.
Because the OTA-C video-lter represents a prototype and individual testing of
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 99
system components is desired, three sections were implemented separately on the IC,
each possessing individual input and output pads as indicated in Fig.4.10:
1. 5th-order elliptic lter, comprising OTA2 to OTA13 according to Fig.4.5a
2. Video sinc(x)-equaliser according to Fig.4.5b
3. Filter OTA1 (i.e. the gain OTA) having twice the transconductance value of the
remaining lter OTAs
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
sinc(x)-equaliser
gainOTA
Filter
GND
Vdd
Figure 4.10: Video-lter microchip oorplan
4.3.4 Design Rule Check
During the layout of the IC, design rules have to be followed which are imposed by
the CMOS foundry to ensure reliable fabrication of the semiconductor structures and
to allow for any misalignment of the lithographic masks by ensuring a minimum over-
lap between layers. In particular, the rules protect the design against violations of
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 100
minimum dimensions (width), minimum spacing between geometries (spacing), min-
imum distance by which one layer has to be surrounded by another (surround) and
the minimum length by which one layer has to extend from another (extend). Note
that violating a design rule will result in a non-functional circuit. The most important
design rules for the 0.8m n-well CMOS process provided by the AMS foundry [1]
are summarised in Table 4.7. The layout software [35] provides automated checking
of these design rules during the layout process . The design rule check will highlight
every violation of these rules which have to be rectied manually.
4.4 Video-Filter Implementation and Testing
After the layout has been completed, a netlist description is extracted from the layout
le which can be compared to the original simulation netlist. The process of checking
the identity of the two netlists is known as layout-versus-schematic (LVS) and is the last
step in the bottom-up design ow (see Fig.4.6) . Provided the two netlist are identical,
the layout description is sent out to the CMOS foundry for fabrication. Fig.4.11 shows
a chip microphotograph of the fabricated chip, now encased in a 16 pin DIL package
and providing the bonded connections indicated on the oorplan (Fig.4.10). Some of
the building blocks, like the padring, the capacitor arrays and the areas occupied by
transistors, can clearly be identied.
4.4.1 Test Environment
The fabricated chip represents a prototype and will not be tested in-situ together
with other system components. Instead, its functionality will be assessed in a specic
test environment, consisting only of the lter chip and a network analyser which will
provide graphical representations of the system's frequency response. Owing to the
fully-balanced circuit design of the chip, the single-ended input signal from the net-
work analyser has to be converted to fully-balanced signals. This is best achieved by
a set of dierential line drivers and receivers which are normally employed to drive
high-frequency signals over twisted pair lines. A number of components are commer-
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 101
rule layer 1 layer 2 width spacing surround extend(m) (m) (m) (m)
3.1 NTUB 5 53.2 DIFF 2 1.83.4 POLY1 0.8 13.5 NPLUS 1.6 1.63.6 PPLUS 1.6 1.63.7 POLY2 1.6 1.83.8 CONT 1 1.23.9 MET1 1.4 13.10 VIA 1.2 1.63.11 MET2 1.6 1.23.12 PAD 15 254.2.1 NDIFF PPLUS 0.84.2.2 NDIFF NTUB 34.3.1a PDIFF PPLUS 0.84.3.1b PDIFF NPLUS 0.84.3.2 PDIFF NTUB 34.4.1 POLY1 DIFF 0.44.5.3 POLY2 DIFF 1.24.5.4 POLY2 PPLUS 0.64.5.5 POLY2 POLY1 1.4 1.44.8.4 CONT MET1 0.24.8.5 CONT DIFF 0.54.8.6 CONT POLY1 0.44.8.7 CONT POLY2 0.64.8.8 DIFFCON POLY1 0.84.8.9 DIFF POLY1CON 0.84.8.10 DIFFCON PPLUS 0.84.8.11 DIFFCON PPLUS 0.84.8.12 POLY1CON POLY2 1.64.8.13 POLY2CON POLY1 1.64.9.3 VIA MET1 0.24.9.4 VIA MET2 0.34.9.5 VIA CONT 1.24.9.6 VIA POLY1 1 14.9.8 VIA POLY2 1.2 1.25.1.1 GATE 0.85.1.3 GATE POLY1 0.65.1.4 GATE DIFF 1.46.1.4 PAD MET1 20 56.1.5 PAD VIA 13 36.1.6 PAD MET2 20 56.1.7 PADVIA MET1 26.1.8 PADVIA MET2 26.1.9 PAD DIFF 106.1.10 PAD POLY1 306.1.11 PAD CONT 13
Table 4.7: AMS 0.8m n-well CMOS process design rules
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 102
pads
gainOTA
filtersection
sinc(x)-equaliser section
capacitors
Figure 4.11: Chip microphotograph
cially available (such as the ELANTEC 2141/2142 [24], the HARRIS HFA1212 [80] and
the MAXIM 4145/4147 [38] chipsets). All three devices oer very linear transmission
characteristics up to a minimum of 100MHz. Because it is the functionality of the mi-
crochip that is to be established and to be compared with the simulated performance,
it is desirable to include the behaviour of the driver into the simulation. Because the
MAXIM 4145/4147 dierential driver/receiver circuits are the only commercially avail-
able products which oer SPICE models, this chipset was selected for the fabrication
of a test jig.
As Fig.4.12 shows, the test jig implements a single-ended to fully-balanced driver /
receiver set-up, which is equally terminated to 75. The jig has been realised in surface
mount technology on a double-sided PCB with top ground plane. The two switches A
and B allow the individual testing of the three IC system blocks and are realised as
0 links.
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 103
+3.3V
NC NC
a1
a2
a3
b1
b2
b3
A
B
filter in boost in boost out
sinc in sinc out
filter outFaraday Chip
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
+3.3V
-3.3V
75ΩBNC
-3.3V -3.3V
NC NC
+3.3V
MAX4147
1 2 3 4
14 13 12 11 10 9 8
5 6 7
75Ω
BNC+3.3V
-3.3V -3.3V -3.3V
NC NC
+3.3V
NC NC
MAX4145
1 2 3 4
14 13 12 11 10 9 8
5 6 7
Figure 4.12: Microchip test jig
4.4.2 Test Results
In order to investigate the correlation between simulated and measured results, it is
better to start the examination with the simpler chip component. For this reason,
the rst system component to be tested is the sinc(x)-equaliser. Fig.4.13 shows its
measured frequency response between 100kHz and 100MHz. Note that the reference
level is located at the top of the graph.
Compared to the transistor-level simulation in Fig.4.4, the measured frequency
response exhibits maximum amplitude lift of 4.67dB at 40MHz instead of 4.2dB max-
imum lift at 19MHz. The magnitude of the lift is within 12% of the specication,
which may be considered sucient for a rst prototype. However, this lift occurs at a
frequency 110% higher than simulated, which is clearly not acceptable given the lter
specication. These measured results give rise to two questions which may explain this
deviation in the frequency response. The rst concerns the reliability of the test set-up
and the second concerns the accuracy of the models on which the simulation is based.
To verify the operation of the test set-up, the frequency response of the test jig alone
has been measured. The chip has been replaced with straight resistive connections of
100. The test jig measured frequency response is shown in Fig.4.14.
The sloping response in Fig.4.14 is the amplitude characteristic of the driver/receiver
circuit. As can be seen, it is very linear, having only 0.09dB loss up to 100MHz.
The constant graph in Fig.4.14 is the group-delay characteristic of the driver/receiver
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 104
Figure 4.13: Sinc(x)-equaliser frequency response
circuit, which is constant over the entire frequency range. Given the fact that the
driver/receiver jig operates with high linearity and that hence the measured response
in Fig.4.13 is indeed the frequency response of the sinc(x)-equaliser, the next step is to
investigate fabrication tolerances.
Section 4.2.2 has already performed worst case analysis on the accuracy of the block-
diagram capacitor values. While these results show only low sensitivity of the sinc(x)-
equaliser to variations in C, the in uence of transistor model parameter variations on
the frequency response has not yet been investigated. It is generally agreed [7, 26],
that the most signicant parameter is a variation the gate oxide thickness tox, since
it will not only in uence the OTA input impedance and the transistor drain current,
but also the values of the circuit capacitors. The CMOS foundry [1] species nominal
thickness of 15.5nm, which can vary from 15nm to 17nm.
If statistical process variations are to be taken into consideration, Monte Carlo
analysis must be used with the simulation software. Running the transistor-level sim-
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 105
Figure 4.14: Test-jig frequency response
ulation of the sinc(x)-equaliser with 100 Monte Carlo runs and varying only the tox
parameter between 15nm and 17nm generates a range of frequency responses. For the
investigation at hand, Fig.4.15 focuses on two of these graphs, which are close to the
measured results (runs 19 and 41) .
This result clearly shows, that the measured sinc(x)-equaliser frequency response in
Fig.4.13 can be explained by process variations in the gate oxide thickness parameter
tox. For example run 41 has gain peaking at 36.3MHz. Together with the capacitor
value variations, this result matches the measured peak frequency of 40MHz.
To complete the investigation, Fig.4.16 shows the measured frequency response of
the 5th-order elliptic video-lter. Note that the lter section works as a lowpass lter
with two clearly identied notch positions. However, the elliptic lter has measured
notch positions at 52.1MHz and 161.8MHz, compared to 22.8MHz and 35.8MHz in
SPICE simulation. Also, its amplitude roll-o does not meet the tight transition band
specication. These deviations in the lter frequency response can also be attributed
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 106
0Hz 20MHz 40MHz 60MHz 80MHz 100MHzFrequenc y
12
8
4
0
-4
-8
-12
run 42: 11dB @ 36.3MHz
run 19: 3.6dB @ 31.6MHz
dB
Figure 4.15: Simulated Monte Carlo analysis of the video sinc(x)-equaliser
to the same process variations as the deviations in the sinc(x)-equaliser.
One of the major problems in integrated lter design is, that components cannot
be matched to an arbitrary degree of precision within the chip. This inaccuracy leads
to a mismatch in the gain constants of the various integrators of the lter, altering its
frequency response. This problem can be severe in video lters, because the value of
capacitors used in integrators are of the order of a few picofarads and matching them
across the chip to the required degree of precision is dicult [28]. To over come this
problem, on-chip tuning schemes are normally employed. The most common technique
is based on a master-slave lter approach set in a phase-locked feedback loop (see
chapter 4 for more information).
4.5 Integrated Circuit Tuning
As indicated in the previous section, the performance of integrated analogue lters is
limited by the deviation of critical circuit parameters to their respective theoretical
values due to CMOS process variations. In particular, these critical parameters are
the time constants of the OTA-C integrators, whose absolute values depend on the
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 107
Figure 4.16: Filter frequency response
ratio gm=Ci for every capacitor Ci in the lter. Because the gm are designed to be
equal throughout the lter, the time constant ratios are set by the ratios between the
capacitors. Typically, this ratio can be matched with high accuracy to within 0.5%,
provided the capacitors are laid out according to the strategies introduced in section
4.3.2.3.
The purpose of this section is to introduce the most widely accepted method to
adjust the lter time constants by means of automatic electronic on-chip gm tuning.
This method is usually referred to as indirect master-slave tuning [44, 53, 85]. A typical
automatic tuning system is shown in Fig.4.17, where the voltage-controlled oscillator
acts as the master and the video lter acts as the slave. The tuning is indirect because
it relies on close correlation of the mismatches between the master and the slave.
Although it would be preferable to tune the slave lter directly and hence eliminate
matching errors between master and slave, no feasible direct tuning strategy has yet
been reported, since reference signal and main signal cannot be applied to the main
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 108
phasedetector
lowpassfilter
voltage-controlledoscillator
slave(video filter)
vref(t)
vm(t)
y(t)y(t)
vsig(t) vsig(t)
Figure 4.17: Block diagram of an automatic tuning scheme
lter simultaneously.
This master-slave tuning scheme is realised using a phase-locked loop (PLL) ap-
proach, which entails the following subsystem components:
A voltage-controlled oscillator (VCO), designed to oscillate at the reference fre-
quency vref (t), is subject to process variations. Due to these variations, it oscil-
lates at a dierent frequency vm(t).
A phase detector (i.e. an analogue multiplier) compares an external reference
signal vref(t) with the signal vm(t) generated by the master VCO to produce a
raw error signal y(t).
This signal is passed through a lowpass lter (LPF) to eliminate all undesirable
high-frequency components from the raw error signal y(t), leaving only a DC
signal component which is a measure for the phase dierence between signal
vm(t) and reference vref (t).
The cleaned error signal y(t) is then applied to the master and the matched and
tracking slave in a way that corrects the detected errors. As discussed before,
the success of this tuning scheme relies on close matching between the master
(VCO) and slave (lter) section. To ensure a close match, it may be advisable
CHAPTER 4. VOLTAGE-MODE CMOS OTA-C VIDEO-FILTER 109
to construct a VCO from a lter by using a biquad section of such high quality
factor Q that the biquad oscillates.
Note that this section has presented only an outline of a possible automatic tuning
scheme which must be realised in future implementations together with any analogue
lter chip.
4.6 Concluding Remarks
This chapter has introduced the design and layout of monolithic OTA-C video lters
in CMOS technology. In particular, it has described the fully-balanced implemen-
tation of an analogue video lter system comprising a 5th-order elliptic lter and a
biquadratic sinc(x)-equaliser, designed to meet the CCIR 601 specications. Evaluat-
ing the fabricated device in a test environment has demonstrated, that the lter and
the sinc(x)-equaliser function correctly as a video-lter. However, detailed comparison
between simulated and measured results of the analogue chip components shows that
neither the lter nor the sinc(x)-equaliser meet the system specications with respect
to amplitude response characteristics.
Monte Carlo analysis has shown, that the measured performance of the system
is mainly due to fabrication tolerances in the thickness of the transistor gate oxide
parameter as discussed in section 4.4.2. To account for these process variations and
ensure correct analogue video-lter operation, it is now clear that automatic tuning
schemes need to be implemented with the ltering system on the chip to guarantee the
system performance.
Chapter 5
Current-Mode OTA-C Filters
5.1 Introduction
In the previous four chapters it has been demonstrated, that the transconductor-
capacitor approach is one of the most successful methods in the design of integrated
continuous-time lters. Although single-output OTAs provide current at their outputs,
lter transfer functions based on these devices are normally expressed as voltage ra-
tios, which limits their capabilities of processing current signals [55]. Current-mode
signal processing is a very attractive approach to integrated lter design because of
the simplicity associated with implementing basic operations such as signal summing
and replication, and the potential to operate at higher signal bandwidths than the
voltage-mode approach. In general, three advantages of current-mode circuits over
their voltage-mode equivalents can be identied:
1. The circuits consist of only low impedance nodes, resulting in low parasitic time
constants throughout, which provide the capability to operate at high signal
bandwidths. This is owing to the fact that stray-inductance eects, which oc-
cur in low impedance circuits, aect the performance less severely than stray-
capacitance eects in high impedance circuits [49].
2. Current-mode implementations generally result in simpler circuit topologies, since
for example the summing of signals requires only a circuit node and current signals
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 111
can be easily replicated using current mirrors. In turn, the summing operation in
voltage-mode circuits requires voltage-current conversion, current summing and
current-voltage conversion. This clearly increases circuit complexity and can lead
to non-capacitively loaded uncompensated nodes that introduce excess phase.
Due to their simple topology, current-mode circuits can be very compact, which
leads to reduced silicon area requirements as well as contributing to improved
high frequency performance [69].
3. With the shrinking feature size of digital CMOS devices and the associated nec-
essary reduction of supply voltages, process parameters like threshold voltage will
be chosen to optimise digital performance and hence voltage domain behaviour
will suer as a consequence. This problem can be overcome by exclusively op-
erating in the current domain [94]. Furthermore, compatibility with digital and
mixed-signal single-poly CMOS technologies necessitates the use of only grounded
capacitors, which have the additional benet of being not only easier to integrate
but also being less aected by parasitics than oating capacitors.
As a result, current-mode signal processing has become an attractive research topic.
It has been successfully implemented in various high-performance applications such as
D/A and A/D converters [94] and signal ltering, which is the focus of this chapter.
Numerous current-mode lters have been proposed, examples are [2, 55, 67, 88, 97]. In
order to benet from the monolithic integrability of the OTA-C approach, current-mode
operation implies the use of multiple-output OTAs (MO-OTAs), because a current
signal is available only once for each signal path. One or more outputs will transmit
the signal to the next stage in the circuit, while at least one other output is used for
feedback. Furthermore, there are continuing motivations for developing new current-
mode circuits, especially with regard to VLSI realisation:
Filters should be simple and with minimumnumber of OTAs, since OTAs occupy
a relatively large area, consume power and are sources of noise.
Filters should employ only identical OTAs, having the same number of output
currents. Identical OTAs simplify the transistor-level lter implementation and
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 112
provide compact and dense layout since they can be developed as pre-designed
cells.
Filters should be versatile, such that multiple transfer characteristics are achieved
without modifying the lter topology.
Filter characteristics should be tunable electronically in terms of frequency re-
sponse using external bias current or voltage source(s). The lter can hence be
integrated as a versatile IC capable of providing any type of lter function.
The purpose of this chapter is to introduce current-mode signal processing based on
the transconductance-capacitor approach. It will present design methodologies for MO-
OTA based lters within the framework of the four motivations stated above. In order
to relate to the work reported in chapter 2, the design of current-mode elliptic ladder
lters will rst be reviewed. The design of ladder lters with MO-OTAs based on LC
simulation has been described [69]. Note that current-mode elliptic ladder lters do
not exploit the third advantage stated above, since their realisations generally rely on
oating capacitors. Furthermore, their frequency response characteristics are generally
not tunable, which seriously limits their versatility in IC applications.
In order to overcome these two shortcomings of ladder-based elliptic lter design,
section 5.4 will introduce a methodology to obtain tunable elliptic frequency response
characteristics by cascading lowpass or highpass-notch biquads. This is achieved by in-
troducing a novel programmable current-mode lter structure, which is capable of
generating lowpass-notch and highpass-notch responses without changing the lter
topology. Theoretical analysis will be conrmed using simulations based on CMOS
OTAs and experimental results of a cascaded biquad elliptic lowpass lter will be
presented based on discrete implementation. In addition, this section will investigate
in detail MO-OTA high-frequency non-ideal eects, including input capacitance and
output resistance on the performance of this novel lter structure.
It has been demonstrated, that not all of the advantages of current-mode lters,
which address partially con icting requirements, can be exploited simultaneously with
the lter structures and design methodologies presented so far. In addition, the focus of
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 113
current-mode lter design in many modern mixed-signal applications has changed from
high-order circuits with narrow transition bands to simpler and more versatile all-pole
structures used as oversampling lters at the front end of data converters. Hence, with
emphasis on lter versatility and tunability, section 5.5 will develop and investigate a
universal biquadratic current-mode lter structure, capable of realising various lter
responses as well as signal conditioning functions such as allpass response and sinc(x)-
equalisation capability. This novel universal current-mode biquad based only on MO-
OTAs and grounded capacitors has the major benet of achieving maximum exibility
without the need to modify the circuit topology.
5.2 Current-Mode Building Blocks
Section 5.1 has identied the MO-OTA device as the basic building block in the
transconductor-capacitor approach to current-mode analogue signal processing. The
MO-OTA symbol is shown in Fig.5.1, where Vb is an external bias voltage source used
for altering the transconductance gm. The output currents Io1, Io2 to IoN all have
identical transconductance values, they may dier only in their current directions as
indicated. Assuming ideal transfer characteristics, the output currents in Fig.5.1 are:
Io1 = Io2 = IoN = gm (Vin+ Vin). Throughout this chapter, MO-OTAs will be
implemented with the structure identied in chapter 3.
Vb
Vin gm
1
2
N
Io1
Io2
IoN
Figure 5.1: Multiple-output OTA
Based on this denition of MO-OTAs, two types of building blocks for the genera-
tion of current-mode lter structures will be introduced. One is a current-mode integra-
tor to implement the lter time constants, the other is a current-amplier/replicator.
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 114
Current-mode operation implies that these building blocks will have pure current trans-
fer characteristics. A MO-OTA based implementation hence requires current-voltage
conversion at the input of the device. This is best achieved by inserting an grounded
impedance Z at its non-inverting input terminal. This section will show, how this gen-
eral approach can be used to derive all the necessary building blocks from the MO-OTA
based circuit shown in Fig.5.2a.
gmIo2
IoN
Iin
Io1
gmIin C
Io1
Io2
IoN
gmIin Z
Io1
Io2
IoN
(a) (b) (c)
Figure 5.2: (a) Basic MO-OTA building block, (b) Current-mode integrator, (c) Cur-
rent buer
In the case of Fig.5.2a, Z is a general passive impedance and the transfer charac-
teristics of this basic building block are:
Io1 = Io2 = IoN = Z gm Iin (5.1)
From Eqn.5.1 it is evident that a current-mode integrator can be implemented with
this structure if the impedance block is replaced by a capacitor such that Z = 1/sC, as
indicated in Fig.5.2b. In this case, the multiple-output current-mode integrator, which
is characterised by the transconductance gain gm and the capacitor value C, has the
transfer function:
Io1Iin
=Io2Iin
= IoNIin
=gmsC
(5.2)
Note that this particular integrator implementation utilises a grounded capacitor
and hence exploits the associated advantages with respect to CMOS implementation.
If the impedance Z is replaced by a resistor (i.e. Z = R), the structure implements a
current-mode amplier with the transfer function:
Io1Iin
=Io2Iin
= IoNIin
= gm R (5.3)
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 115
where the amplier gain is determined by the variable transconductance gm, while
the grounded resistor R will usually be of xed value. With respect to monolithic
implementations it should be noted that, although it is possible to fabricate passive
resistors on-chip, active CMOS simulations are generally more ecient in terms of
component accuracy and silicon area requirement. One possibility to simulate the
grounded resistor function is to use a single-output OTA with the output directly to
the inverting amplier input [91]. However, this has the disadvantage of using an
additional OTA. A more ecient method of simulating the resistor function arises in
the special case of R = 1=gm. In this case, it is possible to connect an inverting output
of the MO-OTA directly to the input of the active device as indicated in Fig.5.2c. This
simulates a grounded resistor and causes the active device to present an impedance of
1=gm to the applied input signal:
Io1 = gm Vin+
Iin + Io1 = 0
Iin = gm Vin+
Zin =Vin+Iin
=1
gm
This structure hence implements a current-mode buer and Eqn.5.3 modies to
unity transfer characteristics.
5.3 Ladder-Based Elliptic Filter Design
It has been noted in chapter 4 that elliptic functions are the preferred approach to
the realisation of high-specication lters, since they provide the lowest lter order
when compared with other approximations. The most widely used technique to design
elliptic lters is the LC ladder simulation approach. Its biggest advantage is, that the
active circuit will retain the low sensitivity properties of the equally terminated passive
ladder prototype. Also, a circuit capacitor is generally present at all circuit nodes in the
LC ladder prototype which permits the pre-absorption of unavoidable parasitics [15].
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 116
The approach to derive transconductor-capacitor current-mode lters from passive LC
prototypes has recently been presented [29, 69]. It is based on current-mode signal
ow graph representations of the state variable equations and uses MO-OTA based
integrators and buers.
5.3.1 Ladder Filter Structure Generation
As with voltage-mode ladder lters and without loss of generality, consider for example
the design of a 5th-order all-pole lowpass lter whose passive prototype is shown in
Fig.2.2.
From the state variable equations in chapter 2, standard analysis yields the signal
ow graph (SFG) description of the ladder as shown in Fig.5.3a. Note that the
branch weights in the SFG are either +1 or -1 unity branches or are of the
integrator form 1=sTi, where Ti is the value of an inductor or capacitor in the LC
network and s is the complex frequency variable.
In order to realise a current-mode implementation, the +1 and -1 branches, which
occur in pairs, are combined at the outputs of the 1=s type integrators, yielding
a realisation in terms of dierential output devices as shown in Fig.5.3b. This
dierential output type of signal ow graph realisation is necessary because in
current-mode implementations, a current signal is available only once for each
signal path and hence each signal path requires a separate output. Note how
the structure in Fig.5.3b relies on direct connection of pairs of integrator outputs
together to achieve addition at the integrator inputs, which requires that the
signals are currents.
The ladder structure facilitates the absorption of parasitic capacitances, since every
circuit node is connected to a grounded capacitor at every integrator input as demon-
strated in section 5.2. Also, note that the only building blocks necessary to generate
this un-terminated ladder structure are current-mode integrators (see section 5.2) and
current summing nodes.
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 117
V1 V3 V5
I2 I4
sC1
1sL2
1sC3
1sL2
1sC5
1
+1-1 +1-1 +1-1
+1 -1 +1 -1 +1 -1
-
1/sT1 1/sT2 1/sT3 1/sT4 1/sT5
+
- +
- +
- +
- +
∫ ∫ ∫ ∫ ∫
(a)
(b)
Figure 5.3: Current-mode ladder-based lter (a) SFG and (b) Realisation using dier-
ential output integrators
It has been demonstrated in chapter 4, that it is possible to added oating ca-
pacitors, which dene the notch positions later to the active simulation, in order to
modify the all-pole characteristics of Fig.5.3b into an elliptic lter response. In the
case of Fig.5.3b, oating capacitors need to be included between the outputs of the
integrators T2 and T4.
The design of ladder lters generally starts from the simulation of passive ladder
prototypes with element values given in standard lter tables. These element values
are usually given with respect to equal termination at the lter input and output. The
next step in the design of current-mode ladder lters is hence the implementation of
termination resistors. It has been claried in chapter 2, that in integrated active ladder
lter design, all active devices should have the same transconductance gain gm. This
also hold for current-mode lters. In section 5.1, a direct feedback from a negative
current output to the MO-OTA input terminal was used to implement a resistor of
value 1=gm. Using this knowledge it is not dicult to terminate the signal ow
graph at the input by closing the loop from the negative output of the rst integrator
to its input, hence realising a termination resistance of 1=gm. Similarly, to realise
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 118
the output termination, a third negative output is added to the last current-mode
integrator. As discussed, the generation of additional current replicas in MO-OTAs
is relatively inexpensive. While the positive integrator output current is used as the
lter output, the additional negative current replica is used to close the feedback loop
to the integrator input. A complete circuit diagram of a 5th-order current-mode ladder
lter including the appropriate terminations and the two elliptic oating capacitors is
shown in Fig.5.4.
Iin C1 C3 C5
C2 C4 Iout
C7
- +
- +
- +
- +
-
+
∫ ∫ ∫ ∫ ∫
-
C6
Figure 5.4: Current-mode 5th-order elliptic lowpass ladder lter
5.4 Tunable Elliptic Filter Design Based on Cas-
caded Biquads
While the LC simulation approach presents an ecient and well developed method to
design elliptic lters, recently the demands and design considerations for elliptic lters
have changed, especially with respect to monolithic VLSI implementations and ASIC
design. For example, if the lter has to be implemented in a single-poly CMOS process
because of compatibility with digital components in a mixed-signal chip, and hence
only grounded capacitors are available, the current-mode implementation becomes in-
creasingly dicult and requires additional building blocks, including multiple-output
current buers and current ampliers. This has been demonstrated on a 3rd-order ellip-
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 119
tic lowpass ladder lter conguration described in [69], but a complete methodology to
design high-order elliptic lters with only grounded capacitors has not been described.
A better method of obtaining high-order elliptic lter responses using only grounded
capacitors is to cascade lowpass or highpass-notch biquad sections. In addition, this
approach allows to obtain tunable elliptic frequency response characteristics, if the
nite transmission zeros of the biquads can be controlled electronically.
Cascade designs are widespread in industry, primarily because of their generality,
mathematical simplicity and the direct correspondence between particular capacitors
and pole-zero positions which makes them easy to tune. Especially with regard to
mixed-signal VLSI implementations, the cascade approach of current-mode lters oers
a better design alternative for two reasons. Firstly, the generated lters have the option
of tunable bandwidth characteristics, unlike the case with LC simulation designs where
the bandwidth is xed since the lter !0 and Q parameters are distributed over the
network branches. Tunability of the lter characteristics using external bias current
or voltage source(s) is an important issue for IC designers since it permits the lter
to be used for dierent applications and also allows the adjustment of designs after
fabrication to account for manufacturing process variations.
Secondly, the cascade approach is based on connecting a number of identical lter
sections which will lead to simplied IC implementation and regular layout since they
can be developed as pre-designed cells. However, careful choices are required in the
remaining degrees of freedom in the design, such as pairing of poles and zeros, ordering
of sections and scaling of intermediate signals to yield high-performance lters.
2nd-order lowpass-notch and highpass-notch sections are the key building blocks in
the design of high-order elliptic lters based on the cascade approach. Each biquadratic
function is realised in a separate block using an appropriate MO-OTA based biquad and
the high-order transfer function is the product of those cascaded biquad sections. Over
the past few years, various authors have proposed 2nd-order notch structures [55, 87].
However, they only provide symmetrical notch responses which are not suitable for
the realisation of elliptic functions, apart from [51] which has reported a lowpass-
notch lter using MO-OTAs. Although it is not a dicult task to modify one of
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 120
the reported MO-OTAs biquads to generate highpass-notch characteristics, this is not
an ideal solution for VLSI implementation, since two dierent lters are needed for
implementing lowpass and highpass elliptic functions.
A better solution would be to develop one lter which provides both lowpass and
highpass-notch characteristics with tunable frequency response and without changing
the lter structure. The possibility of cascading arbitrary lowpass and highpass-notch
characteristics not only allows the realisation of elliptic lowpass and highpass lters,
but also facilitates the design of elliptic bandpass lters. Furthermore, to provide oper-
ational exibility and VLSI compatibility [51], the lter function should be congurable
using CMOS switches controlled using a digital word and employ only grounded capac-
itors. This section will present a current-mode lter conguration based on MO-OTAs
and grounded capacitors and which is recongurable using a 2-bit digital word. It is
capable of generating both lowpass and highpass-notch responses. This is achieved
using a symmetrical current switching technique. Also, the design, simulation and
implementation of current-mode elliptic lters with tunable frequency characteristics
using the proposed conguration is considered.
5.4.1 Tunable Filter Conguration
In general, the transfer function of a second-order elliptic lter is:
H(s) =s2 + !2
z
s2 +!pQ + !2
p
(5.4)
Where !z is the zero frequency and !p is the pole frequency. Depending on the
positions of !z and !p, the following ltering characteristics are obtained:
!z = !p, symmetrical notch
!z > !p, lowpass-notch
!z < !p, highpass-notch
In order to incorporate both lowpass and highpass-notches in Eqn.5.4, the following
transfer function is required:
H(s) =s2 + (D + ELP EHP )
s2 +!pQ + !2
p
(5.5)
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 121
where LP and HP are two digitally controlled switches, D and E are two variables
controlled by current sources. The parameters LP and HP can be viewed as two
symmetrical current switches capable of switching E in or out of the lter transfer
function. This symmetry ensures that the same E will be added or subtracted from
the numerator of Eqn.5.5 Selecting both LP and HP to be '0' or '1', a symmetrical
notch is obtained. Setting LP to '1' and HP to '0' provides a lowpass-notch and LP
to '0' and HP to '1' yields a highpass-notch. Fig.5.5 shows the circuit diagram of the
programmable current-mode lter structure, detailing how the symmetrical switching
can be achieved using the two switches LP and HP .
IinIout
ηLP
ηHP
gm4
Vb4
gm3
Vb3
C2
gm2
Vb2
C1
gm1
Vb1
R1
Figure 5.5: Proposed current-mode lowpass and highpass notch lter structure
This lter is obtained by modifying the notch circuit reported in [55] and adding
an additional MO-OTA with digitally controlled switches. By analysing the structure
in Fig.5.5 and assuming R1 = 1=gm1, the following parameters are obtained:
D =
sgm2gm3
C1C2
E =
sgm4
C1C2
!pQ
=R1gm1gm2
C1
!2z = D + ELP EHP (5.6)
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 122
Note that gm4 can be used to tune the notch frequency of the pole parameters
using the OTA bias voltage Vb4 (see Fig.5.5). Table 5.1 gives !z and !p expressions for
dierent lters.
Function LP HP !z !p gm1 = gm2 gm3 gm4
Symmetrical notch 0 0q
gm2gm3
C1C2
qgm2gm3
C1C2
!pQ
!p Q
Highpass notch 0 1q
gm2(gm3gm4)C1C2
qgm2gm3
C1C2
!pQ
!p Q(!2p!
2
z)Q
!p
Lowpass notch 1 0q
gm2(gm3+gm4)C1C2
qgm2gm3
C1C2
!pQ
!p Q(!2z!
2p)Q
!p
Table 5.1: Dierent ltering functions of the proposed lter structure
This lter structure can be used to design both high-order lowpass or highpass
elliptic lters by cascading two or more of the circuits shown in Fig.5.5. The design
process is simplied by standard lter tables [32], where the general even-order elliptic
lter functions are expressed in terms of polynomial coecients (, , and ). A
general even-order elliptic function of order n is:
H(s) =n=2Yi=1
s2 + is2 + i s+ i
(5.7)
It is hence more convenient to express the lter design equations in terms of the
elliptic polynomial coecients. Assuming C1 = C2 = 1F and R1 = 1=gm1 = 1, the
lowpass and highpass-notch lter design equations are shown in Table 5.2.
Function LP HP gm1 = gm2 gm3 gm4
Highpass notch 0 1
Lowpass notch 1 0
Table 5.2: Filter design equations in terms of elliptic lter polynomial coecients
The proposed lter has low !z, !p and Q sensitivities with respect to passive com-
ponent tolerances. For example, the lowpass-notch lter sensitivities are:
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 123
S!zgm1= S!pgm1
= SQgm1= 0 S!zgm4
= gm4
2(gm3+gm4); S!pgm4
= SQgm4= 0
S!zgm2= S!pgm2
= 1=2; SQgm2= 1=2 S!zC1
= S!pC1
= 1=2; SQC1= 1=2
S!zgm3= gm3
2(gm3+gm4); S!pgm3
= SQgm3= 1=2 S!zC2
= S!pC2
= SQC2= 1=2
It can be readily shown that the sensitivities of the symmetrical and highpass-notch
lters also vary from 0 to 1/2.
5.4.2 Design Examples
To conrm the theoretical analysis of the previous section, two examples of frequency
tunable elliptic lters are given. They include a 4th-order lowpass and highpass response
with stopband attenuation Ap = 26dB and 1dB passband ripple. Cascading two 2nd-
order elliptic function polynomials yields:
HLP (s) = HA s2 + 1
s2 + 1 s+ 1
s2 + 2s2 + 2 s+ 2
(5.8)
where HA is a scaling factor. The lowpass polynomial coecients are taken from
lter tables [76], while the highpass polynomial coecients are obtained using lowpass-
to-highpass transformation. It is well known, that the pole-zero locations of highpass
lters can be obtained from their lowpass equivalents, if the normalised cut-o frequen-
cies are both equal to unity. In this case, the complex frequency variable is transformed
by the following expression:
sHP =1
sLP(5.9)
which represents a pole-zero re ection through the unit circle. The highpass poly-
nomial coecients (i, i and i) of each 2nd-order section are readily obtained by
inserting Eqn.5.9 into Eqn.5.8, which leads to the following highpass design equations:
HP =1
LP
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 124
HP =LPLP
HP =1
LP
HAHP = HALP n=2Yi=1
iLPiLP
(5.10)
Using this transformation, the elliptic lowpass and highpass polynomial coecients
can be derived as shown in Table 5.3.
Function 1 1 1 2 2 2 HA
lowpass 1.57240 0.79909 0.47990 6.22422 0.15515 1.01180 0.04465
highpass 0.63597 1.66512 2.08377 0.16066 0.15334 0.98834 0.89996
Table 5.3: 4th-order elliptic polynomial coecients (Ap = 26dB, 1dB passband ripple)
Now, consider a 4th-order lowpass lter based on cascading two 2nd-order sections.
Using Tables 5.2 and 5.3, and denormalisation for a frequency of 0.65MHz with equal
capacitor values of 10pF, the rst row of Table 5.5 gives the lter OTA transconduc-
tance values and their bias voltages (Vb). The simulations are based on the voltage-
tunable CMOS multiple-output OTA presented in section 3.5. The gm of this MO-OTA
is variable over a wide range by varying the external bias voltage Vb between the sup-
ply rails, hence providing the ability to tune the lter !z and !p parameters. Table
5.4 gives the transistor sizes of the OTA based on the AMS double-metal double-poly
0.8m CMOS process. To allow full CMOS integration of the lter, the resistor R1
in Fig.5.5 should be replaced by an active circuit. A complexity-ecient method to
modify the rst dual-output OTA of the lter into a triple-output OTA such that the
third output is connected to the input of the active device has been presented in section
5.2.
Note that the open MO-OTA outputs and the open switches LP and HP in Fig.5.5
can be left unconnected. Because of the internal structure of the MO-OTA in section
3.5, the current-mirrors can remain unloaded and their non-use will not in uence the
transfer characteristics of the OTA. Instead, the unused output current of the MO-OTA
will simply ow between the supply terminals.
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 125
M1-M3 M4-M9 M10-M13
W (m) 32 92 32
L (m) 2 2 2
Table 5.4: Transistor dimensions of the MO-OTA based on 0.8m CMOS process
Based on this CMOS MO-OTA, Fig.5.6 shows the simulated frequency response
of the 0.65MHz cut-o frequency lter. The lter has two notches as expected in
the stopband located at 807kHz and 1.58MHz compared to the calculated notches at
815kHz and 1.61MHz. The lter also has an insertion loss of 1dB and passband ripple
of 1.6dB compared to the theoretical values of 0dB and 1dB.
The discrepancies between the theoretical and simulation results are due to the
non-ideal input capacitance and output resistance of the MO-OTAs as will be discussed
later (section 5.4.4). Varying the OTA transconductance values by adjusting the bias
voltages (Vb) according to Table 5.5, the lowpass lter cut-o frequency was varied from
0.65MHz to 1.3MHz as shown in Fig.5.6. This clearly demonstrates the bandwidth
tunability of elliptic lters designed using the proposed lter structure. Note that the
lter frequency range has been chosen arbitrarily to conrm the theoretical analysis.
Changing the lter switches from LP = '1' and HP = '0' to LP = '0' and HP
= '1' and adjusting the OTA transconductance values and bias voltages according to
Table 5.5, a 4th-order elliptic highpass lter with tunable bandwidth from 0.65MHz to
1.3MHz is obtained as shown in Fig.5.7. Again, generally there is a good agreement
between the lter shape of the theoretical and simulated frequency responses.
5.4.3 Experimental Results
In order to verify the theoretical analysis, discrete implementations of the lters were
produced. The discrete realisation is based on Linear Technology LT1228 single-output
OTAs [14], Maxim MAX312 analogue switches [37], passive components with 1% toler-
ances and 5V supplies. Note that the implementation of MO-OTAs with the LT1228
device implies the combination of two or more single-ended transconductors, each pro-
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 126
1st second-order section 2nd second-order section
fC gm1 Vb1 gm3 Vb3 gm4 Vb4 gm1 Vb1 gm3 Vb3 gm4 Vb4
(MHz) (S) (V) (S) (V) (S) (V) (S) (V) (S) (V) (S) (V)
LP 0.65 65.2 -3.66 49.0 -3.67 111.6 -3.55 12.6 -3.73 0.532 -0.70 2.740 -2.18
1.3 135.6 -3.46 101.8 -3.58 231.8 -3.03 24.6 -3.69 1.110 -3.61 5.700 -0.10
HP 0.65 136.0 -3.45 102.2 -3.57 71.0 -3.65 12.5 -3.73 0.526 -0.77 0.440 -1.61
1.3 282.5 -2.75 212.3 -3.13 147.5 -3.41 26.0 -3.69 1.090 -3.61 0.915 -3.61
Table 5.5: Transconductance values of 4th-order tunable elliptic lowpass lter, assuming
all capacitors = 10pF
100kHz 300kHz 1.0MHz 3.0MHzFrequency
dB
0
-20
-40
-60
-80
Fc = 0.65MHz Fc = 1.3MHz
Figure 5.6: 4th-order tunable elliptic lowpass lter
ducing on of the output currents [69] as indicated in Fig.5.8. Their transconductances
were dened by a set of bipolar current sources realised using MPQ7093 transistor
arrays [34]. Fig.5.8 shows a 4th-order elliptic lter discrete prototype with V-I and
I-V converters which were used at the input and output respectively to facilitate lter
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 127
100kHz 300kHz 1.0MHz 3.0MHzFrequency
dB
0
-20
-40
-60
-80
Fc = 0.65MHz Fc = 1.3MHz
Figure 5.7: 4th-order tunable elliptic highpass lter
testing. The output I-V conversion is performed using an Elantec EL2030 wideband
current feedback amplier [23] in a transimpedance conguration. To reduce parasitic
eects, the lter capacitor values considered in the previous section were scaled up
from 10pF to 82pF. Note that the bias currents of the LT1228 devices were set up in-
dividually to allow adjustment of dierent gm values. Furthermore, each of the device
pairs which constitute the MO-OTA were provided with potentiometers to investigate
and compensate the eect of driving dierent loads with each current output.
Fig.5.9 shows the measured frequency response of the lowpass lter. Generally there
is good agreement between theoretical and measured results in terms of the overall lter
shapes. However, the stopband attenuation of the measured lters has been reduced
from 26dB to 24dB due to small shifts in notch positions. Note that the second notch
of the 1.3MHz lter has disappeared due to inadequate high frequency board layout
restricting experimentation with higher bandwidth lters. The THD of the lowpass
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 128
lter is -58dB with an input signal of 0.5Vpp and frequency of 100kHz.
Iin
R1
-VCC
+VCC
Vin
V - I conversion
Iout
I - V conversion
VoutEL2030
transconductance control
-VCC
C1 C2
LT1228
LT1228
LT1228
LT1228
LT1228
LT1228
LT1228
LT1228 ηLP
ηHP
C1 C2
LT1228
LT1228
LT1228
LT1228
LT1228
LT1228
LT1228
LT1228 ηLP
ηHP
R1
dual-output OTA
1st, second-order section 2nd, second-order section
Figure 5.8: Discrete implementation of 4th-order elliptic lter with V-I and I-V con-
verters
Figure 5.9: Measured frequency response of 4th-order elliptic lowpass lter with tunable
frequency range of 0.65MHz to 1.3MHz
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 129
5.4.4 High-Frequency Analysis of the Filter Structure
At high frequencies, the performance of the lter is limited by the non-ideal character-
istics of the active devices. The detailed analysis in section 2.3.1.2 and previous work
[5, 19] have shown, that input capacitance and output resistance of an OTA form the
signicant parasitics in OTA-C circuits. Therefore, a realistic high frequency model
for a multiple-output OTA is shown in Fig.5.10, where Ci is the common-mode input
capacitance and go is the output conductance.
V -
V +
Ci
gm
go
Iout1
Ci gm
go
Iout2
Figure 5.10: High-frequency model of MO-OTA
The equivalent circuit of Fig.5.5 can be obtained by replacing each MO-OTA build-
ing block with the realistic model in Fig.5.10. In order to simplify the circuit analysis
and obtain meaningful results, it has been assumed that all OTAs have the same input
capacitance and output conductance. Note that this assumption is valid, provided all
OTAs have identical input stage transistor dimensions (responsible for Ci), identical
output current mirror set-ups (responsible for go) and operate in the linear region,
which is the case in this work. The lter frequency performance can then be analysed
using the high-frequency circuit transfer function. Without loss of generality, consider
the lowpass-notch conguration presented in section 5.4.2. Its ideal frequency response
behaviour (Eqns.5.5 and 5.6) is modied to:
H(s) =gm1
1 + 2go
2s2 + 1s+ 0
3s2 + 2s2 + 1s+ 0(5.11)
where
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 130
2 = 4Ci(C + Ci) + C2
1 = 3go(C + 2Ci)
0 = 2g2o + gm2(gm3 + gm4)
3 = 3Ci(4Ci(C + Ci) + C2)
2 = 2go(C2 + 13C2
i ) + gm1(C2 + 4C2
i ) + CiC(4gm1 + 17go)
1 = 3Ci(2g2o + gm2gm3) + (C + 2Ci)(3gogm1 + gm1gm2 + 6g2o)
0 = 2go(gm2gm3 + gm1go + 2g2o ) + gm1gm2(gm3 + go)
Clearly this shows, that the ideal lter transfer function is aected by the non-
ideal parameters of the OTAs. To illustrate these eects, consider the lowpass lter
design example of section 5.4.2, where the lter bandwidth has now increased from
1.3MHz to 10MHz. SPICE simulations have shown, that the CMOS OTA of section
3.5.4 has input capacitance Ci = 0.52pF and output conductance go = 5S. Fig.5.11
shows the simulated frequency response of the ideal and the CMOS based 4th-order
elliptic lowpass lter. The modications to the ideal lter response are summarised as
follows:
1. The lter insertion loss has now increased from 1dB to 1.8dB as indicated by the
constant factor H0 of Eqn.5.11.
2. The ideal lter complex zeros on the j! axis are shifted to the left half s-plane
as shown in Table 5.6. The eect of this zero position shift is a reduction in the
notch frequency attenuation and an early lter roll-o, resulting in bandwidth
mismatch of 3.4MHz.
3. In the 1st lter section, the normalised pole position real part is changed by 0.317
rad/s, indicating a transition in the biquad lter response from low-Q to high-Q
characteristics as shown in Table 5.6.
4. In the 2nd lter section, the normalised pole position real part is changed by -
0.323 rad/s, indicating a shift in the biquad lter response from high-Q to low-Q
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 131
characteristics as shown in Table 5.6. Note that the eect of this shift in the
2nd section on the overall 4th-order lter response cancels with the eect of the
1st section due to the fact that both shifts are almost equal in magnitude but of
opposite direction.
5. Each biquadratic lter section order is increased from 2nd to 3rd (see Eqn.5.11).
This will introduce two additional real poles into the transfer function of the
4th-order lowpass lter (see Table 5.6). However, the real poles are far away from
the origin when compared to the dominant complex poles and hence their eect
on the overall lter performance is small.
poles zeros
1st section 2nd section 1st section 2nd section
ideal lter -0.3995j0.5659 -0.0776j1.0029 j1.2539 j2.4948
CMOS lter -0.0828j0.9981 -0.4068j0.5647 -0.0144j1.2383 -0.0144j2.4637
-9.0770 -42.3539
Table 5.6: Pole-zero positions of ideal and CMOS 10MHz 4th-order elliptic lowpass
lter
It may be possible to compensate for the non-ideal OTA parameters by adjusting
the theoretical OTA transconductance values in practice, however, a better approach
would be to use an optimisation technique to solve for the lter component values
as reported in [19]. Improved correlation between the ideal and the high-frequency
response may be obtained, if more complex OTAs are used in the implementation such
as cascode OTAs [102, 105], rather than the simple OTA in Fig.3.8.
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 132
1.0MHz 3.0MHz 10MHz 30MHzFrequency
dB
0
-20
-40
-60
-80
1MHz 3MHz 10MHz 30MHzFrequency
dB
0
-1
-2
-3
-4
-5
1.8dB
3.4MHz
CMOS filter response ideal filter response
Figure 5.11: Simulated frequency response of ideal and CMOS 10MHz 4th-order elliptic
lowpass lter
5.5 Universal Biquad for Oversampling Applica-
tions
Regarding continuous-time lter structures, the focus has so far been on high-order
circuits with narrow transition bands. In many modern mixed-signal applications,
however, the focus in current-mode lter design has changed towards simpler and more
versatile all-pole structures used as oversampling lters at the front end of data con-
verters. As indicated in section 5.1, there are a number of motivations for developing
multiple-output OTA based lters suitable for VLSI realisation. However, the exist-
ing MO-OTA current-mode lter structures in the literature cannot achieve all the
motivations and design criteria listed in section 5.1 simultaneously.
The biquad in [2] meets the reasons one and two by having one MO-OTA but
it does not meet the others since oating capacitors are needed to implement high-
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 133
pass and bandpass lters, modications to the biquad topology are needed to generate
the dierent ltering functions and due to the lter structure, tunability can not be
achieved. The various biquads reported in [55, 88] satisfy reasons two and four. How-
ever, the rst and third reason is not met, since the biquads require a large number
of active devices with up to six MO-OTAs and dierent output nodes have to be cho-
sen to implement dierent ltering functions. The biquad presented in [68, 67] meets
the rst criterion and the third current-mode motivation, but not the second criterion
since non-identical OTAs are used. Furthermore, the third criterion is not met since
dierent circuit topologies are used to generate dierent functions. For example, to
obtain a bandpass lter, two OTAs with triple-output and one OTA with single output
are needed, whilst to obtain an all-pass lter, one of the three-output OTAs should
be replaced by a ve-output OTA. This means that the biquad topology needs to be
changed to produce dierent functions which is clearly not acceptable for monolithic
implementation if a universal lter chip is to be produced. The biquad reported in
[97] meets the rst reason, but not the second one since non-identical OTAs are used.
Furthermore, the third and fourth reason is not met since dierent circuit topologies
are used to generate dierent functions which do not achieve tunability.
This section will describe, how MO-OTAs facilitate the development of a new
current-mode universal biquad conguration capable of generating various lter trans-
fer functions using digitally programmable zeros. This is achieved without excessive
use of active devices and without changing the biquad topology. The biquad zeros may
be independently programmed using four switches producing the following ltering
functions: lowpass, highpass, bandpass, notch, allpass, lowpass notch and amplitude
equaliser. Further advantages of the biquad are (!0 and Q) electronic tunability, low
sensitivity, and ease of design. For demonstration purposes, simulated and measured
results of voltage tunable lowpass and bandpass lters over the frequency range of
0.7MHz to 4MHz are included in this section.
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 134
5.5.1 Universal Biquad Conguration
Firstly, it is important to determine the minimum number of OTA outputs required
to develop a universal biquad structure. A MO-OTA with two outputs is not capable
of generating all 2nd-order ltering functions without an excessive use of OTAs due to
the lack of additional output currents [55]. Analysis has shown, that MO-OTAs with
three outputs facilitate the development of ltering structures capable of generating
all functions (lowpass, highpass, bandpass, allpass, notch) with a minimum number
of three TO-OTAs. It should be noted, that two triple-output OTAs can generate
some of the lter functions, but not all of them. Furthermore, MO-OTAs provide
sucient output currents allowing the biquad zero locations to be explicitly dened
using digitally controlled CMOS switches and hence producing the required ltering
functions.
The MO-OTA symbol has been introduced in Fig.5.1, where Vb is an external
bias voltage source used for altering the transconductance, gm, of the OTA. In this
application, the OTA has three equal output currents denoted by Io1, Io2 and Io3.
The current Io1 is the current going into the amplier and is used for feedback. The
current Io2 is the feedforward signal and is used either as an output current or as an
input to another amplier. The current Io3 can be either a feedback or a feedforward
signal depending on the required ltering function as will be shown later. A canonical
universal biquad structure can be generated using two MO-OTAs with three outputs,
one MO-OTA with two outputs, one resistor and two grounded capacitors as shown in
Fig.5.12.
This structure will subsequently be modied to design a fully integrated universal
biquad based on only MO-OTAs as the active devices. The universal biquad transfer
function is:
H(s) =IoutIin
=N(s)
s2
R1gm1+ (gm2
C1)s+ gm2gm3
C1C2
(5.12)
where
N(s) = S1(s2) S2(
sgm2
C1) + (S3 + S4)(
gm2gm3
C1C2) (5.13)
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 135
Vb2
gm1
3
2
Vb1
gm3
3
2
1
Vb3
C1
C2
gm2
3
1
2
S1IoutS3 S4S2
Iin
R1
Figure 5.12: Proposed universal biquad
The numerator polynomial N(s) of the biquad transfer function depends on the
positions of the switches S1 S4, which can take the binary values '0' or '1', where
'1' indicates a closed switch and '0' indicates an open switch. The positions of the
switches S1, S2, S3 and S4 determine the ltering functions. Note that the switch
S2 is used to provide either a positive feedforward current or a negative feedforward
current, as indicated by the sign of the lter numerator polynomial N(s), where a
"+" sign indicates a current owing out of the device and "-" sign indicates a current
owing into the device. The poles of the transfer function are xed and determined
by the two integrator loops, while the zeros are determined by switches which can
independently insert zeros at appropriate locations in the s-plane producing dierent
ltering functions. For example, switch S1 can introduce two zeros at the origin and
can therefore be used to generate a highpass lter, switch S2 can introduce one zero at
the origin and can therefore be used to generate a bandpass lter and switches S3 and
S4 can introduce zeros at innity producing lowpass lters with dierent DC values.
A combination of switches can be used to generate the other lter functions such as
allpass, notch and lowpass-notch as shown in Table 5.7.
Note, in the case of the bandpass lter and the amplitude equaliser, the current Io3
of OTA2 is feedforward, whilst in the case of the allpass lter this current is feedback.
This means that if both functions are required then an additional switch and current
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 136
Function Type N(s) S1 S2 S3 S4
Lowpass (DC gain = 1) gm2gm3
C1C2
0 0 1 0
Lowpass (DC gain = 2) 2gm2gm3
C1C2
0 0 1 1
Highpass s2 1 0 0 0
Bandpass (IC2 feedforward)sgm2
C1
0 1 0 0
Notch s2 + gm2gm3
C1C2
1 0 1 0
Lowpass notch s2 + 2gm2gm3
C1C21 0 1 1
Allpass (IC2 feedback) s2 sgm2
C1
+ gm2gm3
C1C2
1 1 1 0
Amplitude equaliser (IC2 feedforward) s2 + sgm2
C1
+ gm2gm3
C1C2
1 1 1 0
Table 5.7: Transfer functions available from the universal biquad
replica must be used. Although it is possible to fabricate the resistor R1 as a passive
on-chip resistor, it has been shown in section 5.1 that an active simulation of R1 is
more ecient in terms of silicon area and accuracy, as commonly known. Furthermore,
an active simulation of R1 is necessary to achieve tunable lter response by varying the
transconductance characteristics. The MO-OTA is hence modied such that a third
output is connected to the input of the active device as shown in Fig.5.13.
Vb2
gm1
3
2
Vb1
gm3
3
2
1
Vb3
C1
C2
gm2
3
1
2
S1IoutS3 S4S2
Iin1
Figure 5.13: Proposed universal biquad based on MO-OTAs
Adding a third output to the MO-OTA ensures that the biquad is based upon
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 137
only one type of active device, hence simplifying the transistor level design and layout
stage. Note that this modication is only valid, if the value of the simulated resistor is
equal to the reciprocal of the transconductance of the OTA. Based on this assumption
(R1 = 1=gm1), the universal biquad has the following pole frequency !0 and quality
factor Q:
!20 =
gm2gm3
C1C2!0Q
=gm2
C1(5.14)
This shows that Q is varied using gm2 and !0 can be tuned with gm3. Since the
transconductances gm2 and gm3 are proportional to the bias voltages of the OTAs (Vb2
and Vb3), it is seen that electronic tunability of the biquad characteristics is possible.
The !0 and Q sensitivities of the biquad are:
S!0gm1= 0 S!0gm2
=1
2S!0gm3
=1
2S!0C1
= 1
2S!0C2
= 1
2
SQgm1= 0 SQgm2
= 1
2SQgm3
=1
2SQC1
=1
2SQC2
= 1
2
all of which are small. To implement the universal biquad in Fig.5.13 using CMOS
technology, triple-output OTAs are required (section 3.5). The OTA of section 3.5 is
voltage-tunable over a wide gm range. This provides the ability to tune the lter !0
and Q parameters using an external voltage. In the proposed ltering structure two
positive and one negative replica are needed to generate the necessary currents (Io1,
Io2, Io3).
5.5.2 Design Examples
To conrm the theoretical analysis of the universal biquad, two design examples are
given. In the rst example, a 1MHz lowpass Butterworth lter was designed resulting
in the following component values: C1 = C2 = 10pF, gm1 = gm2 = 88.86S and gm3
= 44.43S. The transconductance values of the OTA were set using bias voltages Vb1
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 138
= Vb2 = -2.85V and Vb3 = -3.6V. Fig.5.14 shows the simulated frequency response of
the lter using 0.8m AMS CMOS process parameters and SPICE level 6 transistor
models and assuming an input current of 100A. The triple-output OTA transistors
sizes for this circuit are given in Table 5.8.
M1-M3 M4-M11 M12-M17
W (m) 20 46 16
L (m) 8 10 10
Table 5.8: Transistor dimensions of the MO-OTA based on 0.8m CMOS process
100kHz 300kHz 1.0MHz 3.0MHz 10MHzFrequency
10
0
-10
-20
-30
-40
-50
dB
Iout
Iin1MHz
4MHz
Figure 5.14: Simulated lowpass tunable lter (1-4MHz)
The lter exhibits a transition slope of -40dB/dec, which is in agreement with
theoretical lter synthesis. Changing the OTA bias voltages from Vb1 = Vb2 = -1.55V
to 5V and Vb3 = -3V to -1.8V, the lter cut-o frequency was varied from 1MHz
to 4MHz as shown in Fig.5.14. This frequency range has been chosen arbitrarily to
demonstrate the lter performance. Note, that the biquad switches (S1, S2, S3 and S4)
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 139
were simulated using paralleled n-channel and p-channel enhancement transistors.
100kHz 300kHz 1.0MHz 3.0MHz 10MHzFrequency
0
-10
-20
-30
-40
dB
Iout
Iin
Fo = 0.7MHz Fo = 3MHz
Figure 5.15: Simulated bandpass tunable lter (Q = 5)
In the second example, a bandpass lter with F0 = 1MHz and Q = 5 was designed
having the component values C1 = C2 = 10pF, gm1 = gm2 = 12.57S and gm3 =
314.16S. The gm values of the OTA were set using bias voltages Vb1 = Vb2 = -3.8V
and Vb3 = -2.3V. Fig.5.15 shows the simulated frequency response of the lter. The
close agreement between theory and simulation can be seen clearly.
Changing the bias voltage of the OTAs from Vb1 = Vb2 = -4V to 3.4V and Vb3
= -3.2V to 1.1V, the lter centre frequency was varied from 0.7MHz to 3MHz as
shown in Fig.5.15. Other ltering functions including highpass, notch and all-pass
were simulated and performed as expected.
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 140
5.5.3 Experimental Results
S1
Iout
I - V conversion
VoutEL2030
Iin
R1
-VCC
+VCC
Vin
V - I conversion
C2
transconductance control
-VCC
LT1228
LT1228
LT1228
LT1228
LT1228
LT1228
LT1228
LT1228
C1
S2 S3 S4
Figure 5.16: Discrete Implementation of universal biquad with V-I and I-V conversion
(C1 = C2 = 10pF)
In order to verify the theoretical analysis, a discrete implementation of the universal
biquad was produced. It is based on Linear Technology LT1228 single-output OTAs
[14], Maxim MAX312 analogue switches [37], passive components with 1% tolerances
and 5V supplies. Note that the implementation of MO-OTAs with the LT1228 device
implies the combination of two or more single-ended transconductors, each producing
one of the output currents [69] as indicated in Fig.5.16. Their transconductances were
dened by a set of bipolar current sources realised using MPQ7093 transistor arrays
[34]. Fig.5.16 shows a discrete prototype of the universal biquad with V-I and I-V
converters, which were used at the input and output respectively to facilitate lter
testing. The output I-V conversion is performed using an Elantec EL2030 wideband
current feedback amplier [23] in a transimpedance conguration. The gm of the various
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 141
OTAs were set manually using an external voltage sources to obtain a at response for
the lter passband.
Figure 5.17: Universal biquad lowpass frequency response (1-2MHz)
The measured response of a tunable Butterworth lowpass lter over the frequency
range of 1MHz to 2MHz is shown in Fig.5.17. Generally the lter frequency responses
are as theory predicts, however, there are some discrepancies between the ideal and
measured results. For example, the measured lters have insertion loss of -0.5dB com-
pared to 0dB (ideal), and up to 0.3dB passband peaking in the case of the 2MHz lter.
The maximumpower consumption of the biquad was approximately 220mW with 5V
power supplies in the case of the 2MHz lowpass lter. The THD of this lter is -58dB
with an input signal of 1Vpp and frequency of 100kHz.
Fig.5.18 shows the measured frequency response of (1MHz-2MHz) tunable bandpass
lter with Q = 5. Again generally there is a good agreement between the shape of
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 142
the ideal and measured frequency responses. However, some measured lters have an
insertion loss at F0 of -2dB, and up to 10% error in Q in the case of the 1MHz response.
The discrepancies between ideal and measured results can be directly attributed to
layout parasitic capacitances and accuracy problems in realising the W/L ratios of the
MO-OTAs.
Figure 5.18: Universal biquad bandpass frequency response (1-2MHz)
In summary, based on the presented typical measured results, it is fair to say
that the universal biquad has performed as theoretical analysis predicted. However,
it is possible that better correlation between ideal and measured performance may be
obtained if the eect of high-frequency parasitics and OTA input capacitances and
output resistance were taken into account. Also, previous work on digitally controlled
voltage-mode continuous-time lters [51] has identied that the parasitic impedances
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 143
of CMOS analogue switches may in uence the lter transfer function. Preliminary
simulations showed, that the proposed lter structure is little aected by the analogue
switch parasitics when operating at video frequencies.
5.6 Concluding Remarks
This chapter has reviewed the design of current-mode elliptic ladder lters based on the
signal ow graph simulation of passive lter prototypes using MO-OTAs. While this
approach exploits the low sensitivity properties of the ladder topology, it is relatively
dicult to implement and to tune. It has been shown, that for VLSI implementations, a
more ecient approach to the realisation of current-mode elliptic lters is based on the
cascade approach and the use of a recongurable notch lter structure with digitally
and independently programmable !z and !p positions. Section 5.4 has presented a
cascaded current-mode elliptic lter based on multiple-output OTAs and grounded
capacitors. The lter has the ability to generate both lowpass and highpass-notch
responses without changing the lter structure. This was achieved using a symmetrical
current switching technique based on two switches controlled by a 2-bit digital word.
It has been shown, how the proposed lter facilitates the design of high-order lowpass
and highpass elliptic lters with tunable bandwidth characteristics.
The theoretical analysis has been conrmed using simulation based on CMOS OTAs
and experimental results were obtained based on discrete implementations. Detailed
analysis of the lter high frequency response has shown how the response is aected
by the non-ideal characteristics of the OTAs. Although the chapter has focused on the
design of lowpass and highpass lters, the presented lter conguration is capable of
implementing elliptic bandpass functions by cascading lowpass and highpass sections.
The proposed lter should be particularly suitable for IC implementation because of
its regular structure, bandwidth tunability and the use of grounded capacitors.
With the focus on more versatile all-pole structures used as oversampling lters
toghether with data converters and with emphasis on lter versatility and tunability,
section 5.5 has introduced a new current-mode biquad with the ability to generate var-
CHAPTER 5. CURRENT-MODE OTA-C FILTERS 144
ious lter functions using digitally programmable zeros. It has been demonstrated that
the use of MO-OTAs facilitates the development of a universal biquad capable of com-
bining all the features of recently published current-mode lters. This includes the use
of minimum number of OTAs, utilisation of one type of active device, electronic tun-
ability and achieving dierent ltering functions without changing the biquad topology.
Simulated and measured results of various lter functions have conrmed the electronic
tunability advantage of the presented lter. The presented biquad is a key addition to
the building blocks of monolithic current-mode continuous-time lters and because of
its grounded capacitors, the biquad is particularly suitable for integrated mixed-signal
designs where single-poly CMOS processes are usually employed.
Chapter 6
Current-Mode Group-Delay
Equalisers
6.1 Introduction
So far, all previous chapters have focused on the analysis of gain-shaping lters, in
which the gain or magnitude response was specied. However, chapter 1 has claried
that in video signal processing, the phase response of a lter is of equal importance
for the signal processing task. If a signal is applied to a system input, the eect is not
immediately observable at the output, but occurs at a later time. Two useful measures
to describe this delay are the group-delay and the phase-delay functions, which arise
from the determination of signal transit time through linear time-invariant systems [9].
In general, the group-delay describes the delay of a packet of frequencies, whereas the
phase-delay is the delay of a single sinusoid waveform. The group-delay (!) is dened
as:
(!) = d(!)
d!(6.1)
and the phase-delay p(!) is dened as:
p(!) = (!)
!(6.2)
where (!) is the phase function of the system in radians. Note that these two
denitions yield the same value, if (!) is linear. In practical applications, the phase
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 146
function is not linear and therefore needs to be corrected, as indicated in section 1.1.1.
Particularly with respect to amplitude-modulated signals, the group-delay measure is
better suited to analyse physical video systems, because it can be shown that constant
group-delay enables distortionless transmission of the amplitude-modulated envelope
waveform [9]. This chapter will hence utilise the group-delay measure based on Eqn.6.1
to analyse video systems.
The compensation applied to correct delay distortions introduced by gain-shaping
lters and other parts of the signal processing system is referred to as group-delay
equalisation. One popular method to achieve at group-delay is to cascade a delay
equaliser, which may consist of several sections, with the gain-shaping lter [30, 45,
106]. The purpose of the delay equaliser is to introduce sucient additional delay
to the system to make the overall delay as at as possible. In addition, the delay
equaliser must not alter the gain response provided by the lter (i.e. it must exhibit
allpass amplitude characteristics).
The gain-shaping lter group-delay function is mathematically obtained as the
derivative of the phase function indicated by Eqn.6.1. In practical applications, how-
ever, it is common that the lter group-delay function to be equalised is represented
by a series of data points obtained from simulated or measured results.
In order to realise their full potential, current-mode lters must be capable of
use in applications where phase linearity or group-delay atness in the passband is a
major design consideration, such as video and high-frequency communication systems.
So far, only very little work has been reported which addresses the design of group-
delay equalisers, either current-mode or voltage-mode [30]. Exploiting the general
current-mode advantages discussed in chapter 5, this chapter will show that group-
delay equalisers can be realised based on MO-OTA circuit structures. Two design
methodologies will be discussed:
The rst method is the cascade approach, where 1st and 2nd-order allpass sections
are combined to yield a high-order group-delay function. Section 6.2 will intro-
duce a 1st-order current-mode allpass section based on MO-OTAs and present
its design equations. Furthermore, it will investigate the eectiveness of the uni-
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 147
versal biquad introduced in section 5.5 for the compensation of delay distortion
and propose a specic 2nd-order current-mode allpass section based on MO-OTAs
and grounded capacitors, including techniques for minimisation of the equaliser
active device count. In addition, a design strategy for high-order group-delay
functions will be presented and the numerical optimisation of circuit parameters
will be discussed.
The second method is the ladder-based approach, where high-order lter group-
delay functions are approximated directly without the typical high-Q peaks of
cascaded realisations, which will be claried later. Ladder-based group-delay
equalisation hence yields superior correction accuracy. Section 6.3 will introduce
a novel current-mode ladder-based group delay equaliser based on MO-OTAs and
grounded capacitors. Furthermore, a design algorithm for the numerical optimi-
sation of high-order group-delay functions will be presented and the coecient
matching of circuit parameters will be discussed.
In order to investigate the performance of the two design methodologies and com-
pare their component count, component spread and sensitivity, two 6th-order group-
delay equalisers will be designed in section 6.4 as an example.
6.2 Cascaded Group-Delay Equalisers
The most popular method to equalise the group delay of a lter is to cascade several
1st and 2nd-order allpass sections with the lter, such that the total delay of the system
comprises of the product of the delays of each section plus the gain-shaping lter.
The following sections will introduce such allpass congurations based on MO-OTAs,
present their design equations and discuss the numerical optimisation of their circuit
parameters.
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 148
6.2.1 First-order Equaliser Sections
For the realisation of cascaded odd-order allpass functions it is necessary to implement
1st-order allpass sections. Generally, a 1st-order allpass response is characterised by:
H1(s) =s
s+ (6.3)
where is the real pole-zero position. The group delay has been dened by Eqn.6.1
as the derivative of the phase with respect to frequency which results in
gd(!) =2
2 + !2(6.4)
Therefore, the delay at DC is calculated, given by
gd(DC) =2
(6.5)
The basic 1st-order allpass structure based on MO-OTAs is shown in Fig.6.1. Note,
that the overall output Iout is obtained as the sum of the gm1 negative output current
and the gm2 positive output current. To allow full CMOS integration, the grounded
resistor R1 should be replaced by an active circuit, which has been demonstrated in
section 5.2. The complete CMOS 1st-order allpass structure is shown in Fig.6.2. Note,
that this simulation of R1 is only valid if the value of the simulated resistor is equal to
the reciprocal of the transconductance of the associated OTA. It will be shown, that
this presents no problem, as it is necessary that gm1 = 1=R1 for the presented structure
to realise allpass response.
The current transfer function of the circuit in Fig.6.1 is derived as:
IoutIin
= s
gm2C1
sR1gm1
+ gm2C1
(6.6)
Under the assumption that gm1 = 1=R1, the transconductance gm1 cancels from the
transfer function (Eqn.6.6). To simplify the design procedure, the transconductances
can be arbitrarily set to gm1 = gm2 = gm. In this case, Eqn.6.6 will simplify to
IoutIin
= s gm
C1
s+ gmC1
=s
s+ (6.7)
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 149
C1
gm1
gm2
R1 Iout
Iin
Vb1
Vb2
Figure 6.1: 1st-order delay equaliser
C1
gm1
gm2
Iout
Iin
Vb1
Vb2
Figure 6.2: 1st-order delay equaliser with simulation of R1
Since the transconductance gm is usually proportional to an external bias current
or voltage, it is seen from Eqn.6.7 that electronic tunability of the DC delay is possible.
Under the above assumption for the transconductances, the real pole position of the
1st-order MO-OTA based allpass section is dened by the following equation:
=gmC1
(6.8)
Thus, this 1st-order allpass section will introduce gm-tunable DC group-delay char-
acteristics according to Eqn.6.5 depending on the value of the pole-zero position .
This is indicated in Fig.6.3, where ranges from 0.4 rad/s to 2 rad/s.
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 150
Figure 6.3: Normalised 1st-order group-delay graph
6.2.2 Second-order Equaliser Sections
It has been shown in the previous chapter, section 5.5, that the universal current-mode
biquad is capable of generating allpass response, if the switches S1, S2 and S3 are closed
and the current replica I3 of OTA2 provides a positive feedback current as indicated
in Fig. 5.5. The allpass transfer function of this circuit is given in Table 5.7. In order
to simplify the design process, it will be assumed that all transconductance values are
equal and normalised to unity: gm1 = gm2 = gm3 = 1S. Comparison with the standard
2nd-order allpass function yields the following design equations:
C1 =!0Q
C2 =1
!0Q(6.9)
The universal biquad hence provides a versatile and exible implementation of a
group-delay equaliser, which is in accordance with the current-mode design criteria
outlined in section 5.1.
However, in some applications it is desirable to implement specically 2nd-order
allpass sections using current-mode realisations, in order to minimise the overall tran-
sistor count and avoid the use of analogue switches, which can be sources of noise.
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 151
For these applications, a 2nd-order allpass based exclusively on MO-OTAs is shown in
Fig.6.4.
C1
gm1
gm2
R1
Iin
C2
gm4
gm3
IoutVb1
Vb2
Vb3
Vb4
Figure 6.4: 2nd-order delay equaliser
C1
gm1
gm2
Iin
C2
gm3
Iout
Vb1
Vb2
Vb3
Figure 6.5: 2nd-order delay equaliser with impedance simulation of R1 and reduction
of OTA device count
This structure is based on the two integrator loop lter in [88] with the addition of
OTA4 whose output is combined with the output of OTA1 to give the desired allpass
output. The current transfer function of the circuit can be formulated as:
H2(s) =IoutIin
=C1C2R1gm1s
2 C2R1gm1gm4s+R1gm1gm2gm3
C1C2s2 + C2R1gm1gm2s+ gm2gm3=s2 !0
Qs+ !2
0
s2 + !0Qs+ !2
0
(6.10)
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 152
where !0 and Q are the pole frequency and quality factor of the allpass respectively,
provided that gm1 = 1=R1, and gm2 = gm4.
Examining Fig.6.4 reveals that OTA2 and OTA4 have the same input voltage which
means that both will have the output current of equal value provided that gm2 = gm4.
This implies that the two OTAs may be combined into a single MO-OTA with the third
output current representing the output of OTA4, which is Iout in this case. Fig.6.5
shows the fully integrated 2nd-order delay equaliser using the optimum number of MO-
OTAs [4]. Assuming gm1 = gm2 = gm3 = gm4 = 1S yields the following simple design
equations :
C1 =Q
!0C2 =
1
!0Q(6.11)
From the design equations it is clear, that this 2nd-order allpass section will in-
troduce electronically variable group-delay characteristics with Q as parameter, as
indicated in Fig.6.6 where Q ranges from 0.5 to 6.
Figure 6.6: Normalised 2nd-order group-delay graph
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 153
6.2.3 Cascaded Group-Delay Equaliser Design
The previous two sections have introduced topologies and design equations for MO-
OTA based 1st and 2nd-order allpass sections. Cascading these sections aims to ap-
proximate a group-delay function of opposite shape to the lter group-delay graph.
To solve this general equaliser design problem for a given lter group-delay F (!),
two sets of parameters have to be determined: The rst is the minimum number n of
1st and 2nd-order allpass sections, whose group-delays achieve the desired at group-
delay characteristic total(!), when added together with F (!). The second is a set
of 1st-order pole-zero positions (if appropriate) and 2nd-order !0 and Q parameters,
whose group-delay functions approximate the inverse lter group-delay graphs. The
!0 and Q parameters are linked to the 1st and 2nd-order section component values by
means of coecient matching through the design equations Eqn.6.8 and Eqn.6.11. This
equalisation procedure is based on four steps:
1. An initial guess solution is generated for the component values Ci and gmi of a
2nd-order equaliser section with the equaliser delay E(!; k) for the rst iteration
(k = 1).
2. The total group-delay total(!; k) for the kth iteration is obtained by Eqn. 6.12
within the desired frequency band (!min ! !max) for the kth iteration.
total(!) = F (!) + E(!) (6.12)
3. The variation total(!; k) of the group-delay total(!; k) is calculated using the
cost function:
total(!; k) = max(total(!; k))min(total(!; k))
= max(F (!; k) + E(!; k)min(F (!; k) + E(!; k))
4. If a desired minimal group-delay variation is not achieved, the order n of the
group delay equaliser is increased and the algorithm continues from step (2).
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 154
Following this procedure will yield the required equaliser order n and the neces-
sary !0 and Q parameters to equalise the gain-shaping lter group-delay within the
frequency band of interest. A complete design example based on this procedure will
be presented in section 6.4.
6.3 Ladder-Based Group-Delay Equalisers
In the case of gain-shaping lters, chapter 2 and chapter 5 have already established the
ladder-based approach as the preferred method for high-order monolithic implementa-
tions. The low sensitivity properties of ladder realisations provide a strong motivation
to develop high-order group-delay equalisers based on the ladder approach. This tech-
nique aims to realise allpass characteristics by mirroring the poles of a ladder network
into the right-hand s-plane to generate opposite zero positions. It relies on active sim-
ulations of ladder networks and the implementation of a structure which will perform
pole mirroring to realise pre-dened group-delay functions of opposite shape to the lter
group-delay. Pole mirroring has initially been developed for digital allpass networks
[60] and has subsequently been applied to switched-capacitor [45] and voltage-mode
OTA-C realisations [106]. In this section, it will be shown how the ladder-based ap-
proach can be extended to the realisation of current-mode MO-OTA based group-delay
equalisers.
6.3.1 Current-Mode Ladder-Based Group-Delay Equalisers
In general, an allpass transfer function H(s) may be expressed as:
H(s) =P (s)
P (s)=
Pni=0 (1)
iisiPn
i=0 isi
(6.13)
where P (s) is a high-order polynomial of the complex frequency variable s with
coecients i. It has been shown [60], that this s-domain allpass function can be
re-arranged such that:
H(s) =P (s)
P (s)=
1 Y (s)
1 + Y (s)= 1
2
1 + Y (s)(6.14)
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 155
where Y (s) is a passive admittance function. Allpass networks may hence be re-
alised by implementing Eqn.6.14, because Y (s) can be expanded in continued fraction
form and can be synthesised by a singly terminated ladder. A current ow block-
diagram of Eqn.6.14 is given in Fig.6.7, in which four dierent blocks are easily identi-
ed: A current replicator to produce two identical current branches a and b, a summing
node to recombine those branches at the output, a gain of two stage and a network to
realise the 1 + Y transfer function, where Y is the admittance function Y of a singly
terminated ladder stage.
( )−
+1
1 Y s
Iin
Iout
Iin
Iin 1
2
Figure 6.7: Current-mode realisation of all-pass functions
Note that this block diagram already exploits two major advantages of current-
mode signal processing: Firstly, signal summing is performed simply by a circuit node
and secondly, the negative sign in Eqn.6.14 is implemented by reversing the current
direction after the gain block. Although the admittance function Y (s) will inherently
only provide complex pole positions, their locations are mirrored into the right hand
s-plane by the additional circuitry to provide allpass characteristics.
A signal ow graph (SFG) representation of Fig.6.7 and Eqn.6.14 as a generalised
approach to the realisation of ladder-based allpass functions is shown in Fig.6.8. Note
that all variables and operations (integration, scaling and summation) in this SFG refer
to currents and the signals in the nodes have unity gain, except where stated otherwise.
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 156
Iin
Iout
ab sC1
1sC2
1sCn
1sCn-1
1
-1 +1-1 +1-1
+1 +1 +1 -1 +1 -1
+1
Figure 6.8: Signal ow graph representation of ladder-based allpass function
6.3.2 MO-OTA Ladder-Based Group-Delay Equalisers
From the pure current branch representation of Fig.6.8, a block diagram realisation of a
general current-mode ladder based allpass lter is easily derived. For reasons discussed
in section 5.3, note that in Fig.6.9 an independent output from each block is indicated
for every signal path in which an output signal is required.
Iin
Iout
a
b+
+1
1/sT1 1/sT2 1/sTn-1 1/sTn
- +
- +
- +
- +
∫ ∫ ∫ ∫
-
2
pole-mirroring network active OTA-C ladder network
Figure 6.9: Current-mode ladder-based group-delay equaliser block diagram
Each of the fundamental building blocks in Fig.6.9 implements pure current transfer
characteristics. Hence, MO-OTAs can only be used in their implementation if the
impedance simulation techniques presented in section 5.2 are used. To realise the
block diagram operations of Fig.6.9, the following basic current-mode building blocks
have to be implemented:
1. A current duplicator, to provide two positive output currents, one connected
to the equaliser output and one providing the input for the ladder stage of the
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 157
circuit. This block is readily implemented by using the current buer introduced
in section 5.2 and utilising two positive output currents.
2. A block to provide a gain of two together with a reversal of the current direction.
This block cannot easily be implemented since a MO-OTA based amplier with
non-unity gain will always require an additional ohmic resistance at the input (see
section 5.2). Because of current-mode operation, however, one simple solution is
to sum two equi-directional output currents from a current buer to amplify the
current by a factor of two.
3. A current-mode integrator to form the ladder stage. This block has already been
presented in section 5.2.
Using these building blocks together with the signal ow graph in Fig.6.8, the
general topology for an nth-order current-mode ladder based group delay equaliser is
given in Fig.6.10.
gm1 gm2
Iin
Iout
C1
gm3gm4
C2
gm5
C3
gmn-1
Cn-1
gmn
Cn
Figure 6.10: nth-order current-mode ladder-based group-delay equaliser structure
It is clear from Fig.6.10 that the MO-OTAs gm3 to gmn implement the current
integrators of the ladder stage. The MO-OTA gm1 is a current replicator. One of its
two positive output currents (designated owing out of the device) is directly connected
to the output. The other current serves as input for the ladder stage. gm2 has all its
output currents designated negative. Its grounded input resistor provides the "1 + Y "
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 158
section of the group-delay function, while its other two output currents ensure a gain
of -2 is transmitted to the output.
Having established the general nth-order current-mode ladder-based group-delay
equaliser structure, the next step is to derive its transfer function coecients i for
any order n (see Eqn.6.13).
Using the Matlab c symbolic toolbox to solve the state variable expressions of the
equaliser structure, the following paragraph presents the relationships between i and
gm and Ci for equaliser orders 4 n 10.
4th-order
H4(s) =4s
4 3s3 + 2s
2 1s+ 04s4 + 3s3 + 2s2 + 1s+ 0
4 = C1C2C3C4
3 = gmC2C3C4
2 = g2m(C1C2 + C1C4 + C3C4)
1 = g3m(C2 + C4)
0 = g4m
5th-order
H5(s) =5s
5 + 4s4 3s
3 + 2s2 1s+ 0
5s5 + 4s4 + 3s3 + 2s2 + 1s+ 0
5 = C1C2C3C4C5
4 = gmC2C3C4C5
3 = g2m(C1C2(C3 + C5) + C4C5(C1 + C3))
2 = g3m(C2C3 + C2C5 + C4C5)
1 = g4m(C1 + C3 + C5)
0 = g5m
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 159
6th-order
H6(s) =6s
6 5s5 + 4s
4 3s3 + 2s
2 1s+ 06s6 + 5s5 + 4s4 + 3s3 + 2s2 + 1s+ 0
6 = C1C2C3C4C5C6
5 = gmC2C3C4C5C6
4 = g2m(C1C2(C3C4 + C3C6 + C5C6) + C4C5C6(C1 + C3))
3 = g3m(C5C6(C2 + C4) + C2C3(C4 + C6))
2 = g4m(C3C4 + C6(C3 + C5) + C1(C2 + C4 + C6))
1 = g5m(C2 + C4 + C6)
0 = g6m
7th-order
H7(s) =7s
7 + 6s6 5s
5 + 4s4 3s
3 + 2s2 1s+ 0
7s7 + 6s6 + 5s5 + 4s4 + 3s3 + 2s2 + 1s+ 0
7 = C1C2C3C4C5C6C7
6 = gmC2C3C4C5C6C7
5 = g2m(C1C2C3(C6C7 + C4C7 + C4C5) + C5C6C7(C1C2 + C1C4 + C3C4))
4 = g3m(C2C3(C4C5 + C4C7 + C6C7) + C5C6C7(C2 + C4))
3 = g4m(C1C2(C3 + C5 + C7) + C1C7(C4 + C6) + C3C4(C5 + C7) +
+C6C7(C3 + C5) + C1C4C5)
2 = g5m(C2(C3 + C5 + C7) + C7(C4 + C6) + C4C5)
1 = g6m(C1 + C3 + C5 + C7)
0 = g7m
8th-order
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 160
H8(s) =8s
8 7s7 + 6s
6 5s5 + 4s
4 3s3 + 2s
2 1s+ 08s8 + 7s7 + 6s6 + 5s5 + 4s4 + 3s3 + 2s2 + 1s+ 0
8 = C1C2C3C4C5C6C7C8
7 = gmC2C3C4C5C6C7C8
6 = g2m(C1C2C3(C8(C4C5 + C6C7 + C4C7) + C4C5C6) +
+C5C6C7C8(C3C4 + C1C2 + C1C4))
5 = g3m(C2C3C4C5(C6 + C8) + C7C8(C6(C2C3 + C2C5 + C4C5) + C2C3C4))
4 = g4m(C1C4(C5C6 + C7C8 + C5C8) + C3C4C5(C6 + C8) + C1C2(C3(C4 + C6 +
+C8) + C5(C6 + C8)) + C7C8(C6(C1 + C3 + C5) + C1C2 + C3C4))
3 = g5m(C7C8(C2 + C4 + C6) + C5(C2 + C4)(C6 + C8) + C2C3(C4 + C6 + C8))
2 = g6m(C1(C2 + C4 + C6 + C8) + C3(C4 + C6 + C8) + C5(C6 + C8) + C7C8)
1 = g7m(C2 + C4 + C6 + C8)
0 = g8m
9th-order
H9(s) =9s
9 + 8s8 7s
7 + 6s6 5s
5 + 4s4 3s
3 + 2s2 1s+ 0
9s9 + 8s8 + 7s7 + 6s6 + 5s5 + 4s4 + 3s3 + 2s2 + 1s+ 0
9 = C1C2C3C4C5C6C7C8C9
8 = gmC2C3C4C5C6C7C8C9
7 = g2m(C1C2C3(C4C5(C8C9 + C6C7 + C6C9) + C6C7C8C9)
+C7C8C9(C5C6(C1C4 + C1C2 + C3C4) + C1C2C3C4))
6 = g3m(C2C3C4(C8C9(C5 + C7) + C5C6(C7 + C9))
+C7C8C9(C5C6(C2 + C4) + C2C3C6))
5 = g4m(C1C2(C3C4(C5 + C7 + C9) + C3C6(C7 + C9) + C3C8C9)
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 161
+C8C9((C5 + C7)(C1C4 + C1C2 + C3C4) + C1C6C7) + C5C6(C4(C7 + C9)
(C1 + C3) + C6C7(C3 + C5) + C1C2C7))
4 = g5m(C7C8C9(C2 + C4 + C6) + C2C3(C4C7 + C6C7 + C4C5)
+C2C3C9(C4 + C6 + C8) + C5(C6(C7 + C9) + C8C9)(C2 + C4))
3 = g6m(C4(C1 + C3)(C5 + C7 + C9) + C1C2(C3 + C5 + C7 + C9)
+C8C9(C1 + C3 + C5 + C7) + C6(C 1 + C3 + C5)(C7 + C9))
2 = g7m(C2(C3 + C5 + C7 + C9) + C4(C5 + C7 + C9) + C6(C7 + C9) + C8C9)
1 = g8m(C1 + C3 + C5 + C7 + C9)
0 = g9m
10th-order
H10(s) =10s
10 9s9 + 8s
8 7s7 + 6s
6 5s5 + 4s
4 3s3 + 2s
2 1s+ 010s10 + 9s9 + 8s8 + 7s7 + 6s6 + 5s5 + 4s4 + 3s3 + 2s2 + 1s+ 0
10 = C1C2C3C4C5C6C7C8C9C10
9 = gmC2C3C4C5C6C7C8C9C10
8 = g2m(C1C2C3C4C5(C6C7(C8 + C10) + C9C10(C6 + C8)) +
+C1C2C3C4C7C8C9C10 + C6C7C8C9C10(C4C5(C1 + C3) + C1C2(C3 + C5)))
7 = g3m(C7C8C9C10(C2C3(C4 + C6) + C5C6(C2 + C4)) +
+C2C3C4C5(C6C7(C8 + C10) + C9C10(C6 + C8)))
6 = g4m(C1C2C3(C4C5(C6 + C8 + C10) + (C4C7 + C7C7)(C8 + C10) +
+C9C10(C4 + C6 + C8)) + C7C8C9C10(C1(C2 + C4 + C6) +
+C3(C4 + C6) + C5C6) + (C1C2C5 + C1C4C5 + C3C4C5)(C6C7(C8 + C10) +
+C9C10(C6 + C8)))
5 = g5m(C2C3C4(C5(C6 + C8 + C10) + C7(C8 + C10) + C9C10) +
+C8C9C10(C2(C3 + C5 + C7) + C4(C5 + C7) + C6C7) +
+(C2C3C6 + C2C5C6 + C4C5C6)(C7C8 + C7C10 + C9C10))
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 162
4 = g6m(C1C2C3(C4 + C6 + C8 + C10) + C1C9C10(C2 + C4 + C6 + C8) +
+C5(C1C2 + C1C4 + C3C4)(C6 + C8 + C10) +
+(C8 + C10)(C1C7(C2 + C4 + C6) + C3C7(C4 + C6) + C5C6C7) +
+C3C9C10(C4 + C6 + C8) + C5C9C10(C6 + C8) + C7C8C9C10)
3 = g7m(C2C3(C4 + C6 + C8 + C10) + C9C10(C2 + C4 + C6 + C8) +
+C4C5(C6 + C8 + C10) + (C8 + C10)(C2C7 + C4C7 + C6C7))
2 = g8m(C1(C2 + C4 + C6 + C8 + C10) + C3(C4 + C6 + C8 + C10) +
C5(C6 + C8 + C10) + C7(C8 + C10 + C(C10)
1 = g9m(C2 + C4 + C6 + C8 + C10)
0 = g10m
To demonstrate the normalised correction capability of ladder-based group-delay
equalisers, consider for example normalised equalisers of order n = 6 to n = 9, as
indicated in Fig.6.11.
Figure 6.11: Normalised 6th-order ladder-based group-delay graph
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 163
6.3.3 Ladder-Based Group-Delay Equaliser Design
The previous section has introduced a technique to generate ladder-based allpass
topologies using MO-OTAs. In contrast to the cascaded biquad approach (see sec-
tion 6.2), the ladder-based design methodology is integral and aims to appoximise
lter group-delay graph directly. This is achieved by curve-matching the high-order
polynomial E(!) to the inverse of the lter group-delay graph F (!). The result of this
design process is a signicantly better approximation than is possible with a cascade
of 2nd-order sections with its signicant high-Q peaks.
To solve the general equaliser design problem for a given lter group-delay F (!),
two sets of parameters have to be determined: The rst is the required order n of
the ladder-based allpass structure to achieve the desired at group-delay characteristic
total(!), when added together with F (!). The second is a set of polynomial coecients
i of the nth-order group-delay function that approximates the lter group-delay. Note
that these coecients i are directly linked to the equaliser component values by means
of coecient matching with the equations of section 6.3.2. The equalisation procedure
consists of minimising the overall group-delay ripple total(!; k) by means of curve-
matching approximation with the following steps:
1. An initial guess solution is generated for the order n and the coecients i of an
allpass function with the equaliser delay E(!; k) for the rst iteration (k = 1)
2. Given the order n of the equaliser transfer function, the associated group-delay
function E(!; k) can be derived according to Eqn.6.1 from the equaliser phase
function E(!). Note that the coecients i correspond to Eqn.6.13.
E(!) = 2 arctan
OdP (s)=j
EvP (s)
!j!
= 2arctan
0@Pn=2
i=1 (1)i12i1!
2i1Pn=2i=0 (1)
i2i!2i
1A (6.15)
3. Hence, the group-delay function E(!) is:
E(!) = d
d!(2 arctan(
Pn=2i=1 (1)
i12i1!2i1Pn=2
i=0 (1)i2i!2i
)) (6.16)
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 164
4. The overall group-delay total(!; k) for the kth iteration is obtained by Eqn. 6.17
within the desired frequency band (!min ! !max) for the kth iteration.
total(!) = F (!) + E(!) (6.17)
5. The variation total(!; k) of the group-delay total(!; k) is calculated using the
cost function:
total(!; k) = max(total(!; k))min(total(!; k))
= max(F (!; k) + E(!; k)min(F (!; k) + E(!; k)) (6.18)
6. If a desired minimal group-delay variation is not achieved, the order n of the
group-delay equaliser is increased and the algorithm continues from step (1).
By following this procedure, the required order n of the allpass and the coecients
i(k) of the nth-order allpass curve matching polynomial are determined. The result
represents coecients of a group-delay function of opposite shape to the lter group-
delay graph.
In the case of the cascade approach, the procedure to match the equaliser component
values to the 2nd-order !0 and Q parameters was simple and straight forward since it
was supported by design equations. This is not the case with ladder-based group-delay
equalisers since the transfer function polynomial is of higher order.
Manual calculation of the component values from the curve-matching polynomial
coecients is error-prone and tedious. To simplify the design process, a software has
been developed, which allows the automatic calculation of component values during
the optimisation process. This software incorporates an algorithm from the Matlab c
optimisation toolbox [36]. The curve matching algorithm is required to match an nth-
order polynomial to a series of data points within a given frequency range and return
the associated polynomial coecients. This algorithm is illustrated in Fig.6.12. The
input le listing for the Matlab c optimisation based on Fig.6.12 is reproduced in
appendix B, section B.3.
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 165
solution(C, gm)
error(αi)
analysis(αi)
polynomialcoefficients (αi)
initial guess(C, gm)
accept
specification(C, gm)
polynomialcoefficients (αi)
minimisation(αi)
reject
Figure 6.12: Optimisation algorithm ow chart
6.4 Design Examples and Comparison
To compare the performance of the two presented design methodologies, consider for
example the delay equalisation of a 7th-order elliptic lowpass lter designed to meet
the CCIR 601 specication as dened by the ITU (International Telecommunication
Union). The lter has the following characteristics: FC = 5.75MHz, passband ripple
= 0.03dB, stopband attenuation >40dB and transition bandwidth <2MHz.
This type of lter is often used as antialiasing or reconstruction lter in oversampling
digital video applications [10]. Typically, such lters require a group-delay ripple of
<4ns over 90% of the lter passband (5.2MHz). Based on current-mode operational
simulation introduced in section 5.3, simulation with typical transistor parameters of
the 0.8m AMS CMOS process shows that the lter has a group-delay ripple of F =
108ns up to 5.2MHz.
In the following sections, this lter group-delay will be equalised using the two pre-
sented design methodologies: The rst example utilises the ladder-based approach, the
second uses the cascade approach. Note that a comparison between the two methods
is only meaningful, if the equalisers are of the same order n.
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 166
6.4.1 Group-Delay Equaliser Example 1
Evaluating Eqn.6.18 and following the design procedure in section 6.3, it is calculated
that a 6th-order current-mode group-delay equaliser will reduce the lter delay ripple
to <4ns, which is within the specication. On the basis of Fig.6.10, the current-mode
implementation of a 6th-order allpass is :
gm1 gm2
Iin
Iout
C1
gm3 gm4
C2
gm5
C3
gm6
C4
gm7
C5
gm8
C6
Figure 6.13: 6th-order current-mode group delay equaliser
The transfer function of this equaliser is obtained from the equations in section 6.3.2.
Numerical optimisation based on the procedure outlined there yields the component
values of Table 6.1. Note that the maximum component spread between C1 and C6 is
8, which is small and hence desirable for monolithic implementation. Note also, that
the optimisation was terminated when the solution converged to <3.8ns group-delay
ripple.
component values C1 C2 C3 C4 C5 C6
normalised 0.4061 1.0536 1.4836 1.8288 2.3092 3.5106
assuming gm = 100S 1.2pF 3.2pF 4.5pF 5.6pF 7.1pF 10.7pF
Table 6.1: Optimised component values for 6th-order ladder-based group-delay equaliser
As mentioned before, the zero positions of an allpass function are mirror images of
the pole positions in the s-plane. Fig.6.14 conrms this result based on the values of
Table 6.1 showing the pole-zero plot of the 6th-order ladder-based group-delay equaliser
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 167
discussed above. In particular, the normalised equaliser pole and zero positions for this
example are:
p1 = z1 = 0:3927 j0:9855
p2 = z2 = 0:2323 j0:5336
p3 = z3 = 0:6267
p4 = z4 = 0:3488
(6.19)
-1 -0.5 0 0.5 1-1
-0.5
0
0.5
1
Re
Im
Figure 6.14: Pole-zero plot of 6th-order ladder-based group-delay equaliser
The denormalised component values for an equaliser having identical transconduc-
tances gm of 100S can also be found in Table 6.1. To implement the presented delay
equaliser using CMOS technology, the MO-OTAs are realised using the structure pre-
sented in section 3.5, with SPICE level 6 transistor models of the 0.8m AMS CMOS
n-well process. Utilising the component values of Table 6.1, the resulting group-delay
response is shown in Fig.6.15.
6.4.2 Group-Delay Equaliser Example 2
In order to allow comparison with the ladder-based example presented in the previous
section, a 6th-order group delay equaliser is designed based on the cascaded biquad
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 168
100kHz 300kHz 1.0MHz 3.0MHz 5.2MHzFrequency
500ns
400ns
300ns
200ns
100ns
0s
filter group-delay
equaliser group-delay
filter + equaliser group-delay
Figure 6.15: Simulated group-delay response of the lter, the ladder-based equaliser
and the combined response
structure outlined in section 6.2.2. Since the 2nd-order allpass in section 6.2.2 is struc-
turally simpler than the universal biquad, we will only consider its implementation
for this example (Fig.6.16). Numerical optimisation based on the procedure outlined
in section 6.2.2, yields the transfer function !0 and Q parameters for each 2nd-order
section I, II and III, which are given in Table 6.2.
section I section II section III
!0 0.5393 1.3052 0.8059
Q 0.4865 0.9877 0.6959
Table 6.2: 6th-order cascaded biquad group-delay equaliser !0 and Q parameters
Inserting the !0 and Q parameters into the equaliser design equations (Eqn.6.11)
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 169
C1
gm1Iin
gm2
C2
gm3
Vb1
Vb2
Vb3
section I section II section III
C3
gm4
Iout
gm5
C4
gm6
Vb4
Vb5
Vb6
C5
gm7
gm8
C6
gm9
Vb7
Vb8
Vb9
Figure 6.16: 6th-order cascaded biquad group-delay equaliser
and assuming all gm = 1S, we nd the normalised component values as shown in Table
6.3. Note that the component spread is less than 6 which is in the same order of
magnitude as the component spread for the ladder-based equaliser example.
component values C1 C2 C3 C4 C5 C6
normalised 0.9021 3.8117 0.7567 0.7758 0.8635 1.7827
assuming gm = 100S 2.8pF 11.7pF 2.3pF 2.3pF 2.6pF 5.5pF
Table 6.3: Optimised component values for 6th-order cascaded biquad group-delay
equaliser
The equaliser pole and zero positions for this example are shown below, together
with the pole-zero plot of the 6th-order cascaded biquad group-delay equaliser.
p1 = z1 = 0:6607 j0:9319
p2 = z2 = 0:5790 j0:6861
p3 = z3 = 0:5543 j0:4817
(6.20)
The denormalised component values for the cascaded biquad based equaliser having
identical transconductances gm of 100S are also included in Table 6.3. To implement
the presented delay equaliser using CMOS technology, multiple-output OTAs are re-
alised using the structure presented in section 3.5. Utilising the component values of
Table 6.3, the resulting group-delay response is shown in Fig.6.18. The overall equaliser
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 170
-1 -0.5 0 0.5 1-1
-0.5
0
0.5
1
Re
Im
Figure 6.17: Pole-zero plot of 6th-order cascaded biquad equaliser
group-delay is realised as the sum of the group-delays of each biquadratic section I, II
and III.
6.4.3 Group-Delay Equaliser Performance Comparison
Fig.6.15 shows, that the lter has group-delay ripple of 108ns between DC and 5.2MHz
(90% of lter passband edge). Comparing Fig.6.15 and Fig.6.18, it is clear that the
ladder-based equaliser has signicantly better correction accuracy since it has decreased
the overall lter group-delay ripple by 96.5% to 3.83ns, while the cascaded biquad based
equaliser only compensated the group-delay to 22.9% and exhibits 83.3ns overall ripple.
The eect of the lter delay variation is the introduction of distortion or ringing in
the lter step response. For example, the simulated step response of the 601 lter has
over 35% ringing, when a 250kHz squarewave of 1mA amplitude is applied to its input
(see Fig.6.19).
As Fig.6.19 shows, the 6th-order ladder-based equaliser reduces the ringing by 15%,
now exhibiting a peak of 305A compared to 342A without the equaliser. However,
the cascaded biquad equaliser in Fig.6.20 exhibits virtually no equalisation, and has
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 171
100kHz 300kHz 1.0MHz 3.0MHz 5.2MHz
Frequency
500ns
400ns
300ns
200ns
100ns
0s
filter group-delay
equaliser group-delay
equaliser + filter group-delay
group-delay section III
group-delay section II
group-delay section I
Figure 6.18: Group delay response of the lter, the cascaded biquad equaliser and the
combined response
not reduced the amplitude distortion.
This comparison proves the eciency of the proposed ladder-based group-delay
equalisation methodology. To achieve results comparable to those in Fig.6.19 with the
cascaded biquad approach, much higher equaliser orders have to be considered. This
will lead to increased component count and hence increased silicon area requirements.
Note that the ladder-based allpass generation technique is highly ecient in terms of
component count, as shown in Table 6.4, because independent of the equaliser order
n, only two MO-OTAs are required in addition to the current-mode integrators which
form the ladder stage. As a comparison, Table 6.4 includes the component count for
the current-mode biquadratic allpass structures presented in the previous section. It
is clear that, for transfer function orders n4, both techniques are equally ecient in
terms of component count. However, from orders n5 the ladder-based equalisation
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 172
2µs 3µs 4µs 5µs 6µs 7µs 8µs 9µs 10µs
Time
400µA
200µA
0A
-200µA
-400µA
Iout
filter filter + equaliser
342µA
305µA
244µA
Figure 6.19: Simulated step response of the lter only and combined with the ladder-
based equaliser
technique is more ecient, saving on average one OTA per order n.
Equaliser order Number of MO-OTAs Number of capacitors
cascaded biquad n 3n+mod2(n)2
n
Ladder-based n n+2 n
Table 6.4: Component count comparison of cascaded biquad and ladder-based group
delay equalisers (where n is the equaliser order and mod2(n) is the modulo remainder
of n divided by 2)
In active lter design, it is generally accepted that one-OTA-per-pole realisations
are canonical for low sensitivity realisation. For OTA-C realisations of ladder-based l-
ters, two additional OTAs are required to implement the termination resistors. Hence,
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 173
2µs 3µs 4µs 5µs 6µs 7µs 8µs 9µs 10µs
Time
400µA
200µA
0A
-200µA
-400µA
Iout
filter filter + equaliser
342µA
340µA
244µA
Figure 6.20: Simulated step response of the lter only and combined with the cascaded
biquad equaliser
a lter realisation is usually dened canonical, if it exhibits one-OTA-per-pole charac-
teristic plus two additional OTAs, which implement the terminations, and all OTAs
have identical transconductance values. Similarly, a group-delay equaliser can be de-
ned canonical, if it exhibits one-OTA-per-pole characteristic and only employs two
additional OTAs, which perform the pole mirroring, and all have identical transconduc-
tance values. The current-mode implementation presented in this section is canonical
by this denition, unlike the ladder-based voltage-mode implementation presented in
[45], which has to rely on dierent transconductance values.
An other advantage of the ladder-based approach to group-delay equalisation is its
low sensitivity to passive component tolerances. The detailed analysis in Appendix
A indicates, that the 6th-order ladder-based group-delay equaliser is four times less
sensitive to passive component tolerances than its cascaded biquad counterpart.
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 174
6.5 Discrete Equaliser Implementation
In order to verify the theoretical analysis presented in section 6.4.1, a discrete im-
plementation of the 6th-order ladder-based group-delay equaliser was produced. The
discrete realisation is based on Linear Technology LT1228 single-output OTAs, passive
components with 1% tolerances and 5V supplies. Note that the implementation of
MO-OTAs with the LT1228 device implies the combination of two or more single-ended
transconductors, each producing on of the output currents [69] as indicated in Fig.6.21.
Their transconductances were dened by a set of bipolar current sources realised using
MPQ7093 transistor arrays.
transconductance control
Iout
I - V conversion
VoutEL2030
Iin
-VCC
+VCC
Vin
V - I conversionLT1228
LT1228
C6
LT1228
LT1228
C5
LT1228
LT1228
C4
LT1228
LT1228
C3
LT1228
LT1228
C2
LT1228
LT1228
C1
LT1228
LT1228
R1
LT1228
LT1228
R2
-VCC
Figure 6.21: Discrete implementation of 6th-order ladder-based group-delay equaliser
Fig.6.21 shows the 6th-order ladder-based group-delay equaliser with V-I and I-V
converters which were used at the input and output respectively to facilitate testing.
The output I-V conversion is performed by an Elantec EL2030 wideband current feed-
back amplier in transimpedance conguration.
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 175
Figure 6.22: Comparison of simulated and measured group-delay of 6th-order ladder-
based group-delay equaliser
6.6 Concluding Remarks
This chapter has investigated in detail the theory and application of group-delay equal-
isation structures based on MO-OTA current-mode circuit topologies. Two design
methods have been presented, cascaded biquadratic allpass sections and ladder-based
allpass structures. The performance of the MO-OTA based universal biquad for the
realisation of allpass functions has brie y been reviewed. In addition, two new simple
current-mode delay equalisers based on MO-OTAs have been presented.
Furthermore, an ecient and canonical approach to MO-OTA based allpass sec-
tions has been introduced with the design of current-mode ladder-based group-delay
equalisers. Its main advantage is the use of only basic current-mode building blocks
CHAPTER 6. CURRENT-MODE GROUP-DELAY EQUALISERS 176
and grounded capacitors. The presented method is superior in terms of correction accu-
racy when compared with cascaded biquad equalisation methods, which will typically
exhibit group-delay ripple about 6 times larger than ladder-based equalisers.
In addition, detailed sensitivity analysis has shown that the presented method is
four times less sensitive to passive component tolerances than traditional techniques
based on biquadratic sections. Also, the presented methodology allows the ecient
design of high-order group-delay equalisers without excessive active device count.
Chapter 7
Conclusions and Areas of Further
Research
7.1 Conclusions
The main aim of this thesis has been the detailed investigation into the analysis and
design of transconductor-capacitor based structures for analogue video-lters including
phase and amplitude equalisation.
It has been demonstrated in chapter 2, that operational simulation is the most
ecient and exible approach to simulate the behaviour of passive ladder prototypes.
This approach should hence be used in all implementations of monolithic analogue
lters because operational simulation is canonical and oers the advantage that the
active circuit maintains the low sensitivity properties of the passive prototype.
Furthermore, the problem of amplitude equalisation and sinc(x)-correction has been
addressed and solved in chapter 2 with the design of two new OTA-C equalisers. In
applications where low lter passband ripple is specied, the equaliser 1 structure is
preferred over a recently introduced structure because it exhibits superior correction
accuracy and better performance due to a pair of complex transmission zeros, which
allow increased exibility in the shaping of the equaliser transfer function. The com-
pensation of OTA non-ideal eects in this equaliser 1 operating at video-frequencies
has been achieved by deriving a set of design equations incorporating the OTA input
CHAPTER 7. CONCLUSIONS AND AREAS OF FURTHER RESEARCH 178
capacitance and output resistance and the polynomial coecients used to correct the
sinc(x)-distortion. Because the equaliser 1 !0 and Q parameters cannot be indepen-
dently tuned, compensation of OTA non-ideal eects is only possible with the aid of
complex circuit analysis. The equaliser 2 structure has been introduced because it ex-
hibits enhanced compensation features owing to independent electronic control of its !0
and Q parameters by means of gm tuning, which allows simpler compensation for active
device non-ideal eects that the equaliser 1 structure. Equaliser 2 is the most eective
and versatile structure reported so far to allow easy correction of sinc(x)-distortion in
voltage-mode video-lters.
For the CMOS implementation of video-lters, a comprehensive selection of transistor-
level OTAs have been investigated in detail in chapter 3 with reference to performance
criteria including linearity, bandwidth, harmonic distortion and tuning range. Exten-
sive simulations have shown that the simple fully-balanced CMOS OTA introduced
by [58] is the preferred active device when designing in the voltage-mode approach,
because it exhibits a number of attractive features including very wide bandwidth,
low power dissipation and single low-voltage supply operation. Furthermore, when
designing in the current-mode approach, chapter 3 has identied a CMOS MO-OTA
structure [69] capable of providing multiple output currents with varying current di-
rections, which is a fundamental requirement for current-mode OTA-C lters. This
MO-OTA operates from 5V supply, exhibits good linearity and has the advantage of
structural simplicity, which allows easy conguration of the transistor-level topology
with respect to number and direction of output currents.
To examine the performance of an integrated OTA-C video-lter system, chapter
4 has reported on the design and implementation of a voltage-mode elliptic lowpass
lter and a biquadratic sinc(x)-equaliser. In order to increase the dynamic range of the
system, it has been based on fully-balanced topology. Although great care was taken
during the layout to ensure accurate circuit operation, it is now clear that automatic
tuning schemes have to be included in any analogue ltering system to compensate for
inevitable fabrication tolerances.
In chapter 5, methods and structures for the realisation of current-mode lters
CHAPTER 7. CONCLUSIONS AND AREAS OF FURTHER RESEARCH 179
based on the OTA-C approach have been presented. Two design methodologies have
been investigated, ladder-based topologies and cascaded biquad structures. While the
design of current-mode elliptic ladder lters has been reported, it does not oer tunable
frequency response characteristics which are required in most antialiasing and recon-
struction lter applications. To overcome this problem, section 5.4 has introduced a
methodology to obtain elliptic frequency response characteristics by cascading low-
pass or highpass-notch biquads. This oers the advantage that the elliptic response
is tunable, which is demonstrated with reference to a novel function-programmable
current-mode lter structure based on MO-OTAs capable of generating lowpass-notch
and highpass-notch responses. This was achieved without changing the lter topol-
ogy by using a symmetrical current switching technique controlled by a 2-bit digital
word. Simulation and measured results have conrmed the wide tuning capability of
the presented structure. Furthermore, the presented structure employs only grounded
capacitors which is advantageous in mixed-signal designs since cost-eective single-poly
CMOS processes can be employed. In contrast, elliptic ladder lters generally rely on
oating capacitors for the denition of the notch positions. Based on these advantages,
it is fair to say that the new biquad is a valuable addition to the building blocks of
current-mode elliptic lter design.
In many current-mode mixed-signal applications the focus is changing from high-
order circuits with narrow transition bands to simpler and more versatile all-pole struc-
tures used as oversampling lters at the front end of data converters. To account
for these changes, section 5.5 has developed and investigated a universal biquadratic
current-mode lter structure, capable of realising all commonly known lter responses
as well as allpass and amplitude equalisation characteristics. The biquad transfer func-
tion is digitally programmable and hence achieves maximum exibility without the
need to modify the circuit topology. This is an attractive feature, especially with re-
spect to automated VLSI implementation since it allows the biquad to be implemented
as a pre-dened layout cell. For these reasons, the presented biquad is a key addition
to the building blocks of monolithic current-mode lters and represents an important
step towards automatic analogue layout.
CHAPTER 7. CONCLUSIONS AND AREAS OF FURTHER RESEARCH 180
The investigation into the current-mode approach has been extended in chapter 6 by
discussing in detail the theory and application of group-delay equalisers based on MO-
OTA current-mode circuit topologies. Two design methodologies have been presented,
cascaded biquad and ladder-based allpass structures. In the cascade approach, new
current-mode 1st and 2nd-order allpass sections have been introduced which minimise
overall transistor count and circuit complexity. In the ladder-based approach, a novel
current-mode ladder-based group-delay equaliser structure based on MO-OTAs has
been presented. Simulations have conrmed, that the ladder-based design method is
more ecient to realise current-mode group-delay equalisers in terms of component
count, component spread, sensitivity and correction accuracy when compared to the
cascaded biquad approach. For any given group-delay specication, the required order
n of the ladder-based equaliser transfer function is signicantly lower that the cascaded
biquad transfer function. In turn, this means a signicant saving of active devices which
will minimise power consumption and silicon area requirement.
The research contained in this thesis allows the monolithic realisation of complete
transconductor-capacitor video-lters based on the presented structures. The design of
individual components of the video-lter, including lter sections, amplitude equalisers
and group-delay equalisers has been investigated in detail and ecient OTA-C solutions
have been proposed. Based on the preliminary measured results presented in this
thesis, complete video-lters including amplitude and group-delay equalisation can be
implemented using either the voltage-mode or the current-mode approach. However,
the current-mode approach oers additional benets including structural simplicity and
technological compatibility with digital circuit components. It is therefore likely, that
the current-mode approach represents a better choice for implementation of analogue
video-lters.
7.2 Areas of Further Research
In connection with the work presented in this thesis, four areas of further research may
be proposed:
CHAPTER 7. CONCLUSIONS AND AREAS OF FURTHER RESEARCH 181
The rst concerns an investigation into current-mode sinc(x)-equalisers based on
MO-OTAs and grounded capacitors. Although the universal biquad in chapter
5 is capable of realising sinc(x)- correction, it is not certain that this is the most
ecient structure possible. This investigation should consider various equalis-
ers with or without numerator s-term and preferably focus on tunable sinc(x)-
equaliser structures.
The second area concerns the practical verication of monolithic video-lters
based on the current-mode approach. The preliminary results indicate superior
performance in simulation and discrete realisation when compared to voltage-
mode structures. It is important to establish that superiority in CMOS imple-
mentation. This necessitates the availability of ecient current-mode sinc(x)-
equalisers. This investigation should include the research, design and implemen-
tation of automatic on-chip tuning schemes based on phase-locked loops to ensure
lter operation within the specication.
While this thesis has identied an approach for designing MO-OTAs by including
additional current sources to generate output currents, a more detailed investi-
gation should identify a better solution to the design of MO-OTAs which incor-
porates aspects of low-power single supply operation, minimal transistor count
and wide tuning range.
Another interesting area of research is based on the recently introduced current-
mode wave-active lter design methodology [47, 92, 39]. The wave-active design
of ladder lters, sinc(x)-equalisers and group-delay equalisers can be investigated
and ecient structures for the realisation of video-lters may be proposed.
Bibliography
[1] Austria Micro Systeme International AG. 0.8m CMOS Process Parameters,
1998.
[2] B.M. Al-Hashimi. Current-mode lter structure based on dual-output transcon-
ductance ampliers. Electronics Letters, 32(1):2526, 1996.
[3] B.M. Al-Hashimi, F. Dudek, M. Moniri, and J. Living. Integrated universal
biquad based on triple-output OTAs and using digitally programmable zeros.
IEE Proceedings, Part G: Circuits, Devices and Systems, 145(3):192196, 1998.
[4] B.M. Al-Hashimi, F. Dudek, and Y.C. Sun. Current-mode delay equaliser using
multiple-output OTAs. Analog Integrated Circuits and Signal Processing, 1999.
accepted for publication.
[5] E. Alacorn, A. Podeva, and E. Vidal. A complete OTA frequency model. IEEE
Proceedings of the 39th Midwest Symposium on Circuits and Systems, pages 455
458, 1997.
[6] M. Ali, M. Howe, E. Sanchez-Sinencio, and J. Ramirez-Angulo. A BiCMOS
low distortion tuneable OTA for continuous-time lters. IEEE Transactions on
Circuits and Systems I-Fundamental Theory and Applications, 40(1):4349, 1993.
[7] P.E. Allen and D.R. Holberg. CMOS Analog Circuit Design. Holt, Rinehart and
Winston, New York, 1987.
182
BIBLIOGRAPHY 183
[8] B.J. Blalock and P.E. Allen. A one-volt 120-W 1MHz OTA for standard CMOS
technology. IEEE International Symposium on Circuits and Systems (ISCAS),
1:305307, 1996.
[9] H.J. Blinchiko and A.I. Zverev. Filtering in the time and frequency domains.
Wiley, New York, 1976.
[10] P. Browdon, K.A. Mezher, and A.A. Muhieddine. The dynamic range of second-
order continuous-time active lters. IEEE Transactions on Circuits and Systems
I-Fundamental Theory and Applications, 43(5):370373, 1996.
[11] L.T. Bruton. Network transfer functions using the concepts of frequency-
dependent negative resistance. IEEE Transactions on Circuit Theory, 16(8):406
408, 1969.
[12] Z. Ciota, A. Napieralski, and J.L. Noullet. Analogue realisation of integrated FIR
lters. IEE Proceedings, Part G: Circuits, Devices and Systems, 143(5):274281,
1996.
[13] A.L. Coban, P.E. Allen, and X. Shi. Low-voltage analog IC design in CMOS
technology. IEEE Transaction on Circuits and Systems I-Fundamental Theory
and Applications, 42(11):955958, 1995.
[14] Linear Technology Corporation. Datasheet LT1228 - Current Feedback Amplier
with DC Gain Control, 1998.
[15] W.R. Daasch, M. Wedlake, and R. Schaumann. Automatic generation of
continuous-time elliptic lters. Electronics Letters, 28(24):22152216, 1992.
[16] G.A. De Veirman and R.G. Yamasaki. Design of a bipolar 10MHz programmable
continuous-time 0.05degree equiripple linear phase lter. IEEE Journal of Solid-
State Circuits, 27(3):324331, 1992.
[17] M. De Yong and J. Ramirez-Angulo. A hybrid OTA with very wide gain adjust-
ment range. IEEE International Symposium on Circuits and Systems (ISCAS),
1992.
BIBLIOGRAPHY 184
[18] F. Dudek, B.M. Al-Hashimi, and M. Moniri. CMOS equaliser for compensating
sinc(x)-distortion of video D/A converters. Electronics Letters, 33(19):16181619,
1997.
[19] F. Dudek, B.M. Al-Hashimi, and M. Moniri. Analysis and compensation of
OTA non-ideal eects in video frequency sinc(x)-equalisers. IEEE International
Symposium on Circuits and Systems (ISCAS), 1998.
[20] F. Dudek, B.M. Al-Hashimi, and M. Moniri. Compensation of non-ideal eects
in video frequency sinc(x)-equalisers using tunable gm-C structure. IEEE Inter-
national Symposium on Circuits and Systems (ISCAS), 1999.
[21] F. Dudek, B.M. Al-Hashimi, and M. Moniri. Current-mode elliptic lter design
based on symmetrical current switching. International Journal of Electronics,
1999. accepted for publication.
[22] F. Dudek, B.M. Al-Hashimi, and M. Moniri. Current-mode ladder-based group
delay equalisation. IEE Proceedings, Part G: Circuits, Devices and Systems,
1999. submitted for publication.
[23] Elantec Inc. Datasheet EL2030 - 120MHz Current Feedback Amplier, 1989.
[24] Elantec Inc. Datasheet EL2141 / EL2142 - 150MHz Dierential Twisted Pair
Driver, 1994.
[25] P.J. Fish. Electronic noise and low noise design. Macmillan Press Ltd., London,
1993.
[26] J.E. Franca and Y. Tsividis. Design of analog-digital VLSI circuits for telecom-
munications and signal processing. Prentice-Hall, London, 1994.
[27] R.L. Geiger and E. Sanchez-Sinencio. Active lter design using operational
transconductance amplers: A tutorial. IEEE Circuits and Devices Magazine,
1(2):2032, 1985.
BIBLIOGRAPHY 185
[28] V. Gopinathan, Y.P. Tsividis, K. Tan, and R.K. Hester. Design considerations
for high-frequency continuous-time lters. IEEE Journal of Solid-State Circuits,
25(6):13681378, 1990.
[29] D.G. Haigh, J.T. Taylor, and B. Singh. Continuous-time and switched-capacitor
monolithic lters based on current and charge simulation. IEE Proceedings, Part
G: Circuits, Dievices and Systems, 137(2):147154, 1990.
[30] R.K. Henderson, L. Ping, and J.I. Sewell. Extended remez algorithms for lter
amplitude and group delay approximation. IEE Proceedings, Part G: Circuits,
Devices and Systems, 138(3):289300, 1991.
[31] J.H. Huang, Z.H. Liu, M.C. Jeng, K. Hui, M. Chan, P.K. Ko, and C. Hu. BSIM3
manual. Department of Electrical Engineering and Computer Science, University
of California, Berkeley, California, 1989.
[32] L.P. Huelsman. Optimization - A powerful tool for analysis and design. IEEE
Transactions on Circuits and Systems I-Fundamental Theory and Applications,
40(7):431439, 1993.
[33] C.C. Hung, K. Halonen, V. Porra, and M. Ismail. Low-voltage CMOS gm-C lter
with rail-to-rail common-mode voltage. IEEE Proceedings of the 39th Midwest
Symposium on Circuits and Systems, pages 921924, 1997.
[34] Motorola Inc. Datasheet MPQ7093 - Quad PNP Transistor Array, 1997.
[35] Tanner Inc. L-Edit c Version 6.0, 1998.
[36] The Math Works Inc. Matlab c , 1997.
[37] MAXIM Integrated Products Inc. Datasheet MAX312 - Quad CMOS Analog
Switches, 1995.
[38] MAXIM Integrated Products Inc. Datasheet MAX4145 / MAX4145 - 300MHz
Low Power Dierential Line Driver / Receiver, 1996.
BIBLIOGRAPHY 186
[39] Tingle J. and C. Toumazou. Integrated current mode wave active lters based
on lossy integrators. IEEE Transactions on Circuits and Systems I-Fundamental
Theory and Applications, 42(5):237244, 1995.
[40] G. Jordan and N.A. Jordan. Theory of noise in metal oxide semiconductor de-
vices. IEEE Transactions on Electron Devices, 12(2):148156, 1965.
[41] A. Kaiser. A miropower CMOS continuous-time lowpass lter. IEEE Journal of
Solid-State Circuits, 24(3):736743, 1989.
[42] H. Khorramabadi and P.R. Gray. High-frequency CMOS continuous-time lters.
IEEE Journal of Solid-State Circuits, 19(6):939948, 1984.
[43] J.M. Khoury. Design of a 15MHz CMOS continuous-time lter with on-chip
tuning. IEEE Journal of Solid-State Circuits, 26(12):19881997, 1991.
[44] F. Krummenacher and N. Joehl. A 4MHz CMOS continuous-time lter with
on-chip automatic tuning. IEEE Journal of Solid-State Circuits, 23(3):750758,
1988.
[45] Ping. L. and J.I. Sewell. Active and digital ladder-based allpass lters. IEE
Proceedings, Part G: Circuits, Devices and Systems, 137(6):439445, 1990.
[46] K.R. Laker and W.M.C. Sansen. Design of Analog Integrated Circuits and Sys-
tems. McGraw-Hill Inc., New York, 1994.
[47] J.D. Lancaster, B.M. Al-Hashimi, and M. Moniri. Ecient S-I wave elliptic lters
based on direct and inverse Bruton transformation. IEE Proceedings, Part G:
Circuits, Devices and Systems, 1999. accepted for publication.
[48] M. Lee and M.A. Brooke. Design, fabrication and test of a 125Mb/s tran-
simpedance amplier using MOSIS 1.2m standard digital CMOS process. IEEE
37th Midwest Symposium on Circuits and Systems, pages 155157, 1994.
BIBLIOGRAPHY 187
[49] S. Lee, R.H. Zele, D.G. Allstot, and G. Liang. CMOS continuous-time current-
mode lters for high-frequency applications. IEEE Journal of Solid-State Cir-
cuits, 28(3):323329, 1993.
[50] S. Lee, R.H. Zele, D.J. Allstot, and G. Liang. A 40MHz CMOS continuous-
time current-mode lter. Proceedings of the IEEE Custom Integrated Circuits
Conference, pages 24.5.124.5.4, 1992.
[51] K.H. Loh, D.L. Hiser, W.J. Adams, and R.L. Geiger. A versatile digitally con-
trolled continuous-time lter structure with wide range and ne resolution capa-
bility. IEEE Transactions on Circuits and Systems II-Analog and Digital Signal
Processing, 39(5):265276, 1992.
[52] H.S. Malvar. Electronically controlled active-C lter and equaliser with opera-
tional transconductance ampliers. IEEE Transactions on Circuits and Systems
I-Fundamental Theory and Applications, 31(7):645649, 1984.
[53] I. Mehr and D.R. Welland. A CMOS continuous-time gm-C lter for PRML
read channel applications at 150Mb/s and beyond. IEEE Journal of Solid-State
Circuits, 32(4):499513, 1997.
[54] MicroSim Corp. PSpice c Version 7.2, Reference Handbook, 1997.
[55] M. Moniri and B.M. Al-Hashimi. Systematic generation of current-mode dual-
output OTA lters using a building block approach. IEEE International Journal
of Electronics, 83(1):3748, 1997.
[56] J. Nabicht and E. Sanchez-Sinencio. Low-voltage current-mode lters: High
performance and limitations. IEEE 37th Midwest Symposium on Circuits and
Systems, pages 103106, 1994.
[57] B. Nauta. Linear CMOS transconductance element for VHF lters. Electronics
Letters, 25(7):448450, 1989.
[58] B. Nauta. A CMOS transconductance-C lter technique for very high frequencies.
IEEE Journal of Solid-State Circuits, 27(2):142153, 1992.
BIBLIOGRAPHY 188
[59] A. Nedlungadi and T.R. Visvanathan. Design of linear CMOS transconductance
elements. IEEE Transactions on Circuits and Systems I-Fundamental Theory
and Applications, 31(10):891894, 1984.
[60] B. Nowrouzian and L.T. Bruton. Novel approach to exact design of digital LDI
allpass networks. Electronics Letters, 25(22):14821485, 1989.
[61] H.J. Orchard. Inductorless lters. Electronics Letters, 2(3):224225, 1966.
[62] C.S. Park and R. Schaumann. A high-frequency CMOS linear transconductance
element. IEEE Transactions on Circuits and Systems I-Fundamental Theory and
Applications, 33(11):11321138, 1986.
[63] C.S. Park and R. Schaumann. Design of a 4MHz analog integrated CMOS
transconductance-C bandpass lter. IEEE Journal of Solid-State Circuits,
23(4):987995, 1988.
[64] L. Pennock. CMOS triode transconductor for continuous-time active integrated
lters. Electronics Letters, 21(18):817818, 1985.
[65] K.D. Peterson and R.L. Geiger. CMOS OTA structures with improved linearity.
IEEE International Symposium on Circuits and Systems (ISCAS), 1987.
[66] Christophe Pujol. CMOS Group-Delay Equaliser Design using Transconductance
Ampliers, 1997. MSc thesis, School of Engineering and Advanced Technology,
Staordshire University.
[67] J. Ramirez-Angulo, M. Robinson, and E. Sanchez-Sinencio. Current-mode
continuous-time lters: Two design approaches. IEEE Transactions on Circuits
and Systems II-Analog and Digital Signal Processing, 39:337341, 1992.
[68] J. Ramirez-Angulo and E. Sanchez-Sinencio. Programmable BiCMOS transcon-
ductor for capacitor-transconductor lters. Electronics Letters, 28(13):11851188,
1992.
BIBLIOGRAPHY 189
[69] J. Ramirez-Angulo and E. Sanchez-Sinencio. High-frequency compensated
current-mode ladder lters using multiple-output OTAs. IEEE Transactions
on Circuits and Systems II-Analog and Digital Signal Processing, 41(9):581586,
1994.
[70] J. Ramirez-Angulo, E. Sanchez-Sinencio, and M. Howe. Large fQ second-order
lters using multiple-output OTAs. IEEE Transactions on Circuits and Systems
I-Fundamental Theory and Applications, 41(9):587592, 1994.
[71] J. Ramirez-Angulo and K.H. Treece. A second generation linear low voltage BiC-
MOS OTA. IEEE International Symposium on Circuits and Systems (ISCAS),
2:11721175, 1994.
[72] F. Rezzi, A. Baschirotto, and R. Castello. A 3V pseudo-dierential transconduc-
tor with intrinsic rejection of the common-mode input signal. IEEE 37th Midwest
Symposium on Circuits and Systems, pages 8588, 1994.
[73] F. Rezzi, A. Baschirotto, and R. Castello. A 3V 12-55MHz BiCMOS pseudo-
dierential continuous-time lter. IEEE Transactions on Circuits and Systems
I-Fundamental Theory and Applications, 42(11):896903, 1995.
[74] M. Robin and M. Poulin. Digital Television Fundamentals. McGraw-Hill, New
York, 1997.
[75] R. Schaumann. Design of continuous-time fully integrated lters: A review. IEE
Proceedings, Part G: Circuits, Devices and Systems, 136(4):184190, 1989.
[76] R. Schaumann, M.S. Ghausi, and K.R. Laker. Design of analog lters: passive
active RC and switched capacitor. Prentice-Hall, London, 1990.
[77] R. Seara, S.N. Filho, J.C.M. Bermudez, and J. Mayer. On the compensation
of the (sinx)/x distortion in discrete-time to continuous-time signal conversions.
IEEE Transactions on Circuits and Systems I-Fundamental Theory and Appli-
cations, 42(6):343351, 1995.
BIBLIOGRAPHY 190
[78] A.S. Sedra and P.O. Brackett. Filter theory and design: active and passive.
Matrix Inc., Portland, Oregon, 1978.
[79] E. Seevinck and R.F. Wassenaar. A versatile CMOS linear transconductor /
square-law function circuit. IEEE Journal of Solid-State Circuits, 22(3):366377,
1987.
[80] HARRIS Semiconductor Corporation. Datasheet HFA1212 - Dual 350MHz
Closed Loop Buer Amplier, 1996.
[81] S. Sharma, J.T. Taylor, and D.G. Haigh. Stray-free second-order circuit for
correction of sample-and-hold amplitude distortion in switched-capacitor lters.
Electronics Letters, 24(16):10071008, 1988.
[82] Z. Shujiang and G. Li Ping. A novel approach for designing continuous-time
lters based on CCII. IEEE International Symposium on Circuits and Systems
(ISCAS), 5:301304, 1994.
[83] J. Silva-Martinez, M.S.J. Steyaert, and W.M.C. Sansen. A large-signal very
low distortion transconductor for high-frequency continuous-time lters. IEEE
Journal of Solid-State Circuits, 26(7):946954, 1991.
[84] J. Silva-Martinez, M.S.J. Steyaert, and W.M.C. Sansen. Design techniques for
high-perforamnce full-CMOS OTA-RC continuous-time lters. IEEE Journal of
Solid-State Circuits, 27(7):9931000, 1992.
[85] W.M. Snelgrove and A. Shoval. A balanced 0.9m CMOS transconductance-
C lter tuneable over the VHF range. IEEE Journal of Solid-State Circuits,
27(3):31433, 1992.
[86] B. Stefanelli and A. Kaiser. A 2m CMOS fth-order lowpass continuous-time
lter for video frequency applications. IEEE Journal of Solid-State Circuits,
28(7):713718, 1993.
BIBLIOGRAPHY 191
[87] Y.C. Sun and J.K. Fidler. Minimum component multiple integrator loop OTA-
grounded capacitor all-pole lters. Proceedings of the 37th Midwest Symposium
on Circuits and Systems, 1:983986, 1994.
[88] Y.C. Sun and J.K. Fidler. Structure generation of current-mode 2 integrator loop
dual-output-OTA grounded capacitor lters. IEEE Transactions on Circuits and
Systems II-Analog and Digital Signal Processing, 43(9):659663, 1996.
[89] S. Szczepanski, A. Wyszynski, and R. Schaumann. Highly-linear voltage-
controlled CMOS transconductors. IEEE Transactions on Circuits and Systems
I-Fundamental Theory and Applications, 40(4):258262, 1993.
[90] M.A. Tan and R. Schaumann. Design of a general biquadratic lter section with
only transconductances and grounded capacitors. IEEE Transactions on Circuits
and Systems I-Fundamental Theory and Applications, 35(4):478480, 1988.
[91] M.A. Tan and R. Schaumann. Simulating general-parameter LC-ladder lters
for monolithic realisations with only transconductance elements and grounded
capacitors. IEEE transactions on Circuits and Systems I-Fundamental Theory
and Applications, 36(2):299307, 1989.
[92] J. Tingle and C. Toumazou. Low sensitivity simulation of LC lattice sections
using the current-mode wave active topology. Electronics Letters, 29(4):396398,
1993.
[93] R.R. Torrance, T.R. Viswanathan, and J.V. Hanson. CMOS voltage to current
transducers. IEEE Transactions on Circuits and Systems I-Fundamental Theory
and Applications, 32(11):10971104, 1985.
[94] C. Toumazou. Current-mode analogue signal processing - Editorial. IEE Pro-
ceedings,Part G: Circuits, Devices and Systems, 137(2):1, 1990.
[95] Y. Tsividis, M. Banu, and J. Khoury. Continuous-time MOSFET-C lters in
VLSI. IEEE Transactions on Circuits and Systems I-Fundamental Theory and
Applications, 33(2):125140, 1986.
BIBLIOGRAPHY 192
[96] Y.P. Tsividis. Integrated continuous-time lter design - An overview. IEEE
Journal of Solid-State Circuits, 29(3):166175, 1994.
[97] T. Tsukutani, M. Higashimura, M. Ishida, S. Tsuiki, and Y. Fukui. A general
class of current-mode high-order OTA-C lters. International Journal of Elec-
tronics, 81(6):663669, 1996.
[98] International Telecommunication Union. CCIR601 - Encoding Parameters of
Digital Television for Studios. International Telecommunication Union, Geneva,
Switzerland, 1990.
[99] G. Van Ruymbeke, C.C. Enz, and F. Krummenacher. A BiCMOS programmable
continuous-time lter using image-parameter method synthesis and voltage-
companding technique. IEEE Journal of Solid-State Circuits, 32(3):377387,
1997.
[100] M.E. Van Valkenburg. Analog lter design. Holt, Rinehart and Winston, New
York, 1982.
[101] R. Wang and R. Harjani. Partial positive feedback for gain enhancement of low-
power CMOS OTAs. Analog Integrated Circuits and Signal Processing, 12(8):21
35, 1995.
[102] P. Wu, R. Schaumann, and W.R. Daasch. A 20MHz fully-balanced
transconductance-C lter in 2m CMOS technology. IEEE International Sym-
posium on Circuits and Systems (ISCAS), 2:11881191, 1993.
[103] A. Wyszinski, R. Schaumann, S. Szczepanski, and P. Van Halen. Design of
a 2.7GHz linear OTA and a 250MHz elliptic lter in bipolar transistor array
technology. IEEE Transactions on Circuits and Systems I-Fundamental Theory
and Applications, 40(1):1931, 1993.
[104] A. Wyszynski and R. Schaumann. A current-mode biquadratic amplitude equal-
izer. Analog Integrated Circuits and Signal Processing, 4(2):161166, 1993.
BIBLIOGRAPHY 193
[105] A. Wyszynski and R. Schaumann. VHF highly linear fully-balanced CMOS OTA.
IEEE International Symposium on Circuits and Systems (ISCAS), pages 1156
1159, 1993.
[106] L. Yue, N.P.J. Greer, and J.I. Sewell. Ecient design of ladder-based
transconductor-capacitor lters and equalisers. IEE Proceedings, Part G: Cir-
cuits, Devices and Systems, 142(4):264272, 1995.
[107] R.H. Zele, S. Lee, and D.J. Allstot. A 3V-125MHz CMOS continuous-time lter.
IEEE International Symposium on Circuits and Systems (ISCAS), 2:11641167,
1994.
[108] A.I. Zverev. Handbook of lter synthesis. Wiley, New York, 1976.
Appendix A
Sensitivity Comparison
The purpose of this comparison is to evaluate the group-delay equaliser design method-
ologies presented in chapter 6 with respect to their passive component sensitivities by
numerically deriving sensitivity expressions for the two 6th-order design examples pre-
sented in section 6.4.
In general, the measured response of a circuit can dier signicantly from its nom-
inal response (i.e. the response obtained from the circuit design process) due to in-
accuracies in component values. For example, manufacturing tolerances of CMOS
capacitors can be up to 20% of their respective absolute value. Moreover, component
values vary owing to environmental eects such as temperature, humidity and ageing.
The study of these eects of component deviation on the circuit response is known as
sensitivity analysis, where the term sensitivity is usually dened as
SPx =x
P
@P
@x(A.1)
The above equation expresses the relative dierential sensitivity of a function P to
a variable x (normally a circuit component). The concept of sensitivity is of great im-
portance to the designer, since it allows to quantify the eects of component tolerances
on the circuit performance.
194
APPENDIX A. SENSITIVITY COMPARISON 195
A.1 Sensitivity Relations
Before Eqn.A.1 can be evaluated for the given design examples, it is necessary to
introduce some important sensitivity relationships, which will be used later in this
section. Note that the following relations are not exhaustive and a more comprehensive
overview can be found in [76] and [100]. If P is dened as a rational function (P =
N=D), where N and D are generally complex functions of s = j!, then Eqn.A.1 can
be rewritten as:
SPx =@(logP )
@(log x)(A.2)
and with the identity expression for natural logarithms (logP = logN logD), the
overall network sensitivity can be expressed by the dierence between the numerator
and denominator sensitivity.
SPx = SNx SDx (A.3)
It is necessary to introduce another sensitivity measure, called semi-relative sensi-
tivity. This measure is particularly useful if either x or P are nominally zero, which
would render Eqn.A.1 useless. Semi-relative sensitivity will be dened as
SRPx =
@(logP )
@x=
1
P
@P
@xjx=0 (A.4)
or
SRPx =
@P
@(logx)= x
@P
@xjP=0 (A.5)
Finally, and most importantly, it will be shown how to derive the relative magnitude
sensitivity and the semi-relative phase sensitivity. Because P is assumed to be generally
complex, it can be written in modulus and argument form (P = jP j ej). Taking
natural logarithms,
log P = log jP j+ j
and
@(logP )
@(log x)=@(log jP j)
@(log x)+ j
@
@(log x)
APPENDIX A. SENSITIVITY COMPARISON 196
yields
SPx = S jP jx + jSR
x (A.6)
Eqn.A.6 re ects an important result. The relative magnitude sensitivity SjP jx and
the semi-relative phase sensitivity SRx may simply be found from the corresponding
network function sensitivity as:
S jP jx = <fSPx g
SRx = =fSPx g (A.7)
where <fSPx g and =fSPx g are the real and the imaginary part of the function
sensitivity respectively.
Using these equations the following section will show, that if P is an allpass function,
then the relative magnitude sensitivity is zero for all frequencies !. It has been shown
(Eqn.6.14), that any allpass function can be expressed as:
H(j!) =P (j!)
P (j!)=N(j!)
D(j!)=<fP (!)g j=fP (!)g
<fP (!)g+ j=fP (!)g= ej(!) (A.8)
Starting from Eqn.A.3, it is:
SH(s)x = SP (s)x SP (s)x = S<fP (s)gj=fP (s)g
x S<fP (s)g+j=fP (s)gx (A.9)
In turn, this equation can also be expressed as follows by means of complex function
manipulation. Note that for reasons of clarity, the independent frequency variable (s)
has been omitted during this deduction, such that P = P (s):
SHx =<fPgS<fPg
x j=fPgS=fPgx
<fPg j=fPg<fPgS<fPg
x + j=fPgS=fPgx
<fPg+ j=fPg(A.10)
Remember that this a complex equation in s. It can hence be split into real and
imaginary part according to Eqn.A.6 and it will be shown that the real part of this
equation is identical zero.
APPENDIX A. SENSITIVITY COMPARISON 197
<fSHx g =<fPg(<fPgS<fPg
x <fPgS<fPgx ) + =fPg(=fPgS=fPg
x =fPgS=fPgx )
<fPg2 + =fPg2
=fSHx g ==fPg(<fPgS<fPg
x + <fPgS<fPgx )<fPg(=fPgS=fPg
x + =fPgS=fPgx )
<fPg2 + =fPg2
Observe, that the real part of the sensitivity expression is identical zero since the
numerator sensitivity expressions in round brackets cancel. In turn, the imaginary part
of the sensitivity expression simplies to:
=fSH(s)x g =
2=fP (s)g<fP (s)g(S<fP (s)gx S=fP (s)g
x )
<fP (s)g2 + =fP (s)g2(A.11)
Substantiated by the above equations, and owing to the fact that in allpass functions
the numerator and denominator coecients are equal per denition (see Eqn.A.8), it
has been shown that the relative magnitude sensitivity of the transfer function is zero
independent of the frequency variable (s).
To compare the performance of the two group-delay equaliser examples presented in
section 6.4, only the semi-relative phase sensitivity measure needs to be examined. The
semi-relative phase sensitivities of the transfer functions to all the passive components
in the two circuits were calculated over the normalised frequency range ! = 0.01 to 2
radians per second, where !=1 corresponds to the gain shaping lter passband edge.
The sensitivity graphs are intended to illustrate the range of sensitivity values for
a particular equaliser topology, rather than the sensitivity function of a particular
component.
Based on the normalised component values of the cascaded-biquad equaliser in
Table 6.3, Eqn.A.12 shows the transfer function of the 6th-order allpass, which gives
rise to the normalised sensitivity graph in Fig.A.1. Note that in the cascaded biquad
example some components share the same sensitivity function, resulting in fewer plots
per graph than number of components in the circuit.
H(s) =(s2 1:1085s + 0:2908)(s2 1:3215s + 1:7034)(s2 1:1581s + 0:6496)
(s2 + 1:1085s + 0:2908)(s2 + 1:3215s + 1:7034)(s2 + 1:1581s + 0:6496)(A.12)
APPENDIX A. SENSITIVITY COMPARISON 198
Figure A.1: Phase sensitivity of 6th-order cascaded biquad group-delay equaliser
Using the normalised component values of the ladder-based equaliser in Table 6.1,
Eqn.A.13 shows the transfer function of the 6th-order allpass, which gives rise to the
normalised sensitivity graph in Fig.A.2.
H(s) =9:4118s6 23:1737s5 + 15:7919s4 33:4022s3 + 18:6248s2 6:3929s + 1
9:4118s6 + 23:1737s5 + 15:7919s4 + 33:4022s3 + 18:6248s2 + 6:3929s + 1(A.13)
In order to compare the phase sensitivity graphs, two methods may be considered.
Firstly, they can be compared on the basis of the peak or the peak-to-peak dierences in
the sensitivities of the most sensitive components, or secondly on the maximum peak-
to-peak sensitivities of all the components. Although these options are not exhaustive,
in both cases the same order of merit appears to emerge, namely that the ladder-based
allpass approach is signicantly less sensitive to passive component tolerances than the
cascaded biquad allpass approach.
APPENDIX A. SENSITIVITY COMPARISON 199
Figure A.2: Phase sensitivity of 6th-order ladder-based group-delay equaliser
In particular, the maximum peak-to-peak sensitivity spread using the ladder-based
approach is 2 percent (element C6 from -0.4% to +1.6%), while in the cascaded biquad
approach the same measure is 8 percent (element C5 from -2.5% to +5.5%). This
sensitivity spread is four times bigger than with ladder-based group-delay equalisers.
Also, the actual position of the peak sensitivity in the frequency response can be
seen to dier amongst the two allpass structures. In the case of the ladder-based allpass,
the sensitivity maxima are well conned to the passband, whereas the cascaded biquad
based allpass exhibits sensitivity peaks close to the passband edge.
Appendix B
Optimisation Source Code Listings
This appendix provides listings of three Matlab c [36] m-les, which were developed
to carry out the curve-matching optimisation. All three programs consist of two parts,
the main program which denes the initial guess and calls the optimisation routine,
and the function to be optimised, which is being called by the optimisation routine
constr. The three m-les are:
1. sinc1.m for the sinc(x)-equaliser 1 structure of chapter 2
2. sinc2.m for the sinc(x)-equaliser 2 structure of chapter 2
3. group6.m for the ladder-based group-delay equaliser of chapter 6
Note that some of the group-delay equalisation m-le group6.m was originally
developed by [66] for the design of ladder-based group-delay equalisers based on the
voltage-mode approach. The m-les return a graphical representation of the normalised
frequency responses of the matched curves and the normalised values of the respective
circuit components.
200
APPENDIX B. OPTIMISATION SOURCE CODE LISTINGS 201
B.1 Sinc(x)-Equaliser 1
************* sinc1.m main program *************
function [num,den] = ampopt5(Fcoralpha,Fs,C2real,printornot);
format long;
if exist('printornot')==0,
printornot ='xxxxx';
else,
printornot='print';
end;
if exist('C2real')==0 & exist('Fc')==0,
C2real=1;
Fc=1;
alpha=Fcoralpha;
else,
Fc=Fcoralpha;
alpha=Fs/Fc;
end;
disp(' 2nd-order sinc(x)-equaliser design program:- F.Dudek 1996 ');
disp(' for equaliser 1, based on five OTA`s ')
fvar=linspace(0,1,1024); %frequency vector
mag=1./sinc(fvar/(alpha)); %magnitude vector to be approximated
x0 = [0.83 1.25 3]; %initial guess set up as [Ks^2 + Wo/Q*s + Wo^2]
options = [];
vlb=zeros(size(x0)); %lower bound = 0 for K,Wo/Q,and Wo^2;
vub=3*ones(size(x0)); %upper bound
options(1) = 1; %show optimisation result as they occur
options(14)=10\^10; %max number of iterations
[x,options]=constr('aofunc5', x0, options,vlb,vub,[],mag,fvar); %optimisation
a=x(1);
b=x(2);
c=x(3);
num=[a b c];
den=[1 b c];
h = freqs(num,den,fvar);
magni = abs(h);
plot(fvar,magni,fvar,mag,'-.');
pause;
APPENDIX B. OPTIMISATION SOURCE CODE LISTINGS 202
if printornot == 'print',
print;
end;
close;
C1=1;
C2=(c/(b^2*a))*C1;
gm=(c/(a*b))*C1;
gm5=(c/b)*C1;
disp('Equaliser 1, based on five OTAs');
disp('=================================');
disp(sprintf('alpha = %.6E' ,alpha));
disp(sprintf('C1 = %.6E' ,C1));
disp(sprintf('C2 = %.6E' ,C2));
disp(sprintf('gm = %.6E' ,gm));
disp(sprintf('gm5 = %.6E' ,gm5));
[z,p,k]=tf2zp(num,den);
if max(real(p))>=0,
disp('*** Warning *** equaliser is unstable');
end;
************* sinc1.m optimisation routine *************
function [f,g] = aofunc5(x,mag,fvar);
a=x(1);
b=x(2);
c=x(3);
num=[a b c];
den=[1 b c];
h = freqs(num,den,fvar);
magni = abs(h);
dff = (magni - mag);
f = norm(dff,inf);
[z,p,k]=tf2zp(num,den);
g=real(p);
APPENDIX B. OPTIMISATION SOURCE CODE LISTINGS 203
B.2 Sinc(x)-Equaliser 2
************* sinc2.m main program *************
function [num,den] = ampopt6(Fcoralpha,Fs,C1real,printornot);
format long;
if exist('printornot')==0,
printornot ='xxxxx';
else,
printornot='print';
end;
if exist('C1real')==0 & exist('Fc')==0,
C1real=1;
Fc=1;
alpha=Fcoralpha;
else,
Fc=Fcoralpha;
alpha=Fs/Fc;
end;
disp(' 2nd-order sinc(x)-equaliser design program:- F.Dudek 1996 ');
disp(' for equaliser 2, based on six OTA`s ');
fvar=linspace(0,1,1024); %frequency vector
mag=1./sinc(fvar/(alpha)); %magnitude vector to be approximated
x0 = [2.4 2 3.2]; %initial guess set up as [Ks^2 + Wo/Q + Wo^2 ]
options = [];
vlb=zeros(size(x0)); %lower bound = 0 for K and Wo\^2;
vub=5*ones(size(x0)); %upper bound
options(1) = 1; %show optimisation result as they occur
options(14)=10\^10; %max number of iterations
[x,options]=constr('aofunc6', x0, options,vlb,vub,[],mag,fvar); %optimisation
a=x(1);
b=x(2);
c=x(3);
num=[1 a c];
den=[1 b c];
h = freqs(num,den,fvar);
magni = abs(h);
plot(fvar,magni,fvar,mag,'-.');
APPENDIX B. OPTIMISATION SOURCE CODE LISTINGS 204
pause;
if printornot == 'print',
print;
end;
close;
Wo=sqrt(c);
Qz=sqrt(c)/a;
Qp=sqrt(c)/b;
C1=1;
gm5=a*C1;
gm=b*C1;
C2=(b^2/c)*C1;
disp('Equaliser2, based on six OTAs');
disp('================================');
disp(sprintf('Error value =%.6E' ,options(8)));
disp(sprintf('Maximum error = %.6E', norm(magni - mag,inf)));
disp(' ');
disp(sprintf('alpha = %.6E' ,alpha));
disp(sprintf('C1 = %.6E' ,C1));
disp(sprintf('C2 = %.6E' ,C2));
disp(sprintf('gm = %.6E' ,gm));
disp(sprintf('gm5 = %.6E' ,gm5));
disp(sprintf('Error value =%.6E' ,options(8)));
************* sinc2.m optimisation routine *************
function [f,g] = aofunc6(x,mag,fvar);
a=x(1);
b=x(2);
c=x(3);
num=[1 a c];
den=[1 b c];
h = freqs(num,den,fvar);
APPENDIX B. OPTIMISATION SOURCE CODE LISTINGS 205
magni = abs(h);
dff = (magni - mag);
f = norm(dff,inf);
[z,p,k]=tf2zp(num,den);
g=real(p);
APPENDIX B. OPTIMISATION SOURCE CODE LISTINGS 206
B.3 6th-order Ladder-Based Group-Delay Equaliser
************* group6.m main program *************
function [x] = optimla6(L1,L2,L3,C1,C2,C3,f0,filt52);
format long e;
load E:\Phd\Matlab\Delay\filt52.txt; %filter group-delay data
save f0.txt f0 /ascii; %upper frequency bound
Freq=filt52(:,1);
Delay=filt52(:,2);
fn=Freq./(2*pi*f0);
dfn=Delay.*(2*pi*f0);
dfnmax=max(dfn);
dfnmin=min(dfn);
ripplefilter=dfnmax-dfnmin;
options(1)=1;
options(14)=5000;
w=2*pi*fn;
x=[L1,L2,L3,C1,C2,C3];
[x,options]=constr('ladder6',x,options);
L1=x(1);
L2=x(2);
L3=x(3);
C1=x(4);
C2=x(5);
C3=x(6);
f1=(C3*L3+C2*(L2+L3)+C1*(L1+L2+L3));
f2=C3*L2*L3+C3*L1*L3+C2*L1*(L2+L3);
f3=C2*C3*L2*L3+C1*(C3*L2*L3+C3*L1*L3+C2*L1*(L2+L3));
f4=-w.^6*L1*L2*L3*C1*C2*C3+w.^4*(C2*C3*L2*L3+C1*
(C3*L2*L3+C3*L1*L3+C2*L1*(L2+L3)))
-w.^2*((C3*L3+C2*(L2+L3)+C1*(L1+L2+L3)))+1;
N=6.*w.^10.*C1.*(L1.*L2.*L3.*C2.*C3).^2-w.^8.*L1.
APPENDIX B. OPTIMISATION SOURCE CODE LISTINGS 207
*L2.*L3.*C2.*C3.*(4.*f3+6.*f2.*C1)+w.^6.*(2.*f1.*L1.
*L2.*L3.*C2.*C3+6.*(L1+L2+L3).*L1.*L2.*L3.*C1.*C2.*C3+4.*f2.*f3)
+w.^4.*(5.*f4.*L1.*L2.*L3.*C2.*C3-2.*f1.*f2-4.*f3.*(L1+L2+L3))
+w.^2.*(-3.*f2.*f4+2.*f1.*(L1+L2+L3))+f4.*(L1+L2+L3);
D=f4.^2+(w.^5.*L1.*L2.*L3.*C2.*C3-w.^3.*f2+w.*(L1+L2+L3)).^2;
t1=2*N./D;
DTotal=t1+dfn;
ripple=max(DTotal)-min(DTotal);
ripple_equ=max(t1)-min(t1);
disp('ripplefilter=');disp(ripplefilter);
disp('ripple_total=');disp(ripple);
disp('ripple_equ=');disp(ripple_equ);
disp('x');disp(x);
%disp('xn=');
L1=x(1)/(2*pi*f0);
L2=x(2)/(2*pi*f0);
L3=x(3)/(2*pi*f0);
C1=x(4)/(2*pi*f0);
C2=x(5)/(2*pi*f0);
C3=x(6)/(2*pi*f0);
%disp(sprintf('xden=\%.3E/n',x));
plot(fn,dfn,'w',fn,t1,'c',fn,DTotal,'r');
grid;
xlabel('Normalised frequency');
ylabel('Normalised delay');
title('Equalisation of a filter');
APPENDIX B. OPTIMISATION SOURCE CODE LISTINGS 208
************* group6.m optimisation routine *************
function [ripple,g]=ladder6(x,f0,filt52);
load E:\Phd\Matlab\Delay\filt52.txt; %filter group-delay data
load E:\Phd\Matlab\Delay\f0.txt; %upper frequency bound
Freq=filt52(:,1);
Delay=filt52(:,2);
f0=f0(1,1);
dfn=Delay.*(2*pi*f0);
dfnmax=max(dfn);
dfnmin=min(dfn);
ripplefilter=dfnmax-dfnmin;
fn=Freq./(2*pi*f0);
w=2*pi*fn;
L1=x(1);
L2=x(2);
L3=x(3);
C1=x(4);
C2=x(5);
C3=x(6);
f1=(C3*L3+C2*(L2+L3)+C1*(L1+L2+L3));
f2=C3*L2*L3+C3*L1*L3+C2*L1*(L2+L3);
f3=C2*C3*L2*L3+C1*(C3*L2*L3+C3*L1*L3+C2*L1*(L2+L3));
f4=-w.^6*L1*L2*L3*C1*C2*C3+w.^4*(C2*C3*L2*L3+C1*
(C3*L2*L3+C3*L1*L3+C2*L1*(L2+L3)))
-w.^2*((C3*L3+C2*(L2+L3)+C1*(L1+L2+L3)))+1;
N=6.*w.^10.*C1.*(L1.*L2.*L3.*C2.*C3).^2-w.^8.*L1.*L2.
*L3.*C2.*C3.*(4.*f3+6.*f2.*C1)+w.^6.*(2.*f1.*L1.*L2.
*L3.*C2.*C3+6.*(L1+L2+L3).*L1.*L2.*L3.*C1.*C2.*C3+4.*f2.*f3)
+w.^4.*(5.*f4.*L1.*L2.*L3.*C2.*C3-2.*f1.*f2-4.*f3.*
(L1+L2+L3))+w.^2.*(-3.*f2.*f4+2.*f1.*(L1+L2+L3))+f4.*(L1+L2+L3);
D=f4.^2+(w.^5.*L1.*L2.*L3.*C2.*C3-w.^3.*f2+w.*(L1+L2+L3)).^2;
t1=2*N./D;
DTotal=t1+dfn;
ripple=max(DTotal)-min(DTotal);