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Introduction to VHDL
VHDL
Page 1 - 1
XILINX XILINX VHDL ClassVHDL Class
Presented by
Training & Design Center
Introduction to VHDL
VHDL
Page 1 -
XILINX VHDL Class AgendaXILINX VHDL Class Agenda
1. Introduction to VHDL1. Introduction to VHDL
2. Design with VHDL 1 (Combinatorial Logic)2. Design with VHDL 1 (Combinatorial Logic)
3. Design with VHDL 2 (Sequential Logic)3. Design with VHDL 2 (Sequential Logic)
4. Design with VHDL 3 (Hierarchical Design)4. Design with VHDL 3 (Hierarchical Design)
5. Implementation5. Implementation
2
Introduction to VHDL
VHDL
Page 1 -
Introduction to VHDLIntroduction to VHDL
VVery High Speed Integrated Circuitery High Speed Integrated Circuit
HHardwareardware
DDescriptionescription
LLanguageanguage
3
Introduction to VHDL
VHDL
Page 1 -
• Digital Logic Design 환경의 변화
– ASIC Technology 의 발전• 대용량 , 고속 System 의 IC 구현가능
– Computing System 의 발전• 고성능 설계 자동화 Tool 의 보급
– 단위 기간 당 설계량의 증가
– 새로운 설계 방법이 요구됨
Design 환경의 변화
4
Introduction to VHDL
VHDL
Page 1 -
• Schematic Design Method
• Language Based Design– VHDL– Verilog
Design Method
5
Introduction to VHDL
VHDL
Page 1 -
• Schematic Design Method ( 장점 )
– 설계 방법 습득이 쉬움 .• AND, OR, NOT, Latch, Flip-Flop 이면 Cover
– Best Performance for Best Engineer– Tool 비용이 저렴
Design Method 1 (Schematic)
6
Introduction to VHDL
VHDL
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• Schematic Design Method ( 단점 )– Flexibility 가 떨어짐 .
• Target Technology 를 Fix 해야 함 .
• Design 에 따라 Logic Size 가 결정됨 .
• Design 에 따라 System Performance 가 결정됨
– Tool, Technology 에 대한 호환성 부족– 수정이 어려움 (Time Consuming, Risc)
• 대용량 설계에 제약
– Verify Stage (Gate Level 부터 가능 )– Documentation 이 어려움 .
Design Method 1 (Schematic)
7
Introduction to VHDL
VHDL
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• VHDL Design Method ( 장점 )– 개발 기간 단축 효과– Flexibility 가 높음
• Target Technology 에 Independent.
• Logic Size vs System Performance 절충 가능 .
– Tool, Technology 에 대한 탁월한 호환성– 수정이 용이 (Text Edit & Quick Simulation)
• 대용량 설계에 적합
– Verify Stage (Behavioral,RTL,Gate Level)– Design File(Text) 에 Documentation 포함 .
Design Method 1 (VHDL)
8
Introduction to VHDL
VHDL
Page 1 -
• VHDL Design Method ( 단점 )
– Schematic Designer 에게 익숙치 않은 방법• 초기 접근 ( 습득 ) 에 어려움 .
– Better Performance (?) but ...• Best Schematic Design 보다는 경우에 따라 열세• 그러나 개발 기간은 ...
Design Method 1 (VHDL)
9
Introduction to VHDL
VHDL
Page 1 -
• VHDL Code for Multiplier
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity mult isport (
a,b : in std_logic_vector(3 downto 0);y : out std_logic_vector(7 downto 0));
end mult;
architecture a_mult of mult isbegin
y <= a * b;
end a_mult;
Sample VHDL Code
a
by
Library
Entity
Architecture
10
Introduction to VHDL
VHDL
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• VHDL Design 의 목적
– H/W Implementation
– H/W Modeling for Simulation first
– More Effective with Synthesis and Simulation
VHDL Design 의 목적
11
Introduction to VHDL
VHDL
Page 1 -
• Simulation– 설계한 Code 의 동작을 검증– Behavioral, RTL, Gate Level 등에서 검증
• Synthesis– 설계한 Code 를 Gate Level H/W 로 변환 .– Translation and Optimization – Mapping with Target Technology
Simulation 과 Synthesis
12
Introduction to VHDL
VHDL
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VHDL Standard
IEEE 1076(modeling)
IEEE 1076(synthesis)
Not all VHDL constructs are synthesizable.For example, “wait for 10 ns” is a common
modeling construct, but does not generate any corresponding gate-level component.
13
Introduction to VHDL
VHDL
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Subsets
IEEE 1076(modeling)IEEE 1076
(synthesis)
Tool & Vendor Specific
N P Z“None Portability Zone”
14
Introduction to VHDL
VHDL
Page 1 -
• VHDL Design 시 고려해야 할 사항
– 어떤 H/W 로 구현 될 것인가• Logic Size, Architecture, Glitch ..
• Propagation Delay and Timing Margin
– Flexible, but need ConsiderationFlexible, but need Consideration
VHDL Design 시 고려 사항
15
Introduction to VHDL
VHDL
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VHDL Study 방법
학구적 접근
- VHDL Syntax 를 충분히 습득한 후 실무 에 적용한다 .
- 장 점 : VHDL 의 Full Function 활용 가능 .
- 단 점 : 습득에 많은 어려움 . ( 시간 ,노력 )
실무적 접근
- 필요한 최소한의 Syntax 를 익힌 후 설계 시작 , 필요한 내용을 추가 습득해 나간다 .
- 장 점 : 단기간에 설계 업무 수행 가능 .
- 단 점 : 활용 범위가 부분적 기능에만 국한되기 쉬움 .
16
Introduction to VHDL
VHDL
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• Schematic Design 의 장 , 단점은 ?
• Language Based Design 의 장 , 단점은 ?
• VHDL Design 의 목적은 ?
• Simulation, Synthesis 란 무엇인가 ?
Quiz
17
Introduction to VHDL
VHDL
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Design with VHDL(1)Design with VHDL(1)
(Combinatorial Logic)(Combinatorial Logic)
1
Introduction to VHDL
VHDL
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• Basic Rule for VHDL Coding
– 모든 문장은 “ ;” 으로 종료 (Line 이 아님 )
– 대 , 소문자 구별이 없다 .
– Space 는 하나 이상이면 동일 ( 필요 시 Line Change, Tap 사용 가능 )
– Reserved Word 는 User Define Name 으로 사용 금지
– Syntax 에 규정된 Pattern 은 정확히 지켜야 한다 .
– Comment 는 “ --” 로 시작• 해당 Line 에만 영향을 미침 .
• Comment 가 복수 Line 일 경우에는 매 Line 에 “ --” 를 Type 해야 함 .
Basic Rule for VHDL Coding
2
Introduction to VHDL
VHDL
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Data-types are very important in VHDL. A given data-type define all possible values within its range. Only values within that range may be applied. Each VHDL object (signal, variable, constant) or port must have its type defined when declared.
VHDL is considered to be a strongly “typed” language, connected signals must be of the same type!
The wide range of data-types available provides both flexibility in hardware modeling, and built-in error checking to ensure signal compatibility in large and complex models.
Data-Types
3
Introduction to VHDL
VHDL
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Signals & Ports
signal A : integer ; signal B : bit ;signal C : integer ;signal D : std_logic ; A <= C;
A <= C + 1;A <= B;D <= C;B <= D;
Data-types must match on signal assignments !
4
Introduction to VHDL
VHDL
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Data-types
– In VHDL, this class includes:
Bit Boolean Integer Std_logic (Std_ulogic)EnumeratedRealPhysicalCharacter
5
Synthesizable
Simulatable
Introduction to VHDL
VHDL
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Bit & Boolean
type bit is ( ‘0’, ‘1’ ) ;
type boolean is ( false, true ) ;
Type bit is helpful and concise for modeling hardware, but does not provide for high-impedance, unknown, don’t care, Etc.
Type boolean is useful for modeling at the more abstract level. All relational operations return a value of type boolean.
architecture BEHAVE of MUX issignal A,B,Sel, Z : bit ; begin if Sel = ‘1’ then Z <= A ; else Z <= B ; end if . . .
if Sel =‘1’, if F >= G..
both yield boolean result
6
Introduction to VHDL
VHDL
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Integer & Real
type integer is range . . .
Type integer allows for flexible, readily intuitive quantities and values in our models. It is essential to specify the range of any object of type integer, otherwise the language requires that synthesis tools generate a minimum 32 bit implementation.
type real is range . . .
Type real allows us to utilize floating point values and operations in our models. Since the range of real numbers is unlimited, we declare our type with the intended range of real values. (Real Values are not synthesizable !)
signal A : integer range 0 to 7;signal B : integer range 15 downto 0 ;
type CAPACITY is range -25.0 to 25.0 ;signal Sig_1 : CAPACITY := 3.0 ;
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Introduction to VHDL
VHDL
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Std_logic
type std_logic is ( ‘U’ ; -- Uninitialized ‘X’ ; -- Forcing Unknown
‘0’ ; -- Forcing Zero‘1’ ; -- Forcing One‘Z’ ; -- High Impedance
‘W’ ; -- Weak Unknown‘L’ ; -- Weak Zero‘H’ ; -- Weak One‘ - ‘; -- Don’t Care )
Type Std_logic was developed from the MVL (Multi-Value Logic) system and provides for more detailed hardware modeling. It supports different signal strengths, “don't-care” conditions and bussed structures with tri-state drivers. (Defined in package std_logic_1164)
Note: type bit is limited to (‘0’, ‘1’).
8
Introduction to VHDL
VHDL
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EnumeratedEnumerated types offer perhaps the most flexibility in abstract hardware models. User defined enumerated types allow values that are immediately recognizable and intuitively relevant to the operation of the model.
This capability makes our code more readable when describing state machines and complex systems. FPGA Express can encode enumerated types in either binary or “OHE”.
type My_State is ( RST, LOAD, FETCH, WAIT, SHIFT ) ;. . .signal STATE, NEXT_STATE : My_State ;. . .
Case STATE iswhen LOAD => . . .if COND_A and COND_B thenNEXT_STATE <= FETCH ;else NEXT_STATE <= WAIT ;. . .
9
Introduction to VHDL
VHDL
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• VHDL Code for Simple Gate (1)
library ieee;use ieee.std_logic_1164.all;
entity and2 isport(
a : in std_logic;b : in std_logic;y : out std_logic);
end and2;
architecture a_and of and2 isbegin
y <= a and b;
end a_and;
Simple Gate Logic (1)
a
byGate
10
Introduction to VHDL
VHDL
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Logical Operators
andornandnorxornotxnor (VHDL-93)
Z <= A and B ;
ZB
A
11
Introduction to VHDL
VHDL
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Logical Operations on Arrays
signal A_vec, B_vec, C_vec : std_logic_vector ( 7 downto 0 ) ;
B_vec (7)A_vec (7)
C_vec (7)
B_vec (6)A_vec (6)
C_vec (6)
B_vec (5)A_vec (5)
C_vec (5)
B_vec (0)A_vec (0)
C_vec (0)
.
.
.
C_vec <= A_vec and B_vec ;
12
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VHDL
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• VHDL Code for Simple Gate (2) library ieee;use ieee.std_logic_1164.all;
entity gate isport(
a,b : in std_logic;c,d : in std_logic;y : out std_logic);
end gate;
architecture a_g of gate isbegin
y <= a and b or c and d;
end a_g;
-- 위의 Code 에 대한 Logic Diagram 은 ?
Simple Gate Logic (2)
a
b
c
d
y
Gate
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VHDL
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• VHDL Code for Simple Gate (3) library ieee;use ieee.std_logic_1164.all;
entity gate isport(
a,b,c,d : in std_logic;y : out std_logic);
end gate;
architecture a_g of gate isbegin
y <= (a and b) or (c and not d);
end a_g;
-- Not 을 제외한 Logic Operator 의 -- 우선 순위는 같다
Simple Gate Logic (3)
a
b
c
d
y
Gate
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VHDL
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• Signal 선언 및 활용 library ieee;use ieee.std_logic_1164.all;
entity gate isport(
a,b,c,d : in std_logic;y : out std_logic);
end gate;
architecture a_g of gate issignal e,f : std_logic;begin
e <= a and b;f <= c and d;y <= e or f;
end a_g;
-- Signal 은 Entity 내부의 Node.
Simple Gate Logic (4)
a
b
c
d
y
Gate
15
Introduction to VHDL
VHDL
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• Decoder with Gate Combination 아래의 Truth Table 과 같은 출력을 갖는Decoder 에 대한 Code 를 작성하라 .
A B C D Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0
Decoder Logic (1)
a
b
c
d
y
Decoder
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VHDL
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• Decoder (1) : (Gate Combination)library ieee;use ieee.std_logic_1164.all;
entity dec isport(
a,b,c,d : in std_logic;y : out std_logic);
end dec;
architecture a_dec of dec issignal v3,v4,v6,va : std_logic;begin
v3 <= (not a) and (not b) and c and d;v4 <= (not a) and b and (not c) and (not d);v6 <= (not a) and b and c and (not d); va <= a and (not b) and c and (not d);y <= v3 or v4 or v6 or va;
end a_dec;
Decoder Logic (2)
a
b
c
d
y
Decod
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Introduction to VHDL
VHDL
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• Decoder (1) : (WHEN ELSE 구문 (1), Concatination)library ieee;use ieee.std_logic_1164.all;
entity dec isport(
a,b,c,d : in std_logic;y : out std_logic);
end dec;
architecture a_dec of dec issignal din : std_logic_vector(3 downto 0);signal v3,v4,v6,va : std_logic;begin
din <= a & b & c & d;v3 <= ‘1’ when din = “0011” else ‘0’;v4 <= ‘1’ when din = “0100” else ‘0’;v6 <= ‘1’ when din = “0110” else ‘0’;va <= ‘1’ when din = “1010” else ‘0’;y <= v3 or v4 or v6 or va;
end a_dec;
Decoder Logic (3)
a
b
c
d
y
Decod
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VHDL
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ArraysArrays are groups of elements, all of the same type !
type WORD is array (3 downto 0) of std_logic ;
index position0123
B_bus
What are the possible values for each element of the array ?
signal B_bus : WORD ;
type DATA is array (3 downto 0) of integer range 0 to 9 ;
Remember to specify the integer range, to limit width of synthesized module !
signal B_bus : DATA ;
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VHDL
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Array Assignments When assigning arrays, the following rules apply.
1. The arrays must be the same type.2. The arrays must be the same length.3. The assignment is positional, from left to right!
signal My_BusA, My_BusB: bit_vector (3 downto 0 ) ;signal My_BusC, My_BusD: bit_vector ( 0 to 3 ) ;
3 012
3 012
3 012
0 321
My_BusA My_BusA
My_BusCMy_BusB
My_BusB <= My_BusA ; . . . .My_BusC <= My_BusA ;
Inadvertent bit-swap ?
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VHDL
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Composite Data-Types
Composite Data_types are groups of elements in the form of an array.
( Bit_vector and Std_logic_vector are pre-defined composite types.)
signal A_word : bit_vector (3 downto 0) := “0011” ;
This represents four “bit” elements grouped together into an array, there is no pre-defined LSB or MSB interpretation, therefore it is not read as 3, ‘3’, or “3”.
21
Introduction to VHDL
VHDL
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Concatenation
The Concatenation operator (&) allows flexible grouping of scalars and arrays into larger arrays.
signal A_vec, B_vec : std_logic_vector ( 7 downto 0 ) ; signal Z_vec : std_logic_vector ( 15 downto 0 ) ;signal A_bit, B_bit, C_bit, D_bit : std_logic ;signal X_vec : std_logic_vector ( 2 downto 0 ) ;signal Y_vec : std_logic_vector ( 8 downto 0 ) ;
Z_vec <= A_vec & B_vec ;
X_vec <= A_bit & B_bit & C_bit ;
Y_vec <= B_vec & D_bit ;
This type of assignment uses positional association.
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Introduction to VHDL
VHDL
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Aggregates Aggregates are a convenient means of grouping both scalar and
composite data-types for assignment.
signal H_BYTE, L_BYTE: std_logic_vector (7 downto 0); signal DATA : std_logic_vector (15 downto 0); signal A, B, C, D : std_logic;signal WORD : std_logic_vector (3 downto 0);
( H_BYTE, L_BYTE ) <= DATA ;
WORD <= ( 2 => ‘1’, 3 => D, Others => ‘0’ ) ;
DATA <= ( Others => ‘1’) ;
WORD <= ( A, B, C, D ) ;
The total number of elements on both sides of the assignment must match, “Others” can be used as a default assignment, regardless of the array size.
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• Decoder (1) : (WHEN ELSE 구문 (2))library ieee;use ieee.std_logic_1164.all;entity dec isport(
a,b,c,d : in std_logic;y : out std_logic);
end dec;
architecture a_dec of dec issignal din : std_logic_vector(3 downto 0);-- signal v3,v4,v6,va : std_logic;begin
din <= a & b & c & d; y <= ‘1’ when din = “0011” else
‘1’ when din = “0100” else‘1’ when din = “0110” else‘1’ when din = “1010” else‘0’;
end a_dec;
Decoder Logic (4)
a
b
c
d
y
Decod
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Introduction to VHDL
VHDL
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• Decoder (1) : (WHEN ELSE 구문 (3))library ieee;use ieee.std_logic_1164.all;entity dec isport(
a,b,c,d : in std_logic;y : out std_logic);
end dec;
architecture a_dec of dec issignal din : std_logic_vector(3 downto 0);begin
din <= a & b & c & d;y <= ‘1’ when
(din = “0011”) or (din = “0100”) or(din = “0110”) or (din = “1010”)
else ‘0’;
end a_dec;
Decoder Logic (5)
a
b
c
d
y
Decod
25
Introduction to VHDL
VHDL
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• 2 to 1 Multiplexer – 2 to 1 mux 에 대한 Gate 조합형 Code 를 작성 하라 .
– 2 to 1 mux 에 대한 Behavioral Code 를 작성하라 .
Multiplexer Logic (1)
I0 I1sel
y
Mux
26
Introduction to VHDL
VHDL
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• 2 to 1 Mux (Gate Combination)library ieee;use ieee.std_logic_1164.all;
entity mux2 isport (
i0,i1 : in std_logic;sel : in std_logic;y : out std_logic);
end mux2;
architecture gate_mux2 of mux2 isbegin
y <= (i0 and (not sel)) or (i1 and sel);
end gate_mux2;
Multiplexer Logic (2)
I0 I1sel
y
Mux
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Introduction to VHDL
VHDL
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• 2 to 1 Mux (WHEN ELSE 구문 )library ieee;use ieee.std_logic_1164.all;
entity mux2 isport (
i0,i1 : in std_logic;sel : in std_logic;y : out std_logic);
end mux2;
architecture behave_mux2 of mux2 isbegin
y <= i0 when sel = ‘0’ else i1;
end behave_mux2;
Multiplexer Logic (3)
I0 I1sel
y
Mux
28
Introduction to VHDL
VHDL
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• 4 to 1 Mux (WHEN ELSE 구문 )library ieee;use ieee.std_logic_1164.all;
entity mux4 isport (
i0,i1,i2,i3 : in std_logic;sel : in std_logic_vector(1 downto 0);y : out std_logic);
end mux4;
architecture behave_mux4 of mux4 isbegin
y <= i0 when sel = “00” else i1 when sel = “01” elsei2 when sel = “10” elsei3 when sel = “11” else‘0’;
end behave_mux4;
Multiplexer Logic (4)
I0 I1sel
y
Mux
I2 I3
2
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Introduction to VHDL
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• 4 to 1 Mux (WITH SELECT WHEN 구문 )library ieee;use ieee.std_logic_1164.all;
entity mux4 isport (
i0,i1,i2,i3 : in std_logic;sel : in std_logic_vector(1 downto 0);y : out std_logic);
end mux4;
architecture behave_mux4 of mux4 isbegin
with sel selecty <= i0 when “00”,
i1 when “01”,i2 when “10”,i3 when “11”,‘0’ when others;
end behave_mux4;
Multiplexer Logic (5)
I0 I1sel
y
Mux
I2 I3
2
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Introduction to VHDL
VHDL
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Multiplxer Logic(6)
Y
Sel
I3
Z
- 다음의 두 가지 4 to 1 Mux 사이에는 어떤 차이가 있는가 .
<when else> 구문 <with select when> 구문
I0
I1
I2
I3
I2
I1
I0
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Introduction to VHDL
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• Compare Logic
– 아래의 Symbol 과 진리 표에 해당하는 Code 를 작성 하라 .
Output = EQ, AGB, ALB
Input = A[3:0], B[3:0]
EQ AGB ALB
1 0 0 A=B
0 1 0 A>B
0 0 1 A<B
Compare Logic (1)
A
BAGBALB
EQ
Comp
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Relational Operators
= Equality/= Inequality< Less than<= Less than or equal > Greater than>= Greater than or equal
Relational operators are pre-defined for most data-types.
All Relational operations return type Boolean
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• Compare Two Variable Inputlibrary ieee;use ieee.std_logic_1164.all;
entity comp isport (
a,b : in std_logic_vector(3 downto 0); eq,agb,alb : out std_logic );
end comp;
architecture a_comp of comp isbegin
eq <= ‘1’ when a = b else ‘0’;agb <= ‘1’ when a > b else ‘0’;alb <= ‘1’ when a < b else ‘0’;
end a_comp;
Compare Logic (2)
A
BAGBALB
EQ
Comp
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Introduction to VHDL
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• Compare with Constant
– Single Input을 Constant “0100”과 비교하는 Comparator를 설계하라 .
– 위의 두 방법의 차이점은 무엇인가 ?
Compare Logic (3)
A
“0100”AGBALB
EQ
Comp
AAGBALB
EQComp with“0100”
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Introduction to VHDL
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Arithmetic
+ Addition
- Subtraction
* Multiplication
/ Division
abs Absolute Value
** Exponentiation
Arithmetic operators are not pre-defined for std_logic type !!
signal A, B, Z : std_logic_vector(3 dowtno 0) ;
Z <= ( A + B ) ;
+ Z
A
B Infers a 4 bit adder..
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Arithmetic of ArraysTo accomplish arithmetic operations on arrays --in effect treating them as binary or numerical representations, requires functions (sub-programs) supplied by the IEEE or the tool vendor.
The package std_logic_unsigned is an IEEE standard library and will provide maximum code portability.
Such functions will normally be included in so-called “arithmetic packages”. The package may require compilation into the work library. FPGA Express has pre-compiled these packages into its own internal library.
package std_logic_unsigned is function “+” (A,B: bit_vector) return bit_vector ; function “+” (A: bit_vector, B: integer ) return bit_vector ; function “-” (A,B: bit_vector) return bit_vector ;. . . .
library IEEE ;use IEEE.std_logic_1164.all ;use IEEE.std_logic_unsigned.all ;
The operator “+” is overloaded in that it refers to a different function call, based on the left and right operand, and the return parameter in the function declaration.
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• Arithmetic Operator (1) library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity adder isport (
a,b : in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0) );
end adder;
architecture a_adder of adder isbegin
y <= a + b;
end a_adder;
Arithmetic Operator (1)
A
BY
Adder
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• Arithmetic Operator (2) -- 아래의 Code 에 대한 Architecture 를 그려 보시오 .
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity adder isport (
a,b,c,d : in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0) );
end adder;
architecture a_adder of adder isbegin
y <= a + b + c + d;
end a_adder;
Arithmetic Operator (2)
B
D
Y
AdderA
C
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• Arithmetic Operator (3) -- 아래의 Code 에 대한 Architecture 를 그려 보시오 .
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity adder isport (
a,b,c,d : in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0) );
end adder;
architecture a_adder of adder isbegin
y <= (a + b) + (c + d);
end a_adder;
Arithmetic Operator (3)
B
D
Y
AdderA
C
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Grouping Operators
Grouping operators in a given expression can help to guide some aspects of logic synthesis while enhancing the readability of the code.
Z <= A + B + C + D ; Z <= ( A + B ) + ( C + D) ;
B
A
CD
Z
3 logic levels
D
Z
A
B
C
2 logic levels
This is especially important when the target technology is LUT (Look-Up Table) based. Each added level of logic incurs additional block and routing delays.
+++
++
+
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• Arithmetic Operator (4) -- Overflow 에 대한 고려 .
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity adder isport (
a,b : in std_logic_vector(3 downto 0); y : out std_logic_vector(4 downto 0) );
end adder;
architecture a_adder of adder isbegin
y <= (‘0’ & a ) + (‘0’ & b );
end a_adder;
Arithmetic Operator (4)
A
BY
Adder
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• Logic Operator• Arithmetic Operator• Relational Operator• Concatenation • Bus < bit direction >• when < > else 구문• with < > select < > when 구문
Combinational Logic Summary
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• RTL Synthesis : Single Cycle 만 설정 가능 .
• Hard Ware Architecture Design 은 Manual 로– (A + B + C + D ) vs (A + B) + (C + D)
• Synthesis Tool 의 한계
• 좋은 Synthesis Tool 이란 ?
Synthesis 에 대한 고려
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Design with VHDL(2)Design with VHDL(2)
(Sequential Logic )(Sequential Logic )
1
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DFF Architecture
Clk
Rst
D Q- Sequential Logic 을 위한 Process 구문 .- if then else 구문 .- clock 처리 구문 .
library ieee;use ieee.std_logic_1164.all; entity DFF is port (
D,Clk : in std_logic; Rst : in std_logic; Q : out std_logic
);end entity DFF ; architecture Behave of DFF isbegin process (Clk, Rst)begin if Rst = ‘1’ then Q <= ‘0’ ; elsif ( Clk’event and Clk = ‘1’ ) then Q <= D ; end if ;end process; end Behave;
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Process 구문
process (sensitivity list here)begin
end process; .
* Sequential Control 을 위한 구문 .
* Architecture 내부에 존재 .
* Sensitivity List 의 Signal 에 변화있을 때 구동 .
* Process 구문 내의 Instruction 들은 순차적으로 수행 . (Process 밖의 구문은 Concurrent 로 수행 .)
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If then else 구문
if (condition 1) then
elsif (condition 2) then
elsif (condition 3) then
else
end if;
.
* Alternative Selection 을 위한 구문 .
* Process 문 내부에 존재 .
* 존재 가능한 모든 Selection 조건을 Cover 해야 함 .
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Clock Define 구문
. (signal’event and signal = ‘1’) -- rising edge
(signal’event and signal = ‘0’) -- falling edge
* Clock 동기 회로 설계를 위한 구문 .
* Process 문 내부에서 if then else 구문과 함께 사용 .
* Rising, Falling Edge 선택 .
* 동일 Process 내에서는 단일 Clock, 단일 Edge 만
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Register 구문
library ieee;use ieee.std_logic_1164.all; entity reg8 isport (
d : in std_logic_vector(7 downto 0); rst : in std_logic;
clk : in std_logic; q : out std_logic_vector(7 downto 0)
);end reg8;architecture Behave of reg8 isbegin process (clk,rst)begin if rst = ‘1’ then q <= (others =>‘0’) ; elsif ( clk’event and clk = ‘1’ ) then q <= d ; end if ;end process; end Behave;
Clk
Rst
D Q8 8
- Basic Register 구문
Reg8
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Counter 구문 (1)
Clk
Rst
Q8
- Basic Counter 구문
Cnt8
Clk Rst
Q8 8
Reg8+ 1
Cnt8
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I/O Port Direction Types
IN : Input Only
OUT: Output Only
INOUT: In and Out
BUFFER: Out and Feedback to inside
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Counter 구문 (1)library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity cnt8 isport (
rst : in std_logic; clk : in std_logic;
q : out std_logic_vector(7 downto 0));
end cnt8 ;
architecture Behave of cnt8 issignal tq : std_logic_vector(7 downto 0);begin
process (clk,rst)begin if rst = ‘1’ then tq <= (others =>‘0’) ; elsif ( clk’event and clk = ‘1’ ) then tq <= tq + 1; end if ; q <= tq;end process; end Behave;
Clk
Rst
Q
8
Cnt8
9
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VHDL
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Counter 구문 (2)
Clk
Rst
Q8
- Counter with Enable Logic 의 설계
Cnt8EEN
Clk Rst
Q8 8
Reg8
+ 1
Cnt8E
EN
1
0
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Counter 구문 (3)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity cnt8e isport (
rst,en : in std_logic; clk : in std_logic;
q : out std_logic_vector(7 downto 0));
end cnt8e ;
architecture Behave of cnt8e issignal tq : std_logic_vector(7 downto 0);begin process (clk,rst)begin if rst = ‘1’ then tq <= (others =>‘0’) ; elsif ( clk’event and clk = ‘1’ ) then if en = ‘1’ then
tq <= tq + 1; end if ; end if ; q <= tq;end process; end Behave;
Clk
Rst
Q
8
Counter with Enable
Cnt8EEN
11
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VHDL
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Counter 구문 (4)- Counter with Enable and Synchronous Reset Logic 의 설계
* Enable 과 Synchronous Reset 간의 우선 순위는 ?
Clk Rst
Q8 8
Reg8+ 1
Cnt8ESR
EN
1
0
SR
1
0
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Counter 구문 (5)library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;entity cnt8sre isport (
rst,en : in std_logic; clk,sr : in std_logic;
q : out std_logic_vector(7 downto 0));
end cnt8sre ;
architecture Behave of cnt8sre issignal tq : std_logic_vector(7 downto 0);beginprocess (clk,rst)begin if rst = ‘1’ then tq <= (others =>‘0’) ; elsif ( clk’event and clk = ‘1’ ) then if sr = ‘1’ then
tq <= (others =>‘0’) ;elsif en = ‘1’ then
tq <= tq + 1; end if ; end if ; q <= tq;end process; end Behave;
Clk
Rst
Q8
Counter with Enable and Sync Reset
cnt8sreSR
EN
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If / Else Statements
The if / else statement allows operations to be performed based on certain conditions. It has three basic forms.
processbegin
if ( boolean expression ) thensequential statements;end if ;
processbegin
if ( boolean expression ) thensequential statements ;else sequential statements ; end if ;
processbegin
if ( boolean expression ) thensequential statements ;elsif ( boolean expression ) then sequential statements ; elsif ( boolean expression ) then sequential statements ; end if ;
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If/Elsif Example and Rules1. The first condition found to be true will be executed.2. Conditions can overlap.3. The first condition of an if / elsif will have priority.
process ( A, B, C, D, Sel )beginIf ( Sel = “00” ) then
Z <= A;elsif ( Sel = “01” ) then
Z <= B;elsif ( Sel = “10” ) then
Z <= C; else
Z <= D; end if; end process ;
Z
D
C
B
A
Sel
D
C
B
AZ
Z <= A when (Sel = “00”) elseB when (Sel = “01”) else C when (Sel = “10”) elseD ;
Compare with Same Function Code
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Case Statement
The CASE statement allows operations to be performed based on the value of a single expression, as indicated by the “selector expression”.
process (…) begin
case ( selector expression ) iswhen .. . =>
sequential statements ;when ... =>
sequential statements ; when ... =>
sequential statements ; end case ;
process (...)begin
case ( selector expression ) iswhen ... =>
sequential statements ; . . . when others =>
sequential statements ; end case ;
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Case Examples and Rules1. All possible conditions must be specified.2. No conditions can overlap.3. All range specifications must be of a discrete type.
Z
D
C
B
A
Sel
process (A, B, C, D, Sel )begincase Sel is when “00” => Z <= A ; when “01” => Z <= B ; when “10” => Z <= C ; when others => Z <= D ;end case ;
Case statements are preferable for LUT architectures given that most synthesis tools will produce a mux, or similarly minimal logic level structure. With sel select
Z <= A when “00”,B when “01”, C when “10”,D when others;
Compare with Same Function Code
17
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Loop Statements
Loop statements can be constructed for any repetitive operation. There are different forms, each having a different method of control. We shall examine the “for loop”.
The loop variable Index is not declared, and is not visible outside the loop. It is treated as a constant.
With each loop iteration, it successively assumes the discrete values indicated in the range.
process ( A, B_bus ) begin
for I in 0 to 7 loop C_bus (I) <= A and B_bus (I) ; end loop ;
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VHDL
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S to P Shift Register 구문
Clk
Rst
Q8
- For Loop 구문을 이용한 Serial in Parallel Out Shift Register 설계
StoPSIN
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S to P Shift Register 구문
Clk
Rst
Q8
- Serial in Parallel Out Shift Register
StoPSIN
library ieee;use ieee.std_logic_1164.all;entity s2p8 isport (
rst,sin : in std_logic; clk : in std_logic;
q : out std_logic_vector(7 downto 0) );end s2p8;
architecture Behave of s2p8 issignal tq : std_logic_vector(7 downto 0)beginprocess (clk,rst)begin if rst = ‘1’ then tq <= (others =>‘0’) ; elsif (clk’event and clk = ‘1’) then
tq(0) <= sin; for I in 1 to 7 loop
tq(I) <= tq(I-1); end loop; end if;end process; q <= tq;
end Behave;
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Inside Vs. Outside Process
architecture ...process ( ) begin Z <= A; Z <= B; . . . end process ;end architecture ;
architecture . . . begin Z <= A; Z <= B; . . . end architecture ;
B
B
The last assignment takes effect.
Z
? Z
A
Both assignments are concurrent. A resolution function will be required on the output signal “Z”.
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Page 1 - 22
Using Signals
process ( B, C, D, F) beginA <= B and D ;A <= B and C ;B <= F or G;E <= B and C ;end process;
A
E
The current value of the signals are read
What are final inputs to the gates ?
B
Introduction to VHDL
VHDL
Page 1 - 23
Using Signals process ( clk) begin
if clk’event and clk = ‘1’ then A <= B and D ;A <= B and C ;B <= F or G;E <= B and C ;end if; end process;
The current value of the signals are read
A
E
Clk
Clk
C
C
Clk
BF
Any signal under the statement
“if clock’event and clock = ‘1’ then”
will infer the use of a register.
G
Introduction to VHDL
VHDL
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• 1. Process 문이 구동 되기 위한 조건은 ?
• 2. If 문과 Case 문의 차이는 ?
• 3. 하나의 Entity 에서 이용할 수 있는 Clock 수는 ?
• 4. Process 문 내부와 외부의 동작 차이는 ?
Quiz
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Design with VHDL (3)Design with VHDL (3)
Hierarchy DesignHierarchy Design
Design FlowDesign Flow
1
Introduction to VHDL
VHDL
Page 1 -
Hierarchical Design (1)
+ D Q8 8
CLK
RST
Adder with Register
ADD
A
B 8
8SUM
2
Introduction to VHDL
VHDL
Page 1 -
ADD 에 대한 Coding
Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity add isport (
a,b : in std_logic_vector(7 downto 0);y : out std_logic_vector(7 downto 0));
end add1;
architecture a_add of add isbegin
y <= a + b;end a_add;
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ADD with Reg. 에 대한 Codinglibrary ieee;use ieee.std_logic_1164.all;entity adr isport (
rst,clk : in std_logic;a,b : in std_logic_vector(7 downto 0);q : out std_logic_vector(7 downto 0));
end adr;architecture a_adr of adr is
component addport (
a,b : in std_logic_vector(7 downto 0);y : out std_logic_vector(7 downto 0));
end component;
signal sum : std_logic_vector(7 downto 0);begin
u0 : add port map (a => a,b => b,y => sum);
process (rst,clk)begin
if rst = ‘1’ then q <= (others => ‘0’);
elsif clk’event and clk = ‘1’ thenq <= sum;
end if;end process;end a_adr;
Component Declaration
u0 : add port map(a,b,sum);
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Registered Logic The “register rich” Xilinx FPGA architecture is excellent for synchronous design, which is the very essence of RTL (Register Transfer Level) level description.
There are 2 registers per CLB. Use pipelining as necessary to increase performance
RTL
Behavioral
Logic
CLB 1 CLB 2
5
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Global Buffers Xilinx global clock resources are absolutely essential to any registered logic. FEXP will automatically identify any signal that is sourced from an I/O and drives a clock pin within the device.
This is referred to as “global buffer insertion“.
BUFG
Automatic
Buffer Insertion
6
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Global Buffers Global buffer insertion is not automatic for internally sourced clocks, this can be controlled via the constraint tables.
Control
Unwanted Effect
BUFG
Instantiate BUFG Here
7
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VHDL
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Global Buffers Global buffer insertion is not automatic for internally sourced clocks, this can be controlled via the constraint tables.
FYI: A better solution than gating the clock? Use one of the signals as a CE, keeping your design fully synchronous.
Control
CE
BUFG
8
Introduction to VHDL
VHDL
Page 1 -
1.System Define
2. Algorithm Define
3. Architecture Define
4. VHDL Code Design
5. Function Simulation
6. Synthesis
7. Timing Simulation 1
8. Place & Route
9. Timing Simulation 2
10. Target Device 제조
11. Hard Ware Test
12. Mass Production
Design Flow
1. System Define- 설계할 System 의 기능과 입출력에 대한 조건을 정의한다 .
2. Algorithm Define- System 에서 정의된 기능을 구현 할 Algorithm 을 정의 한다 .
3. Architecture Design- 정의된 Algorithm 에 대한 H/W Architecture 를 설계 한다 .
- 각 입력과 출력에 대한 Timing Chart 를 작성 한다 .
4. Circuit Design (VHDL Coding) 5. Function Simulation- Stimulus 나 Test Bench 를 작성한다 . (Simulator 선정 )
- 정의된 Algorithm 과 Timing Chart 에 의한 검증 .
Design Flow (1)
9
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1.System Define
2. Algorithm Define
3. Architecture Define
4. VHDL Code Design
5. Function Simulation
6. Synthesis
7. Timing Simulation 1
8. Place & Route
9. Timing Simulation 2
10. Target Device 제조
11. Hard Ware Test
12. Mass Production
Design Flow
6. Synthesis- Target Technology Library, Constraint
7. Timing Simulation 1- Synthesis 결과로 Cell Delay 가 반영된 Simulation.
8. Place & Route- Target Device 에 맞추기 위한 (Timing, Size) Cell 배치 , 배선 .
9. Timing Simulation 2- Cell + Routing Delay 가 포함된 Simulation.
10. Target Device 제조- ASIC : Gate Array, Standard Cell, Full Custom (Test Vector,NRE)
- PLD : FPGA, PLD (Programming)
11. Hard Ware Test (On Board, Test Logic)
12. Mass Production
Design Flow (2)
10
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완성도
개발기간
90%
완성도 vs 개발기간
Early Detect Error => Cheap to fix
Debug & Enhancement
11
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좋은 Solution 을 얻으려면
1. 안정된 Design
- Timing Margin, Fan Out 등을 고려한 설계 .- Synchronous Design (Counter, Example)- Target Technology 에 맞는 설계 (FPGA Example)
2. Synthesis Tool 에서의 Control.(Tool Performance, Option)
3. Place and Routing 에서의 Control.
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Design with VHDL (4)Design with VHDL (4)
- State Machine Design- State Machine Design
- Devices for Implementation- Devices for Implementation
Introduction to VHDL
VHDL
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State Machine Design (1)
State Machine 이란 .
- Sequential Logic 설계의 편의를 위해 도입된 설계 방법 .
- 주로 VHDL 의 case 구문을 사용 한다 .
- 일련의 동작들을 상태 (State) 조건에 따라 분류한다 .
- 각각의 상태에 대한 제어 Logic 을 설계 한다 .
Introduction to VHDL
VHDL
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State Machine Design (2)
State Machine Design Example
- 시 , 분 , 초 Control 을 갖는 시계 .
- 동작 조건. 초기화 , 시 조정 , 분 조정 , 정상 동작의 4 개 Mode 를 갖는다 .
- 입력 조건
. Clock Input : 1 Hz Pulse.
. Mode Key, Set Key.
- 출력 조건 . 시 , 분 , 초 Counter 출력 .
Introduction to VHDL
VHDL
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State Machine Design (3)
State 동작 조건
- 초기화 State (Reset 시 ). 시 Counter 를 12 로 Set. 분 , 초 Counter 는 Clear
- 시 조정 State. Set 단자 입력의 Rising Edge 에서 시 Counter Increment.
- 분 조정 State. Set 단자 입력의 Rising Edge 에서 분 Counter Increment.
. 초 Counter 는 Clear.
- 정상 동작 State . 정상 시계 동작 .
- State Change 는 Mode Key 의 입력에 의해 .
Introduction to VHDL
VHDL
Page 1 -
State Machine Design (4)
1. VHDL Code 해설
2. Simulation 결과 해설
Introduction to VHDL
VHDL
Page 1 -
Potential Solutions• Discrete logic
– not practical approach any longer
– few available 3.3V/2.5V devices available
• Chip sets– few available
– expensive
• Custom ASIC– long design cycle
– costly to rework
• Programmable Logic
Introduction to VHDL
VHDL
Page 1 -
FPGAs and CPLDs• FPGAs excel at:
– higher density– pipelined logic– FIFOs, register files
• using RAM
• CPLDs excel at:– deterministic performance– fast pin-to-pin speed– state machines– wide decoding
Introduction to VHDL
VHDL
Page 1 -
Xilinx FPGA Architecture Benefits• SRAM programming cells
– easy design changes
• On-chip distributed SelectRAM memory– efficient FIFOs
• Segmented routing– high speed and low power
• Dedicated carry logic– high speed counters and arithmetic
Introduction to VHDL
VHDL
Page 1 -
The FPGA Die
CLB
CLB
CLB
CLB
SwitchMatrix
ProgrammableInterconnect
I/O Blocks (IOBs)
ConfigurableLogic Blocks (CLBs)
Introduction to VHDL
VHDL
Page 1 -
• Combinatorial logic is implemented in Look-Up Tables (LUT)
– Look-Up Tables are also known as a function generators
– Look-Up Tables can be used as synchronous RAM
• Output can be registered (XQ) or purely combinatorial (X)
CLB Resources
H1H2H3
G_LUT
H_LUT
FFX
F_LUT
FFY
G1G2G3G4
F1F2F3F4
XQ
X
Y
YQ
Introduction to VHDL
VHDL
Page 1 -
Look-Up Tables• Combinatorial logic is stored in Look-Up Tables (LUTs) in a CLB
• Capacity is limited by number of inputs, not complexity• Delay through CLB is constant
Combinatorial Logic
AB
CD
Z
A B C D Z
0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1 . . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1
Introduction to VHDL
VHDL
Page 1 -
IOB Resources• Input, output, or bi-directional
pad
• Inputs and outputs can be registered or latched
• Tri-state output
• Programmable output slew rate
• Variable input delay for zero hold time
FF
FF orLATCH
IN
OUT
DELAY
FASTLATCH
SLEW RATECONTROL
PULL-UPPULL-DOWN
PAD
Introduction to VHDL
VHDL
Page 1 -
CPLDs• XC9500 devices are similar to
having multiple PAL devices interconnected in one chip
• Best applications– Wide functions – Fast arithmetic– Complex counters– Complex state machines– PAL/GAL or TTL integration– Non-volatile
PAL
PAL
PAL
PAL
Swi-tch
Mat-rix
Prog.ANDarray
FixedOR
array
FF/Macro-
cell
FF/Macro-
cell
Introduction to VHDL
VHDL
Page 1 -
XC9500XL Architecture• New extra-wide function block inputs
Introduction to VHDL
VHDL
Page 1 -
XC9500XL Macrocell
Flexible clocking and three-state control
Local macrocell clock inversion control
Introduction to VHDL
VHDL
Page 1 -
Design Example Device Logic Unit Delay Used Gate32bit Decoder XC9536xl- 10 1 Macro Cell 10ns 22
XC4005xl- 09 15 CLB 22ns 3838bit Counter XC9536xl- 10 8 Macro Cell 10ns 178
XC4005xl- 09 5 CLB 9ns 1288bit Adder XC9536xl- 10 11 Macro Cell 36ns 244
XC4005xl- 09 5 CLB 16ns 1288bit 2to1 Mux XC9536xl- 10 8 Macro Cell 10ns 178
XC4005xl- 09 4 CLB 15ns 1028bit 16진 XC95144xl- 10 128 Macro Cell 2844
Shift XC4005xl- 09 64 CLB(F/F) 1633Register 7 CLB(RAM) 179
- XC9536XL-10 : 36 Macro Cell CPLD, Speed Grade 10ns, 800 Usable Gate
- XC4005XL-09 : 196 CLB, 0.9ns Cell Delay, 5000 Usable Gate
Compare FPGA and CPLD