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ECE 322
Digital Design with VHDL
Introduction to VHDL #4
Lecture 9 & 10
California State University
Single-Bit Adders
Half-adder
Adds two binary (i.e. 1-bit) inputs A and B
Produces a sum and carryout
Problem: Cannot use it alone to build larger adders
Full-adder
Adds three binary (i.e. 1-bit) inputs A, B, and carryin
Like half-adder, produces a sum and carryout
Allows building M-bit adders (M > 1)
Simple technique
Connect Cout of one adder to Cin of the next
These are called ripple-carry adders
Shown in next section
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Half-Adder
Sum
s
0
1
1
0
Carry
c
0
0
0
1
0
0 +
0
1 +
1 0 0 0
1
0 +
1 0
1
1 +
0 1
x
y +
s c
Sum Carry
(a) The four possible cases
x y
0
0
1
1
0
1
0
1
(b) Truth table
x
y s
c
HAx
y
s
c
(c) Circuit (d) Graphical symbol
Sum
s
0
1
1
0
Carry
c
0
0
0
1
0
0 +
0
1 +
1 0 0 0
1
0 +
1 0
1
1 +
0 1
x
y +
s c
Sum Carry
(a) The four possible cases
x y
0
0
1
1
0
1
0
1
(b) Truth table
x
y s
c
HAx
y
s
c
(c) Circuit (d) Graphical symbol
Sum
s
0
1
1
0
Carry
c
0
0
0
1
0
0 +
0
1 +
1 0 0 0
1
0 +
1 0
1
1 +
0 1
x
y +
s c
Sum Carry
(a) The four possible cases
x y
0
0
1
1
0
1
0
1
(b) Truth table
x
y s
c
HAx
y
s
c
(c) Circuit (d) Graphical symbol
California State University
VHDL Code for Half-Adder
library ieee ;
use ieee.std_logic_1164.all;
entity HA is
port(x, y : in std_logic;
s, c : out std_logic);
end HA;
architecture dataflow of HA is
begin
s <= x xor y;
c <= x and y;
end dataflow;
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Full-Adder
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VHDL Code for Full-Adder
library ieee ;
use ieee.std_logic_1164.all;
entity FA is
port(ci, xi, yi : in std_logic;
si, ci+1 : out std_logic);
end FA;
architecture LogicFunc of FA is
begin
Si <= xi xor yi xor ci;
ci+1 <= (xi and yi) or (ci and xi) or (ci and yi);
end LogicFunc;
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Decomposed Implementation of Full-Adder
HA
HA s1
c1
s
c2 c i
x i y i
c i 1 +
s i
c i
x i
y i
c i 1 +
s i
(a) Block diagram
(b) Detailed diagram
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VHDL Code for Full-Adder Using Half-Adder
library ieee ;
use ieee.std_logic_1164.all;
entity FA is
port(ci, xi, yi : in std_logic;
si, ciplus1 : out std_logic);
end FA;
architecture structure_FA of FA is
signal s1,c1,c2 : std_logic;
component HA
port(x, y : in std_logic;
s, c : out std_logic);
end component;
begin
HA1:HA port map(xi, yi, s1, c1);
HA2:HA port map(ci, s1, si, c2);
ciplus1 <= c2 or c1;
end structure_FA;
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1 0 1 0
1 0 0 1 +
1 Carry-in
0 1 0 0 1 Carry-out
1 1
Carry ripples from one column to the next
Multi-Bit Ripple-Carry Adder
Called a ripple-carry adder because carry ripples from
one full-adder to the next.
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Cin c1 c2 … c3 cn-1 Cout
s0
y0 x0 Carry-out
Carry ripples from one stage to the next
Carry-in
LSB position MSB position
y1 x1 y2 x2 yn-1 xn-1
s1 s2 sn-1
FAn-1 FA2 FA1 FA0
An n-bit RCA consists of n Full Adders
The carry-out from bit i is connected to the carry-in of bit (i+1)
Multi-Bit Ripple-Carry Adder
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Consists of 4 Full Adders
4-Bit Ripple-Carry Adder
Cin
c1 c2 c3
s0
y0 x0 y1 x1 y2 x2
s1 s2
FA2 FA1 FA0 FA3 Cout
s3
y3 x3
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VHDL Code for 4-Bit Ripple-Carry Adder
library ieee ;
use ieee.std_logic_1164.all;
entity adder4 is
port(Cin : in std_logic;
x3, x2, x1, x0 : in std_logic;
y3, y2, y1, y0 : in std_logic;
s3, s2, s1, s0 : out std_logic
Cout : out std_logic);
end adder4;
architecture structure_adder4 of adder4 is
signal c1,c2,c3 : std_logic;
component FA
port(Cin, x, y : in std_logic;
s, Cout : out std_logic);
end component;
begin
FA1:FA port map(Cin, x0, y0, s0, c1);
FA2:FA port map(c1 , x1, y1, s1, c2);
FA3:FA port map(c2 , x2, y2, s2, c3);
FA4:FA port map(c3 , x3, y3, s3, Cout);
end structure_adder4;
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Alternative Approach for Component Declaration
Another way to declare component in VHDL is to place it in
VHDL package.
A package allows VHDL constructs to be defined in one
source code file and then used in other source code files.
Package declaration has its own LIBRARY and USE
clauses.
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Alternative Approach for Component Declaration
library ieee;
use ieee.std_logic_1164.all;
package fulladd_package is
component FA
port(Cin, x, y : in std_logic;
s, Cout : out std_logic);
end component;
end fulladd_package;
Example: Declaration of Full-Adder package
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VHDL Code for 4-Bit Adder Using Full-Adder package
library ieee ;
use ieee.std_logic_1164.all;
use work.fulladd_package.all;
entity adder4 is
port(Cin : in std_logic;
x3, x2, x1, x0 : in std_logic;
y3, y2, y1, y0 : in std_logic;
s3, s2, s1, s0 : out std_logic
Cout : out std_logic);
end adder4;
architecture structure_adder4 of adder4 is
signal c1,c2,c3 : std_logic;
begin
FA1:FA port map(Cin, x0, y0, s0, c1);
FA2:FA port map(c1 , x1, y1, s1, c2);
FA3:FA port map(c2 , x2, y2, s2, c3);
FA4:FA port map(c3 , x3, y3, s3, Cout);
end structure_adder4;
