Introduction to the World of Analogue-to-Digital Conversion

Introduction to the World of

Analogue-to-Digital Conversion

Shraga Kraus

Analogue and Mixed Signal

Haifa Research Laboratory

ADC

«2»©2016 Copyright Shraga Kraus

Contents

• Introduction to A/D Conversion

• Building Blocks

• Basic Architectures

• More Advanced Architectures

• The ΔΣ Architecture


Contents


• Building Blocks





Introduction to A/D Conversion


Types of Signals

• Analogue signal:

– Continuous in time

– Continuous in value (within its range of existence)

• Digital signal:

– Discrete in time

– Discrete in value


The Two Conversions

• Conversion 1: Sampling

– Continuous time discrete time

– Creates aliasing

• Conversion 2: Quantisation

– Continuous value discrete value

– Creates quantisation noise


Sampling

• Sampling = multiplication by an impulse train

• Y(t) = X(t) · S(t)

• Ts = sampling interval

• fs = 1/Ts = sampling frequency

t

Ts


Sampling in the Frequency Domain

• In the frequency domain:

• Y(f) = X(f) * S(f)

• “Aliasing” is evident


Over/Under Sampling

• Nyquistsampling:

• Over-sampling:

• Under-sampling:


Information at the Output

• Nyquistsampling:

• Over-sampling:

• Under-sampling:

–fs –fs/2 0 fs/2 fs




“Folding” the Frequency Axis


Finding the Final Frequency


Example 1: f = 13 MHz

• fs = 20 MHz

• ADC’s output contains information up to 10 MHz

• 13 MHz folds to 7 MHz


Example 2: f = 23 MHz

• fs = 20 MHz

• ADC’s output contains information up to 10 MHz

• 23 MHz folds to 3 MHz


Anti-Aliasing Filter

These interferers can be removed digitally

• Never use your ADC at full Nyquist

• A rule of thumb: over sampling ratio (OSR) of 2 is minimal


Quantisation

• Δ = LSB

• m = number of bits

• Full scale amplitude:

0

Δ

A

76543210

2

2

m

A


Quantisation Error

• If the input signal is not synchronised with the sampling clock, the error is uniformly distributed between –Δ/2 and +Δ/2

t


ADC model

• In this case, the ADC is modelled as a linear system with noise

• The noise comes from the quantisation process

• If we refer the noise to the input:

• At every sampling moment a small noise is added to the input signal, bringing it to the centre of the quantisation range


A Test Case: Continuous-Wave

• The input signal a sinusoidal wave not synchronised with the sampling clock, with a full-scale amplitude

• Quantisation error distribution is:

–Δ/2 +Δ/20

1/ΔFqn

x


Signal and Noise Power

• Signal power:

• Quantisation noise power:

2

2 2 2 31 1 22

2 2 2

mm

sigP A

3 22 2

2 2

2 2

1 1 1

3 4 12qn qnP F x x dx x dx


Signal and Noise Power

• SNR:

• Effective number of bits (ENOB):

2 2 32

2

10

2 32

212

10log 6.02 1.76

msig m

qn

dB

PSNR

P

SNR SNR m

1.76

6.02

dBSNRENOB


Practical ENOB

• In practice, another noise mechanisms exist in the ADC

• Thermal / shot noise

• Nonlinearity (not strictly a noise, but contributes to non-signal power)

• To get the practical resolution of an ADC, the signal to noise-and-distortion ratio (SNDR) should be derived


Derivation of ENOB

• For a given SNDR of an ADC, the effective resolution is:

𝐸𝑁𝑂𝐵 =𝑆𝑁𝐷𝑅𝑑𝐵 − 1.76

6.02

• The above is valid for a full-scale sinusoidal continuous wave input

• This test setup is feasible using standard lab equipment


Simulation Example

• Simulation of an ideal 7-bit ADC

• SNR = 43.8 dB ENOB = 7

Quantisation noise is

approximately white

(as expected from a unifor-

mly distributed noise)

Quantisation noise spectral density is

∆2

12

𝑓𝑠2


Simulation Example - Oversampling

• Out-of-band noise is filtered out digitally

• OSR = 2 SNR x2 (+3dB) ENOB += ½

𝐸𝑁𝑂𝐵 =𝑆𝑁𝐷𝑅𝑑𝐵 − 1.76

6.02


What is ½ Bit?

• 6½ decimal digits = 106.5

levels

• 7½ bits (binary digits) = 27.5

levels


Integral Nonlinearity

Vin

outputcode

76543210

Vref0

INL is the horizontal distance between the actual and ideal curves.

Usually expressed in units of Δ.


Differential Nonlinearity

Vin

outputcode

76543210

Vref0

DNL is the difference between the actual and ideal step widths.

Usually expressed in units of Δ.


Nonlinearity Information

• INL and DNL provide a lot of information on what’s going on inside the ADC

• Analysis of the data depends on the structure of the specific ADC being tested


Clock Jitter

• Jitter = the time domain equivalent of phase noise

• Clock jitter = changes in clock period

• Deterministic / random jitter


Sampling With Clock Jitter

• Clock jitter results in sampling the wrong value

The higherthe slope of the signal,

the larger the error


Effect of Clock Jitter

• fsig = input signal frequency

• Tj,RMS = random clock jitter RMS (in unit time)

• SNRj = SNR of an ADC as if clock jitter was the only noise source

𝑆𝑁𝑅𝑗 =1

2𝜋 ∙ 𝑓𝑠𝑖𝑔 ∙ 𝑇𝑗,𝑅𝑀𝑆


Meaning of Clock Jitter

• Clock jitter is painful in sampling of high frequency signals

• No solution was found to date

𝑆𝑁𝑅𝑗 =1

2𝜋 ∙ 𝑓𝑠𝑖𝑔 ∙ 𝑇𝑗,𝑅𝑀𝑆

SNRj depends only on the input signal frequency, NOT

sampling frequency!


Lab Characterisation - SNR

Pure Sine

Signal Generator

Signal Generator

ADC


Lab Characterisation - SNDR

Dual Tone

Signal Generator

Signal Generator

ADC

SFDR


Contents


• Building Blocks





Building Blocks


Latched Comparator

• Differential pair– When CLK = ‘1’ the input

difference is amplified

• Regenerative load (positive feedback)– When CLK = ‘0’ the

amplified difference if further enhanced to the rails

– Regardless of the inputsOne of many topologies, from Wikipedia


Comparator’s Nonidealities

• Offset

– Originates from mismatch in the differential pair

• Noise

– Like in every active circuit

– The input-referred noise may result in incorrect decision for small input difference



• Regeneration Time

– The smaller the input signal, the longer the regeneration is

• Metastability

– Occurs when the regeneration is too long

– Adding digital buffers at the output can reduce the probability of metastability



• Hysteresis

– A result of residual charge somewhere in the load network

– Some circuit techniques alleviate this effect


Master-Slave Comparator

• Consists of two cascaded latched comparators

• Reduces the probability of metastability

• Has constant input-to-output delay

• But – the delay is long (½ clock cycle)

inp

inn

outp

outn

CK

inp

inn

outp

outn

CK


More Information


Op Amp

• Serves in almost every type of ADC

• Based on a differential pair at the input

– except of low voltage technologies, but this makes no difference for our discussion


Op Amp’s Nonidealities

• Offset

– Originates from mismatch in the differential pair

• Noise

– Like in every active circuit

• Finite Gain and Bandwidth

– Feedback is imperfect, results in gain error


Op Amp’s Nonidealities

• Inaccurate Gain

– Due to either gain error or mismatch between the feedback devices

• Settling Time

– May set a limit in several architectures


More Information


MOS Switch

• Switch resistance (“ON”) depends on Vin

Vctrl = VDD ; Vctrl = 0

VGS = Vctrl – Vin Vin

RSW

Both

PMOS

NMOS

Both


What’s the Problem With That?

• Nonlinear RSW results in a nonlinear voltage divider

• Signal is distorted


Parasitic Capacitances

• The gate overlaps with the areas of source and drain

• In addition, the gate capacitance exists

DS

G

B

COL COL

CG


Charge Injection

• When φ goes down, the charge in the channel is drained to both sides

Vin CL

φ The voltage on

CL changes!

The exact amount of

charge is input dependent

The path of the charge depends on the values of

VOL, CG, and tfall of the clock


Bootstrapped Switch

• Keeps VGS constant

• Usually incorporates a charge pump

• May also include a sub circuit for alleviating charge injection effect

From P.E. Allen’s lecture notes, 2010

http://www.aicdesign.org/SCNOTES/2010notes/Lect2UP140_%28100325%29.pdf


More Information


Sample & Hold / Track & Hold

• Tracks the input signal when clock is low

• Freezes (“holds”) the input value upon clock rising

• Uses a capacitor to store the analogue information (voltage)

φ


S&H Nonidealities

• Charge injection by the switch

• Leaky capacitor

• Buffer’s nonidealities (including noise)

• Total noise of the capacitor itself is φ 𝐾𝑇

𝐶𝑉2


More Information


Contents


• Building Blocks





Basic Architectures


Flash ADC

• Nº of comparators = 2m – 1

• Thermometer code output

• Converted to binary by a simple logic

• Fastest topology

VREF

Vin

Thermo- meter

to Binary

Dout <2:0>


Thermometer Code

• Like a bar graph indicator

• The represented decimal number is the number of ‘1’s.

00000000

00000001

00000011

00000111

00001111

00011111

00111111

01111111

11111111

012345678


Limitations of the Flash ADC

• Many comparators

– area, power

• Resistor matching

– area

• Input capacitance

– requires a buffer

• Comparators’ offset

– Can generate bubbles

VREF

Vin

Thermo- meter

to Binary

Dout <2:0>


Nonlinearity of the Flash ADC

• Input buffer

• Resistor mismatch

• Comparators’ offset

• Clock/Vin skew or input S&H

VREF

Vin

Thermo- meter

to Binary

Dout <2:0>


Folding ADC

• Nº of comparators = 2m/2 + 1 – 2

• Reduces area and power significantly– Compared to flash

• In the blue zones, zeros should be counted rather than ones (in )

vout

vin

VREF

VREF


Numerical Example

• Consider an 8-bit ADC:

• A flash ADC requires 28 – 1 = 255 comparators

• A folding ADC, with 4-4 structure, requires 2 · (24 – 1) = 30 comparators


Limitations of the Folding ADC

• Same as flash: the MSB flash, , must be as accurate as the LSB (Δ)

– Resistor matching

– Comparators’ offset

• The folding amplifier, , must be as accurate as the LSB (Δ)

– Transistor matching


Limitations of the Folding ADC

• The folding amplifier introduces a delay and results in skew between the two flash ADCs

– Significant at high frequencies

– Requires introduction of a S&H at the input


Nonlinearity of the Folding ADC

• Nonlinearity of the flash ADCs

– In particular

• Nonlinearity of the folding amplifier

• Clock/Vin skew between the two flashes or input S&H


Single Slope ADC

t

VREF

vin

Start!

• Counter reset to 0 and starts counting• Slope initiates

Stop!

• Comparator’s output flips • Counter stops

S&H

vslope


Limitations of the Single Slope ADC

• The slope must be calibrated

– Its exact slope is unknown

• The comparator makes a decision around Vin, not around a constant voltage

– If the comparator’s offset is constant for every Vin, this only shifts the range of voltages being quantised

– If the comparator’s offset changes with Vin, this results in nonlinearity


Limitations of the Single Slope ADC

• The S&H has its own nonidealities

• The slope can be nonlinear

• Incomplete capacitor discharge (“memory effect”)

• It’s Slooooooooooow

– 2m clock cycles / conversion


Single Slope ADC in Digital Cameras

• A line of ADCs samples a line of pixels simultaneously

• To implement the line:– One slope for the entire line

– One counter for the entire line or a counter for each ADC

– A S&H, a comparator and a register for each ADC

– Most CCDs do not require a S&H, though.


More Information


Contents


• Building Blocks





More Advanced Architectures


The Pipeline ADC

• Starts from the MSB

• Then moves on to the next stage – to extract the next bit

• Meanwhile, the first stage treats the next sample


Principle of Operation

1. Decide about the MSB

2. According to the decision – magnify the appropriate range (2x, shift to centre)

3. Decide about the next bit; go to 2


Example

C0x2

‘1’

C1

–VREF/2

then

x2

‘0’

C2

‘1’


Implementation

• Implemented in switched-capacitor technique

• A single-stage DAC + 2x amplifier (MDAC):

Josh Carnes and Un-Ku Moon, “The effect of switch resistance on pipelined ADC MDAC settling time”, Proc. ISCAS 2006

Value of VREF is set according to the decision of

the previous comparator


How a Multiplying-DAC Works

• During φ1:• During φ2: 𝑉𝑜𝑢𝑡 = 2𝑉𝑖𝑛 − 𝑉𝑅𝐸𝐹


Offset in the First Comparator

C0x2

‘0’

C1

–VREF/2

then

x2

‘0’

C2

‘1’

Should be ‘0’!


Limitations of the Pipeline ADC

• Sensitive to comparator’s offset– Solved by redundancy (next slide)

• Sensitive to op amp’s offset– Solved by correlated double sampling (CDS)

• Charge injection from the switches– Solved by bottom plate sampling

• Gain must be exactly 2x– Limited by capacitor mismatch & op amp’s gain

• Op amp’s DC gain must be high– To reduce gain error


Redundancy – 1½ Bits Per Stage

–VREF/2

then

x2

‘01’

C2B

‘11’

C2A

C0

–VREF/4

then

x2

‘0’

C1B

C1A

MSB = ‘1’ for sure

B1 = ? We’ll decide

later on

Now we have all the information

for making a decision

We’re in the lower partof the 3 upper values D<2:0> = ‘101


If a Comparator Has Offset

–VREF/2

then

x2

‘00’

C2B

‘10’

C2A

C0

x2

‘1’

C1B

C1A

MSB = ‘1’ for sure

B1 = ‘0’for sure

LSB = ‘1’ for sure


Limitations of the Pipeline ADC

• Sensitive to comparator’s offset– Solved by redundancy

• Sensitive to op amp’s offset– Solved by correlated double sampling (CDS)

• Charge injection from the switches– Solved by bottom plate sampling

• Gain must be exactly 2x– Limited by capacitor mismatch & op amp’s gain

• Op amp’s DC gain must be high– To reduce gain error


Nonlinerity of the Pipeline ADC

• Gain is not exactly 2x

– Capacitor mismatch

– Low DC gain of the op amp (gain error)

– Changes the slope of the transfer function

• Long settling time

– Op amp should settle during a clock period


Notes on the Pipeline ADC

• Nº of comparators = 2m (due to redundancy)

• Nº of MDACs = m – 1

• 1 clock cycle / conversion

• Propagation delay = m clock cycles

• Requires descent op amps

– Not trivial in contemporary CMOS technologies


More Information


The SAR ADC

• Based upon binary search (Successive Approximation Register)

• SAR = ‘10000

• DAC > Vin ?

• SAR = ‘C1000

• DAC > Vin ?

• SAR = ‘CC100

• And so on…

From Wikipedia


Capacitive SAR ADC

• Capacitors are charged to Vin

• Charge is distributed so that 𝑉− = 𝑉𝑅𝐸𝐹 ∙

𝑆𝐴𝑅

2𝑚 − 1− 𝑉𝑖𝑛 = 𝐷𝐴𝐶 − 𝑉𝑖𝑛


Limitations of the SAR ADC

• Comparator’s offset– Solved by redundancy

• Charge injection from the switches– The larger the capacitors, the smaller the effect

but the slower the ADC is

• Capacitor mismatch

• Low impedance sources of Vin end Vref are required


Notes on the SAR ADC

• Only one comparator

• m clock cycles / conversion

– Quite slow

• Exponentially scaled capacitors

– A lot of area

• No op amp (!!!)

– Attractive for contemporary CMOS technologies

– Low power


More Information


Contents


• Building Blocks





The ΔΣ Architecture


The Concept of ΔΣ ADC

• Over sampling

– Relatively high OSR

• Noise shaping

– Quantisation noise is attenuated at the frequencies of interest

– It is amplified, on the other hand, at other frequencies

• Feedback structure


The 1st Order ΔΣ Modulator

• N = loop resolution [bits]

• M = final resolution [bits]“Quantiser”

Loop Filter

For the sake of clarity we will discuss

low pass ΔΣ ADC only


Linear Model

• Linear Model:

• Loop equation:

Quantisationnoise of the

quantiser

Loop filter of a low pass ΔΣ

𝑌 = 𝑋𝑧−1 + 𝐸 1 − 𝑧−1


Linear Model

• Signal Transfer Function (STF):

• Noise Transfer Function (NTF):

• Substituting z = ej·2πf in NTF we get:

𝑆𝑇𝐹 = 𝑌

𝑋𝐸=0

= 𝑧−1

𝑁𝑇𝐹 = 𝑌

𝐸𝑋=0

= 1 − 𝑧−1

𝑁𝑇𝐹 𝑓 2 = 2sin 𝜋𝑓 2

Delay

High pass filter

Indeed, a high pass filter

f is normalized:f / fs


Noise Transfer Function

Quantisationnoise is

attenuated at low frequencies


amplified at high frequencies

Quantisationnoise of high

frequencies can be filtered out

digitally


Example: Ideal 1st Order ΔΣ ADC

OSR = 16

The grey noise is filtered out

digitally(decimation filter)

Here, where our signal resides, the quantisation noise

is significantly attenuated


Example: Discussion

• In a “standard” Nyquist ADC:

– OSR = 16 ENOB += 2

• A 1-bit ADC with OSR = 16:

– ENOB = 3

• A 1-bit 1st order ΔΣ ADC with OSR = 16:

– ENOB = 6.4


How Does It Work?

• Recall the scheme of a feedback system:

• The closed loop gain is approximately 1/B

– Every pole in B becomes a zero

– Every zero in B becomes a pole

A

B


How Does It Work?

• In the signal path, the loop filter serves as the amplifier, and there is unity feedback:

• The signal passes as is, with the integrator limiting its bandwidth


How Does It Work?

• In the error path, the loop filter serves as the feedback, and there is a unity amplifier:

• The closed loop gain is a high pass filter


The 2nd Order ΔΣ Modulator

• N = loop resolution [bits]

• M = final resolution [bits]

Two feedback loops


Linear Model

• Linear Model:

• Loop equation:

𝑌 = 𝑋𝑧−1 + 𝐸 1 − 𝑧−1 2


Linear Model

• Signal Transfer Function (STF):

• Noise Transfer Function (NTF):

• Substituting z = ej·2πf in NTF we get:

𝑆𝑇𝐹 = 𝑌

𝑋𝐸=0

= 𝑧−1

𝑁𝑇𝐹 = 𝑌

𝐸𝑋=0

= 1 − 𝑧−1 2

𝑁𝑇𝐹 𝑓 2 = 2sin 𝜋𝑓 4


Noise Transfer Function


attenuated stronger

OSR x 2 + 1.3 bit (1st order)+ 1.7 bit (2nd order)+ 1.9 bit (3rd order)+ 2.1 bit (4th order)


Higher Loop Orders

• Higher loop orders are possible. However:

• Up to 2nd order the modulator is unconditionally stable– If the linear model shows that the modulator is stable,

it will be stable for every input signal

• From 3rd order and above the modulator is conditionally stable– Even if the linear model shows that the modulator is

stable, it might become unstable for certain input signals


More Information


The Mother of All Rules of Thumb

Never do anything

not understanding

what you’re doing


Thank You!

Documents

Introduction to the World of Analogue-to-Digital Conversion