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Introduction to the Design of Embedded
SystemSystem2008 12 32008. 12. 3
Presented by Sang-Uk Jeon
ⓒ KAIST SE LAB 2008
Contents
Part I – What is Embedded System?Part II – Designing Embedded SystemPart III Software Engineering inPart III – Software Engineering in Embedded System Design
ⓒ KAIST SE LAB 2008 2/35
Part I. What is Part I. What is Embedded System?
ⓒ KAIST SE LAB 2008
Definition of Embedded System*Part I. What is Embedded System?
y
A combination of computer hardware and software, and perhaps additional mechanical or other partspDesigned to perform a dedicated functionIn some cases, part of a large system or productp
e.g.) Antilock Braking System(ABS) in a car
* Michael Barr "Embedded Systems Glossary” Netrino Technical Library* Michael Barr, "Embedded Systems Glossary”, Netrino Technical Library, Available at http://www.netrino.com/Embedded-Systems/Glossary
ⓒ KAIST SE LAB 2008 4/35
Characteristics of Embedded System*Part I. What is Embedded System?
y
Single-functionedExecutes a single program, repeatedly
Tightly-constrainedTightly-constrainedLow power, small, fast, etc.
Reactive and real-timeContinually reacts to changes in the system’sContinually reacts to changes in the system s environmentMust compute certain results in real-timeMust compute certain results in real-time without delay
* Frank Vahid and Tony Givargis Embedded System Design: A Unified* Frank Vahid and Tony Givargis, Embedded System Design: A Unified Hardware/Software Introduction, John Wiley & Sons, ISBN: 0471386782, 2002.
ⓒ KAIST SE LAB 2008 5/35
Categorization of Embedded SystemPart I. What is Embedded System?
g y
Computation orientedMP3 player, MPEG decoder, etc
Control orientedControl orientedHome appliances, industrial controller, safety-
iti l t llcritical controllerHybrid(computation + control)y ( )
Portable information devices• e g) Cellular phonee.g) Cellular phone
Networked multimedia applications
ⓒ KAIST SE LAB 2008 6/35
Part II. Designing Part II. Designing Embedded System
ⓒ KAIST SE LAB 2008
Issues in Embedded System DesignPart II. Designing Embedded System – Traditional Embedded System Design
y g
Top-priority design goalConstruct the system with desired functionality
Design issueDesign issueSimultaneously optimize numerous design
t i tconstraints• Size, performance, power, flexibility, etc.
ⓒ KAIST SE LAB 2008 8/35
Traditional Embedded System DesignPart II. Designing Embedded System – Traditional Embedded System Design
y g
System Specification
HW & SW P titi
•Designers partition the system into hardware and software early in the flow
HW & SW Partition
HW Development
Test not passed
•HW and SW engineers design their respective components in isolation•HW and SW engineers do not talk to each
hp
SW Development
other
•Integration problemsHi h t d l it ti
Prototype Test
•High cost and long iteration
Prototype
Test passed•Need new methodology!!
HW & SW co-designPlatform-based design…
ⓒ KAIST SE LAB 2008 9/35
HW & SW Co-DesignPart II. Designing Embedded System – HW & SW Co-Design
g
System Specification
Design Space ExplorationHW & SW Partition
HW Model SW Model* Synonym *ApplicationFunctionality
* Synonym *ArchitecturePlatform
Map HW & SW
E l ti f il d Evaluation*
SW SynthesisHW Synthesis
Evaluation failed
SW SynthesisHW Synthesis
HW & SW Integrationg*Evaluation subject : Performance, energy, etc.ⓒ KAIST SE LAB 2008 10/35
Design Space Exploration(DSE)*Part II. Designing Embedded System – HW & SW Co-Design
g p p ( )
Finding the optimal design of software and hardware
That satisfies given design objectivesThat satisfies given design objectivesProblem Space
(Characteristics of SW & HW)Solution Space
(Design objectives)
•Software functionality•Hardware parameters
Processor architecture
•Performance objective•Energy objective•…Processor architecture
Clock rateCache size…
Memory architecturePage replacement policy… * M. Gries. Methods for evaluating and
… covering the design space during early design development. Integr. VLSI J., 38(2):131–183, 2004.ⓒ KAIST SE LAB 2008 11/35
HW & SW PartitionPart II. Designing Embedded System – HW & SW Co-Design
Decides whether each functionality is implemented in HW or SW
Requirements : Summing up 100 valuesq g p
Software implementation
Alternative 1 Alternative 2
Software implementationADD v1, v2ADD v1, v3…
ADD v1, v2, …, v100
ADD v1, v100
ADD x1, x2 ADD x1, x2, …, x100Hardware support Hardware support
•More flexible software •Smaller software size•Better performance
pp pp
ⓒ KAIST SE LAB 2008 12/35
Software ModelPart II. Designing Embedded System – HW & SW Co-Design
Kahn process networksDirected Acyclic Graphs(DAG)Directed Acyclic Graphs(DAG)DAGs with periods and deadlinesSynchronous data flowyControl data flow graphs and dynamic data flowHigh-level programming languageCo-Design Finite State MachinesCommunication analysis graphsClick model of computationClick model of computationTransaction Level Modeling
SystemC
Hierarchical and heterogeneous models of computationPtolemy framework, Metropolis meta-model language, etc.
ⓒ KAIST SE LAB 2008 13/35
Hardware ModelPart II. Designing Embedded System – HW & SW Co-Design
Abstract modelsInstruction-accurate modelTask-accurate modelTask accurate modelNon-linear, accumulative service descriptions
E t bl d lExecutable modelsMicro-architecture templatespHardware description languageArchitecture description languageArchitecture description language
ⓒ KAIST SE LAB 2008 14/35
Mapping Software and HardwarePart II. Designing Embedded System – HW & SW Co-Design
pp g
Binding software tasks to hardware building blocks
May require additional jobs such asMay require additional jobs such as• Rewriting/adapting software code
– To link required interface of software and provided interface q pof hardware
• Compilation of the software onto the hardware
Software Tasks
ARM P1 ARM P2 DSP P3Hardware blocks
ⓒ KAIST SE LAB 2008 15/35
Evaluation (1/3)Part II. Designing Embedded System – HW & SW Co-Design
( / )
Simulation-based methodsCycle-accurate simulation
Software HardwareRead Memory
Cycle 1 (do Inst1)
Cycle 2 (do Inst2)
Done! (3 cycle)
Cycle 2 (do Inst2)
Cycle 3 (do Inst2)
System-level simulationSystem level simulationSoftware HardwareRead Memory
Done! (3 cycle)Read Memory :
Assume that it ( y )consumes 3 cycle
ⓒ KAIST SE LAB 2008 16/35
Evaluation (2/3)Part II. Designing Embedded System – HW & SW Co-Design
( / )
Analytical methodsStatic profiling
• Complexity analysis of algorithms, the dependency p y y g , p yanalysis of function call graph, etc.
High-level synthesisg y• Find an optimal mapping for the software tasks to
the hardware– Exact method such as Integer/mixed linear program
formulations, heuristics, evolutionary algorithms, etc.
ⓒ KAIST SE LAB 2008 17/35
Evaluation (3/3)Part II. Designing Embedded System – HW & SW Co-Design
( / )
Combination of simulation-based and analytical methods
Trace-based performance analysisTrace based performance analysisA trace contains all memory access
Cache hit & miss statistics…
Analytical models with initial, calibrating Initial simulation
yUse the trace to calculate performance
simulation
Cache miss rate : 10~20% P = A / B * …
Exhaustive simulation
Simulation results
Obt i f
Cache miss rate : 10 20%…
F d th i f ti
Q = C * 100 + …….
Exhaustive simulation Obtain ranges ofperformance factor
Feed the informationInto the analytical model
ⓒ KAIST SE LAB 2008 18/35
Frameworks for DSEPart II. Designing Embedded System – HW & SW Co-Design
System-level Micro-architecture centricMetropolisMescal
Mescal/TipiASIP-Meister / PEAS-III
StepNPSPADE
EXPRESSIONLisaTek
ArtemisMILAN
Chess / CheckersMaxCore & MaxSim
MESHSEASIncisive-SPWCoCentric System Studio
ⓒ KAIST SE LAB 2008 19/35
Example – Metropolis (1/4)Part II. Designing Embedded System – HW & SW Co-Design
p p ( / )
Functionality modelingProcess Src Medium S Process Sink
Process Src {port Out out;void thread() {
d(d )
Process Sink {port In in;void thread() {
i i (d )
Medium S {void send() {
…}out.send(data);
}void doSomething() {}
in.receive(data);}
}
}void receive() {
…}}
}}
}
Port Out {void send() {}
}
Port In {void receive() {}
}} }
ⓒ KAIST SE LAB 2008 20/35
Example – Metropolis (2/4)Part II. Designing Embedded System – HW & SW Co-Design
p p ( / )
Architecture modelingTask 1
CPU
Task 2
P T k { M di CPU {
Task n
Process Task {port TaskToCPU taskToCPU;void thread() {}
Medium CPU {void read() {
// read from memory}}
void read() {…}
}void write() {
// write to memory}}
void write() {…}
}}
}void execute(int n) {
// Consume n CPU cycles}}
}
ⓒ KAIST SE LAB 2008 21/35
Example – Metropolis (3/4)Part II. Designing Embedded System – HW & SW Co-Design
p p ( / )
MappingProcess Src Medium S Process Sink
Task 1
CPU
Task 2
Mapper {…constraint {constraint {
…Src.send => Task1.write;Src doSomething => Task1 execute(50);Src.doSomething => Task1.execute(50);Sink.receive => Task2.read;
…}}
}ⓒ KAIST SE LAB 2008 22/35
Example – Metropolis (4/4)Part II. Designing Embedded System – HW & SW Co-Design
p p ( / )
A part of the output in “Simple case study” example
ⓒ KAIST SE LAB 2008 23/35
Platform-Based DesignPart II. Designing Embedded System – Platform-Based Design
g
Main ideaReusing & facilitating a common design to a variety of different applicationsy pp
Cell Phone Platform
Phone SW N 1
Phone SW N 2
Phone SW No nNo. 1 No. 2 No. n
Phone Product No. 1 Phone Product No. 2 Phone Product No. nⓒ KAIST SE LAB 2008 24/35
What is the Platform?* (1/2)Part II. Designing Embedded System – Platform-Based Design
( / )
PlatformProcessor
M
BusA library of components• To generate a design at certain level of
Memoryabstraction
Platform instanceA set of components
Processor P1-Clock : 300MhzA set of components
• Selected from the library(platform)P t t
Clock : 300Mhz-Cache size : 16Kb-…
• Parameters are setBus B1
-Bandwidth : 10Mb/s* A. Sangiovanni-Vincentelli, Quo Vadis, SLD? Reasoning About the T d d Ch ll f S t L l D i P di f th -…Trends and Challenges of System Level Design, Proceedings of the IEEE, Vol. 95, No. 3, March 2007.
ⓒ KAIST SE LAB 2008 25/35
What is the Platform? (2/2)Part II. Designing Embedded System – Platform-Based Design
( / )
Multiple abstraction levels of the platformEach platform instance in the abstraction levels can be reused
FunctionalityLevel 1
FunctionalityLevel 2
FunctionalityLevel 3
Processor ARM MIPS ARM920T R2000
Memory Bus
ARM
DDR2 SDRAM
ISA
MIPS
PCI
DDR SDRAMDDR-200
ARM926EJ-S R4600
8-bit ISADDR2 SDRAM PCI
PCI 2.2
DDR-333 16-bit ISA
DDR2-533
PCI 3.0DDR2-800ⓒ KAIST SE LAB 2008 26/35
Design ProcessPart II. Designing Embedded System – Platform-Based Design
g
Meet-in-the-middle processCombination of top-down and bottom-up approachpp
ⓒ KAIST SE LAB 2008 27/35
A Platform for Software ReusePart II. Designing Embedded System – Platform-Based Design
API Platform*
* A. Sangiovanni-Vincentelli and Grant Martin, Platform-Based Design and Software Design Methodology for Embedded Systems, IEEEMethodology for Embedded Systems, IEEE Design & Test, Vol. 18(6), November 2001.
ⓒ KAIST SE LAB 2008 28/35
Part III. Software Engineering in Embedded Engineering in Embedded
System Designy g
ⓒ KAIST SE LAB 2008
Challenge in Embedded System Designg y g
Consideration of flexible implementationTo address rapidly changing & increasing requirementsqSacrificing some degree of performance
Increasing usage of programmable elements instead of ASICs (Application Specific Integrated Circuits)
Increasing complexity of application(software)
ⓒ KAIST SE LAB 2008 30/35
Research Issues (1/3)Part III. Software Engineering in Embedded System Design
( / )
In the view of the software process*Embedded System Engineering
Issue 1 : Coordination of embedded software development process with other sub-processes
Embedded Software Engineering
Electrical Engineering
Mechanical EngineeringEngineering Engineering Engineering
Issue 2 : Specialized software development process for
* Bass Graaf Marco Lormans and Hans Toetenel “Embedded Software Engineering:
dealing with non-functional requirements (Memory, power, real-time requirements, etc.)
Bass Graaf, Marco Lormans and Hans Toetenel, Embedded Software Engineering: The State of the Practice,” IEEE Software, Nov.-Dec., 2003
ⓒ KAIST SE LAB 2008 31/35
Research Issues (2/3)Part III. Software Engineering in Embedded System Design
( / )
In the view of the software modelHW & SW Partition
HW M d l SW M d l
Issue 1 : DSE in a more abstract levelHW Model
(Abstraction lv. 1)SW Model
(Abstraction lv. 1)abstract level
Issue 2 : Performance/ energy aware refactoring
Evaluation
Evaluationfailed
Map HW & SWenergy-aware refactoring
Issue 3 : Performance/ Evaluation
Issue 4 : Model-Driven
energy-related metric
HW Model(Abstraction lv. n)
SW Model(Abstraction lv. n)
Development
Map HW & SW Need to consider the underlying hardwareⓒ KAIST SE LAB 2008 32/35
Research Issues (3/3)Part III. Software Engineering in Embedded System Design
( / )
In the view of the software code
HW & SW Partition
HW Model SW Model Usually SystemC code
Map HW & SWEvaluationfailed
Issue 1 : UML to SystemC
Evaluation*failed
Issue 2 : Application of code-level software engineering techniques
TestingClone detectionReverse engineeringMetric…
ⓒ KAIST SE LAB 2008 33/35
References
[1] Michael Barr, "Embedded Systems Glossary”, Netrino Technical Library, Available at http://www.netrino.com/Embedded-Systems/Glossarya ab e at ttp // et o co / bedded Syste s/G ossa y
[2] Frank Vahid and Tony Givargis, Embedded System Design: A Unified Hardware/Software Introduction, John Wiley & Sons, ISBN: 0471386782, 20022002.
[3] M. Gries. Methods for evaluating and covering the design space during early design development. Integr. VLSI J., 38(2):131–183, 2004.
[4] A. Sangiovanni-Vincentelli, Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design, Proceedings of the IEEE, Vol. 95, No. 3, March 2007.
[5] Bass Graaf, Marco Lormans, and Hans Toetenel, “Embedded Software Engineering: The State of the Practice,” IEEE Software, Nov.-Dec., 2003
[6] A Sangiovanni-Vincentelli and Grant Martin Platform-Based Design and[6] A. Sangiovanni Vincentelli and Grant Martin, Platform Based Design and Software Design Methodology for Embedded Systems, IEEE Design & Test, Vol. 18(6), November 2001.
ⓒ KAIST SE LAB 2008 34/35
Discussion
Q & A
ⓒ KAIST SE LAB 2008 35/35