Introduction to Embedded Systems Research: Speci cation

Introduction to Embedded Systems Research:Specification

Robert Dick

[email protected] of Electrical Engineering and Computer Science

University of Michigan

Fovea

Lens

Cornea

Variable Resolution

and Position Sampling

Change-Adaptive

Signalling

Spatial State

Cache

(Occipital

Place Area)

Analasys, e.g.,

Classification

Adequate

decision confidence?

Sampling Guidance

Y

N

Long-Term Memory

Decision /

Result

(b) Iterative, multi-round human vision system.

Image Signal

Processor

Application Processor

(CPU and/or GPU)

CloudDecision /

Result

(a) Conventional machine vision pipeline.

Image Sensor: typically

homogeneous RGGB or RCCC.

Demosaicing, binning,

denoising, gamma

correction, and compression.

Hardware Feature

Extraction Accelerator

or

Feature extraction on

raw captured data.

Runs CNN, LSTM or

other analysis algorithm.

May drop computation on less

important data, but already payed

Image Signal Processor transfer cost.

May render decision or (at high

energy cost) do feature extraction

and defer decision to cloud.

Minimalistic

Image Pre-Processor

Application Processor

(CPU and/or GPU)

CloudDecision /

Result

Image Sensor: capture only the

most important

data for decision accuracy.

Efficient gamma

correction

and binning.

Decide based on features.

Very high energy cost for

wireless data transfer.

Scene Cache

Capture ControllerHardware Feature

Extraction Accelerator

or

Adequate

decision confidence?

or

Y

N

Captures most relevant

and rapidly changing data.

Learns important sample locations

from prior rounds.

Maintains state built from

prior still-relevant samples.

Determine and

transmit

relevant data.

Decide based on features.

Very high energy cost for

wireless data transfer.

Issue commands to

capture important data.

(c) Goal: multi-round, energy-efficient, low-latency

continuous learning machine vision.

Feature extraction on sparse captured

data with similar distribution to processed data.

Continuously learn features and important

data based on prior captures.

1.1040

2.1041

385

2.1039

704

1.1039

36

2.1040

1734

0.1039

1

3.1040

4

4.1039

642

3.1039

4.1040

409

3.1041

396665

5.1042

108612774

5.1040

337

4.1041

10644

6.1044

117

6.1039

609

6.1045

164

6.1040

841434 723938

6.1042

209

5.1041

4 12 164

5.1045

529417

5.1044

140105 88

5.1039

154 10551 90677

7.1039

1248

7.1047

2106

7.1040

29773362 241966 22903106

6.1041

3119 1936 40

6.1047

4128 253

8.1050

4

8.1042

9.1050

24784

8.1039

89632

8.1044

2840

8.1040

1088

9.1039

10.1040

4

11.1039

957

10.1050

144

11.1040

156

10.1041

32 16

10.1047

87780

10.1045

2152

10.1039

1165

12.1040

145

13.1052

2404

12.1042

24

12.1045

33008

12.1044

8217

12.1041

8

12.1039

135427

14.1049

113

14.1040

229

13.1050

132

13.1042

74433

13.1041

17187

13.1040

2715

13.1039

170059 90

15.1040

16

15.1050

242 1225

14.1050

237

14.1042

6200

14.1041

4

14.1044

720

14.1052

20

14.1039

84 36939

16.1040

88

15.1049

6

15.1039

56

17.1054

2919

16.1050

129

16.1041

36

16.1047

49154

16.1045

2632

16.1049

27

16.1052

16

16.1039

222734

18.1048

133

18.1039

3439

18.1040

241

17.1050

16

18.1049

36 339224

17.1042

172832

17.1041

49620 448

17.1040

1376493 2883

17.1045

72

17.1044

1073

17.1049

55441826

17.1048

124 3648290

17.1052

3547

17.1039

2484110477445

17.1047

24

19.1040

72

19.1039

6 88 60631617

18.1041

28 76

18.1047

3305

18.1054

13744

20.1040

109

20.1039

269

19.1052

8

19.1047

11712

19.1049

10

19.1054

7520

21.1039

82

20.1049

5

20.1047

4896

20.1054

864

22.1040

4

22.1050

23.1040

4

22.1039

144

24.1058

3389

23.1050

76

24.1040

4

23.1042

17528

23.1041

4

23.1054

24

23.1044

6234

23.1058

261

23.1049

4

23.1052

2944

23.1039

3069658

25.1040

80

24.1050

4

24.1039

58

25.1039

26.1040

4

27.1039

489

26.1050

4

27.1040

4

26.1047

3808

26.1045

2248

26.1058

113 80

26.1049

11

26.1039

66

26.1054

840

28.1055

84266 1542

27.1042

1229

27.1041

29619

27.1058

12

27.1049

3984

27.1048

35337

29.1040

262

29.1056

164

29.1039

742

28.1050

4 2464

28.1042

2137912

29.1055

1128

28.1041

4 2633 4

28.1040

2716132 691

28.1058

24 84 32

28.1049

36176 3

28.1048

1192 48

28.1039

365 110957 24475

29.105029.104229.104129.104729.104529.105829.104929.105229.1054

2

3

4

5

6

7

8

0 1 2 3 4 5 6 7 8

Pow

er

(mW

)

Time (s)

35 40 45 50 55 60 65 70 75 80 85 90

-8 -6 -4 -2 0 2 4 6 8

-8

-6

-4

-2

0

2

4

6

8

35 40 45 50 55 60 65 70 75 80 85 90

Temperature (°C)

Position (mm)

Temperature (°C)

Topics

Number Topic11 efficient machine learning including IoT applications10 real-time systems and embedded and real-time OS10 embedded system security8 embedded processor architecture including FPGAs, GPUs,

DSPs, SIMD, and ASICs6 reliability, fault tolerance, testing, and radiation hardening6 space applications6 automotive applications4 wireless communication4 medical and wearable appl ications3 aerospace and unmanned aerial vehicles2 scheduling2 feedback control and cyber-physical systems2 computer vision

1 each industrial automation, home automation, smart grid, robotics,digital signal processing, energy harvesting, user interface anduser experience, biology sensing applications

Changes to plan: cover space applications.

SpecificationDeadlines

Software oriented design representationsHardware oriented design representationsGraph based design representationsResource descriptions

Outline

1. Specification

2. Deadlines

3 R. Dick EECS 507



Why learn about specification languages

Understand different ways of describing design to other people.

Find most appropriate language for your application.

Use for synthesis.

Use for model checking.

4 R. Dick EECS 507



Available resources – system-level

General-purpose SW processors

Digital signal processors (DSPs)

Application-specific integrated circuits

Dynamically reconfigurable hardware

E.g., field-programmable gate arrays (FPGAs)

Busses

Wireless communication channels

Wires

5 R. Dick EECS 507



Available resources – high-level

Simple arithmetic/logic units.

Multiplexers.

Registers.

Wires.

6 R. Dick EECS 507



Specification language requirements

Describe hardware (HW) and software (SW) requirements.

Specify constraints on design.

Indicate system-level building blocks.

To allow flexibility in synthesis, must be abstract.

Differentiate HW from SW only when necessary.

Concentrate on requirements, not implementation.

Make few assumptions about platform.

7 R. Dick EECS 507



Section outline

1. SpecificationSoftware oriented design representationsHardware oriented design representationsGraph based design representationsResource descriptions

8 R. Dick EECS 507



Software oriented design representations

ANSI-C.

SystemC.

Other SW language-based.

9 R. Dick EECS 507



ANSI-C

Advantages.

Huge code base.

Many experienced programmers.

Efficient means of SW implementation.

Good compilers for many SW processors.

Disadvantages.

Little implementation flexibility.

Strongly SW oriented.Makes many assumptions about platform.

Poor support for fine-scale HW synchronization.

10 R. Dick EECS 507



SystemC.

Advantages.

Support from big players.

Synopsys, Cadence, ARM, Red Hat, Ericsson, Fujitsu, InfineonTechnologies AG, Sony Corp., STMicroelectronics, and TexasInstruments.

Familiar for SW engineers.

Disadvantages.

Extension of SW language.

Not designed for HW from the start.

11 R. Dick EECS 507



Many SW language-based

Numerous competitors.

ANSI-C, C++, and Java are most popular starting points.

In the end, few can be widely used.

SystemC has broad support.

12 R. Dick EECS 507



Section outline


13 R. Dick EECS 507



Hardware oriented design representations

VHDL.

Verilog.

Esterel.

14 R. Dick EECS 507



VHDL

Advantages.

Supports abstract data types.

System-level modeling supported.

Better support for test harness design.

Disadvantages.

Requires extensions to easily operate at the gate-level

Difficult to learn

Slow to code

15 R. Dick EECS 507



Verilog

Advantages.

Easy to learn.

Easy for small designs.

Disadvantages.

Not designed to handle large designs.

Not designed for system-level.

16 R. Dick EECS 507



Verilog vs. VHDL

March 1995, Synopsys Users Group meeting.

Create a gate netlist for the fastest fully synchronous loadable 9-bitincrement-by-3 decrement-by-5 up/down counter that generated even parity,carry and borrow.

5 / 9 Verilog users completed.

0 / 5 VHDL users competed.

Does this mean that Verilog is better? Maybe, but maybe it only means that

Verilog is easier to use for simple designs.

17 R. Dick EECS 507



Esterel

Easily allows synchronization among parallel tasks.

Works above RTL.

Doesn’t require explicit enumeration of all states and transitions.

Recently extended for specifying datapaths and flexible clocking schemes.

Amenable to theorem proving.

Translation to RTL or C possible.

Commercialized by Esterel Technologies.

18 R. Dick EECS 507



Section outline


19 R. Dick EECS 507

Graph based design representations

Dataflow graph (DFG).

Synchronous dataflow graph (SDFG).

Control flow graph (CFG).

Control dataflow graph (CDFG).

Finite state machine (FSM).

Petri net.

Periodic vs. aperiodic.

Real-time vs. best effort.

Discrete vs. continuous timing.

Example from research.



Dataflow graph (DFG)

NEG

IOP

FIL

FT

DCT

3 kb

4 kb 4 kb

6 kb

3 kb

Soft DL = 230 ms

Soft DL = 150 ms

5 kbNEG

IOP

FIL

FT

DCT

3 kb

4 kb 4 kb

6 kb

3 kb

Soft DL = 230 ms

Soft DL = 150 ms

Nodes are tasks.

Edges are data dependencies.

Edges have communication quantities.

Used for digital signal processing(DSP).

Often acyclic when real-time.

Can be cyclic when best-effort.

21 R. Dick EECS 507



Dataflow graph (DFG)

NEG

IOP

FIL

FT

DCT

3 kb

4 kb 4 kb

6 kb

3 kb

Soft DL = 230 ms

Soft DL = 150 ms

5 kbNEG

IOP

FIL

FT

DCT

3 kb

4 kb 4 kb

6 kb

3 kb

Soft DL = 230 ms

Soft DL = 150 ms

Nodes are tasks.

Edges are data dependencies.

Edges have communication quantities.

Used for digital signal processing(DSP).

Often acyclic when real-time.

Can be cyclic when best-effort.

21 R. Dick EECS 507



Synchronous dataflow graph (SDFG)

2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

22 R. Dick EECS 507




2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

22 R. Dick EECS 507




2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

22 R. Dick EECS 507




2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

22 R. Dick EECS 507




2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

22 R. Dick EECS 507




2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

22 R. Dick EECS 507




2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C

22 R. Dick EECS 507




2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C2

2

1

3

6

2

A

B

C

2

2

1

3

6

2

A

B

C

22 R. Dick EECS 507



Control flow graph (CFG)

false

false true

trueif i < 2

if k = 3

240 Kb

30 Kb

387 Kb

27 Kb

j = j + 5

k = k − 1

Nodes are tasks.

Supports conditionals, loops.

No communication quantities.

SW background.

Often cyclic.

23 R. Dick EECS 507



Control dataflow graph (CDFG)

≤ 3 msfalse

false true

trueif i < 2

if k = 3

240 Kb

30 Kb

387 Kb

27 Kb

j = j + 5

k = k − 1

Supports conditionals, loops.

Supports communication quantities.

Used by some high-level synthesisalgorithms.

24 R. Dick EECS 507



Finite state machine (FSM)

1 1 0

1

0

1 0

0

00 01

1011

25 R. Dick EECS 507



Finite state machine (FSM)

input0 1

00 10 0001 01 0010 00 0111 10 00

current next

Normally used at lower levels.

Difficult to represent independent behavior.

State explosion.

No built-in representation for data flow.

Extensions have been proposed.

Extensions represent SW, e.g., co-design finitestate machines (CFSMs).

26 R. Dick EECS 507



Petri net

Graph composed of places, transitions, and arcs.

Tokens are produced and consumed.

Useful model for asynchronous and stochastic processes.

Places can have priorities.

Not well-suited for representing dataflow systems.

Timing analysis quite difficult.

Large flat graphs difficult to understand.

27 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

M/D/3/2: Markov arrival, deterministic service delay,

From A. Zimmermann’s token game demonstration.

28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Petri net

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

thinkbusy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think

busy

servers

available

servers

enter

service

waiting

processes

thinking

processesserve

think



28 R. Dick EECS 507



Periodic graphs

Some system specifications contain periodic graphs.

Can guarantee scheduling validity by scheduling to the least commonmultiple of periods.

Can also meet aperiodic specifications, however, resources will sometimes beidle.

29 R. Dick EECS 507



Periodic graphs

period = 20 msdeadline = 20 ms

3 copies


system hyperperiod = 60 ms

2 copies

time


3 copies



2 copies

time


3 copies



2 copies

time

30 R. Dick EECS 507



Periodic graphs


3 copies



2 copies

time


3 copies



2 copies

time


3 copies



2 copies

time

30 R. Dick EECS 507



Periodic graphs


3 copies



2 copies

time


3 copies



2 copies

time


3 copies



2 copies

time

30 R. Dick EECS 507



Aperiodic graphs

No precise periods imposed on task execution.

Useful for representing reactive systems.

Difficult to guarantee hard deadlines in such systems.

Possible if minimum inter-arrival time known.

31 R. Dick EECS 507

Periodic vs. aperiodic

Periodic applications.

Power electronics.

Transportation applications.

Engine controllers.

Brake controllers.

Many multimedia applications.

Video frame rate.

Audio sample rate.

Many digital signal processing (DSP) applications.

However, devices which react to unpredictable external stimuli haveaperiodic behavior

Many applications contain periodic and aperiodic components



Aperiodic to periodic

Can design periodic specifications that meet requirements posed by aperiodicspecifications.

Some resources will be wasted.

Example

At most one aperiodic task can arrive every 50 ms.

It must complete execution within 100 ms of its arrival time.

33 R. Dick EECS 507



Aperiodic to periodic

Can easily build a periodic representation with a deadline and period of50 ms.

Problem, requires a 50 ms execution time when 100 ms should be sufficient.

Can use overlapping graphs to allow an increase in execution time.

Parallelism required.

The main problem with representing aperiodic problems with periodicrepresentations is that the tradeoff between deadline and period must be

made at the time of synthesis.

34 R. Dick EECS 507



Real-time vs. best effort

Why make decisions about system implementation statically?

Allows easy timing analysis, hard real-time guarantees.

If a system doesn’t have hard real-time deadlines, resources can be moreefficiently used by making late, dynamic decisions.

Can combine real-time and best-effort portions within the same specification.

Reserve time slots

Take advantage of slack when tasks complete sooner than theirworst-case finish times

35 R. Dick EECS 507



Discrete vs. continuous timing

System-level: continuous.

Operations are not small integer multiples of the clock cycle.

High-level: discrete.

Operations are small integer multiples of the clock cycle.

Implications

System-level scheduling is more complicated. . .

. . . however, high-level also very difficult.

36 R. Dick EECS 507



Section outline


37 R. Dick EECS 507



Processing resource description

Often table-based.

Price, area.

For each task.

Execution time

Power consumption

Preemption cost

etc.

Similar characterization for communication resources.Wise to use process-based.

38 R. Dick EECS 507



Communication resource description

Can use bus-bridge based models for distributed systems.

Wireless models.

However, in the future, it will become increasingly important to base SOCcommunication model on process parameters.

39 R. Dick EECS 507



System-level representations summary

No single representation has been decided upon.

Software-based representations becoming more popular.

System-level representations will become more important.

This is still an active area of research.

40 R. Dick EECS 507



Notes on clustering and partitioning

Interdependence with architecture.

Heterogeneity’s impact on partitioning.

Applications to grid computing.

Dynamic partitioning.

41 R. Dick EECS 507



Some future direction

Can specification be so simple for some embedded application domains thatapplication experts who are not computer engineers easily do it?

What HCI, compiler, and synthesis support is required?

What impact will increasing use of machine learning in embedded systemshave on specification?

42 R. Dick EECS 507


Outline

1. Specification

2. Deadlines

43 R. Dick EECS 507


Assignments

2 February: L. Yang, H. Lekatsas, R. P. Dick, and S. Chakradhar, “On-linememory compression for embedded systems,” ACM Trans. EmbeddedComputing Systems, vol. 9, no. 3, pp. 27:1–27:30, Feb. 2010 summary.

44 R. Dick EECS 507

http://robertdick.org/publications/yang10feb.html

http://robertdick.org/publications/yang10feb.html

Documents

Introduction to Embedded Systems Research: Speci cation