Introduction to Design Verification

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1

Introduction to design verification

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2

Agenda

Why Verification? Verification Alternatives Languages for System Modeling and Verification Concluding Remarks

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Why Verification

Goal of verification !emonstrate functional correctness of a design

Attem"t to find design errors

Attem"t to sho# that design im"lements s"ecification

Im"ortance of Verification Costs of design errors can $e high

%think &'entium (loating)'oint *rror+ , -./0M12

According to 3456 verification consumes a$out /7)879 design effort in current systems design

345 :; <ergeron6 Writing =est$enches (unctional Verification of >!L Models lu#er Acade

mic 'u$lishers6 @777;

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Verification Reconvergence Model

Verification checks a &transformation+ for correctness R=L !esign and Coding Synthesis 'hysical !esign

Reconvergence Model

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Initial

Specification

Transformation

Result

Transformation

Transformation



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Verification of R=L !esign

=he Idea

Written

Specification RTL Code

RTL Coding

Verification

Written

SpecificationRTL Code

RTL Coding

Verification

Interpretation

How it works



R=L Synthesis flo#

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Verification in the design cycle

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8

=rend of Verification *ffort in the !esign Verification "ortion of design increases to any#here fr

om 07 to 879 of total develo"ment effort for the design;

Code Verify (30 ~ 40%) Synthesis P&R

Code Verify (50 ~ 80%) Synthesis P&R

Earlier

No

Verifcation methodology manual, 2008-TransEDA

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9

'ercentage of =otal (la#s

A$out 079 of fla#s are functional fla#s; Beed verification method to fi logical D functional fla#s

From Mentor presentation material, 2003

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10

Some more interesting stats EE;;

Another recent inde"endent study sho#ed that more than half of all chi"s reFuire one or more re)s"in

s6 and that functional errors #ere found in /.9 of t

hese re)s"ins; With increasing chi" com"leity6 this situation could

#orsen;

Who can afford that #ith H 4M !ollar BR* cost?

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11

<ug (iing Cost in =ime

Cost of fiing a $ug"ro$lem increases as design "rogresses; Beed verification method at early design stage

Behaviora

lDesign

RTL

Design

Gate

LevelDesign

Device

Production

Cost of Fixing

a Proble

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=est$ench <asic $uilding $lock

A test$ench is >!L code to verify a module A""ly in"ut vectors to module in"uts

Check module out"uts

Re"ort errors to user

Why use a test$ench ? 'orta$ility ) test$ench #ill #ork on any >!L simulator

Automatic checking ) donJt have to inter"ret #aveform

*"ressa$ility ) can use the full semantics of >!L to generate in"ut vectors %"ossi$ly from in"ut file2

check out"ut vectors control simulation

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Sim"le >!L =est$ench

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Module Instance:

Device

Under

Verification

(DUV

Testbench Module



Com"aring a""roaches

Visual ins"ection Knly "ractical for small designs

Automatic su""ort timing diagram editor

Kut"ut com"arison

*ffective #hen a good reference model is availa$le sed $y ASIC foundries ) &Gold+ vectors are legal definition o

f a &functional+ chi"

Kut"ut checking Most difficult to code

Mandatory for large designs

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=est$ench A""roaches )Visual Ins"ection

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Device

under

Verification

(DUV

Stimulus

!enerator

Test"enc# $ile

Waveform Vie%er

&R

Te't &utput



=est$ench A""roaches

Kut"ut Com"arison

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Device

under

Verification

(DUV

Test"enc# $ile

Reference

Model

Stimulus

!enerator

&utput

Comparator

rror)Status

Messages

*!old+

Vectors



=est$ench A""roaches

Self)Checking

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Device

under

Verification

(DUV

Stimulus

!enerator

&utput

Signals

Input Signals

Test"enc# $ile

&utput

C#ec,er

rror)Status

Messages



What a test$ench is su""osed to do?

Self)checking test$enches Identify im"ortant features

Create conditions that test these features

Check conditions

Write message #hen error occurs

&Insert+ errors to demonstrate #hen self)check fails

=est for varying values of all "ossi$le in"ut values

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19

Com"letion Metrics >o# do #e kno# #hen the verification is done?

*motionally or Intuitively Kut of money? *hausted?

Com"eting "roduct is there;

Soft#are "eo"le are ha""y #ith your hard#are;

=here have $een no $ugs re"orted for t#o #eeks;

More rigorous criteria All tests "assed

(unctional Coverage

Code Coverage

<ug Rates have flattened to#ard $ottom;

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20

Agenda

Why Verification ? Verification Alternatives

Simulation Emulation Prototyping Formal verification Semi-Formal verification

Languages for System Modeling and Verification Concluding Remarks

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21

Kvervie# of Verification Methodologies

Simulation

Hardware Accelerated

Simulation

Emulation

Formal

Verification

Semi-formal

Verification

Prototyping

F a s t e r s p

e e d, c l o s

e r t o f i n a

l p r o d u c t

B i g g e r c o v e r a g e

Basic

verification

tool

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22

Soft#are Simulation

!ynamic verification method <ugs are found $y running the design im"lementatio

n; =horoughness de"ends on the test vector used;

Some "arts are tested re"eatedly #hile other "arts are not even tested;

a = 1;

#20 b = 1;

$display (“status is = %d”,c);

...

Testbench DUV

So!e "art of

the desi#n is

tested

re"eatedly$

ther "arts

are not een

tested$

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25

Soft#are Simulation

'ros =he design siNe is limited only $y the com"uting re

source; Simulation can $e started as soon as the R=L descri

"tion is finished; Set)u" cost is minimal;

Cons

*low +1233 c!cles'sec, 4 *&eed ga& between

the s&eed of software siulation and realsilicon widens0 +*iulation s&eed 5 si-e ofthe circuit siulated ' s&eed of the siulationengine,

The designer does not exactl! know howuch &ercentage of the design have been12/17/15



26

*mulation

Imitating the function of another system to achieve the same results as the imitated system;

sually6 the emulation hard#are com"rises an array of ('GAOs %or s"ecial)ty"e "rocessors2 and interconnect

ion scheme among them; A$out 4777 times faster than simulation;

Simulation

Hardware

Accelerated

Simulation

EmulationPrototyping

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27

*mulation

ser logic design is ma""ed to emulation $oard #ithmulti"le ('GAOs or s"ecial "rocessors;

=he emulation $oard has eternal interconnection hard#are that emulates the "ins of final chi";

-

-

.

/

Logic design Emulation hardware with multiple FPGAs

Design

mapping

Eternal pins12/17/15



28

'rototy"ing

'ros >igher %than emulation2 clock rate %over 4M cycles

sec2 due to s"ecific design of "rototy"ing $oard; Com"onents as #ell as the #iring can $e customiN

ed for the corres"onding a""lication; Can $e carried along; %>ard#are *mulation? (orge

t it12 Cons

Bot flei$le for design change

%*very ne# "rototy"e reFuires a ne# $oard architecture; *ven a small change reFuires a ne# 'C<;2

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29

Kvervie# of Verification Methodologies

(ormal verification A""lication of logical reasoning to the develo"ment of digita

l system

<oth design and its s"ecification are descri$ed $y a languagein #hich semantics are $ased on mathematical rigor;

Semi)formal verification Com$ination of simulation and formal verification;

(ormal verification cannot fully cover large designs6 and simulation can come to aid in verifying the large design;

Simulation Formal

Verification

Semi-formal

Verification

More complete verification

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30

(ormal Verification

K$Pective Check "ro"erties of model #ith all "ossi$le conditions

'ros Assures 4779 coverage;

(ast;

Cons Works only for small)siNe finite state systems;

ncomforta$le due to culture difference %*;g;6 engineers arenot familiar #ith the use of tem"oral logic used for &"ro"erty

+ descri"tion in Model Checking2

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31

(ormal Verification *Fuivalence Checker

*Fuivalence checker com"ares the golden model #ith the refinedmodel;

(unctional re"resentations are etracted from the designs and com"ared mathematically;

'ros

*haustive design coverage Very fast Cons

Memory e"losion =ools such as L*C %Ver"le26 (ormality %Syno"sys26 (ormal'ro %Me

ntor2 su""orts *Fuivalence checking;

Golden

Model

efined

Model!"

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32

Semi)(ormal Verification ) Assertion

Assertion)$ased verification %A<V2 &Assertion+ is a statement on the intended $ehavior of a desi

gn;

=he "ur"ose of assertion is to ensure consistency $et#een the designerOs intention and the im"lementation;

ey features of assertions 4; *rror detection If the assertion is violated6 it is detected $

y the simulator;

@; *rror isolation =he signals related to the violated assertion are identified;

Q; *rror notification =he source of error is re"orted to the user;

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*am"le of assertion)$ased $ug detection

PC' * Controller

PC'

eent desel +if (,R*E-0) ./$$4

(EVSE1-0)

assert(desel)2

'dentify si#nals related tothe iolated assertion

deselassertion isiolated

Re"ort to the6ser

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34


Simulation uality of assertion)$ased verification

0

u m " e r o f " u g

s f o u n d

Time1 ffortSetup

test"enc#Descri"e

assertions

$ormal verification

Simulation

Simulation %it# assertionsfficienc2 of

assertion

By IBM in “Computer-Aided Verification” 2000

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35

Semi)(ormal Verification ) Coverage

Coverage)directed verification Increase the "ro$a$ility of $ug detection $y checking the Fual

ityO of stimulus

sed as a guide for the generation of in"ut stimulus

Test 3lan

(Coverage

DefinitionDirectives

Random

Test

!enerator Test Vectors

SimulationCoverage

anal2sis

Coverage

Reports

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36


Coverage metrics for coverage)directed verification Code)$ased metrics

Linecode $lock coverage

<ranchconditional coverage

'ath coverage

Circuit structure $ased metrics =oggle coverage

Register activity

State)s"ace $ased metrics 'air)arcs usually covered $y Line T condition coverage

(unctional coverage metrics 9 of s"ecification items satisfied

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37


Coverage Checking tools VeriCover %Veritools2

SureCov %Verisity2

Coverscan %Cadence2

>!LScore6 VeriCov %Summit !esign2

>!LCover6 VeriSure %=rans*!A2

'olaris %Syno"sys2

Covermeter %Syno"sys2

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38

Semi)(ormal Verification

'ros !esigner can measure the coverage of the test environment

as the formal "ro"erties are checked during simulation;

Cons =he simulation s"eed is degraded as the "ro"erties are check

ed during simulation;

Challenges =here is no unified test$ench descri"tion method;

It is difficult to guide the direction of test vectors to increase

the coverage of the design; !evelo"ment of more efficient coverage metric to re"resent

the $ehavior of the design;

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39

S"eed Com"arison

! "H#

Soft%are

Simulation

$! "H#

$%H#

4ard%are5

6ccelerated

Simulation

(from

7uic,turn)D2nalit#3resentation

4ard%are

emulation

(from 7uic,turn

presentation

$!!"H#

&!!'H#

$!!H#

$!! "H#

Speed (C2cles)sec1 log scale

$!%H#$($!%H#

3rotot2ping Semi5formal

(6ssertion5

"ased

verification

&!-)!H#

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40

!esign Com"leity

Gate counts Coents

*iulation'*ei"foral veri%cation

$nliited

#ulation'Hardwar

e"acceleratedsiulation

261276 gates De&ends on the

nuber of FPG(/s inthe architecture

Protot!&ing 26186 gates De&ends on theco&onents on theboard

Foral veri%cation 9 23: gates Liited to about 833)i&")o&s due to stateex&losion

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41

Verification =ime vs; Coverage

Coverage

Verification Time

Si!6lation

Se!i7for!al

Prototy"in#

E!6lation*99elerated si!6lation

Si!6lation set6"

Se!i7for!alset6"

E!6lationset6" Prototy"in# set6"

Redire9tionoftest:en9h9onstraints

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42

Agenda

Why Verification ? Verification Alternatives Languages for System Modeling and Verification

System modeling languages

=est$ench automation D Assertion languages Concluding Remarks

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43

Language >eritage for SoC !esign

Be# languages are develo"ed to fill the "roductivity ga";

Verilog

VHDL

*

*++

,AVA

AssemlySystem*

SystemVerilogVera

.est/uilder

Language for

Software development

Language for

ardware test

Language for

ardware description

Schematic

#ast present12/17/15

F$t$re

S t ! i ti L S



44

System !escri"tion Languages SummaryLanguge Pros Cons

C'C;; • #as! to write testvectors'environent

•$nable to handle soehardwareenvironents0

HDL

+<erilog=<HDL,

•Failiarit!

•#as! to describe H'>designs

•Focuses on the lower"

level designs0• ?&ro&er for s!steodeling0

*!steC •#asil! connected toC'C;; codes0

•#as! to odel s!stebehaviors0

•Liited tools+siulation= s!nthesis=

etc0,

*!ste<erilog

•#as! to learn for theHDL designers0

•#as! to odel s!ste

behaviors0

•Few tools +siulation=s!nthesis= etc0,

•*ubset su&&ort12/17/15



45

ASIC Verification Methods

Running Speed

10Hz

100Hz

1KHz

10KHz

100KHz

1MHz

10MHz

100MHz

SW Simulator

Investment

HW Emulator

Rapid Prototype

Real Silicon

HW Accelerator

Ideal eri!ication

Solution

6ake it faster

6ake it chea&er

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46

Kverall (unctional Verification (lo#

RTL Simulation

S2nt#esis

!ate Level

Simulation

4ard%are

mulation

Verification Completed

Microcode

Description

6rc#itecture Define

RTL Description

(Verilog 4DL

Microcode

Verifier

For version

control

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47

Concurrent Verification

arl2 to

Mar,et88

Design Code S2stem

IntegrationSW

Design 9uild

Design $a"

4W

C4I3 De"ug

4ard%are

Integration De"ug

De"ug

Wit#out mulation

9ac,

annotation Time

Wit# mulation

SW

Design $a"

4W

C4I3

C#ipDe"ug

4W emulation

4W integration- 4W De"ug

S2s integration- SW De"ug

$inal

Integration De"ug

Seuential

Verification

Concurrent

Verification

9ac, annotation

Design Code

Design 9uild

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48

Agenda

Why Verification ? Verification Alternatives Languages for System Modeling and Verification Concluding Remarks

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49

Concluding Remarks

Verification is challenging It needs strategy1 Strategy is to a""ly each method #hen a""ro"riate; Verify as early as "ossi$le Catch the $ug #hen it is small and still

isolated in a smaller region; %!onOt #ait until it gro#s and kills you;2

4st

ste" A""ly formal methods Static formal verification

Assertion)$ased verification

@nd ste" Coverage driven verification aids in $ringing closure Code and functional coverage 6 if not covered design doesnOt #ork 11

Selecting the "ro"er verification methodology Qrd ste" *mulate design

*mulate I' o"eration in ('GA

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50

Concluding Remarks

'o#erful de$ugging features handling $oth hard#are "art and soft#are "art are reFuired; Language6 =ool!ata Interfaces need standardiNation; !(V %!esign for Verification2 Uou lose in the $eginning6 $ut #ill

#in later6 like !esign for Reuse;

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51

=hank Uou11

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52

uestions ???

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53

A""endices

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54

!e$ugging !esign in the ('GA

*m$ed logic analyNer #ith user design in *!I( format Logic to store "re)registered signals into the "ro$ing memory;

Logic for trigger condition generation;

=riggering condition is dynamically configured;

Internal node etraction Sometimes the designer #ants to #atch internal nodes in the

design;

Internal node "ro$ingena$les this $y#iring)out the internalnodes to the $oundaryof the != to" $lock;

D$TBuilt"?nLogic

(nal!-er

;o" :lo9<

S6:7:lo9<

'nternal node

#xternalDu&

6eor!B?L(= D!nalith *!stes12/17/15



55

R=L !e$ugging (eature

*mulation is $ased on gate)level netlist; Gate)level netlist generated from the synthesis tools h

as too com"le name styles difficult to trace manually; =echniFues to resolve R=L sym$ol names from the gat

e)level sym$ol names and to "rovide de$ugging enviro

nment in R=L name s"aces is reFuired; Insert R=L instrumentation I' for de$ugging

!esign flo# Read R=L design %Verilog6 V>!L2 Generate instrumented R=L design %s"iced #ith triggering and d

um" logic2 Synthesis Com"ile %ma""ing D 'AR2

!iaLite %=emento26 Identify %Syn"licity2

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56

R=L !e$ugging (eature

Instrumentation I's for de$ugging logic $locks ma""ed into ('GAs; =rigger

Logic *Fuation Module

>istory Register

=ransaction Register

Random Generator

=raffic AnalyNer

Instrumentation I's are

interconnected tosu""ort variousconfigurations;

Structures of the !TL design

"nterconnection of instrumentation "#s

DiaLite fro Teento12/17/15



57

Connecting Actual Chi" to the Simulator

<uilding a correct and fast reference model for the hard#are is very difficult;

% se the actual discrete chi"for the I' %or ('GA2;

Control the clock signal to the

actual chi" %or ('GA26 i;e6slo# do#n andsynchroniNe #ith the >W simulatorand SW de$ugger in the host machine;

A""lication ('GA "rototy"ing >WSW co)verification Silicon validation

from &im#'(

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58

Micro"rocessor !esign Verification Methodology

Instruction

9e#avior

In C

(3olaris

Micro5

arc#itecturein C

RT5Level

in Verilog

!ate5Level

in Verilog

Real

Mot#er5"oard

4)W

Virtual 3C in C language

(V3C

C Language

Peripherals

HDL

6C< @ 6icrocode <eri%er PL? @ Prograing Language

?nterface

more refined model

MCV$le'3CVirtual C#ip Using

3LI

CPU

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59

'rototy"ing

S"ecial %more dedicated and customiNed2 hard#are architecture made to fit a s"ecific a""lication;

Simulation

Hardware

Accelerated

Simulation

Emulation

Prototyping

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A 'rototy"ing *am"le

'rototy"e of .)'ort Giga$it *thernet S#itch =#o ilin Virte)* @7

77 ('GAs are on ('G

A $oard; (our ('GA $oards are

used;

'rocessor $oard contains 'CI $ridge and M

'C87 micro"rocessor;

#C" bridge

$#C%&'

microprocessor

(ilin) F#*+

Switch board

#rocessor board

Courtes of #aion, "nc-

Documents

Introduction to Design Verification