Introduction to AVR - Milwaukee School of Engineering€¢Atmel architected microcontroller core •AVR has no specified meaning •RISC Instruction Set •Harvard memory architecture

Introduction toAVR

2 © tjEE 2920 – Fall 2016

Introduction to the AVR

• AVR• Atmel architected microcontroller core

• AVR has no specified meaning

• RISC Instruction Set

• Harvard memory architecture

• 8 and 32 bit variants

• Created in 1996

• ATmega328• AVR based

• 32KBytes of Flash Memory

• 8 bit version of AVR

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• ATmega Block Diagram• AVR based CPU

• 8 bit version

for this class

8 or 32 bit CPU

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• ATmega Block Diagram

• Harvard Memory Architecture

• 32KBytes of Flash

• 2KBytes of SRAM

• EEPROM optional32KBytes

2KBytes

Some versions Include EEPROM

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• ATmega Block Diagram• Clock and Power Management

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• Timer / Capture Blocks

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• Analog Comparator

• A/D Converter

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• Communications• USART

• SPI

• TWI

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• I/O Ports

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• AVR Core Block Diagram• ALU – Arithmetic Logic Unit

• Does the actual calculation

• Add, compare, increment, …

• Register File• 32 registers

• Used as inputs and outputs

for the ALU

• Instruction Decode

• Program Counter (PC)

• Status / Control

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• Program Memory• Flash Memory

• 16 bit words

• 32KBytes --> 16K words• 16,383 words

• A section is reserved for a boot loader• Used to load the application program

• Special overwrite protection

• Fuse programmable

0x0000

0x3FFF

16 bits

Boot Section

Application Section

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• Memory Operations

• AVR is “Little Endian”• Least significant byte is at least address of

the word

• e.g 16 bit word 0x2FE3

• Some processors are “Big Endian”• Most significant byte is at least address of

the word

• e.g. 32 bit word 0x2FE3

Memory

Address

(Hex)

Data

Value

. . .

1FFF

2000 2F

2001 E3

2002

2003

2004

. . .

Memory

Address

(Hex)

Data

Value

. . .

2004

2003

2002

2001 E3

2000 2F

1FFF

. . .

Memory

Address

(Hex)

Data

Value

. . .

1FFF

2000 E3

2001 2F

2002

2003

2004

. . .

Memory

Address

(Hex)

Data

Value

. . .

2004

2003

2002

2001 2F

2000 E3

1FFF

. . .

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• Data Memory• SRAM

• 8 bit words

• 32 General purpose registers

• 64 I/O registers

• Space for 160 external I/O registers

• 2KBytes of Data RAM• 2,048 bytes

• Stack• Starts at the bottom of the Data RAM

• Increases upwards (lower addresses)

• Dedicated Stack Pointer

• Points to next available space on the stack 8 bits

0x0000

0x0060

0x0020

0x0100

0x08FF

Internal SRAM2048 Bytes

160 Ext I/O Reg.

64 I/O Registers

32 Registers

Stack

Data

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• Data Memory

• 2 clock cycle data access

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EEPROM1024 Bytes


• Non-Volatile Memory• EEPROM

• 8 bits wide

• 1KBytes • 1,024 bytes

• Separate memory space

• Only accessible with special instructions

• Long R/W times

8 bits

0x0000

0x03FF

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• Memory Map

• Each memory resides in a different address space

Program Memory Data Memory Non-volatile Memory

16K words(32K bytes)

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• Program Counter• Points to the NEXT instruction to be executed

• Used as the address for the next fetch

• 14 bits wide for the ATmega328• 16K words 14 bit addresses

• In most situations increments by 1

• In branch, jump, interrupt situations the PC is modified to point to the new location

• This is a separate register and does not have a memory map address

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• CPU Register File• 32 General purpose registers

• 8 bit wide

• Single clock cycle ALU action• Read, execute, write back (to the register file) in a single clock

cycleBit 7 6 5 4 3 2 1 0

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• Address Pointers (internal memory)• 3 sets of 2 registers can be concatenated to form

address pointers• R27 + R26 X register

• R29 + R28 Y register

• R31 + R30 Z register

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• Stack Pointer• The Stack is used to store data temporarily

• Return address for a subroutine

• Original state of a register when being re-used in a subroutine

• Special instructions used to access the stack

• LIFO – Last In First Out configuration

• Stack Pointer (register) points to the NEXT available location

• Register is located in the I/O section of the Data Memory Map

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• Status Register• SREG

• 8 bit

• Each bit identifies a status of the processor

• Updated after each execution cycle

• Register is located in the I/O portion of the Data Memory Map

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• Status Register• Bit 0 – C (carry)

• Indicates a “carry” was generated in the previous operation

• Bit 1 – Z (zero)• Indicates if the result from the previous operation was zero

• Bit 2 – N (negative)• Indicates if the result from the previous operation was negative

• Bit 3 – V (overflow)• Indicates an “overflow” occurred in the previous operation

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• Status Register• Bit 4 – S (sign)

• Indicates the sign of the previous operation

• S = N V

• Bit 5 – H (half-carry)

• Indicates a half-carry occurred in the previous operation b3 b4

• Used in BCD operations

• Bit 6 – T (bit copy)• Used by the BST and BLD instructions as the destination or source

• Bit 7 – I (global interrupt enable flag)• Enables/Disables interrupts at the global level

• Set / cleared by SEI, CLI instructions

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• The CPU is driven by the CPU clock clkCPU

• 2 stage pipeline• Fetch / Execute

• Single cycle execution on register operations

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• Interrupts (and Reset)• External and internal• Each interrupt has an associated interrupt vector

• Location in program memory which holds the address to jump to, to service the interrupt

• Each interrupt will clear the I enable flag – to prevent nested interrupts• This can be over-ruled by writing to the I enable flag

• On an interrupt• I flag is cleared and the specific interrupt flag is set• PC is pushed on the stack• The interrupt vector is loaded into the PC• Whatever processing desired is done (need to reset the I flag at

end)• When complete – old PC is pop’d from the stack• Execution resumes

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• Interrupts (and Reset)

• Priority set by location – highest priority first

• 4 clock overhead

to get in to or out

of an interrupt

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Interrupt Process

Normal execution

Address Instruction

(hex) (hex)

0000 01EA

0002 01A2

0004 0032

0006 0386

0008 006C

000A 020B

000C 0213

. . .

0110 018E

0112 00D4

0114 0006

0116 00E1

. . .

02DC 032E

02DE 0030

02E0 007E

02E2 03C2

02E4 0338

02E6 0226

02E8 0209

02EA 01E6

PC

SP

(hex) (hex)

0000 D5

0001 D4

0002 3F

…

0100 32

0101 A5

0102 7C

0103 33

…

08FB xxxx

08FC xxxx

08FD xxxx

08FE BC

08FF F7

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Interrupt Process

Normal execution

Address Instruction

(hex) (hex)

0000 01EA

0002 01A2

0004 0032

0006 0386

0008 006C

000A 020B

000C 0213

. . .

0110 018E

0112 00D4

0114 0006

0116 00E1

. . .

02DC 032E

02DE 0030

02E0 007E

02E2 03C2

02E4 0338

02E6 0226

02E8 0209

02EA 01E6

PC

SP

(hex) (hex)

0000 D5

0001 D4

0002 3F

…

0100 32

0101 A5

0102 7C

0103 33

…

08FB xxxx

08FC xxxx

08FD xxxx

08FE BC

08FF F7

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Interrupt Process

Beginning of Interrupt

Address Instruction

(hex) (hex)

0000 01EA

0002 01A2

0004 0032

0006 0386

0008 006C

000A 020B

000C 0213

. . .

0110 018E

0112 00D4

0114 0006

0116 00E1

. . .

02DC 032E

02DE 0030

02E0 007E

02E2 03C2

02E4 0338

02E6 0226

02E8 0209

02EA 01E6

(hex) (hex)

0000 D5

0001 D4

0002 3F

…

0100 32

0101 A5

0102 7C

0103 33

…

08FB xxxx

08FC 01

08FD 14

08FE BC

08FF F7

PC

SP

SP

PC

Set specific interrupt flagClear global interrupt flag

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Interrupt Process

Interrupt Vector

(jsr)

Address Instruction

(hex) (hex)

0000 01EA

0002 01A2

0004 0032

0006 0386

0008 006C

000A 020B

000C 0213

. . .

0110 018E

0112 00D4

0114 0006

0116 00E1

. . .

02DC 032E

02DE 0030

02E0 007E

02E2 03C2

02E4 0338

02E6 0226

02E8 0209

02EA 01E6

(hex) (hex)

0000 D5

0001 D4

0002 3F

…

0100 32

0101 A5

0102 7C

0103 33

…

08FB xxxx

08FC 01

08FD 14

08FE BC

08FF F7

SP

PC

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Interrupt Process

Interrupt Vector

(jsr)

Address Instruction

(hex) (hex)

0000 01EA

0002 01A2

0004 0032

0006 0386

0008 006C

000A 020B

000C 0213

. . .

0110 018E

0112 00D4

0114 0006

0116 00E1

. . .

02DC 032E

02DE 0030

02E0 007E

02E2 03C2

02E4 0338

02E6 0226

02E8 0209

02EA 01E6

(hex) (hex)

0000 D5

0001 D4

0002 3F

…

0100 32

0101 A5

0102 7C

0103 33

…

08FB xxxx

08FC 01

08FD 14

08FE BC

08FF F7

SP

PC

PC

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Interrupt Process

Interrupt Service Routine

(ISR)

Address Instruction

(hex) (hex)

0000 01EA

0002 01A2

0004 0032

0006 0386

0008 006C

000A 020B

000C 0213

. . .

0110 018E

0112 00D4

0114 0006

0116 00E1

. . .

02DC 032E

02DE 0030

02E0 007E

02E2 03C2

02E4 0338

02E6 0226

02E8 0209

02EA 01E6

(hex) (hex)

0000 D5

0001 D4

0002 3F

…

0100 32

0101 A5

0102 7C

0103 33

…

08FB xxxx

08FC 01

08FD 14

08FE BC

08FF F7

SP

PC

33 © tjEE 2920 – Fall 2016


Interrupt Process

Interrupt Service Routine

(ISR)

Address Instruction

(hex) (hex)

0000 01EA

0002 01A2

0004 0032

0006 0386

0008 006C

000A 020B

000C 0213

. . .

0110 018E

0112 00D4

0114 0006

0116 00E1

. . .

02DC 032E

02DE 0030

02E0 007E

02E2 03C2

02E4 0338

02E6 0226

02E8 0209

02EA 01E6

(hex) (hex)

0000 D5

0001 D4

0002 3F

…

0100 32

0101 A5

0102 7C

0103 33

…

08FB xxxx

08FC 01

08FD 14

08FE BC

08FF F7

SP

PC

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Interrupt Process

Return from Interrupt

(Reti)

Address Instruction

(hex) (hex)

0000 01EA

0002 01A2

0004 0032

0006 0386

0008 006C

000A 020B

000C 0213

. . .

0110 018E

0112 00D4

0114 0006

0116 00E1

. . .

02DC 032E

02DE 0030

02E0 007E

02E2 03C2

02E4 0338

02E6 0226

02E8 0209

02EA 01E6

(hex) (hex)

0000 D5

0001 D4

0002 3F

…

0100 32

0101 A5

0102 7C

0103 33

…

08FB xxxx

08FC 01

08FD 14

08FE BC

08FF F7

SP

PC

PC

SP

Set global interrupt flag

35 © tjEE 2920 – Fall 2016


Interrupt Process

Normal Execution

Address Instruction

(hex) (hex)

0000 01EA

0002 01A2

0004 0032

0006 0386

0008 006C

000A 020B

000C 0213

. . .

0110 018E

0112 00D4

0114 0006

0116 00E1

. . .

02DC 032E

02DE 0030

02E0 007E

02E2 03C2

02E4 0338

02E6 0226

02E8 0209

02EA 01E6

(hex) (hex)

0000 D5

0001 D4

0002 3F

…

0100 32

0101 A5

0102 7C

0103 33

…

08FB xxxx

08FC 01

08FD 14

08FE BC

08FF F7

PC

SP

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• Instruction Format• Constant width instruction format – 16 bits

• Opcode (Operand1) (Operand2) (Operand3) (Opcodecont’d)• Where each field is instruction dependent

• Field size/location is not fixed

• Examples:

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instruction

0 0 0 0 0 0 0 1 d d d d r r r r MOVW Move register pair

1 0 0 1 0 1 0 d d d d d 1 0 1 0 DEC Rd

1 0 0 1 1 1 r d d d d d r r r r MUL, unsigned: R1:R0 = Rr×Rd

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• Addressing Modes• Define the way operands are accessed• Allows for pointers, loops, indexing, …• Modes

• Direct• Register Direct – 1 and 2 register

• Data Direct

• I/O Direct

• Indirect• Data Indirect

• Data Indirect with displacement• Data Indirect Pre-increment

• Data Indirect Pre-decrement

• Program Memory• Constant addressing

• Direct addressing

• Indirect addressing• Relative addressing

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• Register Direct• Single Register

• Directly identifies the register to operate on

• Examples:

inc R14

dec R5

clr R21

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• Register Direct• Two Register

• Directly identifies the registers to operate on

• Results are returned to register Rd

• Examples:

cp R6, R14

add R14,R15

mov R15,R6

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• I/O Direct• Directly identifies the registers to operate on

• Directly identifies the I/O register

• These do not work on the ATmega328

• Examples:

in R0, PORTB

out PORTD, R1

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• Data Direct• 2 word instruction

• Directly identifies the register

• Directly identifies the data memory location

• Examples:

lds R1, 0x103A

sts 0x123F, R12

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• Data Indirect• Directly identifies the register• Operand (memory) address is calculated

• X, Y or Z register

• Examples:

ld R0, Xst Z, R5

X = 3A23, [3A23] = FFld R0, XR0 [ 3A23 ] R0 = FF

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• Data Indirect with Pre-Decrement• Directly identifies the register• Operand (memory) address is calculated

• register X,Y,Z value is decremented• value in X, Y or Z register

• Examples:

ld R0, -Xst -Z, R5

X = 3A23, [3A22] = AAld R0, -XR0 [ 3A23 - 1 ] = [3A22]R0 = AA and X = 3A22

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• Data Indirect with Post-Increment• Directly identifies the register• Operand (memory) address is calculated

• value in X, Y or Z register • register X,Y,Z value is incremented

• Examples:

ld R0, X+st Z+, R5

X = 3A23, [3A23] = FFld R0, -XR0 [ 3A23 ] R0 = FF and X = 3A24

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• Data Indirect with Displacement• Directly identifies the register• Operand (memory) address is calculated

• Y or Z register + specified address (q)

• Examples:

ldd R10, Y+29std Z+18, R5

Y = 3A23, [3A40]=FDldd R10, Y+29R10 [ 3A23 + 1D ] = [3A40]R10 = FD

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• Program Memory Constant Addressing• Directly identifies the register• Z register points to a byte in program memory

• bits 15-1 identify the memory address• bit 0 identifies the byte (1 – high byte, 0 – low byte)

• Examples:

lpm R0, Zsp Z, R5

Z = 3A21 = 0011 1010 0010 0001program address 1D10 contains 3FF2lpm R0, ZR0 = 3F

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• Program Memory with Post-Increment• Directly identifies the register• Z register points to a byte in program memory

• bits 15-1 identify the memory address• bit 0 identifies the byte (1 – high byte, 0 – low byte)• After access, Z register is incremented

• Examples:

lpm R0, Z+

Z = 3A21 = 0011 1010 0010 0001program address 1D10 contains 3FF2lpm R0, Z+R0 = 3F, Z = 3A22

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• Direct Program Addressing• 2 word instruction

• Identifies the value to be placed in the PC

• supports up to 4Mwords

• Examples:

jmp 0x2F2E

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• Indirect Program Addressing• Value from Z register is placed in the PC

• Examples:

ijmp

note : PC(21:16)=0

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• Relative Program Addressing• 12 bit value is added to the PC + 1 PC **

• Examples:

rjmp 0x2Erjmp loop

note: 12 bit relative -2048 to 20470x800 to 0x7FF

Documents

Introduction to AVR - Milwaukee School of Engineering€¢Atmel architected microcontroller core •AVR has no specified meaning •RISC Instruction Set •Harvard memory architecture