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Introduction

ManufacturingManufacturingProcessProcess

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What is a Semiconductor?

Low resistivity => “conductor” High resistivity => “insulator” Intermediate resistivity => “semiconductor”

conductivity lies between that of conductors and insulators generally crystalline in structure for IC devices

In recent years, however, non-crystalline semiconductors have become commercially very important

polycrystalline amorphous crystalline

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Semiconductor Materials

Gallium(Ga)

Phosphorus(P)

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Silicon

Si has four valence electrons. Therefore, it can form covalent bonds with four of its nearest neighbors.

When temperature goes up, electrons can become free to move about the Si lattice.

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Doping (N type)

Si can be “doped” with other elements to change its electrical properties.

For example, if Si is doped with phosphorus (P), each P atom can contribute a conduction electron, so that the Si lattice has more electrons than holes, i.e. it becomes “N type”:

Notation:n = conduction electron concentration

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Doping (P type)

If Si is doped with Boron (B), each B atom can contribute a hole, so that the Si lattice has more holes than electrons, i.e. it becomes “P type”:

Notation:p = hole concentration

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CMOS Process

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A Modern CMOS Process

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

Dual-Well Trench-Isolated CMOS ProcessDual-Well Trench-Isolated CMOS Process

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Circuit Under Design

VDD VDD

Vin Vout

M1

M2

M3

M4

Vout2

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Its Layout View

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The Manufacturing Process

For a great tour through the IC manufacturing process and its different steps, checkhttp://www.fullman.com/semiconductors/semiconductors.html

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Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-light

Patternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch

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oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

Photo-Lithographic Process

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CMOS Process at a Glance

Define active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

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CMOS Process Walk-Through

p+

p-epi (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epiSiO2

3SiN

4

(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)

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CMOS Process Walk-ThroughSiO2

(d) After trench filling, CMP planarization, and removal of sacrificial nitride

(e) After n-well and VTp adjust implants

n

(f) After p-well andVTn adjust implants

p

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CMOS Process Walk-Through

(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+ source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2

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CMOS Process Walk-Through

(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO2insulator, etching of via’s,

deposition and patterning ofsecond layer of Al.

AlSiO2

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Advanced Metallization

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Advanced Metallization

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Implantation Diffusion implantation:

The wafers are placed in a quartz tube embedded in a heated furnace.

A gas containing the dopant is introduced in the tube. The high temperatures of the furnace, typically 900 to 1100 °C, cause the dopants to diffuse into the exposed surface both vertically and horizontally.

Ion implantation: Dopants are introduced as ions into the material. The ion implantation system directs and sweeps a beam of purified

ions over the semiconductor surface. The acceleration of the ions determines how deep they will penetrate

the material, while the beam current and the exposure time determine the dosage.

The ion implantation method allows for an independent control of depth and dosage.

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Deposition Oxidation:

The wafer is exposed to a mixture of high-purity oxygen and hydrogen at approximately 1000°C.

The oxide is used as an insulation layer and also forms transistor gates.

Chemical vapor deposition (CVD): CVD uses a gas-phase reaction with energy supplied by

heat at around 850°C. silicon nitride (Si3N4) ,Polysilicon,

Sputtering: The aluminum is evaporated in a vacuum, with the heat for

the evaporation delivered by electron-beam or ion-beam bombarding.

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Etching Wet etching:

It uses many types of acid, base and caustic solutions to remove a material.

For instance, hydrofluoric acid buffered with ammonium fluoride is typically used to etch SiO2.

Dry or plasma etching: A wafer is placed into the etch tool's processing chamber and given

a negative electrical charge. The chamber is heated to 100°C and brought to a vacuum level of

7.5 Pa, It then filled with a positively charged plasma (usually a mix of

nitrogen, chlorine and boron trichloride). The opposing electrical charges cause the rapidly moving plasma

molecules to align themselves in a vertical direction, forming a microscopic chemical and physical “sandblasting” action which removes the exposed material.

It creates patterns with sharp vertical contours.