INTRODUCTION - Caxapacaxapa.ru/thumbs/225950/B_Design_Considerationsrev6.pdf · 2020-02-17 · to the faster families such as LSTTL. This meant sacrificing the best qualities of CMOS

MOTOROLA High–Speed CMOS Logic DataDL129 — Rev 6

2–1

INTRODUCTION

CMOS devices have been used for many years in applica-tions where the primary concerns were low power consump-tion, wide power–supply range, and high noise immunity.However, metal–gate CMOS (MC14000 series) is too slowfor many applications. Applications requiring high–speed de-vices, such as microprocessor memory decoding, had to goto the faster families such as LSTTL. This meant sacrificingthe best qualities of CMOS. The next step in the logic evolu-tion was to introduce a family of devices that were fastenough for such applications, while retaining the advantagesof CMOS. The results of this change can be seen in Table 1where HSCMOS devices are compared to standard (metal–gate) CMOS, LSTTL, and ALS.

The Motorola CMOS evolutionary process shown inFigure 1 indicates that one advantage of the silicon–gateprocess is device size. The High–Speed CMOS (HSCMOS)device is about half the size of the metal–gate predecessor,yielding significant chip area savings. The silicon–gate pro-cess allows smaller gate or channel lengths due to the self–

aligning gate feature. This process uses the gate to definethe channel during processing, eliminating registration errorsand, therefore, the need for gate overlaps. The elimination ofthe gate overlap significantly lowers the gate capacitance,resulting in higher speed capability. The smaller gate lengthalso results in higher drive capability per unit gate width, en-suring more efficient use of chip area. Immunity enhance-ments to electrostatic discharge (ESD) damage and latch upare ongoing. Precautions should still be taken, however, toguard against electrostatic discharge and latch up.

Motorola’s High–Speed CMOS family has a broad range offunctions from basic gates, flip–flops, and counters to bus–compatible devices. The family is made up of devices thatare identical in pinout and are functionally equivalent toLSTTL devices, as well as the most popular metal–gatedevices not available in TTL. Thus, the designer has anexcellent alternative to existing families without having tobecome familiar with a new set of device numbers.

METAL GATE CMOSMETALOXIDEP+ N+ P+ P+ P+N+ N+ N+

120 µm

P– N–

65 µm

POLYMETAL

PSGOXIDE

HIGH–SPEEDSILICON–GATEHSCMOS

P–

N–

N+P

P+ P+N+

N

Figure 1. CMOS Evolution

HANDLING PRECAUTIONS

High–Speed CMOS devices, like all MOS devices, havean insulated gate that is subject to voltage breakdown. Thegate oxide for HSCMOS devices breaks down at a gate–source potential of about 100 volts. Some device inputs areprotected by a resistor–diode network (Figure 2). New inputprotection structure deletes the poly resistor (Figure 3) Usingthe test setup shown in Figure 4, the inputs typically with-stand a > 2 kV discharge.

SILICON–GATE

CMOSINPUT

∼ 150 Ω

POLY

VCC

D1 ∼ 50 Ω

D2TO CIRCUIT

GND

Figure 2. Input Protection Network

SILICON–GATE

CMOSINPUT

∼ 190 Ω

POLY

VCC

TO CIRCUIT

VCC

Figure 3. New Input Protection Network

VCCOR

GROUND

10 M 1.5 k

HIGH VOLTAGEDC SOURCE

TO INPUTUNDER TEST

100 pF VZAP

Figure 4. Electrostatic Discharge Test Circuit

2


2–2

Table 1. Logic Family ComparisonsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGeneral Characteristics (1) (All Maximum Ratings)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Ch i i

ÎÎÎÎÎÎÎÎÎÎÎÎ

S b l

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTTL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCMOS

ÎÎÎÎÎÎ

U iÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic

ÎÎÎÎÎÎÎÎÎÎÎÎSymbol

ÎÎÎÎÎÎÎÎLS

ÎÎÎÎÎÎÎÎÎÎALS

ÎÎÎÎÎÎÎÎÎÎMC14000

ÎÎÎÎÎÎÎÎÎÎHi–Speed

ÎÎÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎOperating Voltage RangeÎÎÎÎÎÎÎÎÎÎÎÎVCC/EE/DD

ÎÎÎÎÎÎÎÎ5 ± 5%

ÎÎÎÎÎÎÎÎÎÎ5 ± 5%

ÎÎÎÎÎÎÎÎÎÎ3.0 to 18

ÎÎÎÎÎÎÎÎÎÎ2.0 to 6.0

ÎÎÎÎÎÎVÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎOperating Temperature RangeÎÎÎÎÎÎÎÎÎÎÎÎTA

ÎÎÎÎÎÎÎÎ0 to + 70

ÎÎÎÎÎÎÎÎÎÎ0 to + 70

ÎÎÎÎÎÎÎÎÎÎ– 40 to + 85

ÎÎÎÎÎÎÎÎÎÎ– 55 to + 125

ÎÎÎÎÎÎCÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎInput Voltage (limits)ÎÎÎÎÎÎÎÎÎÎÎÎVIH min

ÎÎÎÎÎÎÎÎ2.0

ÎÎÎÎÎÎÎÎÎÎ2.0




ÎÎÎÎÎÎÎÎÎÎÎ

p g ( ) ÎÎÎÎÎÎÎÎÎÎÎÎ

VIL maxÎÎÎÎÎÎÎÎ

0.8ÎÎÎÎÎÎÎÎÎÎ



1.04ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Voltage (limits)ÎÎÎÎÎÎÎÎÎÎÎÎ

VOH minÎÎÎÎÎÎÎÎ



VDD – 0.05ÎÎÎÎÎÎÎÎÎÎ

VCC – 0.1ÎÎÎÎÎÎ


p g ( )ÎÎÎÎÎÎÎÎÎÎÎÎ

VOL maxÎÎÎÎÎÎÎÎ




0.1ÎÎÎÎÎÎ


Input CurrentÎÎÎÎÎÎÎÎÎÎÎÎ

IINHÎÎÎÎÎÎÎÎ

20ÎÎÎÎÎÎÎÎÎÎ

20ÎÎÎÎÎÎÎÎÎÎ± 0 3

ÎÎÎÎÎÎÎÎÎÎ± 1 0

ÎÎÎÎÎÎ

µAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

pÎÎÎÎÎÎÎÎÎÎÎÎ

IINLÎÎÎÎÎÎÎÎ

– 400 ÎÎÎÎÎÎÎÎÎÎ

– 200 ÎÎÎÎÎÎÎÎÎÎ

± 0.3 ÎÎÎÎÎÎÎÎÎÎ

± 1.0 ÎÎÎÎÎÎ

µ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Current @ VO (limit)unless otherwise specified


IOHÎÎÎÎÎÎÎÎ

– 0.4 ÎÎÎÎÎÎÎÎÎÎ

– 0.4 ÎÎÎÎÎÎÎÎÎÎ

– 2.1 @ 2.5 VÎÎÎÎÎÎÎÎÎÎ

– 4.0 @VCC – 0.8 V

ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

p ÎÎÎÎÎÎÎÎÎÎÎÎIOL

ÎÎÎÎÎÎÎÎ8.0


ÎÎÎÎÎÎÎÎÎÎ0.44 @ 0.4 V

ÎÎÎÎÎÎÎÎÎÎ4.0 @ 0.4 V

ÎÎÎÎÎÎmAÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎDC Noise Margin Low/HighÎÎÎÎÎÎÎÎÎÎÎÎDCM

ÎÎÎÎÎÎÎÎ0.3/0.7

ÎÎÎÎÎÎÎÎÎÎ0.3/0.7


ÎÎÎÎÎÎÎÎÎÎ0.90/1.354


ÎÎÎÎÎÎÎÎÎÎÎDC FanoutÎÎÎÎÎÎÎÎÎÎÎÎ—

ÎÎÎÎÎÎÎÎ20

ÎÎÎÎÎÎÎÎÎÎ20

ÎÎÎÎÎÎÎÎÎÎ50(1)2

ÎÎÎÎÎÎÎÎÎÎ50(10)2

ÎÎÎÎÎÎ—ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSpeed/Power Characteristics (1) (All Typical Ratings)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Ch i i


S b l

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

TTLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOSÎÎÎÎÎÎ

U iÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CharacteristicÎÎÎÎÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎ

LSÎÎÎÎÎÎÎÎÎÎ

ALSÎÎÎÎÎÎÎÎÎÎ

MC14000ÎÎÎÎÎÎÎÎÎÎ

Hi–SpeedÎÎÎÎÎÎ

UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Quiescent Supply Current/GateÎÎÎÎÎÎÎÎÎÎÎÎ

IGÎÎÎÎÎÎÎÎ




0.0005ÎÎÎÎÎÎ

mAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power/Gate (Quiescent)ÎÎÎÎÎÎÎÎÎÎÎÎ

PGÎÎÎÎÎÎÎÎ




0.001ÎÎÎÎÎÎ

mWÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation DelayÎÎÎÎÎÎÎÎÎÎÎÎ

tpÎÎÎÎÎÎÎÎ




8.0ÎÎÎÎÎÎ

nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Speed Power ProductÎÎÎÎÎÎÎÎÎÎÎÎ

—ÎÎÎÎÎÎÎÎ




0.01ÎÎÎÎÎÎ

pJÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Frequency (D–F/F)ÎÎÎÎÎÎÎÎÎÎÎÎ

fmaxÎÎÎÎÎÎÎÎ




40ÎÎÎÎÎÎ

MHzÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Frequency (Counter) ÎÎÎÎÎÎÎÎÎÎÎÎ

fmaxÎÎÎÎÎÎÎÎ

40 ÎÎÎÎÎÎÎÎÎÎ


5.0 ÎÎÎÎÎÎÎÎÎÎ

40 ÎÎÎÎÎÎ

MHzÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay (1)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCh i i


TTL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOS ÎÎÎÎÎÎU iÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎ

ÎÎÎÎLS ÎÎÎÎÎÎÎÎÎÎ

ALS ÎÎÎÎÎÎÎÎÎÎ

MC14000ÎÎÎÎÎÎÎÎÎÎ

Hi–SpeedÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Gate, NOR or NAND: Product No. ÎÎÎÎÎÎÎÎ

SN74LS00ÎÎÎÎÎÎÎÎÎÎ

SN74ALS00ÎÎÎÎÎÎÎÎÎÎ

MC14001BÎÎÎÎÎÎÎÎÎÎ

74HC00 ÎÎÎÎÎÎ

—


tPLH/tPHL(5) TypicalÎÎÎÎÎÎÎÎ

(10)3 ÎÎÎÎÎÎÎÎÎÎ



(8)3 10 ÎÎÎÎÎÎ

ns


MaximumÎÎÎÎÎÎÎÎ




(15)3 20 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFlip–Flop, D–type: Product No. ÎÎÎÎ

ÎÎÎÎSN74LS74ÎÎÎÎÎ

ÎÎÎÎÎSN74ALS74ÎÎÎÎÎ

ÎÎÎÎÎMC14013BÎÎÎÎÎ

ÎÎÎÎÎ74HC74 ÎÎÎ

ÎÎÎ—


tPLH/tPHL(5) (Clock to Q) TypicalÎÎÎÎÎÎÎÎ





ns






(30)3 32 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCounter: Product No. ÎÎÎÎ

ÎÎÎÎSN74LS163ÎÎÎÎÎ

ÎÎÎÎÎSN74ALS163ÎÎÎÎÎ

ÎÎÎÎÎMC14163BÎÎÎÎÎ

ÎÎÎÎÎ74HC163ÎÎÎ

ÎÎÎ—


tPLH/tPHL(5) (Clock to Q) TypicalÎÎÎÎÎÎÎÎ





ns






(27)3 29 ÎÎÎÎÎÎNOTES:

1. Specifications are shown for the following conditions:a) VDD (CMOS) = 5.0 V ± 10% for dc tests, 5.0 V for ac tests; VCC (TTL) = 5.0 V ± 5% for dc tests, 5.0 V for ac testsb) Basic Gates: LS00 or equivalentc) TA = 25Cd) CL = 50 pF (ALS, HC), 15 pF (LS, 14000 and Hi–Speed)e) Commercial grade product

2. ( ) fanout to LSTTL3. ( ) CL = 15 pF4. DC input voltage specifications are proportional to supply voltage over operating range.5. The number specified is the larger of tPLH and tPHL for each device.

2


2–3

The input protection network uses a polysilicon resistor inseries with the input and before the protection diodes. Thisseries resistor slows down the slew rate of static dischargespikes to allow the protection diodes time to turn on. Outputshave a similar ESD protection network except for the seriesresistor. Although the on–chip protection circuitry guardsagainst ESD damage, additional protection may be neces-sary once the chip is placed in circuit. Both an external seriesresistor and ground and VCC diodes, similar to the inputprotection structure, are recommended if there is a potentialof ESD, voltage transients, etc. Several monolithic diode ar-rays are available from Motorola, such as the MAD130 (dual10 diode array) or the MAD1104 (dual 8 diode array). Thesediodes, in chip form, not only provide the necessary protec-tion, but also save board space as opposed to using discretediodes.

Static damaged devices behave in various ways, depend-ing on the severity of the damage. The most severely dam-aged pins are the easiest to detect. An ESD–damaged pinthat has been completely destroyed may exhibit a low–im-pedance path to VCC or GND. Another common failure modeis a fused or open circuit. The effect of both failure modes isthat the device no longer properly responds to input signals.Less severe cases are more difficult to detect because theyshow up as intermittent failures or as degraded performance.Generally, another effect of static damage is increased chipleakage currents (ICC).

Although the input network does offer significant protec-tion, these devices are not immune to large static voltage dis-charges that can be generated while handling. For example,static voltages generated by a person walking across awaxed floor have been measured in the 4 to 15 kV range(depending on humidity, surface conditions, etc.). Therefore,

the following precautions should be observed.1. Wrist straps and equipment logs should be maintained

and audited on a regular basis. Wrist straps malfunctionand may go unnoticed. Also, equipment gets movedfrom time to time and grounds may not be reconnectedproperly.

2. Do not exceed the Maximum Ratings specified by thedata sheet.

3. All unused device inputs should be connected to VCC orGND.

4. All low impedance equipment (pulse generators, etc.)should be connected to CMOS inputs only after theCMOS device is powered up. Similarly, this type ofequipment should be disconnected before power isturned off.

5. Circuit boards containing CMOS devices are merely ex-tensions of the devices, and the same handling precau-tions apply. Contacting edge connectors wired directlyto device inputs can cause damage. Plastic wrappingshould be avoided. When external connectors to a PCboard are connected to an input or output of a CMOSdevice, a resistor should be used in series with the inputor output. This resistor helps limit accidental damage ifthe PC board is removed and brought into contact withstatic generating materials. The limiting factor for the se-ries resistor is the added delay. The delay is caused bythe time constant formed by the series resistor and inputcapacitance. Note that the maximum input rise and falltimes should not be exceeded. In Figure 5, two possiblenetworks are shown using a series resistor to reduceESD damage. For convenience, an equation is given foradded propagation delay and rise time effects due to se-ries resistance size.

Advantage: Requires minimal area

Disadvantage: R1 > R2 for the same level ofprotection; therefore, rise andfall times, propagation delays,and output drives are severelyaffected.

Advantage: R2 < R1 for the same level ofprotection. Impact on ac and dccharacteristics is minimized.

Disadvantage: More board area, higher initialcost.

where:R=the maximum allowable series resistance in ohmst= the maximum tolerable propagation delay or rise time int= secondsC= the board capacitance plus the driven inputC= capacitance in faradsk= 0.7 for propagation delay calculationsk= 2.3 for rise time calculations

TO OFF–BOARDCONNECTION

R1CMOSINPUT

OROUTPUT

TO OFF–BOARDCONNECTION

CMOSINPUT

OROUTPUT

R2

VCC

D1

D2

GND

Propagation Delay and Rise Time vs. Series Resistance

R

tC ·k

NOTE: These networks are useful for protecting the following:A digital inputs and outputs C 3–state outputsB analog inputs and outputs D bidirectional (I/O) ports

Figure 5. Networks for Minimizing ESD and Reducing CMOS Latch Up Susceptibility

2


2–4

6. All CMOS devices should be stored or transported inmaterials that are antistatic or conductive. CMOS de-vices must not be inserted into conventional plastic“snow”, Styrofoam, or plastic trays, but should be left intheir original container until ready for use.

7. All CMOS devices should be placed on a groundedbench surface and operators should ground them-selves prior to handling devices, because a worker canbe statically charged with respect to the bench surface.Wrist straps in contact with skin are essential andshould be tested daily. See Figure 6 for an example ofa typical work station.

8. Nylon or other static generating materials should notcome in contact with CMOS devices.

9. If automatic handlers are being used, high levels of stat-ic electricity may be generated by the movement of thedevice, the belts, or the boards. Reduce static buildupby using ionized air blowers, anti–static sprays, androom humidifiers. All conductive parts of machineswhich come into contact with the top, bottom, or sidesof IC packages must be grounded to earth ground.

10. Cold chambers using CO2 for cooling should beequipped with baffles, and the CMOS devices must becontained on or in conductive material.

11. When lead straightening or hand soldering is neces-sary, provide ground straps for the apparatus used andbe sure that soldering iron tips are grounded.

12. The following steps should be observed during wavesolder operations:a. The solder pot and conductive conveyor system of

the wave soldering machine must be grounded toearth ground.

b. The loading and unloading work benches shouldhave conductive tops grounded to earth ground.

c. Operators must comply with precautions previouslyexplained.

d. Completed assemblies should be placed in antistaticor conductive containers prior to being moved to sub-sequent stations.

13. The following steps should be observed during board–cleaning operations:a. Vapor degreasers and baskets must be grounded to

earth ground.

b. Brush or spray cleaning should not be used.c. Assemblies should be placed into the vapor de-

greaser immediately upon removal from the anti-static or conductive container.

d. Cleaned assemblies should be placed in antistatic orconductive containers immediately after removalfrom the cleaning basket.

e. High velocity air movement or application of solventsand coatings should be employed only when a staticeliminator using ionized air is directed at the printedcircuit board.

14. The use of static detection meters for production linesurveillance is highly recommended.

15. Equipment specifications should alert users to the pres-ence of CMOS devices and require familiarization withthis specification prior to performing any kind of mainte-nance or replacement of devices or modules.

16. Do not insert or remove CMOS devices from test sock-ets with power applied. Check all power supplies to beused for testing devices to be certain there are no volt-age transients present.

17. Double check test equipment setup for proper polarityof VCC and GND before conducting parametric or func-tional testing.

18. Do not recycle shipping rails. Repeated use causes de-terioration of their antistatic coating. Exception: carbonrails (black color) may be recycled to some extent. Thistype of rail is conductive and antistatic.

RECOMMENDED READING

“Requirements for Handling Electrostatic–DischargeSensitive (ESDS) Devices” EIA Standard EIA–625

Available by writing to:Global Engineering Documents15 Inverness Way EastEnglewood, Colorado 80112

Or by calling:1–800–854–7179 in the USA or CANADA or(303) 397–7956 International

S. Cherniak, “A Review of Transients and Their Means ofSuppression”, Application Note–843, Motorola Semiconduc-tor Products Inc., 1982.

NOTES:1. 1/16 inch conductive sheet stock covering bench-top work

area.2. Ground strap.3. Wrist strap In contact with skin.4. Static neutralizer. (ionized air blower directed at work.)

Primarily for use in areas where direct grounding isimpractical.

5. Room humidifier. Primarily for use in areas where therelative humidity is less than 45%. Caution: buildingheating and cooling systems usually dry the air causingthe relative humidity inside a building to be less thanoutside humidity.

R = 1 M

1

2

3

4

5

Figure 6. Typical Manufacturing Work Station

2


2–5

POWER SUPPLY SIZING

CMOS devices have low power requirements and the abil-ity to operate over a wide range of supply voltages. Thesetwo characteristics allow CMOS designs to be implementedusing inexpensive power supplies without cooling fans. Inaddition, batteries may be used as either a primary powersource or as a backup.

The maximum recommended power supply voltage for HCdevices is 6.0 V and 5.5 V for HCT devices. Figure 7 offerssome insight as to how this specification was derived. In thefigure, VS is the maximum power supply voltage and IS is thesustaining current for the latch–up mode. The value of VSwas chosen so that the secondary breakdown effect may beavoided. The low–current junction avalanche region is be-tween 10 and 14 volts at TA = 25C.

ICC

IS

VS VCC

LATCHUP MODE

SECONDARYBREAKDOWN

LOW CURRENTJUNCTION

AVALANCHE

DATA SHEET MAXIMUM SUPPLY RATING

Figure 7. Secondary Breakdown Characteristics

In an ideal system design, the power supply should be de-signed to deliver only enough current to ensure proper op-eration of all devices. The obvious benefit of this type ofdesign is cost savings.

BATTERY SYSTEMS

HSCMOS devices can be used with battery or batterybackup systems. A few precautions should be taken whendesigning battery–operated systems.

1. The recommended power supply voltages should beobserved. For battery backup systems such as the onein Figure 8, the battery voltage must be at least 2.7 volts(2 volts for the minimum power supply voltage and0.7 volts to account for the voltage drop across the se-ries diode).

2. Inputs that might go above the battery backup voltageshould use the HC4049 or HC4050 buffers (Figure 8).If line power is interrupted, CMOS System A and BufferA lose power. However, CMOS System B and Buffer Bremain active due to the battery backup. Buffer Aprotects System A from System B by blocking activeinputs while the circuit is not powered up. Also, if thepower supply voltage drops below the battery voltage,Buffer A acts as a level translator for the outputs fromSystem B. Buffer B acts to protect System B from anyovervoltages which might exist. Both buffers may bereplaced with current–limiting resistors, however powerconsumption is increased and propagation delays arelengthened.

3. Outputs that are subject to voltage levels above VCC orbelow GND should be protected with a series resistorand/or clamping diodes to limit the current to an accept-able level.

POWER SUPPLY

BATTERY TRICKLERECHARGE

CMOSSYSTEM

Figure 8. Battery Backup System

POWER SUPPLY

LINE POWER ONLYSYSTEM

CMOSSYSTEM

HC4049HC4050

BATTERY BACKUPSYSTEM

HC4049HC4050

BATTERY TRICKLERECHARGE

CMOSSYSTEM

A B

Figure 9. Battery Backup Interface

2


2–6

CPD POWER CALCULATION

Power consumption for HSCMOS is dependent on thepower–supply voltage, frequency of operation, internal ca-pacitance, and load. The power consumption may be calcu-lated for each package by summing the quiescent powerconsumption, ICC • VCC, and the switching power required byeach device within the package. For large systems, the mosttimely method is to bread–board the circuit and measure thecurrent required under a variety of conditions.

The device dynamic power requirements can be calcu-lated by the equation:

PD = (CL + CPD) VCC2f

where: PD = power dissipated in µW

CL = total load capacitance present at the output inpF

CPD = a measure of internal capacitances, calledpower dissipation capacitance, given in pF

VCC = supply voltage in volts

f = frequency in MHz

If the devices are tested at a sufficiently high frequency,the dc supply current contributes a negligible amount to theoverall power consumption and can therefore be ignored.For this reason, the power consumption is measured at1 MHz and the following formula is used to determine the de-vice’s CPD value:

ICC (dynamic)CPD =

VCC • f – CL

The resulting power dissipation is calculated using CPD asfollows under no–load conditions.

(HC) PD = CPDVCC2f + VCCICC

(HCT) PD = CPDVCC2f + VCCICC + ∆ICCVCC

(δ1 + δ2 + … + δn)

where the previously undefined variable, δn is the duty cycleof each input applied at TTL/NMOS levels.

The power dissipation for analog switches switching digitalsignals is the following:

(HC) PD = CPDVCC2fin + (CS + CL)VCC2fout + VCCICC

where: CS = digital switch capacitance, and

fout = output frequency

In order to determine the CPD of a single section of a device(i.e., one of four gates, or one of two flip–flops in a package),Motorola uses the following procedures as defined byJEDEC. Note: “biased” as used below means “tied to VCC orGND.”

Gates: Switch one input while the remaining in-put(s) are biased so that the output(s)switch.

Latches: Switch the enable and data inputs such thatthe latch toggles.

Flip–Flops: Switch the clock pin while changing the datapin(s) such that the output(s) change witheach clock cycle.

Decoders/ Switch one address pin which changes twoDemultiplexers: outputs.

Data Selectors/ Switch one address input with the corre-Multiplexers: sponding data inputs at opposite logic levels

so that the output switches.

Analog Switch one address/select pin whichSwitches: changes two switches. The switch inputs/

outputs should be left open. For digitalapplications where the switch inputs/out-puts change between VCC and GND, therespective switch capacitance should beadded to the load capacitance.

Counters: Switch the clock pin with the other inputsbiased so that the device counts.

Shift Switch the clock while alternating the inputRegisters: so that the device shifts alternating 1s and

0s through the register.

Transceivers: Switch only one data input. Place trans-ceivers in a single direction.

Monostables: The pulse obtained with a resistor and noexternal capacitor is repeatedly switched.

Parity Switch one input.Generators:

Encoders: Switch the lowest priority output.

Display Switch one input so that approximately one–Drivers: half of the outputs change state.

ALUs/Adders: Switch the least significant bit. The remain-ing inputs are biased so that the device isalternately adding 0000 (binary) or 0001(binary) to 1111 (binary).

On HSCMOS data sheets, CPD is a typical value and isgiven either for the package or for the individual device (i.e.,gates, flip–flops, etc.) within the package. An example of cal-culating the package power requirement is given using the74HC00, as shown in Figure 10.

From the data sheet:

ICC = 2 µA at room temperature (per package)

CPD = 22 pF per gate

PD = (CPD + CL)VCC2f + VCCICC

PD1 = (22 pF + 50 pF)(5 V)2(1 kHz) 1.8 µW

PD2 = (22 pF + 50 pF)(5 V)2(1 MHz) 1800 µW

PD3 = (22 pF) (5 V)2(0 Hz) = 0 µW

PD4 = (22 pF)(5 V)2(0 Hz) = 0 µW

PD(total) = VCCICC + PD1 + PD2 + PD3 + PD4

= 10 µW + 1.8 µW + 1800 µW + 0 µW

= 1812 µW

2


2–7

VCC = 5 V

f = 1 kHz

f = 1 MHz

50 pF

1

2

3

4

50 pF

Figure 10. Power Consumption Calculation Example

As seen by this example, the power dissipated by CMOSdevices is dependent on frequency. When operating at veryhigh frequencies, HSCMOS devices can consume as muchpower as LSTTL devices, as shown in Figure 11. The powersavings of HSCMOS is realized when used in a systemwhere only a few of the devices are actually switching at thesystem frequency. The power consumption savings comesfrom the fact that for CMOS, only the devices that are switch-ing consume significant power.

VCC = 5 Vdc

100 m5

210 m

5

21 m

5

2100 µ

5

2

10 µ

10 k2 5

100 k2 5

1 M2 5

10 M2 5

100 M2 5

1 G7 7 7 7 7

FREQUENCY @ 50% DUTY CYCLE (Hz)

POW

ER (W

ATTS

)

MC7400

SN74LS00

SN74ALS00

MC74HC00

Figure 11. Power Consumption Vs. Input Frequencyfor TTL, LSTTL, ALs, and HSCMOS

INPUTS

A basic knowledge of input and output structures is essen-tial to the HSCMOS designer. This section deals with the var-ious input characteristics and application rules regardingtheir use. Output characteristics are discussed in the sectiontitled Outputs .

All standard HC, HCU and HCT inputs, while in the recom-mended operating range (GND Vin VCC), can be mod-eled as shown in Figure 12. For input voltages in this range,diodes D1 and D2 are modeled as resistors representing thehigh–impedance of reverse biased diodes. The maximum in-put current is 1 µA, worst case over temperature, when theinputs are at VCC or GND, and VCC = 6 V.

VCC

R1

10 pF

R1 = R2 = HIGH Z

R2

Figure 12. Input Model for GND Vin VCC

When CMOS inputs are left open–circuited, the inputs maybe biased at or near the typical CMOS switchpoint of 0.45VCC for HC devices or 1.3 V for HCT devices. At this switch-point, both the P–channel and the N–channel transistors areconducting, causing excess current drain. Due to the highgain of the buffered devices (see Figure 13), the device cango into oscillation from any noise in the system, resulting ineven higher current drain.

Vin, INPUT VOLTAGE (V)

V

,O

UTP

UT

VOLT

AGE

(V)

out

5

4

3

2

1

0 1 2 3 4 5

HCT HC

Figure 13. Typical Transfer Characteristicsfor Buffered Devices

For these reasons, all unused HC/HCT inputs should beconnected either to VCC or GND. For applications with inputsgoing to edge connectors, a 100 kΩ resistor to GND shouldbe used, as well as a series resistor (RS) for static protectionand current limiting (see Handling Precautions , this chap-ter, for series resistor consideration). The resistors should beconfigured as in Figure 14.

RS

100 k

FROMEDGE

CONNECTOR

HSCMOSDEVICE

Figure 14. External Protection

2


2–8

For inputs outside of the recommended operating range,the CMOS input is modeled as in Figure 15 and Figure 16.

Current flows through diode D1 or D2 whenever the inputvoltage exceeds VCC or drops below GND enough to forwardbias either D1 or D2. The device inputs are guaranteed towithstand from GND – 1.5 V to VCC + 1.5 V and a maximumcurrent of 20 mA. If this maximum rating is exceeded, the de-vice could go into a latch–up condition. (See CMOS LatchUp, this chapter.) Voltage should never be applied to any in-put or output pin before power has been applied to the de-vice’s power pins. Bias on input or output pins should beremoved before removing the power. However, if the inputcurrent is limited to less than 20 mA, and this current onlylasts for a brief period of time (< 100 ms), no damage to thedevice occurs.

Another specification that should be noted is the maximuminput rise (tr) and fall (tf) times. Figure 17 shows the results ofexceeding the maximum rise and fall times recommended byMotorola or contained in JEDEC Standard No. 7A. The rea-son for the oscillation on the output is that as the voltagepasses through the switching threshold region with a slowrise time, any noise that is on the input line is amplified, andis passed through to the output. This oscillation may have alow enough frequency to cause succeeding stages to switch,giving unexpected results. If input rise or fall times are ex-pected to exceed the maximum specified rise or fall times,Schmitt–triggered devices such as Motorola’s HC14 andHC132 are recommended.

OUTPUTS

All HSCMOS outputs, with the exception of the HCU04,are buffered to ensure consistent output voltage and currentspecifications across the family. All buffered outputs have

guaranteed output voltages of VOL = 0.1 V and VOH =VCC – 0.1 V for Iout 20 µA ( 20 HSCMOS loads).The output drives for standard drive devices are suchthat 54HC/HCT and 74HC/HCT devices can drive ten LSTTLloads and maintain a VOL 0.4 V and VOH VCC – 0.8 Vacross the full temperature range; bus–driver devices candrive fifteen LSTTL loads under the same conditions.

The outputs of all HSCMOS devices are limited to exter-nally forced output voltages of – 0.5 Vout VCC + 0.5 V.For externally forced voltages outside this range a latch upcondition could be triggered. (See CMOS Latch Up , thischapter.)

The maximum rated output current given on the individualdata sheets is 25 mA for standard outputs and 35 mA for busdrivers. The output short circuit currents of these devices typ-ically exceed these limits. The outputs can, however, beshorted for short periods of time for logic testing, if the maxi-mum package power dissipation is not violated. (See individ-ual data sheets for maximum power dissipation ratings.)

For applications that require driving high capacitive loadswhere fast propagation delays are needed (e.g., driving pow-er MOSFETS), devices within the same package may beparalleled. Paralleling devices in different packages may re-sult in devices switching at different points on the input volt-age waveform, creating output short circuits and yieldingundesirable output voltage waveforms.

As a design aid, output characteristic curves are givenfor both P–channel source and N–channel sink currents.The curves given include expected minimum curves forTA = 25C, 85C, and 125C, as well as typical values forTA = 25C. For temperatures < 25C, use the 25C curves.These curves, Figure 18 through Figure 29, are intended asdesign aids, not as guarantees. Unused output pins shouldbe open–circuited (floating).

Figure 15. Input Model for V in > VCC or Vin < GND

150

Vin

Vout

D1

D23 pF 2 pF

Figure 16. Input Model for New ESD Enhanced Circuits

D1

D23 pF 2 pF

Figure 17. Maximum Rise Time Violation

2


2–9

STANDARD OUTPUT CHARACTERISTICS

N–CHANNEL SINK CURRENT P–CHANNEL SOURCE CURRENT

Figure 18. V GS = 2.0 V Figure 19. V GS = – 2.0 V

I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out

Vout, OUTPUT VOLTAGE (V)

I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out

TYPICALTA = 25C

EXPECTED MINIMUM *, TA = 25–125C

TYPICALTA = 25C


25

20

15

10

5

00 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0

– 25

– 20

–15

–10

– 5

0



TYPICALTA = 25C TA = 25C

TA = 85C

TA = 125C

EXPECTED MINIMUM CURVES*

I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out


25

20

15

10

5

00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.0 3.5 3.0 0

– 25

– 20

–15

–10

– 5

0


2.5 2.0 1.5 1.0 0.5

TYPICALTA = 25C

TA = 25C

TA = 85C

TA = 125C


I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out


I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out


25

20

15

10

5

00 1.0 2.0 3.0 4.0 5.0 6.0 6.0 5.0 4.0 3.0 0

– 25

– 20

–15

–10

– 5

0


2.0 1.0

TYPICALTA = 25C

TA = 25C TA = 85C

TA = 125C


TYPICALTA = 25C

TA = 25C TA = 85C

TA = 125C


I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out

*The expected minimum curves are not guarantees, but are design aids.

2


2–10

BUS–DRIVER OUTPUT CHARACTERISTICS

N–CHANNEL SINK CURRENT P–CHANNEL SOURCE CURRENT


I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out


I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out

TYPICALTA = 25C


TYPICALTA = 25C


25

20

15

10

5

00.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0

– 25

– 20

–15

–10

– 5

0


30

35

0

– 30

– 35


TYPICALTA = 25C TA = 25C

TA = 85C

TA = 125C

EXPECTED MINIMUMS*


25

20

15

10

5

00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out

4.5 4.0 3.5 3.0 0

– 25

– 20

–15

–10

– 5

0


2.5 2.0 1.5 1.0 0.5

TYPICALTA = 25C

TA = 25C TA = 85C

TA = 125C

EXPECTED MINIMUMS*

I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out

30

35

– 30

– 35



25

20

15

10

5

00 2.0 3.0 4.0 5.0 6.0

I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out

6.0 5.0 4.0 3.0 0

– 25

– 20

–15

–10

– 5

0


2.0 1.0

TYPICALTA = 25C

TA = 25C

TA = 85C

TA = 125C

EXPECTED MINIMUMS*

TYPICALTA = 25C

TA = 25C

TA = 85C

TA = 125C

EXPECTED MINIMUMS*

I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out

30

35

1.0

– 30

– 35

*The expected minimum curves are not guarantees, but are design aids.

2


2–11

3–STATE OUTPUTS

Some HC/HCT devices have outputs that can be placedinto a high–impedance state. These 3–state output devicesare very useful for gang connecting to a common line or bus.When enabled, these output pins can be considered as ordi-nary output pins; as such, all specifications and precautionsof standard output pins should be followed. When disabled(high–impedance state), these outputs can be modeled as inFigure 30. Output leakage current (10 µA worst case overtemperature) as well as 3–state output capacitance must beconsidered in any bus design.

When power is interrupted to a 3–state device, the busvoltage is forced to between GND and VCC + 0.7 V regard-less of the previous output state.

R1

VCC

R1 = R2 = HIGH Z

OUTPUT

15 pFR2

INTERNALCIRCUITRY

Figure 30. Model for Disabled Outputs

OPEN–DRAIN OUTPUTS

Motorola provides several devices that are designed onlyto sink current to GND. These open–drain output devices arefabricated using only an N–channel transistor and a diode toVCC (Figure 31). The purpose of the diode is to provide ESDprotection. Open–drain outputs can be modeled as shown inFigure 32.

VCC

INTERNALCIRCUITRY

OUTPUT

Figure 31. Open–Drain Output

VCC

LOW Z

HIGH Z

OUTPUT

10 pF

HIGH Z

Figure 32. Model of Open–Drain Output

INPUT/OUTPUT PINS

Some HC/HCT devices contain pins that serve both as in-puts and outputs of digital logic. These pins are referred to asdigital I/O pins. The logic level applied to a control pin deter-mines whether these I/O pins are selected as inputs or out-puts.

When I/O pins are selected as outputs, these pins may beconsidered as standard CMOS outputs. When selected asinputs, except for an increase in input leakage current andinput capacitance, these pins should be considered as stan-dard CMOS inputs. These increases come from the fact thata digital I/O pin is actually a combination of an input and a3–state output tied together (see Figure 33).

As stated earlier, all HC/HCT inputs must be connected toan appropriate logic level. This could pose a problem if an I/Opin is selected as an input while connected to an improperlyterminated bus.

Motorola recommends terminating HC/HCT–type buseswith resistors to VCC or GND of between 1 kΩ to 1 MΩ invalue. The choice of resistor value is a trade–off betweenspeed and power consumption (see Bus Termination , thischapter).

Some Motorola devices have analog I/O pins. These ana-log I/O pins should not be confused with digital I/O pins. Ana-log I/O pins may be modeled as in Figure 34. These devicescan be used to pass analog signals, as well as digital signals,in the same manner as mechanical switches.

I/O

INTERNALCIRCUITRY

Figure 33. Typical Digital I/O Pin

2


2–12

GND OR VEEGND OR VEE

Ron

VCC VCC

HIGH Z

HIGH Z

ANALOGI/O

ANALOGO/I

Figure 34. Analog I/O Pin

BUS TERMINATION

Because buses tend to operate in harsh, noisy environ-ments, most bus lines are terminated via a resistor to VCC orground. This low impedance to VCC or ground (depending onpreference of a pull–up or pull–down logic level) reduces busnoise pickup. In certain cases a bus line may be released(put in a high–impedance state) by disabling all the 3–statebus drivers (see Figure 35). In this condition all HC/HCT in-puts on the bus would be allowed to float. A CMOS input or1/0 pin (when selected as an input) should never be allowedto float. (This is one reason why an HCT device may not be adrop–in replacement of an LSTTL device.) A floating CMOSinput can put the device into the linear region of operation. Inthis region excessive current can flow and the possibility oflogic errors due to oscillation may occur (see Inputs , thischapter). Note that when a bus is properly terminated withpull–up resistors, HC devices, instead of HCT devices, canbe driven by an NMOS or LSTTL bus driver. HC devices arepreferred over HCT devices in bus applications because oftheir higher low level input noise margin. (With a 5 V supplythe typical HC switch point is 2.3 V while the switch point ofHCT is only 1.3 V.)

Some popular LSTTL bus termination designs may notwork for HSCMOS devices. The outputs of HSCMOS maynot be able to drive the low value of termination used bysome buses. (This is another reason why an HCT devicemay not be a drop in replacement for an LSTTL device.)However, because low power operation is one of the mainreasons for using CMOS, an optimized CMOS bus termina-tion is usually advantageous.

BUS

ENABLE INPUT(HIGH = 3–STATE)

ENABLE INPUT(LOW = 3–STATE)

Figure 35. Typical Bus Line with 3–State Bus Drivers

The choice of termination resistances is a trade–off be-tween speed and power consumption. The speed of the busis a function of the RC time constant of the termination resis-tor and the parasitic capacitance associated with the bus.Power consumption is a function of whether a pull–up orpull–down resistor is used and the output state of the devicethat has control of the bus (see Figure 36). The lower the ter-mination resistor the faster the bus operates, but more poweris consumed. A large value resistor wastes less power, butslows the bus down. Motorola recommends a termination re-sistor value between 1 kΩ and 1 MΩ. An alternative to a pas-sive resistor termination would be an active–type termination(see Figure 37). This type termination holds the last logic lev-el on the bus until a driver can once again take control of thebus. An active termination has the advantage of consuming aminimal amount of power. Most HC/HCT bus drivers do nothave built–in hysteresis. Therefore, heavily loaded busescan slow down rise and fall signals and exceed the input rise/fall time defined in JEDEC Standard No. 7A. In this event,devices with Schmitt–triggered inputs should be used tocondition these slow signals.

(a) USING A PULL-UP RESISTOR (b) USING A PULL-DOWN RESISTOR

VCC

VCC

VCC

(L)

I R

BUS

BUS

(H)

I

R

Figure 36.

2


2–13

BUS LINES ENABLE

Figure 37. Using Active Termination (HC125)

TRANSMISSION LINE TERMINATION

When data is transmitted over long distances, the line onwhich the data travels can be considered a transmission line.(Long distance is relative to the data rate being transmitted.)Examples of transmission lines include high–speed buses,long PCB lines, coaxial and ribbon cables. All transmissionlines should be properly terminated into a low–impedancetermination. A low–impedance termination helps eliminatenoise, ringing, overshoot, and crosstalk problems. Also alow–impedance termination reduces signal degradation be-cause the small values of parasitic line capacitance and in-ductance have lesser effect on a low–impedance line.

The value of the termination resistor becomes a trade–offbetween power consumption, data rate speeds, and trans-mission line distance. The lower the resistor value, the fasterdata can be presented to the receiving device, but the morepower the resistor consumes. The higher the resistor value,the longer it will take to charge and discharge the transmis-sion line through the termination resistor (T = R • C).

Transmission line distance becomes more critical as datarates increase. As data rates increase, incident (and reflec-tive) waves begin to resemble that of RF transmission linetheory. However, due to the nonlinearity of CMOS digital log-ic, conventional RF transmission theory is not applicable.

HC devices are preferred over HCT devices due to the factthat HC devices have higher switch points than HCT devices.This higher switch point allows HC devices to achieve betterincident wave switching on lower impedance lines.

HC/HCT may not have enough drive capability to interfacewith some of the more popular LSTTL transmission lines.(Possible reason why an HCT device may not be a drop–inreplacement of an equivalent TTL device.) This does notpose a major problem since having larger value terminationresistors is desirable for CMOS type transmission lines.

By increasing the termination resistance value, the CMOSadvantage of low power consumption can be realized.Motorola recommends a minimum termination resistor valueas shown in Figure 38. The termination resistor should be asclose to the receiving unit as possible. Another method of ter-minating the line driver, as well as the receiving unit, is

shown in Figure 39. Note that the resistor values in Figure 39are twice the resistor value of Figure 38; this gives a netequivalent termination value of Figure 38. Even higher val-ues of resistors may be used for either termination method.This reduces power consumption, but at the expense ofspeed and possible signal degradation.

VCC

R1 = 1.5 kR1 = 1.0 k

HSCMOS(LINE DRIVER)

HSCMOS(RECEIVER)

R1

R2

Figure 38. Termination Resistors at the Receiver

VCCVCC

R1 = R3 = 3.0 kR2 = R4 = 2 k

HSCMOS HSCMOS

R1 R3

R2 R4

Figure 39. Termination Resistors atBoth the Line Driver and Receiver

CMOS LATCH UP

Typically, HSCMOS devices do not latch up with currentsof 75 mA forced into or out of the inputs or 300 mA for theoutputs under worst case conditions (TA = 125C and VCC =6 V). Under dc conditions for the inputs, the input protectionnetwork typically fails, due to grossly exceeding the maxi-mum input voltage rating of – 1.5 to VCC + 1.5 V before latch–up currents are reached. For most designs, latch up will notbe a problem, but the designer should be aware of it, whatcauses it, and how it can be prevented.

Figure 40 shows the layout of a typical CMOS inverter andFigure 41 shows the parasitic bipolar devices that areformed. The circuit formed by the parasitic transistors and re-sistors is the basic configuration of a silicon controlled rectifi-er, or SCR. In the latch–up condition, transistors Q1 and Q2are turned on, each providing the base current necessary forthe other to remain in saturation, thereby latching the deviceon. Unlike a conventional SCR, where the device is turnedon by applying a voltage to the base of the NPN transistor,the parasitic SCR is turned on by applying a voltage to theemitter of either transistor. The two emitters that trigger theSCR are the same point, the CMOS output. Therefore, tolatch up the CMOS device, the output voltage must be great-er than VCC + 0.5 V or less than – 0.5 V and have sufficientcurrent to trigger the SCR. The latch–up mechanism is simi-lar for the inputs.

Once a CMOS device is latched up, if the supply current isnot limited, the device can be destroyed or its reliability canbe degraded. Ways to prevent such an occurrence are listedbelow.

2


2–14

1. Industrial controllers driving relays or motors is an envi-ronment in which latch up is a potential problem. Also,the ringing due to inductance of long transmission linesin an industrial setting could provide enough energy tolatch up CMOS devices. Opto–isolators, such asMotorola’s MOC3011, are recommended to reducechances of latch up. See the Motorola SemiconductorMaster Selection Guide for a complete listing ofMotorola opto–isolators.

2. Ensure that inputs and outputs are limited to the maxi-mum rated values.

– 1.5 Vin VCC +1.5 V referenced to GND or– 0.5 Vin VCC +0.5 V referenced to GND

– 0.5 Vout VCC +0.5 V referenced to GND

|Iin| 20 mA

|Iout| 25 mA for standard outputs

|Iout| 35 mA for bus–driver outputs

3. If voltage transients of sufficient energy to latch up thedevice are expected on the inputs or outputs, externalprotection diodes can be used to clamp the voltage.

Another method of protection is to use a series resistorto limit the expected worst case current to the maximumratings value. See Handling Precautions for otherpossible protection circuits and a discussion of ESDprevention.

4. Sequence power supplies so that the inputs or outputsof HSCMOS devices are not active before the supplypins are powered up (e.g., recessed edge connectorsand/or series resistors may be used in plug–in board ap-plications).

5. Voltage regulating and filtering should be used in boarddesign and layout to ensure that power supply lines arefree of excessive noise.

6. Limit the available power supply current to the devicesthat are subject to latch–up conditions. This can be ac-complished with the power–supply filtering network orwith a current–limiting regulator.

RECOMMENDED READING

Paul Mannone, “Careful Design Methods Prevent CMOSLatch–Up”, EDN, January 26, 1984.

ÇÇÇÇ

ÇÇÇÇÇÇ

VCC VCC

P–CHANNEL N–CHANNELINPUT

OUTPUTP–CHANNELOUTPUT

N–CHANNELOUTPUT

GND

FIELD OXIDE FIELD OXIDE FIELD OXIDEN+ P+ P+ N+ N+ P+

P – WELLN – SUBSTRATE

Figure 40. CMOS Wafer Cross Section

VCC

VCC

P–CHANNEL OUTPUT P – WELL RESISTANCEQ1

P+

P+

N–

P–

N–CHANNEL OUTPUTN – SUBSTRATE RESISTANCE

P–

N+N+N–

Q2

GND

GND

Figure 41. Latch–Up Circuit Schematic

2


2–15

MAXIMUM POWER DISSIPATION

The maximum power dissipation for Motorola HSCMOSpackages is 750 mW for both ceramic and plastic DIPs and500 mW for SOIC packages. The deratings are – 10 mW/Cfrom 65C for plastic DIPs, – 10 mW/C from 100C forceramic packages, and – 7 mW/C from 65C for SOICpackages. This is illustrated in Figure 42.

– 40 0 40 80 120

100

200

300

400

500

600

800

P D, M

AXIM

UM

PAC

KAG

E PO

WER

DIS

SIPA

TIO

N (m

W)

TA, AMBIENT TEMPERATURE (°C)

700CERAMIC

DIP

PLASTICDIP

TSSOPPACKAGE

SOICPACKAGE

Figure 42. Maximum Package PowerDissipation versus Temperature

Internal heat generation in HSCMOS devices comes fromtwo sources, namely, the quiescent power and dynamic pow-er consumption.

In the quiescent state, either the P–channel or N–channeltransistor in each complementary pair is off except for smallsource–to–drain leakage due to the inputs being either atVCC or ground. Also, there are the small leakage currentsflowing in the reverse–biased input protection diodes and theparasitic diodes on the chip. The specification which takes allleakage into account is called Maximum Quiescent SupplyCurrent (per package), or ICC, and is shown on all datasheets.

The three factors which directly affect the value of quies-cent power dissipation are supply voltage, device complexity,and temperature. On the data sheets, ICC is specified only atVCC = 6.0 V because this is the worst–case supply voltagecondition. Also, larger or more complex devices consumemore quiescent power because these devices contain a pro-portionally greater reverse–biased diode junction area andmore off (leaky) FETs.

Finally, as can be seen from the data sheets, temperatureincreases cause ICC increases. This is because at highertemperatures, leakage currents increase.

HC QUIESCENT POWER DISSIPATION

When HC device inputs are virtually at VCC or GND poten-tial (as in a totally CMOS system), quiescent power dissipa-tion is minimized. The equation for HC quiescent powerdissipation is given by:

PD = VCCICC

Worst–case ICC occurs at VCC = 6.0 V. The value of ICC atVCC = 6.0 V, as specified in the data sheets, is used for allpower supply voltages from 2 to 6 V.

HCT QUIESCENT POWER DISSIPATION

Although HCT devices belong to the CMOS family, their in-put voltage specifications are identical to those of LSTTL.HCT parts can therefore be either judiciously substituted foror mixed with LS devices in a system.

TTL output voltages are VOL = 0.4 V (max) and VOH = 2.4to 2.7 V (min).

Slightly higher ICC current exists when an HCT device isdriven with VOL = 0.4 V (max) because this voltage is highenough to partially turn on the N–channel transistor. How-ever, when being driven with a TTL VOH, HCT devices exhibitlarge additional current flow (∆ICC) as specified on HCT de-vice data sheets. ∆ICC current is caused by the off–rail inputvoltage turning on both the P and N channels of the inputbuffer. This condition offers a relatively low impedance pathfrom VCC to GND. Therefore, the HCT quiescent power dis-sipation is dependent on the number of inputs applied at theTTL VIH logic voltage level.

The equation for HCT quiescent power dissipation is givenby:

PD = ICCVCC + η∆ICCVCC

where η = the number of inputs at the TTL VIH level.

HC AND HCT DYNAMIC POWER DISSIPATION

Dynamic power dissipation is calculated in the same wayfor both HC and HCT devices. The three major factors whichdirectly affect the magnitude of dynamic power dissipationare load capacitance, internal capacitance, and switchingtransient currents.

The dynamic power dissipation due to capacitive loads isgiven by the following equation:

PD = CLVCC2f

where PD = power in µW, CL = capacitive load in pF,VCC = supply voltage in volts, and f = output frequency driv-ing the load capacitor in MHz.

All CMOS devices have internal parasitic capacitancesthat have the same effect as external load capacitors. Themagnitude of this internal no–load power dissipation capaci-tance, CPD, is specified as a typical value.

Finally, switching transient currents affect the dynamicpower dissipation. As each gate switches, there is a short pe-riod of time in which both N– and P–channel transistors arepartially on, creating a low–impedance path from VCC toground. As switching frequency increases, the power dis-sipation due to this effect also increases.

The dynamic power dissipation due to CPD and switchingtransient currents is given by the following equation:

PD = CPDVCC2f

Therefore, the total dynamic power dissipation is given by:

PD = (CL + CPD)VCC2f

2


2–16

Total power dissipation for HC and HCT devices is merelya summation of the dynamic and quiescent power dissipationelements. When being driven by CMOS logic voltage levels(rail to rail), the total power dissipation for both HC and HCTdevices is given by the equation:

PD = VCCICC + (CL + CPD)VCC2f

When being driven by LSTTL logic voltage levels, the totalpower dissipation for HCT devices is given by the equation:

PD =VCCICC + VCC∆ICC(δ, + δ2 + … + δn)

+ (CL + CPD)VCC2f

where δn = duty cycle of LSTTL output applied to each inputof an HCT device.

THERMAL MANAGEMENTCircuit performance and long-term circuit reliability are af-

fected by die temperature. Normally, both are improved bykeeping the IC junction temperatures low.

Electrical power dissipated in any integrated circuit is asource of heat. This heat source increases the temperatureof the die relative to some reference point, normally the am-bient temperature of 25°C in still air. The temperature in-crease, then, depends on the amount of power dissipated inthe circuit and on the net thermal resistance between theheat source and the reference point. See page 2–6 for thecalculation of CMOS power consumption.

The temperature at the junction is a function of the packag-ing and mounting system’s ability to remove heat generatedin the circuit — from the junction region to the ambient envi-ronment. The basic formula for converting power dissipationto estimated junction temperature is:

TJ = TA + PD(θJC + θCA) ( 1 )

or

TJ = TA + PD(θJA) ( 2 )

where

TJ = maximum junction temperature

TA = maximum ambient temperature

PD = calculated maximum power dissipation includingeffects of external loads (see Power Dissipation on page 2–15).

θJC = average thermal resistance, junction to case

θCA = average thermal resistance, case to ambient

θJA = average thermal resistance, junction to ambient

This Motorola recommended formula has been approvedby RADC and DESC for calculating a “practical” maximumoperating junction temperature for MIL-M-38510 (JAN) de-vices.

Only two terms on the right side of equation ( 1 ) can bevaried by the user — the ambient temperature, and the de-vice case-to-ambient thermal resistance, θCA. (To some ex-tent the device power dissipation can also be controlled, butunder recommended use the VCC supply and loading dictatea fixed power dissipation.) Both system air flow and the pack-age mounting technique affect the θCA thermal resistanceterm. θJC is essentially independent of air flow and externalmounting method, but is sensitive to package material, diebonding method, and die area.

For applications where the case is held at essentially afixed temperature by mounting on a large or temperature-controlled heat sink, the estimated junction temperature iscalculated by:

TJ = TC + PD(θJC) ( 3 )

where TC = maximum case temperature and the other pa-rameters are as previously defined.

The maximum and average θJC resistance values for stan-dard IC packages are given in Table 2.

Table 2. Thermal Resistance Values for Standard I/C Packages

Thermal Resistance In Still Air

Package Description

No. Bod y Bod y Bod y Die Die Area Flag AreaθJC (°C/Watt)

No.Leads

BodyStyle

BodyMaterial

BodyW × L

DieBonds

Die Area(Sq. Mils)

Flag Area(Sg. Mils) Avg. Max.

14 DIL Epoxy 1/4″ × 3/4″ Epoxy 4096 6,400 38 6116 DIL Epoxy 1/4″ × 3/4″ Epoxy 4096 12,100 34 5420 DIL Epoxy 0.35″ × 0.35″ Epoxy 4096 14,400 N/A N/A

NOTES:1. All plastic packages use copper lead frames.2. Body style DIL is “Dual-In-Line.”3. Standard Mounting Method: Dual-In-Line Socket or P/C board with no contact between bottom of package and socket or P/C board.

2


2–17

AIR FLOW

The effect of air flow over the packages on θJA (due to adecrease in θCA) reduces the temperature rise of the pack-age, therefore permitting a corresponding increase in powerdissipation without exceeding the maximum permissible op-erating junction temperature.

Even though different device types mounted on a printedcircuit board may each have different power dissipations, allwill have the same input and output levels provided that eachis subject to identical air flow and the same ambient air tem-perature. This eases design, since the only change in levelsbetween devices is due to the increase in ambient tempera-tures as the air passes over the devices, or differences inambient temperature between two devices.

The majority of users employ some form of air-flow cool-ing. As air passes over each device on a printed circuitboard, it absorbs heat from each package. This heat gradientfrom the first package to the last package is a function of theair flow rate and individual package dissipations. Table 3 pro-vides gradient data at power levels of 200 mW, 250 mW, 300mW, and 400 mW with an air flow rate of 500 Ifpm. Thesefigures show the proportionate increase in the junction tem-perature of each dual in-line package as the air passes overeach device. For higher rates of air flow the change in junc-tion temperature from package to package down the air-stream will be lower due to greater cooling.

Table 3. Thermal Gradient of Junction Temperature(16-Pin Dual-In-Line Package)

Power Dissipation(mW)

Junction Temperature Gradient(°C/Package)

200 0.4

250 0.5

300 0.63

400 0.88

Devices mounted on 0.062″ PC board with Z axis spacing of 0.5″.Air flow is 500 lfpm along the Z axis.

Table 4 is graphically illustrated in Figure 43 which showsthat the reliability for plastic and ceramic devices is the sameuntil elevated junction temperatures induce intermetallic fail-ures in plastic devices. Early and mid-life failure rates of plas-tic devices are not effected by this intermetallic mechanism.

PROCEDUREAfter the desired system failure rate has been established

for failure mechanisms other than intermetallics, each device

in the system should be evaluated for maximum junctiontemperature. Knowing the maximum junction temperature,refer to Table 4 or Equation ( 1 ) on page 2–16 to determinethe continuous operating time required to 0.1% bond failuresdue to intermetallic formation. At this time, system reliabilitydeparts from the desired value as indicated in Figure 43.

Air flow is one method of thermal management whichshould be considered for system longevity. Other commonlyused methods include heat sinks for higher powered de-vices, refrigerated air flow and lower density board stuffing.Since θCA is entirely dependent on the application, it is theresponsibility of the designer to determine its value. This canbe achieved by various techniques including simulation,modeling, actual measurement, etc.

The material presented here emphasizes the need to con-sider thermal management as an integral part of system de-sign and also the tools to determine if the managementmethods being considered are adequate to produce the de-sired system reliability.

Table 4. Device Junction Temperature versusTime to 0.1% Bond Failures

JunctionTemperature °C Time, Hours Time, Years

80 1,032,200 117.8

90 419,300 47.9

100 178,700 20.4

110 79,600 9.4

120 37,000 4.2

130 17,800 2.0

140 8,900 1.0

1

1 10 100 1000

TIME, YEARS

NO

RM

ALIZ

ED F

AILU

RE

RAT

E

T J=

80C°

T J=

90C°

T J=

100

C°

T J=

110

C°

T J=

130

C°

T J=

120

C°

FAILURE RATE OF PLASTIC = CERAMICUNTIL INTERMETALLICS OCCUR

Figure 43. Failure Rate versus TimeJunction Temperature

2


2–18

CAPACITIVE LOADING EFFECTSON PROPAGATION DELAY

In addition to temperature and power–supply effects, ca-pacitive loading effects should be taken into account. Theadditional propagation delay may be calculated if the shortcircuit current for the device is known. Expected minimumnumbers may be determined from Table 5.

From the equation

Cdvci =

dt

this approximation follows:

I =C∆V

∆t

so

∆t =C∆V

I

or

∆t =I

C(0.5 VCC)

because the propagation delay is measured to the 50% pointof the output waveform (typically 0.5 VCC).

This equation gives the general form of the additional prop-agation delay. To calculate the propagation delay of a devicefor a particular load capacitance, CL, the following equationmay be used.

tPT = tP + 0.5 VCC (CL – 50 pF) / IOS

where tPT = total propagation delay

tp = specified propagation delay with 50 pF load

CL = actual load capacitance

IOS = short circuit current (Table 5)

An example is given here for tPHL of the 74HC00 driving a150 pF load.

VCC = 4.5 V

tPHL (50 pF) = 18 ns

CL = 150 pF

IOS = 17.3 mA

tPHL (150 pF) = 18 ns +(0.5)(4.5 V)(150 pF – 50 pF)

17.3 mA

= 18 ns + 13 ns

= 31 ns

Another example for CL = 0 pF and all other parameters thesame.

tPHL (0 pF) = 18 ns +(0.5)(4.5 V)(0 pF – 50 pF)

17.3 mA

= 18 ns + (– 6.5 ns)

tPHL = 11.5 ns

This method gives the expected propagation delay and is in-tended as a design aid, not as a guarantee.

Table 5. Expected Minimum Short Circuit Currents*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Standard DriversÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Bus DriversÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎÎÎ

VCCÎÎÎÎÎÎÎÎ

25CÎÎÎÎÎÎ

85CÎÎÎÎÎÎÎÎ

125CÎÎÎÎÎÎÎÎ

25CÎÎÎÎÎÎ

85CÎÎÎÎÎÎÎÎ

125CÎÎÎÎÎÎ

UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Short Circuit Source CurrentÎÎÎÎÎÎÎÎÎÎÎÎ

2.04.56.0


1.8918.535.2

ÎÎÎÎÎÎÎÎÎ

1.8315.028.0


1.8013.424.6


3.7537.070.6

ÎÎÎÎÎÎÎÎÎ

3.6430.056.1


3.6026.649.2

ÎÎÎÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Short Circuit Sink CurrentÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2.04.56.0


1.5517.333.4


1.5514.026.5


1.5512.523.2


2.4527.252.6


2.4522.141.7


2.4319.636.5


mA

* These values are intended as design aids, not as guarantees.

2


2–19

TEMPERATURE EFFECTS ONDC AND AC PARAMETERS

One of the inherent advantages of CMOS devices is thatcharacteristics of the N– and P–channel transistors, such asdrive current, channel resistance, propagation delay, andoutput transition time, track each other over a wide tempera-ture range. Figure 44 shows the temperature relationshipsfor these parameters. To illustrate the effects of temperatureon noise margin, Figure 45 shows the typical transfer char-acteristics for devices with buffered inputs and outputs. Notethat the typical switch point is at 45% of the supply voltageand is minimally affected by temperature.

The graphs in this section are intended to be design aids,not guarantees.

–50 0 50 100 1500.5

1.0

1.5

TYPI

CAL

I OH,

tPL

H, t

PHL,

t TLH

THL

C, t

, R,

NO

RM

ALIZ

ED T

O 2

5 C

VAL

UE

TA, AMBIENT TEMPERATURE (°C)

IOH, IOLRC, tPLH, tPHL, tTLH, tTHL

°

Figure 44. Characteristics of Drive Current,Channel Resistance, and AC Parameters

Over Temperature

0 1.0 2.0 3.0 4.0 5.00

1.0

2.0

3.0

4.0

5.0

V out, O

UTP

UT

VOLT

AGE

(V)

Vin, INPUT VOLTAGE (V)

VCC = 5 Vdc

TA = –55°C

VIL

TA = 125°C

TA = 25°CVIH

Figure 45. Temperature Effects on the HCTransfer Characteristics

SUPPLY VOLTAGE EFFECTS ON DRIVECURRENT AND PROPAGATION DELAY

The transconductive gain, lout/Vin, of MOSFETs is pro-portional to the gate voltage minus the threshold voltage,VG – VT. The gate voltage at the input of the final stage ofbuffered devices is approximately the power supply voltage,VCC or GND. Because VG = VCC or GND, the output drivecurrent is proportional to the supply voltage. Propagation de-lays for CMOS devices are also affected by the power supplyvoltage, because most of the delay is due to charging anddischarging internal capacitances. Figure 46 and Figure 47show the typical variation of current drive and propagationdelay, normalized to VCC = 4.5 V for 2.0 VCC 6.0 V.These curves may be used with the tables on each datasheet to arrive at parametric values over the voltage range.

2.0 3.0 4.0 5.0 6.00.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

(NO

RM

ALIZ

ED T

O 4

.5 V

NU

MBE

R)

I OH,

I OL,

TYP

ICAL

OU

TPU

T D

RIV

E C

UR

REN

T

VCC, POWER SUPPLY VOLTAGE (V)

Figure 46. Drive Current versus V CC

2.0 3.0 4.0 5.0 6.0

VCC, POWER SUPPLY VOLTAGE (V)

1.0

2.0

3.0

(NO

RM

ALIZ

ED T

O 4

.5 V

NU

MBE

R)

t PLH

, tPH

L, T

YPIC

AL P

RO

PAG

ATIO

N D

ELAY

CL = 50 pF

Figure 47. Propagation Delay versus V CC

2


2–20

DECOUPLING CAPACITORS

The switching waveforms shown in Figure 48 andFigure 49 show the current spikes introduced to the powersupply and ground lines. This effect is shown for a load ca-pacitance of less than 5 pF and for 50 pF. For ideal powersupply lines with no series impedance, the spikes wouldpose no problem. However, actual power supply and groundlines do possess series impedance, giving rise to noise prob-lems. For this reason, care should be taken in board layouts,ensuring low impedance paths to and from logic devices.

To absorb switching spikes, the following HSCMOSdevices should be bypassed with good quality 0.022 µF to0.1 µF decoupling capacitors:

1. Bypass every device driving a bus with all outputsswitching simultaneously.

2. Bypass all synchronous counters.3. Bypass devices used as oscillator elements.4. Bypass Schmitt–trigger devices with slow input rise and

fall times. The slower the rise and fall time, the larger thebypass capacitor. Lab experimentation is suggested.

Bypass capacitors should be distributed over the circuitboard. In addition, boards could be decoupled with a 1 µFcapacitor.

BUFFERED DEVICE: INPUT tr, tf ≤ 500 ns, CL < 5 pF

I GN

DI C

CV

out

Figure 48. Switching Currents for C L < 5 pF

BUFFERED DEVICE: INPUT tr, tf ≤ 500 ns, CL < 5 pF

I GN

DI C

CV

out

Figure 49. Switching Currents for C L = 50 pF

INTERFACING

HSCMOS devices have a wide operating voltage range(VCC = 2 to 6 V) and sufficient current drive to interface withmost other logic families available today. In this section, vari-ous interface schemes are given to aid the designer (seeFigure 50 through Figure 55). The various types of CMOSdevices with their input/output levels and comments are giv-en in Table 6.

Motorola presently has available several CMOS memoriesand microprocessors (see Table 7) which are designed to di-rectly interface with High–Speed CMOS. With these devicesnow available, the designer has an attractive alternative toLSTTL/NMOS, and a total HSCMOS system is now possible.(See SG102, CMOS System IC Selection Guide, for more in-formation.)

Device designators are as follows:HC This is a high–speed CMOS device with CMOS input

switching levels and buffered CMOS outputs. Thenumbering of devices with this designator follows theLSTTL numbering sequence. These devices arefunctional and pinout equivalents of LSTTL devices(e.g., HC00, HC688, etc.). Exceptions to this aredevices that are functional and pinout equivalents tometal–gate CMOS devices (e.g., HC4002, HC4538A,etc.).

HCU This is an unbuffered high–speed CMOS device withonly one stage between the input and output. Becausethis is an unbuffered device, input and output levelsmay differ from buffered devices. At present, thefamily contains only one unbuffered device, theHCU04A.

HCT This is a high–speed CMOS device with an LSTTL–to–CMOS input buffer stage. These devices aredesigned to interface with LSTTL outputs operating atVCC = 5 V ± 10%. HCT devices have fully bufferedCMOS outputs that directly drive HSCMOS or LSTTLdevices.

VCC

GNDHC OR HCT

DEVICEDIRECT

INTERFACELSTTL

DEVICE

Figure 50. HC to LSTTL Interfacing

VCC

GNDLSTTL

DEVICEDIRECT

INTERFACEHCT

DEVICE

Figure 51. LSTTL to HCT Interfacing

2


2–21

VCC

GNDHC

DEVICEPULL-UP

RESISTORLSTTL

DEVICE

Figure 52. LSTTL to HC Interfacing

5 V

GNDHC

DEVICEHC4049

ORHC4050

LSTTLDEVICE

3 V

GND

Figure 53. LSTTL to Low–Voltage HSCMOS

VDD = 3 –15 V* VCC = 2 – 6 V

GNDHC

DEVICEMC14049UB/14050B

ORHC4049/HC4050

STANDARDCMOS

*VOH must be greater than VIH of low voltage Device;VDD = 3–18 V may be used if interfacing to 14049UB/14050B.

Figure 54. High Voltage CMOS to HSCMOS

HSCMOS/ STANDARD CMOS

STANDARD CMOS/HSCMOS

MC14504B

VCC/VDD VDD/VCC

LEVELSHIFTER

GND

GND

Figure 55. Up/Down Level Shifting Usingthe MC14504B

Table 6. Interfacing Guide

ÎÎÎÎÎÎÎÎÎÎ

Device ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Level ÎÎÎÎÎÎÎÎÎÎ

Output Level ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Comments


HCXXX ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOS ÎÎÎÎÎÎÎÎÎÎ

CMOS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

LSTTL Functional and Pinout Equivalent Devices


HC4XXX ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



CMOS Functional and Pinout Equivalent Devices


HCUXX ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



Used in Linear ApplicationsÎÎÎÎÎÎÎÎÎÎHCTXXX

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎTTL

ÎÎÎÎÎÎÎÎÎÎCMOS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHSCMOS Device with TTL–to–CMOS Input BufferingÎÎÎÎÎ


HC4049,HC4050

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

– 0.5 Vin 15 VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

High–to–Low Level Translators, CMOS Switching Levels

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC14049UBMC14050B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

– 0.5 Vin 18 V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Metal–Gate CMOS High–to–Low Level Translators, CMOS Switching Levels


MC14504BÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOS or TTL ÎÎÎÎÎÎÎÎÎÎ


Metal–Gate CMOS High–to–Low or Low–to–High Level Translator

Table 7. CMOS Memories and Microprocessors


CMOSMemories

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCMOS MicroprocessorsÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MCM6147MCM61L47MCM68HC34

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC68HC01 MC146805G2MC68HC03 MC146805H2MC68HC11A8 MC1468705F2MC68HC11D4 MC1468705G2MC68HC811A2 MC68HC05C4MC68HC811D4 MC68HSC05C4MC68HC04P3 MC68HC05C8MC146805E2 MC68HC805C4MC146805F2 MC68HC000

RECOMMENDED READING

S. Craig, “Using High–Speed CMOS Logic for Micropro-cessor Interfacing”, Application Note–868, Motorola Semi-conductor Products Inc., 1982.

2


2–22

TYPICAL PARAMETRIC VALUES

Given a fixed voltage and temperature, the electrical char-acteristics of High–Speed CMOS devices depend primarilyon design, layout, and processing variations inherent insemiconductor fabrication.

A preliminary evaluation of each device type essentiallyguarantees that the design and layout of the device conformsto the criteria and standards set forth in the design goals.With very few exceptions, device electrical parameters, onceestablished, do not vary due to design and layout.

Of much more concern is processing variation. A digitalprocessing line is allowed to deviate over a fairly broad pro-cessing range. This allows the manufacturer to incur reducedprocessing costs. These reduced processing costs arepassed on to the consumer in the form of lower deviceprices.

Processing variation is the range from worst case to bestcase processing and is defined as the process window. Thiswindow is established with the aid of statistical process con-trol (SPC). With SPC, when a processing parameter ap-proaches the process window limit, that parameter isadjusted toward the middle of the window. This keeps pro-cess variations within a predetermined tolerance.

Motorola characterizes each device type over this processwindow. Each device type is characterized by allowing ex-perimental lots to be processed using worst case and bestcase processing. The worst case processed lots usually de-termine the minimum or maximum guaranteed limit. (Wheth-er the limit is a guaranteed minimum or maximum dependson the particular parameter being measured.)

In production, these limits are guaranteed by probe and fi-nal test and therefore appear independent of process varia-

tion to the end user. However, this does not hold true for themean value of the total devices processed. The mean value,commonly referred to as a typical value, shifts over proces-sing and therefore varies from lot to lot or even wafer to waferwithin a lot.

As with all processing or manufacturing, the total devicesbeing produced fit the normal distribution or bell curve ofFigure 56. In order to guarantee a valid typical value, a typi-cal number plus a tolerance, would have to be specified andtested (see Figure 57). However, this would greatly increaseprocessing costs which would have to be absorbed by theconsumer.

In some cases, the device’s actual values are so small thatthe resolution of the automatic test equipment determinesthe guaranteed limit. An example of this is quiescent supplycurrent and input leakage current.

Most manufacturers provide typical numbers by one of twomethods. The first method is to simply double or halve, de-pending on the parameter, the guaranteed limit to determinea typical number. This would theoretically put all processedlots in the middle of the process window. Another approachto typical numbers is to use a typical value that is derivedfrom the aforementioned experimental lots. However, neithermethod accurately reflects the mean value of devices anyone consumer can expect to receive.

Therefore, the use of typical parametric numbers for de-sign purposes does not constitute sound engineering designpractice. Worst case analysis dictates the use of guaranteedminimum or maximum values. The only possible exceptionwould be when no guaranteed value is given. In this case atypical value may be used as a ballpark figure.

REJECTREGION

REJECTREGION

MINLIMIT

MAXLIMIT

(a) (b)

REJECTREGION

MINVALUE REJECT

REGION

MAXVALUE

MEAN (TYP)VALUE

Figure 56.

Figure 57.

2


2–23

REDUCTION OF ELECTROMAGNETICINTERFERENCE (EMI)

Electromagnetic interference (EMI) and radio frequencyinterference (RFI) are phenomena inherent in all electricalsystems covering the entire frequency spectrum. Althoughthe characteristics have been well documented, EMI remainsdifficult to deal with due to numerous variables. EMI shouldbe considered at the beginning of a design, and taken intoaccount during all stages, including production and beyond.

These entities must be present for EMI to be a factor: (1) asource of EMI, (2) a transmission medium for EMI, and (3) areceiver of EMI. Several sources include relays, FM transmit-ters, local oscillators in receivers, power lines, engine igni-tions, arc welders, and lighting. EMI transmission pathsinclude ground connections, cables, and the space betweenconductors. Some receivers of EMI are radar receivers, com-puters, and television receivers.

For microprocessor based equipment, the source of emis-sions is usually a current loop on a PC board. The chips andtheir associated loop areas also function as receivers of EMI.The fact is that PC boards which radiate high levels of EMIare also more likely to act as receivers of EMI.

All logic gates are potential transmitters and receivers ofemissions. Noise immunity and noise margin are two criteri-on which measure a gate’s immunity to noise which could becaused by EMI. CMOS technology, as opposed to the othercommonly used logic families, offers the best value for noisemargin, and is therefore an excellent choice when consider-ing EMI.

The electric and magnetic fields associated with ICs areproportional to the current used, the current loop area, andthe switching transition times. CMOS technology is preferreddue to smaller currents. Also, the current loop area can bereduced by the use of surface mount packages.

In a system where several pieces of equipment are con-nected by cables, at least five coupling paths should be tak-en into account to reduce EMI. They are: (1) common groundimpedance coupling (a common impedance is shared be-tween an EMI source and receiver), (2) common–mode,field–to–cable coupling (electromagnetic fields enter the loopfound by two pieces of equipment, the cable connectingthem, and the ground plane), (3) differential–mode, field–to–cable coupling (electromagnetic fields enter the loop formedby two pieces of equipment and the cable connecting them),(4) crosstalk coupling (signals in one transmission line arecoupled into another transmission line), and (5) a conductivepath through power lines.

Shielding is a means of reducing EMI. Some of the morecommonly used shields against EMI and RFI contain stain-less steel fiber–filled polycarbonate, aluminum flake–filledpolycarbonate/ABS coated with nickel and copper electroly-sis plating or cathode sputtering, nickel coated graphite fiber,

and polyester SMC with carbon–fiber veil. Several manufac-turers who make conductive compounds and additives arelisted below.

SHIELDING MANUFACTURERS

General Electric Co., Plastics Group, Pittsfield, MA

Mobay Chemical Corp., Pittsburgh, PA

Wilson–Fiberfil International, Evansville, IN

American Cyanamid Co., Wayne, NJ

Fillite U.S.A., Inc., Huntington, WV

Transnet Corp., Columbus, OH

Motorola does not recommend, or in any way warrant themanufacturers listed here. Additionally, no claim is made thatthis list is by any means complete.

RECOMMENDED READING

D. White, K. Atkinson, and J. Osburn, “Taming EMI in Micro-processor Systems”, IEEE Spectrum, Vol. 22, Number 12,Dec. 1985.

D. White and M. Mardiguian, EMI Control Methodology andProcedures, 1985.

H. Denny, Grounding for the Control of EMI.

M. Mardiguian, How to Control Electrical Noise.

D. White, Shielding Design Methodology and Procedures.

For more information on this subject, contact:

Interference Control TechnologiesDon White Consultants, Inc., SubsidiaryState Route 625P.O. Box DGainesville, VA 22065

HYBRID CIRCUIT GUIDELINES

High–Speed CMOS devices, when purchased in chip (die)form, are useful in hybrid circuits. Most high–speed devicesare fabricated with P wells and N substrates. Therefore, thesubstrates should be tied to VCC (+ supply).

Several devices however, are fabricated with N wells andP substrates. In this case, the substrates should be tied toGND. The best solution to alleviate confusion about the sub-strate is the use of nonconductive or insulative substrates.This averts the necessity of tying the substrate off to eitherVCC or GND.

For more information on hybrid technology, contact:

International Society for Hybrid MicroelectronicsP.O. Box 3255Montgomery, AL 36109

2


2–24

SCHMITT–TRIGGER DEVICES

Schmitt–trigger devices exhibit the effect of hysteresis.Hysteresis is characterized by two different switching thresh-old levels, one for positive–going input transitions and theother for negative–going input transitions.

Schmitt triggers offer superior noise immunity whencompared to standard gates and inverters. Applications forSchmitt triggers include line receivers, sine to square waveconverters, noise filters, and oscillators. Motorola offers sixversatile Schmitt–trigger devices in the High–Speed CMOSlogic family (see Table 8).

The typical voltage transfer characteristics of a standardCMOS inverter and a CMOS Schmitt–trigger inverter arecompared in Figure 58 and Figure 59. The singular transferthreshold of the standard inverter is replaced by two distinctthresholds in a Schmitt–trigger inverter. During a positive–going transition of Vin, the output begins to go low after theVT+ threshold is reached. During a negative–going Vin transi-tion, Vout begins to go high after the VT– threshold is reached.The difference between VT+ and VT– is defined as VH, thehysteresis voltage.

As a direct result of hysteresis, Schmitt–trigger circuitsprovide excellent noise immunity and the ability to square up

signals with long rise and fall times. Positive–going inputnoise excursions must rise above the VT+ threshold beforethey affect the output. Similarly, negative–going input noiseexcursions must drop below the VT– threshold before they af-fect the output.

The HC132A can be used as a direct replacement for theHC00A NAND gate, which does not have Schmitt–trigger ca-pability. The HC132A has the same pin assignment as theHC00A. Schmitt–trigger logic elements act as standard logicelements in the absence of noise or slow rise and fall times,making direct substitution possible.

Versatility and low cost are attractive features of CMOSSchmitt triggers. With six Schmitt triggers per HC14A pack-age, one trigger can be used for a noise elimination applica-tion while the other five function as standard inverters.Similarly, each of the four triggers in the HC132A can beused as either Schmitt triggers or NAND gates or some com-bination of both.

Table 8. Schmitt–Trigger Devices


HC14AHCT14AHC132A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Hex Schmitt–Trigger InverterHex Schmitt–Trigger Inverter with LSTTL InputsQuad 2–Input NAND Gate with Schmitt–Trigger

Inputs

VCC

Vout

0 Vin VCC

Figure 58. Standard Inverter Transfer Characteristic

VH

VCC

Vout

0 Vin VCC

VT– VT+

Figure 59. Schmitt–Trigger Inverter Transfer Characteristic

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OSCILLATOR DESIGN WITH HIGH–SPEED CMOS

Oscillator design is a fundamental requirement of manysystems and several types are discussed in this section. Ingeneral, an oscillator is comprised of two parts: an active net-work and a feedback network. The active network is usuallyin the form of an amplifier, or an unbuffered inverter, such asthe HCU04. The feedback network is mainly comprised of re-sistors, capacitors, and depending upon the application, aquartz crystal or ceramic resonator.

Buffered inverters are never recommended in oscillatorapplications due to their high gain and added propagationdelay. For this reason Motorola manufactures the HCU04,which is an unbuffered hex inverter.

Oscillators for use in digital systems fall into two generalcategories, RC oscillators and crystal or ceramic resonatoroscillators. Crystal oscillators have the best performance, butare more costly, especially for nonstandard frequencies. RCoscillators are more useful in applications where stability andaccuracy are not of prime importance. Where high perfor-mance at low frequencies is desired, ceramic resonators aresometimes used.

RC OSCILLATORS

The circuit in Figure 60 shows a basic RC oscillator usingthe HCU04. When the input voltage of the first inverter reach-es the threshold voltage, the outputs of the two inverterschange state, and the charging current of the capacitorchanges direction. The frequency at which this circuit oscil-lates depends upon R1 and C. The equation to calculatethese component values is given in Figure 60.

1/6 HCU04 1/6 HCU04 BUFFER

R2 R1 C 2R1 R2 10 R1C 100 pF1 k R1 1 M

fOSC1

2.3 R1•C

Vout

Figure 60. RC Oscillator

Certain constraints must be met while designing this typeof oscillator. Stray capacitance and inductance must be keptto a minimum by placing the passive components as close tothe chip as possible. Also, at higher frequencies, theHCU04’s propagation delay becomes a dominant effect andaffects the cycle time. A polystyrene capacitor is recom-mended for optimum performance.

CRYSTAL OSCILLATORS

Crystal oscillators provide the required stability and accu-racy which is necessary in many applications. The crystalcan be modeled as shown in Figure 62.

The power dissipated in a crystal is referred to as the drivelevel and is specified in mW. At low drive levels, the resonantresistance of the crystal can be so large as to cause start–upproblems. To overcome this problem, the amplifier (inverter)should provide enough amplification, but not too much as tooverdrive the crystal.

Figure 61 shows a Pierce crystal oscillator circuit, which isa popular configuration with CMOS.

OSCout2OSCin

Rf

1/6 HCU04 1/6 HCU04

OSCout1

BUFFER

R1

C1 C2

Figure 61. Pierce Crystal Oscillator Circuit

Choosing R1

Power is dissipated in the effective series resistance of thecrystal. The drive level specified by the crystal manufactureris the maximum stress that a crystal can withstand withoutdamage or excessive shift in frequency. R1 limits the drivelevel.

Values are supplied by the crystal manufacturer(parallel resonant crystal)

1 2 1 2 1 2Re Xe

Rs Ls Cs

Co

Figure 62. Equivalent Crystal Networks

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To verify that the maximum dc supply voltage does notoverdrive the crystal, monitor the output frequency at OSCOut 2. The frequency should increase very slightly as the dcsupply voltage is increased. An overdriven crystal decreasesin frequency or becomes unstable with an increase in supplyvoltage. The operating supply voltage must be reduced or RImust be increased in value if the overdriven condition exists.The user should note that the oscillator start–up time is pro-portional to the value of R1.

Selecting R fThe feedback resistor (Rf) typically ranges up to 20 MD. Rf

determines the gain and bandwidth of the amplifier. Properbandwidth ensures oscillation at the correct frequency plusroll–off to minimize gain at undesirable frequencies, such asthe first overtone. Rf must be large enough so as not to affectthe phase of the feedback network in an appreciable manner.

RECOMMENDED READING

D. Babin, “Designing Crystal Oscillators”, Machine Design,March 7, 1985.D. Babin, “Guidelines for Crystal Oscillator Design”, MachineDesign, April 25, 1985.

PRINTED CIRCUIT BOARD LAYOUT

Noise generators on the power supply lines should bedecoupled. The two major sources of noise on the power

supply lines are peak current in output stages during switch-ing and the charging and discharging of parasitic capaci-tances.

A good power distribution network is essential before de-coupling can provide any noise reduction. Avoid using jump-ers for ground and power connections; the inductance theyintroduce into the lines permits coupling between outputs.Therefore, use of PC boards with premanufactured groundconnections is advised to connect the device pins to ground.

However, the optimum solution is to use multi–layer PCboards where different layers are used for the supply railsand interconnections. Even with double–sided boards, plac-ing the power and ground lines on opposite sides of theboard whenever possible is recommended. The multi–wireboard is a less expensive approach than the multi–layer PCboard, while retaining the same noise reduction characteris-tics. As a rule of thumb, there should be several ground pinsper connector to give good ground distribution.

The precautions for ground lines also apply to VCC lines:1) separate power stabilization for each board; 2) isolatenoise sources; and 3) avoid the use of large, single voltageregulators.

After all of these precautions, decoupling is an added mea-sure to reduce supply noise. See the Decoupling Capaci-tors section.

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Definitions and Glossary of Terms


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HC vs. HCT

Motorola’s High–Speed CMOS is intended to give the de-signer an alternative to LSTTL. HSCMOS, with the fasterspeed advantage over metal–gate CMOS (MC14000 series)and the lower power consumption advantage over LSTTL, isan optimum choice for new midrange designs. With the ad-vent of high–speed CMOS microprocessors and memories,the ability to design a 100% CMOS system is now possible.

HCT devices offer a short–term solution to the TTL/NMOS–to–CMOS interface problem. To achieve this in-terface capability, some CMOS advantages had to becompromised. These compromises include power consump-tion, operating voltage range, and noise immunity.

In most cases HCT devices are drop–in replacements ofTTL devices with significant advantages over the TTL de-vices. However, in some cases, an equivalent HCT devicemay not replace a TTL device without some form of circuitmodification.

The wise designer uses HCT devices to perform logic levelconversions only. In new designs, the designer wants all theadvantages of a true CMOS system and designs using onlyHC devices.

“A” versus “Non–A”

“A” Versus “Non–A” — Motorola has an on–going de-vice performance enhancement program for the Hi–SpeedCMOS family. This is indicated by the “A” suffix of the deviceidentification. Some of the characteristics of this “A”enhancement program are improved design, a better qualityprocess, faster performing AC propagation delays and en-hancements to various DC characteristics.

The old “Non–A” process was a 5 micron process that wasmodified to run a 3.5 micron family. The new “A” process is atrue 3 micron process and gives better process control, withimproved performance and quality.

GLOSSARY OF TERMS

Cin Input Capacitance — The parasitic capacitanceassociated with a given input pin.

CL Load Capacitance — The capacitor value which loadseach output during testing and/or evaluation. Thiscapacitance is assumed to be attached to each output ina system. This includes all wiring and stray capacitance.

Cout Output Capacitance — The capacitance associatedwith a three–state output in the high–impedance state.

CPD Power Dissipation Capacitance — Used to determinedevice dynamic power dissipation, i.e., PD = CPDVCC2f+ VCCICC. See POWER SUPPLYSIZING for a discussion of CPD.

fmax Maximum Clock Frequency — The maximum clock-ing frequency attainable with the following input andoutput conditions being met:

Input Conditions — (HC) tr = tf = 6 ns, voltageswing from GND to VCC with 50% duty cycle. (HCT) tr =tf = 6 ns, voltage swing from GND to 3.0 V with 50% dutycycle.

Output Conditions — (HC and HCT) waveform mustswing from 10% of (VOH – VOL) to 90% of(VOH – VOL) and be functionally correct under the givenload condition: CL = 50 pF, all outputs.

VCC Positive Supply Voltage — + dc supply voltage(referenced to GND). The voltage range over which ICsare functional.

Vin Input Voltage — DC input voltage (referenced to GND).

Vout Output Voltage — DC output voltage (referenced toGND).

VIH Minimum High Level Input Voltage — The worst casevoltage that is recognized by a device as the HIGHstate.

VIL Maximum Low Level Input Voltage — The worst casevoltage that is recognized by a device as the LOW state.

VOH Minimum High Level Output Voltage — The worstcase high–level voltage at an output for a given outputcurrent (lout) and supply voltage (VCC).

VOL Maximum Low Level Output Voltage — The worstcase low–level voltage at an output for a given outputcurrent (lout) and supply voltage (VCC).

VT+ Positive–Going Input Threshold Voltage — Theminimum input voltage of a device with hysteresis whichis recognized as a high level. (Assumes ramp up fromprevious low level.)

VT– Negative–Going Input Threshold Voltage — Themaximum input voltage of a device with hysteresiswhich is recognized as a low level. (Assumes rampdown from previous high level).

VH Hysteresis Voltage — The difference between VT+ andVT– of a given device with hysteresis. A measure ofnoise rejection.

ICC IC Quiescent Supply Current — The current into theVCC pin when the device inputs are static at VCC or GNDand outputs are not connected.

∆ICC Additional Quiescent Supply Current — The currentinto the VCC pin when one of the device inputs is at 2.4 Vwith respect to GND and the other inputs are static atVCC or GND. The outputs are not connected.

Iin Input Current — The current into an input pin with therespective input forced to VCC or GND. A negative signindicates current is flowing out of the pin (source). Apositive sign or no sign indicates current is flowing intothe pin (sink).

lout Output Current — The current out of an output pin. Anegative sign indicates current is flowing out of the pin(source). A positive sign or no sign indicates current isflowing into the pin (sink).

IIH Input Current (High) — The input current when theinput voltage is forced to a high level.

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Definitions and Glossary of Terms


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IIL Input Current (Low) — The input current when theinput voltage is forced to a low level.

IOH Output Current (High) — The output current when theoutput voltage is at a high level.

IOL Output Current (Low) — The output current when theoutput voltage is at a low level.

IOZ Three–State Leakage Current — The current into orout of a three–state output in the high–impedance statewith that respective output forced to VCC or GND.

tPLH Low–to–High Propagation Delay (HC) — The timeinterval between the 0.5 VCC level of the controllinginput waveform and the 50% level of the outputwaveform, with the output changing from low level tohigh level. (HCT) — The time interval between the 1.3 Vlevel (with respect to GND) of the controlling inputwaveform and the 1.3 V level (with respect to GND) ofthe output waveform, with the output changing from lowlevel to high level.

tPHL High–to–Low Propagation Delay (HC) — The timeinterval between the 0.5 VCC level of the controllinginput waveform and the 50% level of the outputwaveform, with the output changing from high level tolow level. (HCT) — The time interval between the 1.3 Vlevel (with respect to GND) of the controlling inputwaveform and the 1.3 V level (with respect to GND) ofthe output waveform, with the output changing from highlevel to low level.

tPLZ Low–Level to High–Impedance Propagation Delay(Disable Time) — The time interval between the 0.5VCC level for HC devices (1.3 V with respect to GND forHCT devices) of the controlling input waveform and the10% level of the output waveform, with the outputchanging from the low level to high–impedance (off)state.

tPHZ High–Level to High–impedance Propagation Delay(Disable Time) — The time interval between the 0.5VCC level for HC devices (1.3 V with respect to GND forHCT devices) of the controlling input waveform and the90% level of the output waveform, with the outputchanging from the high level to high–impedance (off)state.

tPZL High–Impedance to Low–Level Propagation Delay(Enable Time) — The time interval between 0.5 VCClevel (HC) or 1.3 V level with respect toGND (HCT) of the controlling input waveform and the50% level (HC) or 1.3 V level with respect to GND (HCT)of the output waveform, with the output changing fromthe high–impedance (off) state to a low level.

tPZH High–Impedance to High–Level Propagation Delay(Enable Time) — The time interval between the 0.5VCC level (HC) or 1.3 V level with respectto GND (HCT) of the controlling input waveform and the50% level (HC) or 1.3 V level with respect to GND (HCT)of the output waveform, with the output changing fromthe high–impedance (off) state to a high level.

tTLH Output Low–to–High Transition Time — The timeinterval between the 10% and 90% voltage levels of therising edge of a switching output.

tTHL Output High–to–Low Transition Time — The timeinterval between the 90% and 10% voltage levels of thefalling edge of a switching output.

tsu Setup Time — The time interval immediately preceed-ing the active transition of a clock or latch enable input,during which the data to be recognized must bemaintained (valid) at the input to ensure proper recogni-tion. A negative setup time indicates that the data at theinput may be applied sometime after the active clock orlatch transition and still be recognized. For HC devices,the setup time is measured from the 50% level of thedata waveform to the 50% level of the clock or latchinput waveform. For HCT devices, the setup time ismeasured from the 1.3 V level (with respect to GND) ofthe data waveform to the 1.3 V level (with respect toGND) of the clock or latch input waveform.

th Hold Time — The time interval immediately followingthe active transition of a clock or latch enable input,during which the data to be recognized must bemaintained (valid) at the input to ensure proper recogni-tion. A negative hold time indicates that the data at theinput may be changed prior to the active clock or latchtransition and still be recognized. For HC devices, thehold time is measured from the 50% level of the clock orlatch input waveform to the 50% level of the datawaveform. For HCT devices, the hold time is measuredfrom the 1.3 V level (with respect to GND) of the clock orlatch input waveform to the 1.3 V level (with respect toGND) of the data waveform.

trec Recovery Time (HC) — The time interval between the50% level of the transition from active to inactive state ofan asynchronous control input and the 50% level of theactive clock or latch enable edge required to guaranteeproper operation of a device. (HCT) — The time intervalbetween the 1.3 V level (with respect to GND) of thetransition from active to inactive state of an asynchro-nous control input and the 1.3 V level (with respect toGND) of the active clock or latch edge required toguarantee proper operation of a logic device.

tw Pulse Width (HC) — The time interval between 50%levels of an input pulse required to guarantee properoperation of a logic device. (HCT) — The time intervalbetween 1.3 V levels (with respect to GND) of an inputpulse required to guarantee proper operation of a logicdevice.

tr Input Rise Time (HC) — The time interval between the10% and 90% voltage levels on the rising edge of aninput signal. (HCT) — The time interval between the 0.3V level and 2.7 V level (with respect to GND) on therising edge of an input signal.

tf Input Fall Time (HC) — The time interval between the90% and 10% voltage levels on the falling edge of aninput signal. (HCT) — The time interval between the 2.7V level and 0.3 V level (with respect to GND) on thefalling edge of an input signal.

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