Introducing the 68HC12

Design of Embedded Systems Using 68HC12(11) Microcontrollers - R. E. Haskell

Introducing the 68HC12

Chapter 1



• From Microprocessors to Microcontrollers

• The 68HC12 Registers

• Writing Programs for the 68HC12

• Addressing Modes


A microprocessor (CPU)connected to external memory

Address Bus

Data Bus

RAM

ROM

I/O

CPU

(registers)


The 68HC11

RAM CPU EEPROMROM/ EPROM

TIMER

PARALLEL I/O SPI SCI

A/D

68HC11


Selected 68HC11 Parts

Part No. ROM/EPROM RAM EEPROM I/O Timer A/D68HC11A8 8K 256 512 38 3 IC, 5 OC Yes68HC11D0 0 192 0 14 3/4 IC, 4/5 OC No68HC711D3 4K 192 0 32 3/4 IC, 4/5 OC No68HC711E9 12K 512 512 38 3/4 IC, 4/5 OC Yes68HC711K4 24K 768 640 62 3/4 IC, 4/5 OC Yes


68HC11 ApplicationsConsumer

TelevisionsVCRsCable BoxesCamcodersCamerasSecurity Systems

Home Video Game SystemsCompact Disc PlayersDigital Audio SystemsDigital RadioAppliances

Office AutomationModemsTypewritersSmart FurnitureHard Disk Drives

Tape DrivesMonitorsKeyboardsScanners

CommunicationsHandheld RadiosCellular TelephonesCordless TelephonesDigital Telephones

Telephone SwitchingAnalog TelephonesAnswering MachinesPagers


68HC11 ApplicationsIndustrial Control and Instrumentation

ElevatorsTraffic ControlMeter ReadingATM MachinesVending MachinesCard ReadersBar Code ReadersManufacturing TrackingProcess Control

Fire ControlSecurity SystemsLighting ControlNoise ControlGas FurnacesBlood Pressure MonitorsBlood AnalyzersGlucose MonitorsGas Analyzers

AutomotiveInstrument DisplaysInjection SystemsEmission ControlEngine ControlClimate Control

Cruise ControlActive SuspensionAnti-lock Braking Systems (ABS)Air BagsAutomatic Seat Belts








The 68HC12 Registers

S X H I N Z V C

A B

D

IX

IY

SP

PC

Accum ulator A

Accum ulator D

Inde x register X

Inde x register Y

Sta ck Pointer

Pro gra m counter

Condition code register

Accum ulator B


Load and Store Instructions:LDAA Load A from memoryLDAB Load B from memoryLDD Load D from memorySTAA Store A to memorySTAB Store B to memorySTD Store D to memory

Transfer and Exchange Instructions:TAB Transfer A to BTBA Transfer B to AEXG A,B Exchange A and B

The 68HC12 Accumulators


Addition and Subtraction Instructions:ABA Add B to AADDA Add memory to AADDB Add memory to BADCA Add memory with carry to AADCB Add memory with carry to BADDD Add memory to DSBA Subtract B from ASUBA Subtract memory from ASUBB Subtract memory from BSBCA Subtract memory with borrow from ASBCB Subtract memory with borrow from BSUBD Subtract memory from D

Decrement and Increment Instructions:DECA Decrement ADECB Decrement BINCA Increment AINCB Increment B


Compare and Test Instructions:CBA Compare A to BCMPA Compare A to memoryCMPB Compare B to memoryCPD Compare D to memoryTSTA Test A for zero or minusTSTB Test B for zero or minus

Boolean Logic Instructions:ANDA AND A with memoryANDB AND B with memoryEORA Exclusive OR A with memoryEORB Exclusive OR B with memoryORAA OR A with memoryORAB OR B with memory


Shift and Rotate Instructions:LSLA Logic shift left ALSLB Logic shift left BLSLD Logic shift left DLSRA Logic shift right ALSRB Logic shift right BLSRD Logic shift right DASLA Arithmetic shift left AASLB Arithmetic shift left BASLD Arithmetic shift left DASRA Arithmetic shift right AASRB Arithmetic shift right BROLA Rotate left A through carryROLB Rotate left B through carryRORA Rotate right A through carryRORB Rotate right B through carry


Stacking Instructions:PSHA Push APSHB Push BPSHD Push DPULA Pull APULB Pull BPULD Pull D

Clear, Complement, and Negate Instructions:CLRA Clear ACLRB Clear BCOMA One's complement ACOMB One's complement BNEGA Two's complement ANEGB Two's complement B


Index Registers, X and YLoad and Store Instructions:

LDX Load X from memoryLDY Load Y from memorySTX Store X to memorySTY Store Y to memoryLEAX Load effective address into XLEAY Load effective address into Y

Transfer and Exchange Instructions:EXG X,Y Exchange X and YXGDX Exchange D with XXGDY Exchange D with Y


Addition and Subtraction Instructions:ABX Add B to XABY Add B to Y

Decrement and Increment Instructions:DEX Decrement XDEY Decrement YINX Increment XINY Increment Y

Compare and Test Instructions:CPX Compare X to memoryCPY Compare Y to memory

Stacking Instructions:PSHX Push XPSHY Push YPULX Pull XPULY Pull Y


Stack Pointer, SP

Load and Store Instructions:LDS Load SP from memorySTS Store SP to memoryLEAS Load effective address into SP

Transfer and Exchange Instructions:TSX Transfer SP to XTSY Transfer SP to YTXS Transfer X to SPTYS Transfer Y to SPEXG X,SP Exchange X and SP


Decrement and Increment Instructions:DES Decrement SPINS Increment SP

Compare and Test Instructions:CPS Compare SP to memoryCPY Compare Y to memory


Condition Code Register

H VNS X I Z C

7 6 5 4 3 2 1 0

Overflow

Stop disable

X - Interrupt mask

Negative

ZeroHalf carry

Carry

Interrupt mask








; Example 1 - Chapter 1

ORG $800SUM DW 0DIFF DW 0 ORG $810EX1 LDD #1234 ADDD #5678 STD SUM ;add 1234+5678 LDD #5678 SUBD #1234 STD DIFF ;subtract 5678-1234 END

as12 chap1a.asm >chap1a.lst


; Example 1 - Chapter 10800 ORG $8000800 00 00 SUM DW 00802 00 00 DIFF DW 00810 ORG $810 EX10810 cc 04 d2 LDD #12340813 c3 16 2e ADDD #56780816 7c 08 00 STD SUM ;add 1234+56780819 cc 16 2e LDD #5678081c 83 04 d2 SUBD #1234081f 7c 08 02 STD DIFF ;subtract 5678-1234 END

S014000046696C653A206368617031612E61736D0A6AS107080000000000F0S1130810CC04D2C3162E7C0800CC162E8304D27CC2S10508200802C8S9030000FC

chap1a.lst

chap1a.s19


Downloading a .S10 fileusing HOST.EXE

C:\WHYP\WHYP12\ASM>host

Terminal host...9600 baud(Press F10 to check/change COM port)(Press F6 to download .S19 file)(Press F4 to download .S19 file with * handshake)(Press <Esc> to exit HOST)

>load

Enter .s19 filename to download: chap1a.s19

Getting data...S014000046696C653A206368617031612E61736D0A6AS107080000000000F0S1130810CC04D2C3162E7C0800CC162E8304D27CC2S10508200802C8S9030000FC.Finished downloading...*>


D-Bug12 commands

>md 800 820

0800 00 00 00 00 - 52 00 80 02 - 09 00 28 18 - 90 00 83 00 ....R.....(.....0810 CC 04 D2 C3 - 16 2E 7C 08 - 00 CC 16 2E - 83 04 D2 7C ......|........|0820 08 02 00 00 - 0C 00 40 00 - 42 00 08 00 - 10 00 0C 08 [email protected].......

>rd

PC SP X Y D = A:B CCR = SXHI NZVC0000 0A00 0000 0000 11:5C 1001 0000>rm

PC=0000 810

SP=0A00 .

>rd

PC SP X Y D = A:B CCR = SXHI NZVC0810 0A00 0000 0000 11:5C 1001 0000>


>t

PC SP X Y D = A:B CCR = SXHI NZVC0813 0A00 0000 0000 04:D2 1001 00000813 C3162E ADDD #$162E>t

PC SP X Y D = A:B CCR = SXHI NZVC0816 0A00 0000 0000 1B:00 1001 00000816 7C0800 STD $0800>t

PC SP X Y D = A:B CCR = SXHI NZVC0819 0A00 0000 0000 1B:00 1001 00000819 CC162E LDD #$162E>t

PC SP X Y D = A:B CCR = SXHI NZVC081C 0A00 0000 0000 16:2E 1001 0000081C 8304D2 SUBD #$04D2>t

PC SP X Y D = A:B CCR = SXHI NZVC081F 0A00 0000 0000 11:5C 1001 0000081F 7C0802 STD $0802>t

PC SP X Y D = A:B CCR = SXHI NZVC0822 0A00 0000 0000 11:5C 1001 00000822 00 BGND>


>mdw 800 810

0800 1B00 115C - 5200 8002 - 0900 2818 - 9000 8300 ...\R.....(.....0810 CC04 D2C3 - 162E 7C08 - 00CC 162E - 8304 D27C ......|........|

>

sum difference








1234

1232

X

X

56

78

56

78

56

78

MOVW 0,X,2,-X

1234

1232

Before After

Pre-decrement indexed addressing


Table 1.3 68HC12 Addressing ModesAddressing Mode Description Examples

Inherent Data location is inherent in instruction INXDECB

Immediate Data immediately follows the opcode LDAA #$2CLDD #$1234

Direct Data is on page zero given by an 8-bitaddress ($00-$FF)

STAA $FCSTD $34

Extended Data is in memory given by a16-bit address ($0000-$FFFF)

STAB $1234STX $0848

Relative Opcode is followed by an 8-bit or 16-bitrelative offset from PC

BNE -$2BLBEQ $0452

Indexed(constant offset)

5-bit, 9-bit, or 16-bit constant offsetfrom X, Y, SP, or PC

LDD -2,XJSR 0,Y

Indexed(pre-decrement)

Auto pre-decrement X, Y, or SPby 1 - 8

STAA 1,-XMOVW 0,X,2,-X

Indexed(pre-increment)

Auto pre-increment X, Y, or SPby 1 - 8

LDAB 1,+YSTD 2,+X

Indexed(post-decrement)

Auto post-decrement X, Y, or SPby 1 - 8

STD 2,X-LDAA 4,Y-

Indexed(post-increment)

Auto post-increment X, Y, or SPby 1 - 8

LDD 2,X+STAA 1,X+

Indexed(accumulator offset)

Add contents of A, B, or D toX, Y, SP, or PC

ADDA B,XSTX D,Y

Indexed-Indirect(16-bit offset)

Address of data located at 16-bitconstant offset from X, Y, SP, or PC

LDAA [0,Y]JSR [0,Y]

Indexed-Indirect(D accumulator offset)

Address of data located at X, Y, SP, orPC plus the value in D

ADDA [D,X]JSR [D,Y]

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Introducing the 68HC12