Digital System Design

Introduction

Bassam Jamil

1

Course Administration

Instructor: Bassam Jamil Mohammed

Instructor's e-mail: bassam@hu.edu.jo

Text:

• Advanced Digital Design with Verilog HDL , Michael

Ciletti, Pearson Education Inc, 2003 or 2011

Slides : pdf on the course web page after lecture on

Moodle (not BB)

2

Course Content

This course will discuss:

The hardware description language (Verilog)

Synthesis of digital circuits.

Advanced digital design topics: FSM/Power/Area

Download designs on FPGAs.

3

Course Outline (roughly)

4

Topic Book

Introduction and review of Comb and

sequential design

Chapter 1-3

Verilog Basics Chapter 4

Modelsim Notes

Verilog Advanced Chapter 5

Synthesis (FSM, Datapaths) Chapter 6,7

Optimizations Notes

Acknowledgement

Based my slides on notes from universities notes and book authors, e.g.

MIT

Virginia Tech

Samir Panitkar (Verilog HDL)

Morris Mano (Digital Design)

Ciletti ( Verilog HDL)

And others …

Grading Information

Grade determinates

• Midterm Exam ~20%

Monday, Nov. 13th, in class.

•Final Exam ~50%

TBD

•Project ~30%

Due to Dec. 15.

6

Introduction to Digital System Design

7

Outline

1. Why Digital?

2. Device Technologies

3. System Representation

4. Abstraction

5. Development Tasks

6. Development Flow

8Chapter 1

Advantages

Advantage of digital devices

• Reproducibility of information

• Flexibility and functionality: easier to store, transmit and manipulate information

• Economy: cheaper device and easier to design

Moore’s law

• Chips double its density (number of transistor) in every 18 months

• Devices become smaller, faster and cheaper

• Now a chip consists of hundreds of million gates

• And we can have a “wireless-PDA-MP3-player-camera-GPS-cell-phone” gadget very soon

9Chapter 1

Classification of device technologies

Where customization is done:

• In a fab (fabrication facility): ASIC (Application Specific IC)

• In the “field”: non-ASIC

Classification:

• Full-custom ASIC

• Standard cell ASIC

• Gate array ASIC

• Complex field programmable logic device

• Simple field programmable logic device

• Off-the-shelf SSI (Small Scaled IC)/MSI (Medium Scaled IC) components

10Chapter 1

Chapter 1

What an FPGA?

A field-programmable gate array is a gate array that can be reprogrammed after it is manufactured programmable logic device.

FPGA vendors: Xilinx, Altera, Lattice Semiconductor, Actel, Cypress, Atmel and QuickLogic.

- FPGAs are generally slower than their ASIC counterparts,

- draw more power.

+ shorter time-to-market,

+ lower development costs.

Applications of FPGAs include DSP, Aerospace and defense systems, ASIC Prototyping, Medical imaging, …

VHDL is used to define the behavior of the FPGA.

When compiled, will generate a net list, that can be mapped to the actual FPGA architecture.

When done the binary file generated is used to (re)configure the FPGA device.

11

Cost

Types of cost:

• NRE (Non-Recurrent Engineering) cost: one-time, per-design cost

• Part cost: per-unit cost

• Time-to-market “cost” loss of revenue

Standard cell: high NRE, small part cost and large lead time

FPGA: low NRE, large part cost and small lead time

Chapter 1 12

Graph of per-unit cost

Chapter 1 13

Summary of technology

Trade-off between optimal use of hardware resource and design effort/cost

No single best technologyChapter 1 14

Descriptions/abstractions levels:

Behavioral/Algorithm :

• Describe functionalities and i/o behavior

• Treat the system as a black box

Register Transfer Level (RTL)

Has an explicit clock.

All operations are scheduled to occur in specific clock cycles, but there are no detailed delays below the cycle level.

Structural view:

• Describe the internal implementation (components and interconnections)

• Essentially block diagram Chapter 1 15

Gate level description

Consists of a network of gates and registers instanced from a technology library, which contains technology-specific delay information for each gate.

Chapter 1

Descriptions/abstractions levels:

16

Chapter 1

Level of abstractions

Algorithms are unsynthesizable.

RTL is the input to synthesis.

gate level is the output from synthesis.

The difference between these levels of abstraction can be understood in terms of timing.

17

Chapter 1

Development

Flow

synthesis

placement & routing

device programming

FPGAchip

simulation

simulation

simulation/timing

analysis

Synthesis Physical Design Verification

data file process

RTL description

netlist delay file

configuration file

delay file

testbench1 1

23

445

67

8

18

Chapter 1

Synthesis

A refinement process that realizes a description with components from the lower abstraction level.

The resulting description is a structural view in the lower abstraction level

Type of synthesis:

High-level synthesis

RT level synthesis

Gate level synthesis

Technology mapping19

Chapter 1

Physical Design

Placement and routing

Refining from structural view to physical view

Derive lay out of a netlist

Circuit extraction:

Determine the wire resistance of capacitance

Others

Derivation of power grid and clock distribution network, assurance of signal integrity etc.

20

Chapter 1

Verification

Check whether a design meets the specification and performance goals.

Concern the correctness of the initial design and the refinement processes

Two aspects

Functionality

Performance (timing)

21

Chapter 1

Method of Verification

Simulation

spot check: cannot verify the absence of errors

Can be computation intensive

Timing analysis

Just check delay

Formal verification

apply formal math techniques determine its property

E.g, equivalence checking

Hardware emulation 22

Chapter 1

Testing

Testing is the process of detecting physical defects of a die or a package occurred at the time of manufacturing

Testing and verification are different tasks.

Difficult for large circuit

Need to add auxiliary testing circuit in design

E.g., built-in self test (BIST), scan chain etc.

23