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Intro to Digital Logic, Lab 3 High-Level Verilog

Lab Objectives

Implementing designs directly in schematics or structural (gate-level) Verilog can give you the best control, and often the smallest designs. But sometimes it can be a real pain to optimize all the way down at that level. An alternative is high-level (Register Transfer Level – RTL) Verilog, where you tell the CAD tools what you what the output to look like, and it automatically does the Boolean algebra for you!

Task #1 – Seven-Segment Displays

In lecture, we presented a seven-segment display driver. RTL code for that seven-segment display is given below (Figure 1).

1) Create a new project in Quartus Prime and add the seg7 code to it.

2) Create a new module that uses two instances of the seg7 code – one that uses SW3-SW0 as inputs and outputs to HEX0, and another that uses SW7-SW4 as inputs and outputs to HEX1.

Figure 1: Verilog code for seven-segment display driver.

module seg7 (bcd, leds);

input logic [3:0] bcd;

output logic [6:0] leds;

always_comb

case (bcd)

// Light: 6543210

4'b0000: leds = 7'b0111111; // 0

4'b0001: leds = 7'b0000110; // 1

4'b0010: leds = 7'b1011011; // 2

4'b0011: leds = 7'b1001111; // 3

4'b0100: leds = 7'b1100110; // 4

4'b0101: leds = 7'b1101101; // 5

4'b0110: leds = 7'b1111101; // 6

4'b0111: leds = 7'b0000111; // 7

4'b1000: leds = 7'b1111111; // 8

4'b1001: leds = 7'b1101111; // 9

default: leds = 7'bX;

endcase

endmodule

The seven-segment display on the DE1 is active low. That means putting a FALSE on the wire makes it light up, while a TRUE means that light is off. You will have to adjust your design accordingly.

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Task #2 – UPC code to display

In Lab 2, we built a system that took in a UPC and output whether a returned Nordstrom item was on sale and whether it was stolen. A nearby store, Fred’s Pawn Shop, buys used items from customers that were originally purchased from various stores that also use the UPC system. Fred wants a similar item-checking system, but he has found that devious customers are changing the UPC stickers on the items they are selling to misrepresent the price. To combat that, Fred would like you to add a display on HEX5-HEX0 that describes the product corresponding to that UPC – if the description doesn’t match

the item, then someone is trying to cheat Fred!

You already created the logic to output the Discounted and Stolen signals based on six specific UPCs and whether or not the item was marked. To simplify this lab, we will reuse all of that existing logic, but now add hex display outputs for those six UPCs. To let you exercise your creativity, you are asked to come up with new item names.

1) Come up with exactly six new items to fill out the leftmost column of Table 1 – three expensive items and three inexpensive items. You are not allowed to use any of the items from Lab 2 or the example given below.

a) Make sure to match each item with a corresponding expensive or inexpensive UPC.

b) Since we only have six 7-segment displays, you should consider what items will lend themselves to “good” (easily-distinguishable) displays.

2) Determine corresponding 7-segment encodings for your six items. The displays do not need to use the entire item name, but they need to be at least 3 letters each and should be easily-distinguishable from the other UPC descriptions. You may use upper- and lower-case letters or pictograms.

a) Example: The item “Dress Shoe” could be displayed as

3) Create a high-level design for the circuit using RTL. Whereas the seg7 module had one 4-bit input and one 7-bit output for a 7-seg display, your design should have three inputs (U, P, and C) and six 7-bit outputs for the 7-seg displays.

4) Simulate your design in ModelSim, then test it using the switches and lights of your board.

5) Create a new module that uses one instance of your new display code and one instance of your Lab 2 module. It should use both of them so the system simultaneously computes the Sale LED, Stolen LED, and HEX displays. Test and debug with ModelSim, then load onto your board.

Item Name UPC Discounted? Expensive?

<New Item 1> 0 0 0 No Yes

<New Item 2> 0 0 1 No No

<New Item 3> 0 1 1 Yes No

<New Item 4> 1 0 0 No Yes

<New Item 5> 1 0 1 Yes Yes

<New Item 6> 1 1 0 Yes No Table 1: List of products being sold as well as their UPCs and shopping classifications.

There is no “correct” way to encode the entire alphabet on 7-segment displays. You may use online resources such as http://tinyurl.com/h99785g for inspiration, but you should decide for yourself whether or not your display is easily readable.

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Task #3 – Don’t Cares

Your design has outputs for only 6 of the 8 possible UPC codes. For the other two cases, a line such as

“default: LEDs = 7’bx;” tells Quartus Prime that it can treat these cases as a Don’t Care condition. If you didn’t do this, go back and correct it to do so. Test your design on the circuit board and record the pattern it shows for these Don’t Care conditions (a hand drawn picture or photo will work).

Lab Grading

Working Design: 60 points for correctness, style, and testing.

Lab Demonstration/Turn-In Requirements

Lab Report (before Wednesday section, submit as PDF on Canvas)

Your completed Table 1, showing your new items, their UPC codes, and classifications.

A screenshot of the ModelSim simulations you will demonstrate during the demo.

Drawings of the 7-seg display output for each of the unused UPC codes.

How many hours (estimated) it took to complete this lab in total, including reading, planning, designing, coding, debugging, and testing.

As a separate Canvas file upload, your Verilog code for the double 7-seg and Fred’s Pawn Shop designs.

In-Person Demo (during your demo slot)

Demonstrate both the double 7-seg and the Fred’s Pawn Shop circuits in ModelSim.

Demonstrate both the double 7-seg and the Fred’s Pawn Shop circuits on the DE1.

Be prepared to answer questions on both the theoretical and practical parts of the lab.

ModelSim Tips to help you organize your signals:

Signals from multiple modules can be displayed at the same time. Select modules in the sim tab and then drag-and-drop signals from the Objects pane to the Wave pane.

To (re-)order signals, you can click and drag names in the Wave pane.

You can create groups of signals. Highlight multiple signals in the Wave pane, then right-click on one of the signal names and select “Group.” You can now move the signals as a group and hide/expose them easily. Note: you can only group signals from the same module.

Don’t forget to save the formatting into the <modulename>_wave.do file!

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Lab 3 Rubric

Grading Criteria Points

Q1: Completed table of products being sold 3 pts

Q2: ModelSim screenshot of double 7-seg circuit 3 pts

Explanation of waveforms 5 pts

Q3: ModelSim screenshot of Fred’s Pawn Shop circuit 3 pts

Explanation of waveforms 5 pts

Q4: Drawings of 7-seg display output for the unused UPC codes 4 pts

Time spent 2 pts

Verilog code uploaded 5 pts

LAB DEMO 30 pts

60 pts