interrupts - Georgia Institute of Technologyume.gatech.edu/mechatronics_course/interrupts.pdf · Interrupts and Resets. Introduction to Mechatronics, Georgia TechIntroduction to Mechatronics,

Introduction to Mechatronics, Georgia TechIntroduction to Mechatronics, Georgia Tech

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ME6405

Introduction to Mechatronics

Fall 2004

Instructor: Professor Charles Ume

Interrupts and Resets


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Reason for Interrupts

You might want instructions executed immediately after internal request and/or request from peripheral devices when certain condition are met .

Interrupt provides way to temporarily suspendcurrent program execution in order to execute certain set of tasks.


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Methods of Checking for Requests

There are two methods of checking when requests are made internally or from peripheral devices.– Polling – Interrupts


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Polling

An iterative approach which constantly checks devices for dataInefficient method for checking when input data has come in because no other instructions can be executed during polling process


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InterruptsCommunication between CPU and I/O devices can be established with issue of interrupt request

NOTE: Request can be issued at any time

CPU suspends execution of main program, until instructions in Interrupt Service Routine (ISR) are completely executed

Returns to main program after ISR is completed


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Types of Interrupts

There are two types of interrupts.– Maskable– Non-Maskable


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Maskable Interrupts

15 Maskable Interrupts– Two types of Masking

• Local– Interrupt enable bit

• Global– I-bit in CCR

– Follows a default priority arrangement• Any one interrupt can be promoted to higher

priority using HPRIO register

1. IRQ2. Real-Time Interrupt3. Timer Input Capture14. Timer Input Capture25. Timer Input Capture36. Timer Output

Compare 17. Timer Output



Compare 410. Timer Input Capture

4/Output Compare 511. Timer Overflow12. Pulse Accumulator

Overflow13. Pulse Accumulator

Input Edge14. SPI transfer Complete15. SCI system


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Maskable Interrupts: IRQ Input

IRQ pin provides additional external interrupting sourceIRQE bit in Options Register used to configure IRQ for Edge-Sensitive-Only Operation – IRQE = 0 → IRQ is configured for level sensitive

Operation– IRQE = 1 → IRQ is configured for edge-sensitive-only

Operation


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Maskable Interrupts: Peripheral Subsystems

Interrupts from Internal Peripheral Subsystems– Flag bit, which is set after action takes place– Interrupt enable bit, which enables flag to generate

interrupt service


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Interrupt Priority: MaskableMaskable Interrupts Priority

1. IRQ2. Real Time Interrupt3. Timer Input Capture 14. Timer Input Capture 25. Timer Input Capture 36. Timer Output Compare 17. Timer Output Compare 28. Timer Output Compare 39. Timer Output Compare 410. Timer Input Capture4/Output Compare 511. Timer Overflow12. Pulse Accumulator Overflow13. Pulse Accumulator Input Edge14. SPI Transfer Complete15. SCI System

Any can be assigned the highest maskable interrupt priority...


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HPRIO Register for Maskable Interrupts

Used to elevate priority of any one maskableinterruptDefault is IRQSet using bits 0-3 of HPRIO (Highest Priority Interrupt Register)Can only be written when I-bit is set


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HPRIO Register for Maskable Interrupts

PSEL0PSEL1PSEL2PSEL3IRVNEMDASMODRBOOT

Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7Address: $103C

RBOOT – Read Bootstrap ROM Bit• Has meaning when the SMOD bit is a 1

SMOD – Special Mode Select Bit• Reflect inverse of the MODB input pin

MDA – Mode Select A Bit• Reflects status of the MODA input pin

IRVNE – Internal Read Visibility/Not E Bit• Allows internal read accesses on external bus in expanded mode

• Determines whether E-clock is driven out an external pin

PSEL[3:0] – Priority Select Bits• Selects one interrupts source to be elevated

• Can only be written while I-bit in the CCR is set


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HPRIO register for Maskable Interrupts

Timer input capture 4/output compare 51111

Timer output compare 40111




Timer input capture 30101



Real-time interrupt1110

IRQ (external pin or parallel I/O)0110

Reserved (default to IRQ)1010

SCI serial system0010

SPI serial transfer complete1100

Pulse accumulator input edge0100

Pulse accumulator overflow1000

Timer overflow0000

Interrupt Source PromotedPSEL0PSEL1PSEL2PSEL3


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HPRIO register for Maskable Interrupts

0101

PSEL0PSEL1PSEL2PSEL3IRVNEMDASMODRBOOT

Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7

Example: Set Timer Input Capture 3 to have the highest maskable priority

Address: $103C


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Non-Maskable Interrupts

6 Non-Maskable Interrupts – Follows a default priority

arrangement

– Interrupts are not subject to global masking

1. POR of RESET pin2. Clock monitor reset3. COP watchdog reset4. XIRQ interrupt5. Illegal opcode interrupt6. Software interrupt (SWI)


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Non-Maskable Interrupts:Illegal Opcode

Generates interrupt request to illegal opcode vectorReinitializes stack pointer once interrupt service is completedLeft un-initialized, illegal opcode vector can cause infinite loop causing stack underflow


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Non-Maskable Interrupts: Software Interrupt

Software instruction, thus cannot be interrupted until completedUninhibited by global mask bits in the CCRSimilar to other interrupts, sets I-bit upon servicing


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Non-Maskable Interrupts: XIRQ

Enabled by TAP instruction by clearing X-bit upon system initializationAfter being cleared, software cannot set X-bit, thus XIRQ is non-maskableHigher priority than any source maskable by I-bitBoth X and I bits are automatically set by Reset or recognition of XIRQ interruptRTI restores X and I bit to pre-interrupt states


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Stacking Order when an Interrupt Occurs

CCRSP-8

ACCBSP-7

ACCASP-6

IXHSP-5

IXLSP-4

IYHSP-3

IYLSP-2

PCHSP-1

PCLSP

CPU RegistersMemory Location

Last value to be pulled from stack


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Interrupt Vectors

Each type of interrupt has associated vector addressesVector addresses change depending on whether ROMON is Enabled or Disabled – This has to do with Buffalo – refer to lecture #4

With ROMON enabled, each vector is set of addresses which contain both– Jump (JMP ie 7E) statement, and– starting address of interrupt subroutine (ISR)


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Interrupt Vector Table: ROMON DisabledVector Address Interrupt Source CCR Mask Bit Local Mask

FFC0, C1 – FFD4, D5 Reserved - -FFD6, D7 SCI receive data register full

SCI receiver overrunSCI transmit data register emptySCI transmit completeSCI idle line detect

I

RIERIETIE

TCIEILIE

FFD8, D9 SPI serial transfer complete I SPIEFFDA,DB Pulse accumulator input edge I PAIIFFDC, DD Pulse accumulator overflow I PAOVIFFDE, DF Timer overflow I TOIFFE0, E1 Timer IC4/OC5 I I4/O5IFFE2, E3 Timer output compare 4 I OC4IFFE4, E5 Timer output compare 3 I OC3IFFE6, E7 Timer output compare 2 I OC2IFFE8, E9 Timer output compare 1 I OC1IFFEA, EB Timer input capture 3 I IC3IFFEC, ED Timer input capture 2 I IC2IFFEE, EF Timer input capture 1 I IC1IFFF0, F1 Real-time interrupt I RTIIFFF2, F3 IRQ (external pin) I NoneFFF4, F5 XIRQ pin X NoneFFF6, F7 Software interrupt None NoneFFF8, F9 Illegal opcode trap None NoneFFFA, FB COP failure None NOCOPFFFC, FD Clock monitor fail None CMEFFFE, FF RESET None None


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ROMON Disabled

Interrupt vector addresses are usually occupied by Buffalo

With ROMON disabled, only starting ISR address must be programmed in vector address


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Interrupt Vector Table: ROMON EnabledVector Address Interrupt Source CCR Mask Bit Local Mask

- -

00C4-C6 SCI receive data register fullSCI receiver overrunSCI transmit data register emptySCI transmit completeSCI idle line detect

I

RIERIETIE

TCIEILIE

00C7-00C9 SPI serial transfer complete I SPIE

00CA-00CC Pulse accumulator input edge I PAII

00CD-00CF Pulse accumulator overflow I PAOVI

00D0-00D2 Timer overflow I TOI

00D3-00D5 Timer IC4/OC5 I I4/O5I

00D6-00D8 Timer output compare 4 I OC4I

00D9-00DB Timer output compare 3 I OC3I

00DC-00DE Timer output compare 2 I OC2I

00DF-00E1 Timer output compare 1 I OC1I

00E2-00E4 Timer input capture 3 I IC3I

00E5-00E7 Timer input capture 2 I IC2I

00E8-00EA Timer input capture 1 I IC1I

00EB-00ED Real-time interrupt I RTII

00EE-00F0 IRQ (external pin) I None

00F1-00F3 XIRQ pin X None

00F4-00F6 Software interrupt None None

00F7-00F9 Illegal opcode trap None None

00FA-00FC COP failure None NOCOP

00FD-00FF Clock monitor fail None CME- - - -


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ROMON Enabled

Buffalo is active – READ ONLY MEMORY(ROM)In this case you must write the jump command ($7E) to the first byte of the vector addressThe remaining two bytes write the starting location of your ISR


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is met

Restore Registersw/ org. Values

Standard InterruptTable

Analyze Priority

Store all registerson the Stack

Global Masking

Local Masking

ContinueProgram

Complete CurrentInstruction

A

Set (I) or (X) to prohibit another

Interrupt

Load Address inappropriate vector

YES

NO

NO

YES

ISR instruction

Clear I or X bit inCCR

RTI

YES

NO

B

B

A

Note: Local mask must be cleared prior to performing RTI


ME6405ME6405Write a routine to interrupt the MC68HC11 after 10 msec of elapsed time(Assume E= 1 Mhz, Prescaler = 1)

ORG $1040LDD #$FFFF /*Delays any OC3 compares*/STD TOC3 /*Set output compare to the longest time so that you would not have

output compare occurring when you are initializing*/OR

SEI /*Set I-bit to prevent interrupt service during set-up*/ LDAA #BIT5HI /* BIT5HI = %0010000*/STAA TFLG1 /* Clear previously set OC3 Flag*/STAA TMSKI /* Enable OC3 Interrupt */LDAB #$30STAB TCTL1 /* OC3 will be high for a successful compare */LDAA #JUMP /* JUMP = $7E */STAA FIRSTAD /* FIRSTAD = $00D9 */LDX #OC3ISR /* OC3ISR = $D000, 2 bytes- beginning address of interrupt

service routine*/STX SECONDAD /* SECONDAD = $00DA, This will cause the high byte ($DO) of the

service routine address to be stored in location $00DA and the lowbyte ($00) to be stored in $00DB */

LDD TCNTADDD #DLYIOMS /* DLYIOMS = $2710 = 10000 */STD TOC3 /* IF not done elsewhere */CLI /* Clear I bit */

Elapsed Time Example


ME6405ME6405Write a routine to interrupt the MC68HC11 after 10 msec of elapsed time(Assume E= 1 Mhz, Prescaler = 1)

ORG $1040LDD #$FFFF /*Delays any OC3 compares*/STD TOC3 /*Set output compare to the longest time so that you would not have

output compare occurring when you are initializing*/OR

SEI /*Set I-bit to prevent interrupt service during set-up*/ LDAA #BIT5HI /* BIT5HI = %0010000*/STAA TFLG1 /* Clear previously set OC3 Flag*/STAA TMSKI /* Enable OC3 Interrupt */LDAB #$30STAB TCTL1 /* OC3 will be high for a successful compare */LDD TCNTADDD #DLYIOMS /* DLYIOMS = $2710 = 10000 */STD TOC3 /* IF not done elsewhere */CLI /* Clear I bit */

….SWI END

ORG $00D9JMP OC3ISR

Elapsed Time Example Alternative


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Example: Timer Overflow InterruptTFLG2 EQU $1025 *Timer Interrupt Flag 2TMSK2 EQU $1024 *Timer Interrupt Mask 2TOVISR EQU $1500 *ISR memory locationPROGRAM EQU $1040 STRING EQU $2000OUTSTRG EQU $FFC7VECTOR EQU $00D0

ORG STRING FCC 'TICK'FCB $04ORG PROGRAM

*Set I-bit to prevent interrupt service during set-upSEI LDAA #$80STAA TMSK2 *TOF Interrupt EnabledSTAA TFLG2 *Clears TOF Interrupt FlagLDAA #$7E *JMPSTAA VECTOR *Stores JMP to vectorLDX #TOVISR *Loads register X with #1500

*Stores content of register X to address Vector incrementedSTX VECTOR+1 CLR $0001 CLI * Clears I-bit to allow servicing of

interrupt

LOOP BRA LOOP---SWI *Software InterruptEnd

ORG TOVISR LDAA $0001 * Loads address $0001 content INCA *Increment by 1STAA $0001 *Stores value back to addressCMPA #30 *Compares value to decimal 30BNE A1

*Loads index register X with content of STRINGLDX #STRING JSR OUTSTRG CLR $0001 *Clear address

A1 LDAA #$80 *Loads binary 10000000STAA TFLG2 *Clears local flagRTI

Pre-interrupt service set-up


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Resets

Forces the MCU to:assume set of initial conditionsbegin executing instructions at predetermined starting address.


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Resets

Like interrupts, resets share concept of vector fetching to force new starting point for further CPU operations.In contrast to interrupts, resets stop completely execution of set of instructions. As well, they always rest MCU hardware.


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Sources of Resets

Power on Reset (POR)External Reset (RESET)Computer Operating Properly (COP) ResetClock Monitor Reset


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Power-On Resets

Power-On Reset (POR)Used only for power-up conditions to initialize MCU internal circuits. Applying Vdd to MCU triggers POR circuit, initiates reset sequence, and starts internal timing circuit.4064 clock cycle delay after oscillator becomes active, allows clock generator to stabilize.


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External Reset

System reset can also be forced by applying low level to RESET pin.External source must hold pin low for more than 4 cycles.If this happens, pin is further sampled 2 cycles afterLow level at sampling instant indicates that reset has been caused by external device.


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Computer Operating Properly Reset

Protects against software failuresWhen enabled, software to keep free- running watchdog timer from timing out is activatedSystem reset is initiated when software stops executing in the intended sequence


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COP Reset continued

COP is enabled or disabled by setting NOCOP bit in CONFIG register.To change status of COP system, contents of CONFIG register are changed and system reset is initiated.COP timer rate is controlled in OPTION Register. The system E-clock is divided by 2^15 and further scaled by 1, 2 and 4.


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Clock Monitor Reset

Clock Monitor Reset circuit is based on internal resistor capacitor time delay.

If no MCU clock edges are detected within thisRC time delay, clock monitor, if set by CME control bit, would generate system reset.


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How the MPU Distinguishes between Internal and External Resets

MPU senses whether reset pin rises to logic 1 withintwo E-clock cycles after internal device releases

reset.

When reset condition is sensed, RESET pin is driven low by internal device for 4 E-clock cycles, then released. Two E-clock cycles later, it is sampled.

If pin is still held low, CPU assumes that external reset has occurred. If pin is high, it indicates that reset was internally initiated.


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Occurrence of Reset Affects

CPUMemory MapTimerReal-time InterruptPulse Accumulator

SPIADCSystemCOPSCI


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Process Flow out of Resets

When Reset is triggeredVector fetch (Program counter loaded with contents of specified address)S, X and I bits set in CCRMCU hardware resetChecks for interrupts


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Standby Modes

Suspends CPU operation until reset or interrupt occursUsed to reduce power consumptionTwo standby modes:

• WAIT• STOP


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Standby Modes: WAIT

Opcode (WAI)Suspends CPU processingCPU registers are stackedOn-chip crystal oscillator remains activeExit WAIT mode through external IRQ, XIRQ, or any internally generated interrupts


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Standby Modes: STOP

If S-bit in the CCR is 0, CPU goes into stop modeElse, opcode is treated as NOPAll clocks stopped → internal peripherals stoppedRetains data in Internal RAM if VDD is maintainedCPU state and I/O pin levels are staticExit STOP mode through external interrupts, pending edge-triggered IRQ or RESET pin


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Standby Modes: STOP

Recovering through XIRQX-bit is clear → Returns to stacking sequence leading to normal XIRQ requestX-bit is set → Returns to instruction immediately following STOP instruction


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Questions???

Documents

interrupts - Georgia Institute of Technologyume.gatech.edu/mechatronics_course/interrupts.pdf · Interrupts and Resets. Introduction to Mechatronics, Georgia TechIntroduction to Mechatronics,