International Journal of Emerging Trends in Electrical and ... 2/Issue2/Volume. 2, Issue. 2.pdf · Dr. Rajib Kumar Jha Indian Institute of Technology Ropar. Dr. Amit Mishra Indian

ISSN 2320 - 9569

International Journal of Emerging Trends inElectrical and Electronics (IJETEE)

Volume 2, April Issue.

(Online Journal)

Published by

Institute of Research in Engineering & Technology (IRET)Nagulapalli, Visakhapatnam, Andhrapradesh, India-531001

(www.iieee.co.in)

International Journal of Emerging Trends in Electrical and Electronics ISSN-2320 – 9569

i

Editor in Chief

Dr. TAN CHER MINGInternational Journal of Emerging Trends in Electrical and Electronics (IJETEE)Prof. in Nanyang Technological University (NTU) and Director of SIMTech-NTU Reliability Lab.

Editorial Board Members:

Dr. Dhrubes Biswas,Indian Institute of Technology, Kharagpur, India.

Dr. Rajesh GuptaIndian Institute of Technology Bombay, India.

Dr. Sumana GuptaIndian Institute of Technology Kanpur, India.

Dr. A.K.SaxenaIndian Institute of Technology, Roorkee, India.

Dr. Vijay KumarIndian Institute of Technology Roorkee, India.

Dr. Shaibal MukherjeeIndian Institute of Technology Indore , India.

Dr. S.K. ParidaIndian Institute of Technology Patna, India.

Dr. Manoj Kumar MeshramIndian Institute of Technology(BHU) India.

Dr. SatyabrataJitIndian Institute of Technology (BHU), India.

Dr. Surya Shankar DanIndian Institute of Technology Hyderabad, India.

Dr. Rajib Kumar JhaIndian Institute of Technology Ropar.

Dr. Amit MishraIndian Institute of Technology Rajasthan, India.

Dr. Maode Ma,Nanyang Technological University, Singapoore.

Dr. Kishore Kumar TNational Institute of Technology, Warangal,India.

Dr. Gargi KhannaNational Institute of Technology Hamirpur, India.

Dr. K.S.Sandhu,Ntional Institute of Technology Kurukshetra,India.

Dr. Om Prakash SahuNational Institute of Technology, Kurukshetra,India.

Dr. K. P. GhatakNational Institute of Technology, Agartala, India.

Dr. Ajoy Kumar ChakrabortyNational Institute of Technology, Agartala, India.

Dr. SubhadeepBhattacharjeeNtional Institute of Technolgy (NIT), Agartala,India.

Dr. Rama KomaragiriNational Institute of Technology Calicut, India.

Dr. Elizabeth EliasNational Institute of Technology Calicut, India.

Dr. S. Arul DanielNational Institute of Technology,Trichy, India.

Dr. BidyadharSubudhiNational Institute of Technology Rourkela, India.

International Journal of Emerging Trends in Electrical and Electronics ISSN-2320 – 9569

ii

Dr. Umesh C. PatiNational Institute of Technology Rourkela, India.Dr. ChiranjibKoleyNational Institute of Technology, Durgapur,India.

Dr. SumitKunduNational Institute of Technology, Durgapur,India.

Dr. RajibKarNational Institute of Technology, Durgapur,India.

Dr. Aniruddha ChandraNational Institute of Technology, Durgapur,India.

Dr. Nidul SinhaNational Institute of Technology, Silchar, India.

Dr. JishanMehediNational Institute of Technology Silchar, India.

Dr. Vivekanand MishraSV National Institute of Technology, Surat, India.

Dr. SwapnajitPattnaikVisvesvaraya National Institute of Technology,India.

Dr. Deepak KumarM.N. National Institute of TechnologyAllahabad, India

Dr. ShwetaTripathiMNNIT-Allahabad, India.

Dr. JishanMehediNational Institute of Technology Silchar, India.

Dr. Balwinder RajNational Institute of Technology Jalandhar, India.

Dr . S C GuptaMaulana Azad National Institute of Technology,Bhopal, India.

Dr Ajay SomkuwarMaulana Azad National Institute of TechnologyBhopal, India.

Dr Ajay SomkuwarMaulana Azad National Institute of TechnologyBhopal, India.

Dr. M. Mariya DasAndhra University, Visakhapatnam, AndhraPradesh, India.

Dr. S. TitisM.A.M College of Engineering, Tiruchirapalli,Tamilnadu, India.

Dr. A. ShunmugalathaVelammal College of Eng. & Tech. Madurai.

Dr. R. DhanasekaranSAEC College of Engineering, Chennai, India.

Dr. A. BanumathiThiagarajar college of Engineering, Madurai,India.

Prof. Anoop AryaM.A.N.I.T(Deemed University),Bhopal, India.

Mr. Navneet Kumar SinghMNNIT Allahabad, India.

Mr. BimanDebbarmaNIT Agartala, India

Ms. LaxmiKumreMANIT, Bhopal, India.

Miss. Joyashree DasNIT Agartala, India.

Mr. Santosh Kumar GuptaNehru National Institute of Technology(MNNIT), Allahabad, India.

M r. Mohamed. A. ElbesealyAssuit University, Egypt.

Mr. Hadeed Ahmed SherKing Saud University, Riyadh, Kingdom of SaudiArabia.

Mr. Syed Abdhul Rahman KashifUniversity of Engineering and Technology,Lahore.

Ms. S. Preethy and Mr. B. Arivu Selvam 1

International Journal of Emerging Trends in Electrical and Electronics (IJETEE) Vol. 2, Issue. 2, April-2013.

Underwater Robot for Data Collection UsingOptical Transceiver

Ms. S. Preethy and Mr. B. Arivu Selvam

Abstract – This paper studies the utilization of an autonomousunderwater robot (AUR) to collect data from an underwaterenvironment. The 3-D simulation can be done by using subsimAUV simulator to observe and overcome the problems in anunderwater. Unlike the most existing underwater datacollection systems that focus on radio frequency communicationand acoustic modem this paper focuses on optical modemcommunication that provides an interaction between the userand an underwater robot so that the robot can be controlledfrom land surface. In this paper the design and experimentalresults of a system to control an underwater robot in real-timeusing optical modem link is presented.

Index Terms – Autonomous underwater robot, Optical modem.

I. INTRODUCTIONAn underwater vehicle is a mobile robot which travels

under water with the input from the operator, designed for aaquatic work environments. Here remote control is carriedout through optical cables. A human operator on the basestation watching a display that shows what the robot “sees”.The operator can also maneuver the robot. Sophisticatedunderwater robot incorporates telepresence to give theoperator a sense of being in the place of the machine.

A wire remote control of an underwater robot is turnedinto optical remote control. This optical communicationremote enables to control an underwater robot from landsurface. The robot is demonstrated with a human inputdevice using the optical link remote control. Here the designand experimental results of a system to control anunderwater robot in real-time sing optical modem link ispresented.

For awareness about underwater operation 3D graphicsimulation is done using subsim environment to monitor andovercome the problem in the underwater environment whichmakes more comfortable in the real time implementation.The 3D graphic object is created by using visual C++ and theresult of simulation is shown. The various parameters arewall following, depth, floor measuring and so on.

The working of robotic motor is also shown in simulationby using proteus tool. Embedded c is coded for robotic motorcontrol so that if problem occurs during real timeimplementation the coding is debugged in proteus software.

Ms. S. Preethy M.E, Mr. B. Arivu Selvam M.Tech are with EaswariEngineering College, Chennai, Email: [email protected],[email protected]

II. RELATED WORK

Several approaches have been proposed in literature forunderwater robot for underwater environment monitoringand data collection.

Geoffrey A. Hollinger and Sunav Choudhary [1] haveproposed that ultrasonic acoustic modems are the mostcommonly used underwater communication system but it isextremely slow due to reflections and relatively slow speedof sound under water. Thus it is not possible to dynamicallycontrol under water vehicles remotely using acousticcommunication in real time.

Detweiler C and Vasilesce I [2] have proposed thatunderwater vehicles are typically operated using a tether or aslow acoustic link. An underwater optical communicationsystem that enables a high-throughput and a low-latency linkto an underwater robot. The optical link allows the robot tooperate in cluttered environments without the need for atether.

Vu Minh Hung and Kyungnam Masan Uhn Joo Na [3]have proposed a method of underwater robot using twoacoustic transducers, while radio waves are not used becauseit is strongly attenuated in complex environments as water.Underwater robots can be controlled by cables limited bydistance, environment conditions, and are not flexible.Therefore it is necessary to develop a remote control systemfor underwater robots.

Section I of this paper is a background introduction.Section II discusses a brief literature review of underwaterdata collection methods. Section III describes data collectionusing optical modems. Section IV presents experimentalresults. Concluding remarks and a scope for further researchare given in Section V.

III. PROPOSED SYSTEM

This system consists of optical modem which overcomesthe problems of the previous method (ie) by using radiofrequency communication and by acoustic modems. Thissystem has several advantages in case of sparks it can avoidsparks which is important in flammable or explosive gasenvironments.

It is resistance to corrosion due to non-metallictransmission medium. It consists of high electrical resistance.The use of optical modems can avoid crosstalk. It alsosupports high bandwidth, high speed, low latency and goodefficiency. The following is the schematic flow diagram ofthe system operation. Fiber optic cables have a much greater



bandwidth than metal cables. This means that they can carrymore data. Fiber optic cables are less susceptible than metalcables to interference. Fiber optic cables are much thinnerand lighter than metal wires. Data can be transmitteddigitally (the natural form for computer data) rather thananalogically.

Fig. 1 Flow diagram of system operation

IV. EXPERIMENTAL SETUP

SOFTWARE:Proteus software tool is used to simulate the robot. The

design is created using the proteus tool. The components areselected from PIC component selection dialog box. It can bedebugged at any time by selecting properties edit dialog box.

The circuit to be simulated is shown here, consisting of aPIC16F877 microcontroller unit (MCU), input push buttonsand output LEDs which will display a binary count.

The ISIS user interface is shown here, consisting of edit;overview and object select windows, with edit toolbars.Components are added to the object list from the librariesprovided, dropped onto the schematic, and connected upusing virtual wiring. Components can be labeled and theirsimulation properties are can be modified.

Fig.2 Simulation result of robotic motor control using proteus

SUBSIM:3D graphic simulation of robot is developed in subsim

environment. Application design, controller tuning, missionsimulation, and the fault-tolerance can all be tested with thesimulator. Subsim supports features like, three dimensionaldynamic simulation of an AUV and the underwaterenvironment with different kind of additional objects,simulation controlling, slow motion and time laps effects,feature for debugging the controller program, applicationprogramming interface that is compatible with C and C++,extensible through C++ model.The subsim user interface can be divided into five parts:1) Menu bar

The menu bar allows loading a simulation file and givesaccess to the plug-in and help system. Some features fromthe control panel can be found here as well.

2) World panel

The world panel consists of a main window for thevisualization surrounded by sliders for camera navigation.The user’s viewpoint is controlled by a visual camera whichis taking continuous pictures of the scene. The position,orientation and zoom of the camera can be controlled eitherby mouse, keyboard or GUI sliders.

3) Control panelThe control panel consists of several parts to control the

simulation or change visualization.Simulation control

Start/pause/ and stop the simulation can be controlled bythree buttons on the top, where as pause interrupts just thesimulation, stop resets it as well. The simulation speed sliderallows decelerating or accelerating the simulation. Be awarethat slowing down or fasting up the execution may effects onthe simulation results.



4) Information panelThe information panel holds a set of pages to get informationabout the simulation, world or active objects.

5) Status Bar

The main status bar (along the bottom of the mainwindow) gives useful information about the status of thesimulation. The status bar is divided into fields. The left-most field is for generic text and application messages. Thefield after “Threads” denotes the number of user programscurrently running. The next field to the right shows thesimulation status. This field will read either STOPPED,PAUSED or RUNNING depending on the simulator state.The next field to the right shows the simulation time inseconds. The right-most field shows the frames-per secondrender rate.

Fig. 3 Experimental result of subsim

HARDWARE:i) Transmitter and receiver functions

The robot is allowed to monitor underwater environmentin the submarine which is designed to have the receiversection with it and the motor that used in the robot is DCmotor. The user input is given through the keypad to themicrocontroller in the control room which is then given tothe encoder decoder module then the output is transmittedvia optical cable to the receiver section that is designed in therobot. After receiving, the same process happened in thereceiver section again and the DC motor rotates according tothe user input and the robot reacts according to the input.

Fig. 4 Transmitter functional architecture

Fig. 5 Receiver functional architecture

Fig. 6 Result of transmitter and receiver section

V. CONCLUSION AND FUTURE WORK

The system software developed in Embedded C languagehas the ability of collecting, processing and sending data tocontrol the operation of the motor and to display the sensorvalue. Thus by controlling the DC motor the movement ofrobot is controlled and the temperature sensor will betransmitted by the microcontroller through serialcommunication.



The control of robot is shown in simulation part, in future itcan be extended into demonstration, and the idea behind thisis to turn a wire remote control of an underwater robot intooptical remote control. An underwater optical modem is tobe developed and the design of system to control anunderwater robot in real time using optical modem link isplanned to be done.

REFERENCES

[1] Geoffrey A. Hollinger, Sunav Choudhary, Christopher Murphy,gaurav S. Sukhatme, Milica Stojanovic. “Underwater DataCollection Using Robotic Sensor Networks”, in june 2012.

[2] Detweiler C, Vasilescu, I. Rus D, “Using OpticalCommunication for Remote Underwater Robot Operation”, inoct 2010.

[3] VU MINH HUNG, KYUNGNAM MASAN UHN JOO NA,“Remote control system of 6 DOF Underwater Robot”, in oct2008.

[4] Singh S, Webster, S.E, Freitag l, Whitcomb L.L, “AcousticCommunication Performance Of The Nereus Vehicle to11,000M Depth”,in oct 2009.

[5] Camilli R, Bowen, A, Farr N, “Bright Blue: AdvancedTechnologies for Marine Environmental Monitoring andOffshore Energy”, in may 2010.

Miss S. Preethy is currently pursuing her Master Degree inEmbedded system and Technologies at Easwari EngineeingCollege, Chennai.

Mr. B. Arivu Selvam is an Assistant Professor of Electronics andCommunication Engineering at Easwari Engineering College,Chennai.

G. Sivaranjani and S. Sarika 5


Allocation of Power for Secondary Users in Cognitive Radio Network

G. Sivaranjani and S. Sarika

Abstract: Most of the power allocation schemes rely on centralized server to resolve resource allocation problem, provided the server must have a global knowledge about the Channel State Information and interference information of every receiver. Due to this, computational ability of server becomes tedious as it create interference to other Secondary users. The major contribution of this paper is to allocate power for secondary users in distributed manner using Frequency Division Multiplexing Access within the node power budget. A power allocation algorithm is proposed to maximize throughput of secondary users by calculating pay off function. The pay off function determines the spectrum utilization of each secondary users by using pricing method. Meanwhile the interference between secondary users and primary users is reduced by the proposed distributed algorithm. Keywords: CR network, game theoretical approach, pay off function. Overlay spectrum sharing.

I. INTRODUCTION Among diverse wireless technology supporting Internet

access and other stream traffic services [7], a different vision is to integrate different wireless systems/networks and to appropriately use one of them based on the communication environments and the application requirements, based on reconfigurable communication and networking. Cognitive radio is considered to improve spectrum utilization by minimizing the interference between the users. A cognitive radio consists of a licensed users (Primary Users or PUs) and unlicensed users (Secondary Users or SUs). Radio Resource Management is an important module of a CR node, the aim of which is to evaluate the available resources (power, time slots, bandwidth, etc) and assign them to meet the QoS objectives of the SU, within some constraints on factors (typically interference) which limit the performance of the licensed user or the PU.

The power allocation could be done using various

methods which is studied from [3]-[5].One of the methods involves a centralized server that includes all the state

G.Sivaranjani is working as Lecturer/Department of ECE, Coimbatore Institute of Engineering and Technology, Coimbatore and S.Sarika is working as Lecturer/Department of ECE, Tejaa Shakthi Institute Of Technology For Women Coimbatore, Emails: [email protected], [email protected]

information about the entire network. The server must contain the information about each and every primary user and secondary users. It also contains the capability of the users to withstand the service that is being requested to the Access point (AP).The evaluation of such a type of tedious network is a complicated one because if the server fails at any instant, the entire system goes down. It becomes unusable for future justifications. In order to overcome such a drawbacks, this method is modified into de-centralized technique, where the power allocation is done using a modified game theoretical approach. As a result the power control is done with minimum reduction of interference. The literature review says that most of the power allocation schemes uses underlay spectrum sharing approach in which same frequency band is accessed by both PU and SU.

The main objective of is the use of overlay spectrum

sharing approach in order to minimize the interference between the two PUs and between PU and SU, thereby increasing the SU throughput within the power budget.

II. RELATED WORK

A. A general power allocation in OFDM based cognitive radio networks

Power allocation in OFDM based CRN system have used the adaptive sub-carrier configuration considers not only Channel State Information but also the sensing results of SU and interference limits of PUs[5]. Here a band of SU is divided into several sub channels, each sub channel corresponds to a licensed band of one PU system. As interference limit of each PU introduces the sub channel transmit power constraints for SU, the power allocation in OFDM based CRN must satisfy the sum transmit power constraint and the sub channel transmit power constraints. The transmit power in each sub channel is comprised of the power allocated to the subcarriers inside the sub channel and the side lobes power of the subcarriers in the other sub channels. In this method ,in the power allocation problem, if the effect of side lobes is ignored, then there is a sufficient guard band between any two neighboring sub channels. In order to maximize the capacity and to provide optimal power allocation by satisfying both sum and sub channel transmit power constraints, iterative water-filling algorithm has been used by ignoring the side lobes. Another method is to decouple the sub channel power constraints phase by phase by considering the side lobes. The power allocation problem can be classified into two categories in conventional



OFDM-based systems. The first one is to optimize the power allocation across the subcarriers such that the sum rate is maximized with a given sum transmit power constraint.

B. Mutual interference in OFDM systems based on spectrum pooling systems Interference in OFDM [3] aims at enabling public access

to these spectral ranges without sacrificing the transmission quality of the actual license owners. Unfortunately, using OFDM modulation in a spectrum pooling system has some drawbacks. There is an interaction between the licensed system and the OFDM based rental system due to the non-orthogonality of their respective transmit signals. The author describes the interaction mathematically which provides quantitative evaluation of the mutual interference that leads to an SNR loss in both systems. However, this interference can be mitigated by windowing the OFDM signal in the time domain or by the adaptive deactivation of adjacent subcarriers providing flexible guard bands between licensed and rental system. It is obvious that both approaches sacrifice bandwidth of the rental system. A quantitative comparison of both approaches is given as a trade-off between interference reduction and throughput in the rental system. A potential rental system (RS) needs to be highly flexible with respect to the spectral shape of the transmitted signal. Here, the case of an FDMA/TDMA-based licensed system (LS) is considered. Thus, spectral ranges that are accessed by licensed users (LUs) have to be spared transmission power originating from the RUs. OFDM modulation is a candidate for such a system as it is possible to leave a set of subcarriers unused, thus providing a flexible spectral shape that fills the spectral gaps without interfering with the LUs. This interference is caused by the side lobes of the OFDM signal. This method focuses on parasitic losses in SNR of both LS and RS due to the non-orthogonality of their respective transmit signals. It is possible to reduce the mutual interference of both systems and increasing the throughput of RS can be done by using raised cosine windowing. By using windowing techniques number of transmissions could be increased in a system.

C. A game theoretic approach to interference management in cognitive networks A game theoretic solution [21] for channel selection and

power allocation was proposed in cognitive radio networks. The author enforced the cooperation among nodes in an effort to reduce the overall energy consumption in the network. For designing the power control, the author considered both the case in which no transmission power constraints are imposed and the maximum transmission power is limited.An iterative algorithm for channel scheduling and power allocation has be implemented, which converges to a pure strategy Nash equilibrium solution, i.e., a deterministic choice of channels and the transmission powers for all users.

To tackle the problem, the author proposed a game

theoretic formulation, in which the adaptive channel

allocation and power control problem is modeled as a potential game. The radios are modeled as a collection of agents that distributive act to maximize their utilities in a cooperative fashion. The radios' decisions are based on their perceived utility associated with each possible action which is related to the transmission power and to the channel selection. Two scenarios (power control with and without maximum transmission power limitation) are considered, and the effect of various maximum power levels on the system performance is investigated. By using this method, both channel allocation and power control can independently improve the system performance, in order to achieve a significant gain for the joint algorithm.

III. SCHEMATIC MODEL OF NETWORK

In cognitive radio networks, there are large number of secondary users compete to access the spectrum. There may be occurrence of interference between two SUs or between one PU and one SU. Such a problem could affect the network performance to a large extent. Instead of using a centralized power allocation, in which there is a centralized server. The server must have knowledge about the global information about the network. The distributed algorithm has been formulated in order to improve the spectrum utilization of SU.

Fig. 1 Spectrum Allocation

Compared to OFDM based power allocation in cognitive

where the effect of side lobes in sub channels are considered, the proposed distributed algorithm reduces the interference between the SU pairs. The interference from the licensed system occurs in the OFDM receivers of the Rental systems is reduced by windowing scheme which is very poor performance. If the windowing scheme is used number of transmissions could be increased and there is a chance for occurrence of interference. The overall performance of the network is degraded. The proposed model considers an overlay spectrum sharing approach for PU and SUs to shares spectrum using FDMA technique to maximize throughput of SU by formulating a game theoretical approach. The overlay spectrum approach is interference avoidance scheme which is better in which the SU have to identify and exploit the spectrum holes defined in space time, and frequency, when compared to underlay spectrum approach.



Fig. 2 Network model for CRN

The sequential steps are as follows. The available spectrum is divided into different subcarriers.Each subcarrier is allocated with power that could be updated, if necessary. If in case the adjacent carrier reduces power, then based on the users and carriers, power allocation is done. In order to calculate throughput of SU, pay off function is to be measured. Pay off function is the utility function that describes how well the spectrum is utilized more by SU. Based on the utilization factor, the interference between two SUs, and the interference between one PU and one SU, throughput is measured. By minimizing the interference, throughput could be maximized. The available spectrum is divided into different sub carriers. Each sub carrier is allocated with power that could be adjustable if necessary. If adjacent carriers reduce power, then based on the number of users & carriers, the power is allocated. The allocated power is stored in the vector form. Initially the vector is stored with zero values. After allocation, the current power is stored & compared with the previous power. Based on the values, variation is identified and CINR value is calculated. If there is no power management, then throughput will reduce.A vector is created in which the initial value is zero. As and when the power is allocated by base station to each user, that power is stored in the vector. Each time the current power is stored and compared with the previous power. Based on this value, identify the variations. If there is no power management, then throughput will reduce. After the throughput estimation it is essential to calculate the utility function & pricing function. The utility function is nothing but the pay off function for secondary users. The utility function is given by the following expression.

Where is the utility factor of secondary users,

is the SU throughput.

is the interference occurred between the PU and SU.

is the interference occurred between the secondary users.From the expression it is very clear that by reducing the interference between the PU and SU, we could maximize the throughput ot some extent. The maximum spectrum utilization of SU is given pricing 1 and the minimum utilization of SU is given zero pricing value. Based on the pricing function, channel is allocated to the SU so as to access the service. If two SUs access the same service,the base station will check the capability of SU whether it could access the service requested by SU. If the user doesn’t have the sufficient capacity, the service will not be provided to that SU.

If the service requested by primary user, the free band available service is immediately allocated and the requested packet is sent by the base station. If in case the secondary users request the service, then the cognitive starts to sense the free band availability. If free band is available, then the corresponding frequency is allocated to secondary users. If there is no free band in that particular channel, then channel switching takes place.

Fig. 3 Throughput versus SU pairs in Cognitive Radio Network

Fig.3 shows the throughput measurement..Here a network

has been created with 50 primary users and 100 secondary users and the graph for the number of packets transmitted per second (Throughput) versus secondary user pairs has been obtained and the proposed distributed power allocation is compared with the uniform power allocation is plotted. Throughput comparison is made between the distributed power allocation and uniform power allocation. The simulation results shows that throughput achieved using distributed power allocation algorithm is better.



Fig. 4 Throughput versus Total Power.

From the Figure 4 shown above, for various powers of secondary users, the throughput is measured. From the simulation results, it is observed that using uniform power allocation method, we can’t view the power variation in secondary users as it remains constant throughout the simulation time. But in distributed power allocation, there is a power variation of secondary users with some degradation and the throughput versus total power is plotted.

Fig. 5 Throughput versus Total Power using distributed scheme

From the Figure 5 shown above, for various powers of secondary users, the throughput is measured. From the simulation results, it is observed that using uniform power allocation method, we can’t view the power variation in secondary users as it remains constant throughout the simulation time. But in distributed power allocation, there is no degradation in power of secondary users and the throughput versus total power is plotted.

Fig. 6 Power Vs Carrier Index

From the Figure 6 shown above describes about the power consumption of the entire network. Carrier index refers to the division of subcarrier. The above graph explains that which subcarrier utilizes maximum power that is shown as peaks and the flat response shows that underutilization of the spectrum.

From the Figure 3, it has been observed that the throughput of secondary users using distributed power allocation scheme is improved to four times when compared to the uniform power allocation. It is observed that the distributed power allocation is better with respect to throughput performance.

From the Figure 5, it is observed that the throughput is uniform for the total power of secondary users in case of uniform power allocation, whereas the throughput varies linearly with respect to power of secondary users.

IV. CONCLUSIONS The conventional centralized power allocation method

involves a server that must have knowledge about global information of the network, which controls all the nodes. So by using the distributed power allocation scheme involves a pricing method that determines the utilization of spectrum based on the power level of each secondary user. Meanwhile the interference between one primary user and one secondary user as well as the interference between two secondary users is reduced by allocation of power based in distributed manner. This scheme provides maximum throughput and node power could be measured for all secondary users in cognitive network In cognitive radio network, the number of secondary users per channel could be increased in order to reduce interference and avoiding channel wastage within a threshold limit, without affecting the primary users.

V. SIMULATION PARAMETERS The total system bandwidth assumed is to be 8MHz of

which 7MHz is occupied by SU, while PU occupies 1MHz.The type of channel used is wireless channel having 100 primary nodes and 150 secondary users. The simulation



time is 100s.Here we use two ray ground propagation model. The transmitted power is 1Watt.

VI. FUTURE WORK In cognitive radio network, the power allocation could

be done by using Pareto distribution in cognitive radio network using shadowing propagation model. Also the interference between the secondary users could be reduced to an extent using Full Duplex Relay System and the performance could be compared might be the future work.

REFERENCES

[1] S. Haykin, “Cognitive radio: brain-empowered wireless communications,” IEEE J. Sel. Areas Commun., vol. 23, pp. 201–220, 2005.

[2] I. F. Akyildiz, W.-Y. Leea, M. C. Vuran, and S. Mohantya, “Next generation/dynamic spectrum access/cognitive radio wireless networks:a survey,” Comput. Netw., vol. 50, no. 13, pp. 2127–2159, 2006.

[3] T. Weiss, J. Hillenbrand, A. Krohn, and F. K. Jondral, “Mutual interference in OFDM-based spectrum pooling systems,” in Proc. 2004 IEEE Veh. Technol. Conf. – Spring, vol. 59, May 2004.

[4] G. Bansal, M. J. Hossain, and V. K. Bhargava, “Adaptive power loading for OFDM-based cognitive radio systems,” in Proc. 2007 IEEE International Conf. Commun., pp. 5137–5142.

[5] P. Wang, X. Zhong, L. Xiao, S. Zhou, and J. Wang, “A general power allocation algorithm for OFDM-based cognitive radio systems,” in Proc. 2009 IEEE International Conf. Commun. Workshops, pp. 1–5.

[6] G.P.S. Tej, T. Nadkar, V. M. Thumar, U. B. Desai, and S. N. Merchant,“Power allocation in cognitive radio: single and multiple secondary users,” in Proc. 2001 IEEE Wireless Commun. Netw. Conf., pp. 1420–1425.

[7] V. M. Thumar, G.P.S Tej, T. Nadkar, U. B. Desai, and S. N. Merchant,“Power allocation, bit loading and sub-carrier bandwidth sizing for OFDM-based cognitive radio,” EURASIP J. Wireless Commun. Netw., 2011:87.

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[14] M. R. Musku, A. T. Chronopoulos, and D. C. Popescu, “Joint rate and power control using game theory, in Proc. 2006 IEEE Consumer Commun. Netw. Conf., pp. 1258–1262.

[15] M. Hayajneh and C. T. Abdallah, “Distributed joint rate and power control game-theoretic algorithms for wireless data,” IEEE Commun.Lett., vol. 8, no. 8, pp. 511–513, Aug. 2004.

[16] Q. D. La, Y. H. Chew, and S. Boon-Hee, “An interference minimization game theoretic subcarrier allocation algorithm for OFDMA-based distributed systems,” in Proc. 2009 IEEE Global Telecommun. Conf.,pp.16.

[17] Z. Han, Z. Ji, and K. J. R. Liu, “Fair multiuser channel allocation for OFDMA networks using Nash bargaining and coalitions,” IEEE Trans.Commun., vol. 53, no. 8, pp. 1366–1376, 2005.

[18] H. Kwon and B. Lee, “Distributed resource allocation through nonco-operative game approach in multi-cell OFDMA systems,” in Proc. 2006 IEEE ICC, pp. 4345–4350.

[19] D. Yu, D. Wu, Y. Cai, et al., “Power allocation based on power efficiency in uplink OFDMA systems: a game theoretic approach,” in Proc. 2008 IEEE ICCS, pp. 92–97.

[20] W. Wang, Y. Cui, T. Peng, and W. Wang, “Noncooperative power control game with exponential pricing for cognitive radio network,” in Proc.2007 IEEE Veh. Technol. Conf., pp. 3125–3129.

[21] Nie Nei, “ A game theoretic approach to interference management in cognitive networks,”

G.Sivaranjani received Bachelor of Engineering with first class in Electronics and Communication Engineering at Periyar Maniammai College of Technology, Tanjore in the year 2008 and doing Master of Engineering in Communication Systems at Anna University, Regional Centre, Coimbatore .She has 3.3 years of experience in teaching profession. At present she is working as lecturer in the Department of

ECE at Coimbatore Institute of Engineering and Technology, Coimbatore. Her current research interest includes wireless and mobile communications, OFDM systems and satellite communications.

S.Sarika received Bachelor of Engineering with first class in Electronics and Communication Engineering at Maharaja Prithvi Engineering College at Coimbatore in the year of 2010 and doing Master of Engineering in Communication Systems at Anna University, Regional Centre, Coimbatore .She has 2.2 years of experience in teaching profession. At present she is working as lecturer in the department of ECE at Tejaa Shakthi

Institute of Technology, Coimbatore. Her current research interest includes wireless and mobile communications, wireless networks.

Patel Piyusha B. and Vishal S .Vora 10


Design Control Unit & ROM Unit of Low Power FFT Processor for OFDM System

Patel Piyusha B. and Vishal S .Vora

Abstract: This paper specifically addresses the power efficient design of an FFT processor as it relates to OFDM (Orthogonal Frequency Divison Multi Plexing) communication. The FFT/IFFT are widely used in various area such as telecommunication, speech and image processing, medical electronics etc. FFT/IFFT is used as one of the key component in OFDM-based wideband communication systems, like xDSL modems , wireless mobile terminals and remote communication device that rely on limited battery powered operation. Control Unit & ROM Unit of FFT processor is design in VHDL & Simulate the result.

Keywords: About four key words or phrases in alphabetical order, separated by commas.

I. INTRODUCTION Increasing speeds and complexity of wireless

communication systems have necessitated the progress and advancement of high performance signal processing elements. Today's emerging technologies require fast processing and efficient use of resources. These resources include power, memory, and chip area. Ongoing research seeks to optimize resource usage as well as performance. Design becomes a balance and compromise of flexibility, performance, complexity, and cost.

This project will specifically address the power-efficient design of an FFT processor as it relates to emerging OFDM communications such as cognitive radio. Cognitive radio is a method of wireless communication by way of dynamically adapting the transmission of multiple subcarriers to changing conditions in the communication channels. These subcarriers are enabled by a modulation scheme known as orthogonal frequency division multiplexing (OFDM). OFDM converts a high data rate signal into multiple lower data rate signals for simultaneous transmission through numerous channels.

The Fast Fourier Transform (FFT) processor is the heart of

OFDM that enables its fast and efficient modulation of signals. The FFT algorithm is a fast computation of the Discrete Fourier Transform (DFT) which is an essential component of the modulation scheme used in OFDM. As the FFT processor is the most computationally intensive component in OFDM communication, an improvement in the power efficiency of this component can have great impacts on the overall system. These impacts are significant considering the number of mobile and remote

Patel Piyusha B. is with Department of ECE, Gujarat Technical University, Ahmadabad, India and Vishal S .Vora is with Dept. of ECE, Assistant Professor of Atmiya Institute of Technology & Science, Rajkot, Gujrat Emails: [email protected], [email protected]

communication devices that rely on limited battery-powered operation. This project will serve as an exploration of current FFT processor algorithms and architectures as well as optimization techniques that aim to reduce the power consumption of these devices.

A. OFDM (ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING)

Orthogonal frequency-division multiplexing (OFDM) is a method of encoding digital data on multiple carrier frequencies. OFDM has developed into a popular scheme for wideband digital communication, whether wireless or over copper wires, used in applications such as digital television and audio broadcasting, DSL broadband internet access, wireless networks, and 4G mobile communications.

OFDM technology is already in use for many

communication systems such as ADSL, wireless local area network (WLAN), and multimedia communication services. OFDM is the approach taken to utilize available spectrum. The basic principle of OFDM is to split a high rate data stream into a number of lower rate streams and transmit them simultaneously over a number of subcarriers. that the number of subcarriers could be reduced and that not all used subcarriers will contain useful data, it is again evident that an FFT processor for this application should have the flexibility to accommodate various input lengths. Sub-carrier spacing and symbol duration are selected to obtain orthogonality between subcarriers.

Among these, 1440 and 240 subcarriers are used for data

and pilot transmission, respectively." The number of subcarriers could also be based on bandwidth allocated to each user. Seeing that the number of subcarriers could be reduced and that not all used subcarriers will contain useful data, it is again evident that an FFT processor for this application should have the flexibility to accommodate various input lengths. Sub-carrier spacing and symbol duration are selected to obtain orthogonality between subcarriers. It is this orthogonality that has eliminated cross-talk between the sub-channels and the requirement for inter-carrier guard bands. This has also simplified the design of both the transmitter and the receiver.

Other advantages of OFDM as a modulation scheme are

listed below:

1) OFDM Advantages:

• Robust against narrow-band co-channel interference

• Robust against inter-symbol interference



(ISI) and fading caused by multipath propagation

• High spectral efficiency • Efficient implementation using FFT • Low sensitivity to time synchronization errors • Tuned sub-channel receiver filters are not required • Approach Shannon capacity [the theoretical limit of

data transmission through an additive white Gaussian noise (AWGN) channel]

• Adaptive resource allocation • High data rates • Robustness to multipath delay spread • Integrates with spectrum sensing

2) OFDM Disadvantages:

• Sensitive to Doppler shift • Sensitive to frequency synchronization problems • High peak-to-average-power ratio (PAPR),

requiring linear transmitter circuitry, which suffers from poor power efficiency

1.2 OFDM Application: Many Communication system such as ADSL

(Asymmetric digital subscriber line service used in home networking)

Broadband Communication Technology used for connecting to the internet

Wireless local area network(WLAN) Multimedia Communication

3) OFDM System: OFDM Transmitter:

High Speed Data

Figure 1.OFDM Transmitter

OFDM Receiver: Received High Speed Data

Figure 2.OFDM Receiver

A traditional OFDM system is comprised of several components including a convolutional coder, signal mapper (QPSK, QAM, etc.), FFT processor, parallel-serial converters, and digital-analog converters. A generic block diagram of an OFDM system is shown below. For the purpose of this paper, the discussion of these components

will be limited to the FFT processor. In OFDM, a Fast Fourier Transform (FFT) is used to realize the multi-carrier modulation, which reduces the complexity of OFDM systems. With increasing OFDM system speeds and data throughput demands, the implementation of a high speed FFT processor has become the bottleneck of advancement of OFDM techniques.

II. FAST FOURIER TRANSFORM (FFT)

A. FFT Algorithms

The power of the Fourier Transform comes from the fact that even aperiodic signals can be expressed or approximated as a sum of periodic signals. This is important because most of the signals that are of interest in analyzing are not purely periodic in nature. For example, sound recordings of voice and music or transmission of data contain information of varying periods or frequencies. Being able to represent these signals as a sum of periodic signals becomes important when considering the systems through which one would like to pass these signals, specifically, linear time-invariant (LTI) systems. LTI systems are used for much of the signal processing that occurs today. There exist eigen functions for LTI systems where the output of the system is exactly a scaled version of the unmodified input. Sinusoidal periodic signals that can be written in the form ℮jwt are eigen functions for all LTI systems. Using the Fourier Transform, aperiodic signals that are common in real life systems can be analyzed and processed as periodic eigenfunctions using common LTI systems.

Some of the mathematics involved can be understood in context of a signal, such as sound. A sound signal with a given frequency w can be written mathematically as ℮jwt . The total sound experienced at the ear could be expressed as the sum of all frequencies each with -magnidute X(w) as

∞ x(t)=1/2π ∫ X(w) ℮jwt dw

-∞

The Fourier Transform giving us the magnitudes of each frequency contained in the signal can be written as

∞ X(w)= ∫ x(t) ℮-jwt dt

-∞

The Discrete Fourier transform can then be written as N-1

X(k)= ∑ x(n) e-j2πkn/N , 0≤ k ≤ N-1 n=0

N-1

X(k)= ∑ x(n) WN , 0≤ k ≤ N-1 n=0

Fast Fourier Transform algorithms are mathematical simplifications of the Discrete Fourier Transform (DFT). They exploit symmetries and periodicity in the transform in order to reduce the number of mathematical computations. This is done by a divide and conquer method first invented by Carl Friedrich Gauss around 1805. It was later rediscovered and published by J.W. Cooley and John Tukey and has

Serial to parall-el

IFFT

D/A Conv-eter

Paral-lel to serial

Low pass Filter-ing

Parallel to serial

FFT

Serial to parallel

A/D Conv-erter

Low pass filtering



become known as the Cooley-Tukey algorithm. This method effectively reduces the computational complexity of the DFT from order 0(N2) to 0(N log2(N)). There have since been many variations of this algorithm aimed at reducing the complexity of the DFT calculations. These families of fast algorithms for computing the DFT are commonly known as FFT algorithms. There are also FFT algorithms that are approximations that trade accuracy for computation speed, but these methods of approximation are not covered in this report. FFT computations can also be classified as Decimation In Time (DIT) orDecimation In Frequency (DIF) where the required computations are identical, but the order is essentially reversed.

B. Different radix FFT:

1) Fixed-radix FFT:

Fixed radix decompositions are algorithms in which the same decomposition is applied repeatedly to the DFT equation. The most common decompositions are radix-2, radix-4, radix-8 and radix-16. An algorithm of radix-r can reduce the order of computational complexity to 0(N logr(N)). In general, higher-radix algorithms perform faster but require higher complexity hardware when compared with smaller-radix algorithms. They also require the input to be of a length exponentially related to the radix. This can potentially lead to wasted computations if input lengths are much smaller than the next exponential size required by the radix.

The basic unit of a DFT calculation is often referred to as a "butterfly" calculation because of the shape of its flow diagram. A radix-2 simplified butterfly flow diagram is shown below. In the diagram, WN

-j2π/N which is commonly refered to as the twiddle or phase factor.

ak

N Ak

N bk

N Bk

N

WN x-1

Figure 3. Radix-2 buterfly flow diagram

2) Split-radix FFT: x[n] x[n+N/4] Wk

N x[n+N/2] X[4k+1] -1 Wk

N x[n+3N/4] X[4k+3]

Figure 4. Butterfly signal flow graph of split-radix-2/4 DIF FFT

The split-radix algorithm is a method of blending two or

more radix sizes and reordering the sequence of operations in order to reduce the number of computations while maintaining accuracy. "Split-radix FFT algorithms assume two or more parallel radix decompositions in every decomposition stage to fully exploit advantage of different fixed-radix FFT algorithms [2]." As an example of how this reordering takes place, a radix 2/4 flow graph and implementation are shown below. Similar transformations can be done for split-radix-2/8, -2/16, - 2/4/8, and -2/4/8/16 implementations.

3) Mixed –radix FFT:

Mixed-radix refers to using a variety of radices in succession. One application of this method is to calculate FFTs of irregular sizes. For example, a specific application could use radices 2, 3, and 5 to compute an FFT with a size that has those numbers as factors. Mixed-radix can also refer to a computation that uses multiple radices with a common factor. This could be a combination of radices such as 2, 4, and 8. These can be ordered in a way to simplify and optimize calculations of specific sizes or to increase the efficiency of computing FFTs of variable sized inputs. 3. Architecture of FFT

3.1 Simple Architecture:

The choice of hardware architecture also plays a part in optimizing FFT calculations. The figure below shows simple block diagrams of the most commonly used FFT architectures.

Each architecture comes with advantages and disadvantages. Single- and dual-memory architectures have relatively small processor areas but have lower data throughput and require higher clock frequencies. Dual-memory architecture has separate memory for butterfly inputs and butterfly outputs as opposed to one shared memory .A variation of dual-memory involves memory "ping-ponging" where "source and destination memories are interchanged between stages ." This allows data fetching, FFT butterfly computation, and data storing to memory to be combined into a single cycle loop. Parallel architecture can further increase the data throughput allowing for increased processing speed.

Pipeline architecture is the most popular due to its increased throughput and lower clock rates. Compared with memory-based architecture, however, pipeline architecture needs a more complicated control block . The pipeline architecture includes memory components called buffers between calculations stages. These buffers aid in managing data flow and scheduling. An example of a radix-2 signal flow graph is shown above.



x[0] X[0] x[1] X[8] x[2] X[4] -j x[3] X[12 W0

8 x[4] X[2] W1

8 x[5] X[10 -j W2

8 x[6] X[6] -j W3

8 x[7] X[14 W0

16 x[8] X[1] W1

16 x[9] X[9] W2

16 x[10] X[5] W3

16 -j x[11] X[13 -j W4

16 x[12] X[3] -j W5

16 x[13] X[11 -j W6

16 x[14] X[7] -j W7

16 -j x[15] X[15

Figure 5. Split-radix-2/4 DIF FFT signal flow graph of a 16-point example x=input & X= output

Figure 6 . Single memory architecture block diagram Figure 7 . Dual memory architecture block diagram

Figure 8. Pipeline architecture block diagram

x[0] X[0] x[1] X[4] W0

8 x[2] X[2] W2

8 x[3] X[6] W0

8 x[4] X[1] W1

8 x[5] X[5] W2

8 W08

x[6] X[3] W3

8 W28

x[7] X[7]

Proc

Main Memory

Proc

Main Memory

Main Memory

Buff

Buff

Buff

Proc

Proc



Figure 9 . Projection mapping of the pipeline radix-2 DIF

3.2 FFT processor Block Diagram: In the paper we present the on-going research project

on design of low-power FFT processors. FFT Processor design was to be a 32-bit floating

point FFT processor capable of computing a 2048 point FFT.

Input Output Data Data (Serial (parall /Parall -el/ -el) serial)

Figure 10. Block diagram of FFT Processor This baseline was designed following the organization and

architecture of an 8-point FFT processor set forth in Specifically, it had a single butterfly processing unit, with supporting ROM, RAM, Counter unit, cycles unit, control unit, and address generation unit

The baseline processor made use of dual port RAM

for the reading and writing of processor inputs and results. Using 32-bit floating point number representation and mathematics, the processor was able to compute the DFT with very little error as can be seen in the data analysis.

I have run size configuration unit , Butterfly processing unit,ROM Unit & Control Unit in VHDL and simulate the result.

The two primary strategies for pipeline buffering are Multiple-path Delay Commutator (MDC) and Single-path

Delay Feedback (SDF). Because MDC architecture requires larger memory size and spends lower hardware utilization, it is usually less desirable than the SDF architecture. SDF memory is series-inseries- out and is comprised of a "first-in-first-out (FIFO) shift register to be the delay element and to feedback the previous input data to compute the DFT ." In the SFD pipelined architecture, the butterfly element has two operational modes. The first mode is used to fill the shift register with new inputs while transferring previous results to the next stage. The second mode is used to run calculations using the newly acquired inputs and store the subtraction results back into the shift register while the addition is sent to the next stage (see figures below) . (a) (b) Figure 11. pipelined SDF operational FFT modes Twiddle Factor Figure 12. 8-Point radix-2 singal path delay feedback (SDF) architecture In a fully pipelined architecture, there is one computational block for eachstage in the FFT. For example, in a 2048 point FFT processor, there will be 11 processing units connected together. Inputs and results will progress through the pipelined stages while previous stage processing units are filled with new data. In addition to the computational block, a typical FFT processor includes components such as the address generation block, twiddle factor memory (or generation) block, and control block. 3.3 Platform to be used VHDL stands for VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit, a project sponsered by the US Government and Air Force begun in 1980 to advance techniques for designing VLSI silicon chips. VHDL is an IEEE standard.

Using VHDL for design synthesis:

• Define the design requirement

controller Butterfly

Processing unit

Address Generater unit

Coefficient ROM

S/P

P/S

FFT RAM

Size Configura-tion unit

Buf

fer

BP

BP B

uffe

r BP B

uffe

r

ROM ROM

Shift register

Shift register

4 2 1

Butterfly

Butterfly

Butterfly -j



• Describe the design in VHDL code

• Simulate the source code

• Synthesize, optimize, and fit the design

• Simulate the design

• Implement the design

3.3 Optimization Techniques Several methods have been employed over the years and in recent times to further optimize the calculation of the DFT. Most endeavors attempt to reduce the number of mathematical operations required to arrive at the solution while others strive to optimize for a resource such as power, speed, area, or memory. Of the many optimization methods previously explored by researchers, a few are summarized below. The following summaries are by no means a comprehensive list of possible modifications but will serve as helpful guidelines in determining desirable implementations. Additional methods exist, and still others have yet to be discovered. 3.4 Power Optimization

There are many applications where small power consumption is desired. Such is the case for devices running on battery for extended periods of time. Power reduction can be achieved by reducing the amount of processing needed or by changing device parameters. If the number of operating logic gates is lowered, then the amount of power consumed is also reduced. The dynamic power used in CMOS switching can be characterized by the following equation: Pswitch = (1/2)a*C*FC|k*Vdd2 where a is the switching activity factor, Q is the load capacitance, Fcik is the clock frequency, and Vdd is the supply voltage. This equation can provide some insight on the effects of design decisions. For example, parallelization adds capacitance, but it also lowers frequency. You could then lower the supply voltage and realize quadratic power savings. Thus, the pursuit of lower power consumption is assisted by the emergence of more efficient algorithms, yet it can be hindered by increasing clock rates. 3.5 Speed Optimization

There are many ways to optimize the speed of an FFT processor, and this is still an ongoing area of research with constant improvements. In general, the concept for optimizing the speed of an FFT processor is to minimize the number of calculations or steps needed to arrive at the solution. This is done primarily by optimizing algorithms and processor architectures. Part of the difficulty in realizing speed optimization is finding a solution that is efficient at solving a wide variety of problems. Solutions found for a specific application may not be applicable to another of interest. An evaluation must be made to determine the needs of an application and the optimization technique that is most appropriate. Pruning is a method of determining which FFT calculations are unnecessary for a given input. This applies to the case where many input values are zero. Calculations and time can be saved by not using the processor to needlessly

multiply and add zeros to other inputs. Conversely, there is a cost of additional computation time to create an index which may or may not be made up for by the FFT computations saved. This method is best suited for inputs with regularly occurring zeros and may not be desired for systems with very unpredictable or changing inputs such as cognitive radio.

As it relates to speed optimization, pipelining splits the calculations into multiple distinct steps and allows calculations on the next inputs to be started while previous inputs are shifted to the following step. This allows for increased data throughput with less memory. The hardware required for pipelining involves more controls/timers, but the calculation elements have more regularity and modularity.

Figure 13. Comparison of computation for radix-2 FFT and transform decomposition for N=1024

This modularity can aid in performing efficient FFT calculations on a variety of input sizes. Pipelining can be implemented on individual processes in the processor as well as on the processor architecture as a whole.When architecture is referred to as being pipelined, it consists of multiple processing units that are staged with inputs and outputs timed in a way that enables the next stage to start calculations on current outputs while the current stage receives new data for calculation. Transform decomposition is a method developed in for analyzing the calculation needs for a given input and determining which computations are unnecessary. Its purpose is similar to pruning, but its implementation is different. It is shown that for inputs with a large number of zero values, the number of multiplications performed is dramatically decreased. This method could be advantageous in OFDM if many of the subcarriers are set to zero because of under-utilized or noisy channels. A graph showing the number of multiplications versus number of non-zero inputs using this technique is shown below. Ideally, cognitive radio will be able to dynamically adjust OFDM subcarriers to prevent this large number of irrelevant inputs.

Parallel-butterfly and dual-butterfly are terms used in to describe methodsof parallel computations in a pipeline that includes a separate butterfly for calculating steps involving a twiddle factor that equals 1. This separate butterfly consists of only additions and can be computed in parallel with only



the small increase of adders to hardware. This results in slightly faster computation with minimal increase to chip size. Another parallel architecture dubbed the "Supper-FFT" is a complicated architecture involving an array of pipelined FFT processors each with local cache but with shared global memory. The goal of this processor was to increase data bandwidth while decreasing power consumption. Part of the power reduction is attributed to the strategic placement of devices on the chip to reduce losses due to long wire lengths in the interconnect network.

Much work has been done to simplify the mathematical

algorithms that define the FFT processors. The results of this work have the potential to increase processor speeds, reduce power consumption, reduce chip area, and possibly reduce memory size. So far, no theoretical lower limit to the number of computations needed has ever been determined. The fixed-radix, divide and conquer method, has long been thought of as an efficient method of computing the DFT, but several advancements have increased the efficiency even further.

One method, sometimes referred to as the lifting scheme,

can change a radix-4 computation from 4 real multiplies and 2 real adds to 3 real multiplies and 3 real adds. While this doesn't reduce the total number of mathematical operations needed, it does slightly reduce the complexity of computer processor computations leading to a faster, more efficient algorithm. In 1968, the algorithm known as split-radix was first presented and held the record for lowest published count for power-of-two size N calculation, which requires 4A/log2A/ - 6A/ + 8 real multiplications and additions. This record was broken in 2007 by two groups, Johnson/Frigo and Lundy/Van Buskirk. Each was able to reduce the number of real multiplications and additions to approximately 34/9 N log2(N). These new algorithms were modified versions of the split radix that previously held the record. Another optimization scheme developed is known as the Rader- Brenner algorithm of 1976 which factors the algorithm to use purely imaginary twiddle factors "reducing multiplications at the cost of increased additions and reduced numerical stability." While each of these is an optimization for the FFT, it is important to remember that a general optimization may not be the best method for a specific application, and a specific optimization may not be the best for a general application. Care must be taken to use the correct optimization for any one application. 3.6 Twiddle Factor Storage/Generation The storage and/or generation of twiddle factors (FFT coefficients) has been an item of interest to many processor designers because of its impacts on not only speed, but memory and area as well. Traditional methods of dealing with twiddle factors include either storing or computing the needed values. All needed values can be stored in memory as a look-up table (LUT) or only e1 can be stored while the rest of the values are computed from it. Clearly, one method requires

more memory and the other requires more computation. A system for efficiently storing and generating twiddle factors that balances memory usage and computational needs is proposed in. This implementation exploits coefficient symmetries to store 1/8 of the values for radix-8 (1/4 for radix-4) and computes the rest. The values to be stored are strategically chosen to reduce the amount of computations required to generate the rest. This method requires more hardware and introduces a delay, but results are shown to reduce area, memory, and power for FFT computations greater than 1000 points. The equations and block diagrams for the N/4 and N/8 coefficient generators for reference.

III METHODOLOGY

A. Purpose and Goal

With mobile devices increasing in complexity and capability, the power requirements to operate these devices are continually increasing. Given this trend, low power electronics with the capability of extending run time on limited battery capacity are more important than ever. Based on the growing need for mobile devices to have advanced communication capabilities while extending battery life, this project design had a primary focus on power reduction of the FFT processor. Implementation techniques with potential power savings were reviewed and compared when deciding which designs would have considerable impact when targeting OFDM applications.

This project documented the power savings obtained by

the design and implementation of many of these techniques. Care was taken to achieve a highly organized processor design with modular components that can be easily modified and analyzed independent from other components. This led to a completely synthesizable solution that could serve to facilitate future research in the area of FPGA design of FFT processors.

B. Design Process and Baseline The first task was to come up with a design that would serve as the baseline against which to compare all other design choices and implementations. This baseline design was to be a 32-bit floating point FFT processor capable of computing a 2048 point FFT. This baseline was designed following the organization and architecture of an 8-point FFT processor set forth in . Specifically, it had a single butterfly processing unit, with supporting ROM, RAM, Counter unit, cycles unit, control unit, and address generation unit. The baseline processor made use of dual port RAM for the reading and writing of processor inputs and results. This 2048 point FFT processor was successfully implemented and tested for computational accuracy. C. FFT Processor Components 1. Size Configuration Unit 2. Butterfly Processing Unit



3. ROM Unit 4. Control Unit 5. Address Generator Unit The address generation unit is where most of the complex control actually takes place. This unit takes on the complex role of determining the correct information that needs to go to each unit at specific times. One process completed is to get the correct inputs from the RAM to the butterfly processing unit during the correct cycles. It also determines which twiddle factor is needed from ROM memory during each of the calculations. The final outputs are then coordinated to be written back to the appropriate locations in memory. a. Butterfly Counter: Keeps track of how many butterflies have been computed in the current stage b. Stage Counter: Keeps track of how many stages have been completed c. IO/Stage Done signal generator: Signals the completion of the current process to the control unit. d. Address Index Generator: Uses size, stage, and FFT information to determine needed address information e. 10 Address Generator: Passes unmodified addresses during input operation and bit-reversed addresses during output operation. f. Address Shifters: Store the input address used for the butterfly processor during the pipelined process so that the same address can be used cycles later to store the butterfly processor results. g. Multiplexers: Used to select between addresses generated for input/output and those generated for the butterfly processor operation. h. ROM Address Generator: Determines the address location for the appropriate twiddle factor used in each butterfly calculation. 6. RAM Unit The RAM unit consists of dual-port RAM capable of simultaneous read and write to meet the demands of the pipelined butterfly calculation process. The RAM is used for storing the inputs and results of each stage and has 4096 (2N) available banks of 16 bits each. Real and Imaginary components of the complex data used by the processor are stored in independent memory banks separated by N addresses. In this manner, the first N addresses of the RAM are used to store the real values, while the second N addresses of the RAM contain the imaginary values of the complex inputs and results.

IV. SIMULATION RESULT

1. Size Configuration Unit The size configuration unit is passed information received in the first word of the incoming signal. This input contains the

size of the FFT to be computed. The configuration unit passes this information along with the number of computational stages needed to the other components. All of the components are programmed to automatically decrease or increase calculations or functions performed to match the current input size.

2. Butterfly Processing Unit

The butterfly processing unit computes an inplace radix-2 FFT calculation of two 16-bit fixed point numbers as described previously. a. Flip Flops: Used to control data flow and break the process into separate pipelined steps. b. Multiplexer Units: Used as selectors that control which data is passed on during each cycle in the pipeline. c. Negate Unit: Used to complete necessary mathematical functions of the DFT equation.



d. Multiplier Unit: Used to complete necessary mathematical functions of the DFT equation. e. Adder Units: Used to complete necessary mathematical functions of the DFT equation.

3. ROM Unit The ROM unit stores N/2 complex twiddle factor values that were pre-computed and converted to fixed point binary representation.

4. Control Unit The control unit is an eight stage finite state machine that receives input signals from the other components which indicate the completion of tasks performed. Based on these inputs, the controller progresses through its states from configuration to memory access and calculations to final output. Signals are sent to other components indicating the current process.



A. Fixed Point FFT power Comperison

B. FFT Processor power (W) Comperison :

Floating point 32-bit

Fixed point 16-bit

configuration

Reduced multiplies

Total Quiescent Power

0.10313

0.10313

0.10313

0.10313

Total Dynamic Power

0.48384

0.13037

0.12415

0.11355

Total power

0.58696 0.2335 0.22728 0.21667

Junction temp

25 25 25 25

FFT processor

0.44942 0.10804 0.1047 0.09538

Size configuratio-n unit

0 0 0.00076 0.0009

RAM 0.14729 0.09827 0.09401 0.08366 ROM 0.00022 0.00022 0.00022 0.00022 Butterfly Processing unit

0.27876 0.00565 0.00234 0.00274

Address Generator unit

0.00031 0.00037 0.00047 0.00083

Control unit

0.00063 0.00083 0.00012 0.0001

V. Conclusion This paper considers numerous power-saving techniques

available for FFT processor design while taking into account the current technology requirements that are emerging for tomorrow's communications. As performance requirements continue to increase while devices are becoming more and more portable, the need for power efficiency becomes ever more important.

Acknowledgement We have taken efforts in this paper. However, it would not have been possible without the kind support and help of many

individuals. we have highly indebted to Prof. A.M.Kothari , AITS, Rajkot for his guidance and constant supervision as well as for providing necessary information regarding the paper. we would like to express us gratitude towards him for their kind co-operation and encouragement which help me in completion of this paper.

References

1. www.google.com 2. http://en.wikipedia.org 3. Thomas Lenart and Viktor b a l l “A 2048 COMPLEX POINT

FFT PROCESSOR USING A NOVEL DATA SCALING APPROACH”Jan 2000.

4. Hoffman and Altamiro Susin and Luigi Carro “A bit-serial FFT processor” Electroscience engineering.in 2005.

5. S. Y. Lee and C. C. Chen, "VLSI implementation of programmable FFT architectures for OFDM communication system," in IWCMC proceedings,2006

6. S. Reza Talebiyan and Saied Hosseini-Khayat “POWER ESTIMATION OF PIPELINE FFT PROCESSORS”in 2009.

7. DR. D. RAJAVEERAPPA1, K. UMAPATHY2 “Low-Power and High Speed 128-Point Pipline FFT/IFFT Processor for OFDM Applications” Department of ECE at Loyola Institute of Technology,Chennai,India.

8. Y. Zhao, A. T. Erdogan, and T. Arslan, "A novel low-power reconfigurable FFT processor," Institute of Electrical and Electronics Engineers, 2005.[Online] Available: http://ieeexplore.ieee.org [Accessed: Jul. 30, 2008].

9. Q. Zhang, And B.J. Kokkeler and Gerard J.M. Smit, “Adaptive OFDM System Design For Cognitive Radio”, Department of Electrical Engineering, Mathematics and Computer Science University

10. Weidong Li and Lars Wanhammar “A Pipeline FFT Processor” Electrical Engineering Dept.Linkoping University

11. Bevan M. Baas “AN APPROACH TO LOW-POWER, HIGH-PERFORMANCE, FAST FOURIER TRANSFORM PROCESSOR DESIGN” February 1999.

Patel Piyusha B. has pursuing M.E. in Electronics & Communication from Atmiya Institute of Technology & Science,Rajkot,Gujrat . Her research interest includes Digital Signal Processing & VLSI

Vishal S. Vora has pursuing Ph.D (Embedded system).he is right now

working as an assistant professor in department of Electronics & Communication at Atmiya Institute of Technology & Science, Rajkot, Gujarat . He had published more than 10 papers in reputed national or international journal and conference. He had attended and delivered expert talk in many workshop, STTPS and seminars of embedded system

Shilpa Rao and Arati S. Phadke 20


Implementation of AMBA compliant MemoryController on a FPGA

Shilpa Rao and Arati S. Phadke

Abstract: As microprocessor performance has relentlesslyimproved in recent years, it has become increasingly importantto provide a high-bandwidth, low-latency memory subsystem toachieve the full performance potential of these processors. In thepast years, improvements in memory latency and bandwidthhave not kept pace with reductions in instruction execution time.Caches have been used extensively to patch over this mismatch,but some applications do not use caches effectively. The result isthat the memory access time has been a bottleneck which limitsthe system performance. A Memory Controller is designed tocater to this problem. The Memory Controller is a digital circuitwhich manages the flow of data going to and from the mainmemory. It can be a separate chip or can be integrated into thesystem chipset. This paper revolves around building anAdvanced Microcontroller Bus Architecture (AMBA) compliantMemory Controller as an Advanced High-performance Bus(AHB) slave. The whole design is captured using VHDL,simulated with ModelSim and configured to a FPGA targetdevice belonging to the Virtex4 family using Xilinx.

Keywords: AHB, ARM, AMBA, Memory Controller.

I. INTRODUCTIONSince 1985, microprocessor performance has improved at

a rate of 60% per year. In contrast, latencies have improved byonly 7% per year, and bandwidths by only 15-20% per year.The result is that the relative performance impact of memoryaccesses continues to grow. In addition, the demand formemory bandwidth has increased proportionately (andpossibly even super linearly). These trends make itincreasingly hard to make effective use of the tremendousprocessing power of modern microprocessors.

Hence, Memory Controllers are built to attack thesedisadvantages. It provides a high bandwidth and low latencyaccess to off-chip memory. A Memory Controller translatesthe accesses from the requestors into commands understoodby the memory. It generates the necessary signals to controlthe reading and writing of information from and to thememory, and interfaces the memory with the other major partsof the system. The front end of the general memory controllerbuffers requests and responses and provides an interface to therest of the system. The back end provides an interface towardsthe target memory.

Shilpa Rao and Arati S. Phadke are with Department of ElectronicsEngineering, K.J. Somaiya College of Engineering, Vidyavihar,Mumbai-400077, India, Email: [email protected]

The embedded processors, such as ARM, of today'stechnology operate up to a few hundred mega-hertz. Most ofembedded and SoC applications are suited to operate withthese frequency requirements. But some high end applications,such as InfiniBand, require much more processing power andshould operate at much higher frequency. In such a case, it isdesirable to implement embedded and SoC application withmultiple processors. AMBA (Advanced Micro-controller BusArchitecture) is one of the widely used system bus architecturewhich caters to the above requirements.

The memory controller is compatible with AdvancedHigh-performance Bus (AHB) which is the latest generation ofAMBA bus, and hence called as “AHB-MC”. The AHB-MC isan Advanced Microcontroller Bus Architecture (AMBA)compliant System-on-Chip (SoC) peripheral [6]. It isdeveloped, tested, and licensed by ARM Limited.

The AHB - MC has several features: Adheres to the AMBA AHB protocol Synthesizable VHDL / Verilog RTL source Supports multiple memory devices of different types

like SRAM, ROM, and Flash Provides test bench and verification vectors Shares data path between memory devices to reduce

pin count Supports AHB single beat, 4 beat and 8 beat wrapping

bursts and split transaction.

II. ARCHITECTURE OF AMBA-AHBThe Advanced Microcontroller Bus Architecture (AMBA)

specification defines an on-chip communications standard fordesigning high-performance embedded microcontrollers.AHB is a new generation of AMBA bus which is intended toaddress the requirements of high-performance synthesizabledesigns [2].

The AHB-MC mainly consists of five modules: AHB slaveinterface, configuration interface, external memory interface,memory system, and data buffers [1]. Fig. 1, shows thearchitecture of AHB-MC.



Fig. 1 Architecture of AHB-MC

A. AHB Slave InterfaceThe AHB slave interface [4] converts the incoming AHB

transfers to the protocol used internally by the AHB-MC.Because of the design of the internal inter-connect, someoptimizations are made in the interface to improveperformance. It is a fully validated component which ensuresthat it obeys both the AHB protocol and the internal protocolthat the interconnect uses.

B. Configuration InterfaceThe internal memory controller has an APB configuration

port. The AHB configuration port is mapped to it using anAHB to APB bridge. The main function of the configurationinterface is to change the certain configuration registersaccording to the commands from AHB to APB bridge whichconverts AHB transfers from the configuration port to theAPB transfers that the configuration interface [3] require. Italso provides the read and write enable signals to the databuffers.

C. External Memory InterfaceThe external memory [4] issues commands to the memory

from the command FIFO, and controls the cycle timings ofthese commands. It generates the 1) Memory bank select and2) Memory write control signals.

1) Memory Bank SelectAHB-MC has four memory banks, which are selected by

XCSN signal. The XCSN chip select signal is controlled bythe address of a valid transfer, and the system memory mapmode. Since, the system will change the memory map after thesystem boot, the AHB-MC is designed to support a remapsignal which is used to provide a different memory map [7]. Sobefore the system memory is remapped, the boot ROM at0x3000 0000 is also mapped to the base address of 0x00000000. The relationship between the inputs and the generatedvalue of XCSN [4] is shown in Table I.

Table I. XCSN Coding

2) Memory write controlThe external memory controls XWEN for writes in word

(32-bit), half-word (16-bit), and byte (8-bit) quantities. Theexternal memory uses hsize[1:0] and haddr[1:0] to select thewidth and order of each write to memory. Table II shows therelationship between XWEN and the inputs from AHB bus.

Table II. XWEN coding

D. Memory SystemIn the ARM architecture, instructions are all 32-bits, while

instructions are 8-bits in the external ROM and SRAM.Therefore the lowest two addresses of ROM and SRAM arenot connected to the external address bus. Additionally, tosupport byte writing, SRAM needs to be separated as fourindependent banks or has a byte-write enable signal. The basicmemory system architecture is shown in Fig. 2.

hselect remap haddr[29:28] XCSN

0 X XX 1111

1 0 00 1110

1 0 01 1101

1 0 10 1011

1 0 11 0111

1 1 00 1110

1 1 01 1101

1 1 10 1011

1 1 11 0111

hsize haddr[1:0] XWEN

10(word) XX 0000

01(half) 0X 1100

01(half) 1X 0011

00(byte) 00 1110

00(byte) 01 1101

00(byte) 10 1011

00(byte) 11 0111



Fig. 2 Memory system architecture

The AHB-MC has two clock domains [3]: AHB clockdomain (hclk) and external memory clock domain (mclk).Asynchronous FIFO is used between two clock domains as adata buffer. The main benefit of asynchronous clocking is thatthe system performance can be maximized, while running thememory interface at a fixed system frequency. Additionally, insleep-mode situations when the system is not required to domuch work, you can lower the frequency to reduce powerconsumption.

E. Data BuffersOne of the most popular methods of passing data between

clock domains is to use a FIFO [5]. A dual port memory isused for the FIFO storage. One port is controlled by the senderwhich puts data into the memory as fast as one data word (orone data bit for serial applications) per write clock. The otherport is controlled by the receiver, which pulls data out ofmemory, one data word per read clock. Two control signalsare used to indicate if the FIFO is empty, full or partially full.

III. SYNTHESIS AND SIMULATION RESULTS

The architecture of AHB-MC shown in Fig. 1, can berepresented in form of a block diagram as shown in Fig. 3. Theoverall inputs and outputs of the system are also indicated.

Fig. 3 Overall inputs and outputs of AHB - MCThe functionality of the modules of AHB-MC is tested using

Xilinx ISE 10.1 tool in VHDL and simulated using ModelSim

6.2. The following steps are followed during theimplementation of this design: Code generation, Simulation,Synthesis, Power analysis, RTL schematic, Translate, Map,Place and Route, and finally Configured to a target device.

The RTL Viewer of AHB - MC is shown in Fig. 4. From thisfigure, it can be observed that asynchronous FIFOs are usedbetween two clock domains as data buffers.

Fig. 4 RTL Viewer of AHB-MC

For a target device xc4vlx15-12sf363 belonging to theVirtex4 family the Device Utilization Summary is shown inTable III.

Table III. Device Utilization SummaryLogic Utilization Used Available UtilizationNumber of Slices 2141 6144 34%Number of Slice FFs 2377 12288 19%Number of 4 input LUTs 2409 12288 19%Number of bonded IOBs 84 240 35%Number of GCLKs 16 32 50%

Power analysis of AHB-MC was carried out by using Xilinx’sXPower Analyzer. Table IV which shows the Power reportindicates that the total power dissipated by the AHB - MC is412mW.

Table IV. Power Report of AHB-MC

Power summary I(mA) P(mW)Total estimated power consumption 412Total Vccint 1.20V 182 219Total Vccaux 2.50V 77 193Total Vcco25 2.50V 0 0

Fig. 5, shows read with zero wait states form the ROM. Thecmd_in (10 which indicates the ROM read operation) isregistered at falling edge of hclk (AHB bus clock), after whichrd_fifo_rden (Read FIFO read enable) signal goes high. Theread data then reaches data_out (AHB data bus) at falling edgeof hclk. Write with zero states to the external RAM is also



shown in Fig. 5. A write operation to RAM is initiated whencmd_is set to 00. Then the address is send to AHB address busand wr_fifo_rden (Write FIFO read enable) signal goes high toenable the data from data_in (AHB input data bus) to bestored in the RAM.

Fig. 5 Read and write with zero wait state from ROM and toRAM respectively

IV. CONCLUSIONS

The read write operation is accomplished with zero waitstates from the external ROM and the write operation withzero states to the external RAM. By proposing the parallelcommunication in AMBA-AHB, the data transfer operationwill be fast as compared to serial communication. It alsoprovides the opportunity to use masters and slaves up to 16numbers and the data of every master is read and writtensimultaneously.

With the increase in system frequency, it is hard to achieveaddress decoding and memory access operations in one clockcycle due to which wait states are inserted. But the method ofinserting wait states will result in dramatic drop in systemperformance. Therefore, the burst method is presented in thispaper to resolve the problem. When the first beat of a burst isaccepted, it contains data about the remaining beats. Forexample, when AHB-MC gets the first beat of a read burst, allthe data required to complete the transfer can be read frommemory and restored in the read data FIFO. So this firsttransfer has some delay before data is returned. Butsubsequent beats of the burst can have less delay because thedata they require might have already been prepared in theFIFO.

Power dissipation is becoming a limiting factor for highperformance microprocessor design due to ever increasingdevice counts and clock rates. The proposed architecture ofAHB-MC also aims to optimize power. It is found that itconsumes a power of 412mW with a maximum frequency of355.77MHz.

REFERENCES

[1] Hu Yueli,Yang Ben, “Building an AMBA AHB compliantMemory Controller”, IEEE, 2011.

[2] “AMBA Specification (Rev2.0)”, ARM Inc, 1999.[3] “PrimeCell AHB SRAM/NOR Memory Controller”, Technical

Reference Manual, ARM Inc, 2006.[4] “AHB Example AMBA System”, Technical Reference

Manual, ARM Inc, 1999.[5] Clifford E. Cummings, Sunburst Design Inc., “Synthesis and

scripting Techniques for Designing Multi-Asynchronous ClockDesigns”, 2001.

[6] Sudeep Pasricha, “On-Chip Communication ArchitectureSynthesis for Multi-Processor Systems-on-Chip”, University ofCalifornia, 2008.

[7] “PrimeCell Synchronous Static Memory Controller”, TechnicalReference Manual, ARM Inc, 2001-2005.

Shilpa Rao has obtained Bachelor of Engineeringin Instrumentation Technology at SriJayachamarejendra College of Engineering,Mysore. She is currently pursuing Master ofEngineering in Electronics Engineering from K. J.Somaiya College of Engineering, Mumbai. Shehas worked as a software programmer for twoyears and also as a lecturer in the Department ofElectronics for three years. Her area of interestsinclude Low Power VLSI Design, HardwareDescriptive Languages, and Digital SystemDesign.

Prof. Arati S. Phadke is currently working as anAssociate Professor in the Department ofElectronics Engineering in K. J. Somaiya Collegeof Engineering, Mumbai with 22 years ofexperience in the field of teaching. She completedher Bachelor of Engineering in ElectricalEngineering from College of Engineering, Puneand Master of Technology in Power Electronicsfrom Indian Institute of Technology, Mumbai. Sheis an active member of IEEE since 1993 and hasbeen a Student Branch Counselor from2003-2009. She has been the recipient of the Best

Teacher Award, KJSCE, Mumbai in 2000 for her excellence in academicperformance. She has delivered a lot of guest lectures on HardwareDescriptive Languages and Embedded Systems for faculty and students ofvarious engineering colleges. Her research interests include Digital SystemDesign, Embedded Systems, Microprocessors and Microcontrollers.

Ravi R. Patel and Prof. Vijay K. Patel 24


SER Analysis of Iterative Channel Estimation Based on Least Square Method in OFDM

Ravi R. Patel and Prof. Vijay K. Patel

Abstract: Orthogonal frequency division multiplexing (OFDM) provides an effective and low complexity means of eliminating inter symbol interference for transmission over frequency selective fading channels. In OFDM systems, channel estimation is very crucial to demodulate the data coherently. For good channel estimation, spectral efficiency and lower computational complexity are two important points to be considered. In this paper, we explore Iterative channel estimation based on Least Square (LS) method in order to improve Symbol Error Rate (SER) by applying the feedback for OFDM system. We first investigate simple pilot based least square channel estimation technique and its performance. Then, in order to improve the performance we propose an iterative channel estimation and data detection technique by adding virtual pilots. Using iterative method we get improved Symbol error rate performance than conventional channel estimation method.

Keywords: Channel Estimation, Iterative Channel Estimation, Least square method and Orthogonal Frequency Division Multiplexing.

I. INTRODUCTION Currently, orthogonal frequency-division multiplexing

(OFDM) systems are subject to significant investigation. Since this technique has been adopted in the European digital audio broadcasting (DAB) system [1], OFDM signaling in fading channel environments has gained a broad interest [2]. For instance, its applicability to digital TV broadcasting is currently being investigated [3].

The use of differential phase-shift keying (DPSK) in

OFDM systems avoids the tracking of a time varying channel [4]. However, this will limit the number of bits per symbol and results in a 3 dB loss in signal-to-noise ratio (SNR) [5]. If the receiver contains a channel estimator, multi amplitude signaling schemes can be used.

In [6] and [7], 16-QAM modulation in an OFDM system

has been investigated. A decision-directed channel tracking method, which allows the use of multi-amplitude schemes in a slow Rayleigh-fading environment, is analyzed in [6]. Ravi R. Patel and Prof. Vijay K. Patel are with U. V. Patel College of Engineering, Ganpat University, Kherva, Gujarat, E-mails: [email protected], [email protected]

In the design of wireless OFDM systems, the channel is usually assumed to have a finite-length impulse response. A cyclic extension, longer than this impulse response, is put between consecutive blocks in order to avoid inter block interference and preserve orthogonality of the tones [8]. Generally, the OFDM system is designed so that the cyclic extension is a small percentage of the total symbol length.

In Section II, we describe the system model. Section III

discusses the least-squares (LS) and minimum mean-square error (MMSE) channel estimators. The LS estimator has low complexity, but its performance is not as good as that of the MMSE estimator while the MMSE estimator has good performance but high complexity. In Section IV we present Iterative technique to the LS estimators that use the virtual pilots. In Section V we evaluate the estimators by simulating a BPSK signaling scheme. The performance is presented in terms of symbol error rate (SER).

II. SYSTEM MODEL Figure 1 shows the OFDM base band mode where x is the

transmitted signal, y is the received signal, g(t) is the channel impulse response. Here, we use AWGN channel model and noise is the white Gaussian channel noise. A cyclic prefix (which is not shown in Figure 1) is used to preserve the orthogonality of OFDM consecutive blocks and to avoid the inter-symbol interference between the consecutive OFDM blocks.

Fig.1: Block diagram of OFDM channel estimator and detector



We consider a channel impulse response which is consists of 0 to N numbers and of 0 to N non- zero pulses. The impulse response of the channel is

0

( ) ( )N

m m sm

g t i T

(1)

where, im is the zero mean complex Gaussian random variable, g(t) is treated as the time limited pulse train, TS is the sampling period, τm is the delay of Nth impulse, where the first delay τ0 = 0 and others impulse delay have been uniformly distributed over the length of the cyclic prefix.

Fig 2: Sample spaced channel and non sampled spaced channel.

In the OFDM system, the channel impulse response time duration is less than the OFDM symbol time. The channel transfer function or channel attenuation h absorbs most of the channel energy within few samples. Figure 2 shows the energy absorption in time domain for two types of channel, the sample spaced channel and the non sample spaced channels. The sample spaced channel is a channel whose impulse response is finite and multiple of the system sampling rate, for that reason the DFT gives the optimal energy concentration [9]. For the non-sample-spaced channel, the IDFT of the channel attenuation h does not confine with cyclic prefix, because the channel attenuation h is the continuous Fourier transform of the channel g.

Although the IDFT of h does not confine with cyclic prefix but it preserves the orthogonality. The requirement for orthogonality is that the continuous time channel has length that is shorter than the cyclic prefix. By using the N-point discrete time Fourier transform (DFT) system can be modeled as

[ ( )* ]N N

gy DFT IDFT x nN

(2)

Here 0 1 1[ , , , , , , ]TNx x x x , 0 1 1[ , , ,, , , ]T

Ny y y y ,

0 1 1[ , , , , , , ]TNn n n n and * is called the cyclic convolution and

0 1 1[ , , , ,, , ]TNg g g g is determined by sinc functions [1].

0

sin( )1 ( ( 1) )sin( ( ))

N j mNk m m

mm

g i e k nN k

N

(3)

So, the amplitude im are the complex valued and 0 ≤ τm TS ≤ Tg , k is an integer value range of 0 to N-1, if τm is an integer then all the energy from, im is mapped to taps gk but when τm is not an integer then τm energy will leak to all taps of gk. Usually most of the energy is located near the original pulse location. The overall system can be written as

k k k ky x h n (4)

Here, k = 0, 1, 2………….N-1. hk is the channel attenuation vector for 0 to N-1 channel and gk is the channel energy for

0 to N-1 channel, where 0 1 1[ , , , , , , ] ( )Tk N kh h h h DFT g

For simplicity we may rewrite equation (14) as following y = xFg + n (5) F is the DFT matrix.

III. CHANNEL ESTIMATION The channel estimator provides the knowledge on the

Channel Impulse Response (CIR) to detectors. The channel estimation is based on the known sequence of bits which is unique for a particular transmitter and which is repeated in every transmission burst. The channel estimator is able to estimate the CIR for each burst separately by the exploiting transmitted bits and the corresponding received bits.

A. MMSE estimator The MMSE estimator major rule is to efficiently estimate

the channel to minimize the MSE or SER of the channel. In equation (6), Rgg and Ryy denote as the auto-covariance matrix of g and y respectively, where g is the channel energy and y is the received signal. Moreover, the cross covariance of g and y is denoted by Rgy and the noise variance E {|N|2} is denoted by δ2

n. The channel estimation by using MMSE estimator gMMSE can be derived as follows:

1MMSE gy yyg R R y

(6) Where,

{ }H H Hgy ggR E gy R F x (7)

2{ }H H H

yy gg n nR E yy xFR F x I (8) The columns in F are orthogonal and I is the identity matrix.



Fig 3: Block diagram of channel estimator.

From Figure 3, the channel impulse response hMMSE is as follows:

H HMMSE MMSE MMSEh Fg FQ F x y (9)

Where, 2 1 1[( ) ] ( )H H H H

MMSE gg n ggQ R F x xF R F x Fx (10) hMMSE is the channel attenuation for MMSE estimator, gMMSE is the channel energy, y is received signal, x is the transmitted signal and F is the DFT matrix [1].

B. LS Estimator The LS estimator has lower computational complexity than MMSE. The LS estimator for the cyclic impulse response g minimizes (y-xFg) (y-xFg)H and generates the channel attenuation as bellow

H HLS LSh FQ F x y (11)

Here, 1( )H H

LSQ F x Fx (12) And (y-xFg)H is the conjugate transpose operations. So, the lest square hLS can be written as

1LSh x y (13)

Where, the least square hLS is the channel attenuation for LS. Equations (9) and (13) are the general expressions for MMSE and LS estimators respectively. Both estimators have some own drawbacks. However the MMSE estimator performance is better but computational complexity is high, contrary the LS estimator has high mean-square error but its computational complexity is very low. For reducing computational complexity and improve performance, we have two channel estimation approaches. 1. Mean square error

The mean square error or MSE of an estimator is one of many ways to quantify the difference between the theoretical values of an estimator and the true value of the quantity being estimated. MSE measures the average of the square of the error. The error is the amount by which the estimator differs from the quantity to be estimated. We define the mean square error as Mean square error = mean [{abs (H) –abs (hestimator)}2] (14) Where, H is theoretical transfer function and hestimator is the calculated transfer function for each estimator.

2. Symbol Error Rate Symbol rate is the number of symbol changes made to the transmission medium per second using a digitally modulated signal. Symbol error rate for 16-QAM system is [10]

,160

3 (2 10s QAM

sEP erfcN

(15)

Where, erfc denoted complementary error function, Es denoted signal energy and N0 denoted bit rate.

IV. ITERATIVE CHANNEL ESTIMATION

Fig 4: OFDM receiver for iterative channel estimation

The channel estimation accuracy can be improved by adding virtual pilots using an iterative channel estimation and data detection. The hard decision symbols can be used as virtual pilots. Thus, there will be iteration between the decision and the channel estimation block at the receiver, which is a kind of decision feedback equalization technique, as seen in Figure-4. Initially channel is estimated using LS method which gives initial estimation now this estimated data is detected and again fed back for iterative estimation that gives the improved performance than the conventional LS method. This improved performance is closer to the MMSE method.

V. SIMULATION RESULTS In the simulations we consider a system operating with a

bandwidth of 500 kHz, divided into 64 tones with a total symbol period of 138 µs, of which 10 µs is a cyclic prefix. Sampling is performed with a 500 kHz rate. A symbol thus consists of 69 samples, five of which are contained in the cyclic prefix (i.e. L = 5). Figure 5 shows the comparison between the LS and MMSE estimator based on SER versus SNR. In the SNR range from 2 dB to 20 dB, the MMSE estimator SER is lower than the LS estimator. SERs of LS and MMSE are almost the same from 25 dB SNR range. Figure 6 shows the comparison between LS and iterative LS estimator based on SER versus SNR. From the result we can see that the SER of iterative LS is lower than conventional LS method. So SER is improved using iterative method.



Fig 5: Performance analysis for MMSE and LS based on SER versus SNR

0 2 4 6 8 10 12 14 1610

-2

10-1

100

SNR in DB

Sym

bol E

rror R

ate

SNR V/S SER FOR AN OFDM SYSTEM WITH LS/ITERATIVE LS ESTIMATOR BASED RECEIVERS

LS EstimateITERATIVE LS Estimate

Fig 6: Performance analysis of LS and iterative LS based on SER versus SNR

VI. CONCLUSION In this paper, performance analysis of iterative channel

estimation based on LS method for OFDM system is given. Firstly, we show the general structure of the LS and the MMSE estimator performances. Based on the performance analysis the MMSE estimator is recognized as better than LS estimator, but the MMSE estimator suffers from high computational complexity. After that we introduce iterative LS method to improve the SER. From the result we can conclude that iterative LS method has improved performance which is closer to the MMSE estimation method. REFERENCES [1] Jan-Jaap van de Beek, Ove Edfors, Magnus Sandell Sarah

Kate Wilson and Per Ola Borjesson, "On Channel Estimation in OFDM systems" In proceedings Of VTC'95 Vol. 2 pg.815-819

[2] Leonard J. Cimini, Jr., “Analysis and simulation of a digital mobile channel using orthogonal frequency-division multiplexing”, IEEE Duns. Comm., Vol. 33, no. 7, pp 665-675, July 1985

[3] M. Alard and R. Lassalle, “Principles of modulation and channel coding for digital broadcasting for mobile receivers”, EBU Review, no. 224, pp 3-25, August 1987

[4] B. Marti et al., “European activities on digital television broadcasting-from company to cooperative projects”, EBU Technical Review, no. 256, pp. 20-29, 1993

[5] John Proakis, Digital Communications, McGraw-Hill, 1.989. [6] Sarah Kate Wilson, R. Ellen Khayata and John M. Cioffi,

“16-$AM modulation with orthogonal frequency-division multiplexing in a Rayleigh-fading environment”, In Proc. VTC-1994, pp. 1660-1664, Stockholm, Sweden, June 1994.

[7] Peter Hoeher, “TCM on frequency-selective land-mobile fading channels”, In Proc. of the 5th Tirrenia International Workshop on Digital Communications, Tirrenia, Italy, September 1991.

[8] John A.C. Bingham, “Multicarrier modulation for data transmission: an idea whose time has come”, IEEE Communications Magazine, 28(5):5-14, May 1990.

[9] Ove Edfors, Magnus Sandell, Jan-Jaap van de Beek, Sarah Kate Wilson and Per Ola Borjesson, “Analysis of DFT based channel estimator for OFDM”, IEEE Transactions on Wireless Personal Communications, vol. 12, pp. 55-70, 2000.

[10] ‘‘Symbol error rate for 16-QAM’’.Available: http://en.wikipedia.org/wiki/Symbol-error-rate-for-16-qam

RAVI R. PATEL received his B.E degree in electronics & communication engineering from Government Engineering College, Surat, Gujarat in 2010. His M.TECH is pursuing in U.V.Patel College of engineering, Ganpat University, Kherva, Gujarat. PROF. VIJAY K.PATEL received his M.TECH degree in Telecommunication engineering from IISC Bangalore. His Ph.D. is pursuing in U.V.Patel College of Engineering, Ganpat University, Kherva, Gujarat. He is current an associate professor in U.V.Patel College of Engineering, Ganpat University, Kherva, Gujarat.

Pranjali Vinayak Keskar, Shubhangi Nimba Masare, Manjusha Suresh Kadam and Prof. Mrs. Seema U. Deoghare 28


Leaf Disease Detection and Diagnosis Pranjali Vinayak Keskar, Shubhangi Nimba Masare, Manjusha Suresh Kadam and Prof. Mrs. Seema U.

Deoghare

Abstract: In the research of identifying and diagnosing leaf diseases using computer vision intellectively in the agriculture, feature selection and shape classification is key question in pattern recognition and affects the design and performance of the classifier. Leaf spots can be indicative of crop diseases where leaf spots are usually examined manually and subjected to expert opinion. In this paper leaf disease detection and diagnosis system is developed to automate the inspection of affected leaves and helps identifying the disease type and thus provide corrective action. The developed system consists of four stages which includes HSI transformation, histogram analysis and intensity adjustment. The second stage is segmentation which includes adaption of fuzzy feature algorithm parameter to fit the application in concern. Feature extraction is the third stage which deals with three features, namely; colour, size and shape of the spots. The fourth stage is classification which comprises artificial neural network. Thus the system is applicable for detection and diagnosis of leaf diseases.

Keywords- Feature selection, Healthy leaf image, Disease leaf image, ANN

1 INTRODUCTION

In agriculture mass production, it is needed to discover the beginning of plant diseases batches early to be ready for appropriate timing control to reduce the damage, production cost, increase the income. Leaf batches differ in colour, shape and size according to cause. Leaf batch characteristics play a curial role in differentiating between the different causes. Leaf batches happen as a result of plant pathogen (fungi, bacteria, virus diseases), insect feeding.

The diagnosis of leaf batches may causes some confusion due to the similarities in batch’s shape, size and colour but only an expert could identify it. The first step in fighting against these leaf batches is the adequate recognition of their presence that i.e. correct diagnosis. An abnormal symptom is an indication to the presence of the disease, and hence, can be regarded as an aid in diagnosis.

2 ARCHITECTURE OF PROPOSED SYSTEM

To diagnosis the disease, an image processing system has been developed to automate the identification and classification of various disorders.

Pranjali Vinayak Keskar, Shubhangi Nimba Masare, Manjusha Suresh Kadam are with Pimpri Chinchwad College Of Engg. Nigdi, Pune, and Prof. Mrs. Seema U. Deoghare working as Assistant Professor At Pimpri Chinchwad College Of Engg. Nigdi, Pune, Emails: [email protected], [email protected], [email protected], [email protected]

The main three components are image analyser, feature repository and classifier. The whole process is divided into two phases: Offline and Online. In offline phase a large set of defected input images was processed by image analyser for extracting abnormal features. These features were stored in the feature repository for later usage by the classifier. In online phase, in which abnormal feature of a specific defected image is extracted by image analyser and then classified by the classifier into a specific disorder. [1]

Fig 1. Overall structure of system

3.BLOCK DIAGRAM OF THE SYSTEM

3.1 Block diagram

Fig 2. Block diagram of the system



3.2 Explanation

Computer:

The actual database of the project is stored in the PC. The disease affected leaf to be tested is compared with database in the PC which gives more accurate result and displays result.

Max 232:

The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply 232 voltage levels from a single 5-V supply. Each receiver converts 232 inputs to 5-V TTL/CMOS levels.

AVR ATmega16:

The AVR is a modified Harvard Architecture 8-bit RISC single chip microcontroller. ATmega16 has features like high-performance, Advanced RISC Architecture, 16K Bytes of In-System Self-programmable Flash program memory, high speed.

LCD, relay, computer are interfaced with the microcontroller. So all the controlling actions are taken by the AVR microcontroller.

LCD Display:

We are using LCD display for displaying various massages. We can display type of the disease and pesticide to be sprayed . We are going to use 16 x 2 alphanumeric LCD having inbuilt LCD drivers .

Fig 3. LCD Display

Relay driver IC ULN2003:

We are going to use relay driver IC ULN2003 to drive the relays that will control the pumps used for sprinkling of different pesticides.When the input to relay driver is logic 1, then it will turn on the relay by providing 0V (gnd) at the input of the relay. If logic 0 is applied at input of relay driver then it will go into the tristate.

Relay:

We have used 4 relays to control the pump for sprinkling the 4 different types of pesticides. After sprinkling the desired quantity of pesticide, the particular relay will get turned off. These relays are controlled by relay driver IC.

(a) (b) Fig 4. (a) Relay (b) Internal structure of relay

4 SOFTWARE PROCESSING (MATLAB FLOW):

Fig 5. Flow of proposed System

Image Analyser

The main purpose of image analyser is to extract the abnormal symptom. Image analyser consist of Image enhancement, image segmentation, feature extraction.[1]

4.1 Image Acquisition

The images are captured by using high resolution camera. The image from the camera is digitized into a 24 bit image with resolution 720 x 540 pixels.[3]

4.2 Enhancement phase

Appearance of an image is improved by image enhancement technique, also the Important features of the image can be highlighted. From the inspection of the infected leaves it was found that, the spots has intensity values higher than the other normal tissues. To extract that abnormal tissues, the enhancement processing consists of three steps: transformation of HSI to colour space, analysing the histogram of intensity channel to get the threshold, intensity adjustment by applying the threshold.[1]

5. HSI TRANSFORMATION

HSI (Hue Saturation Intensity) system is commonly used colour space in an image space, which is more intuitive to human vision. HSI system separates colour information of an image from its intensity information. Colour information is represented by hue and saturation value. While intensity



describes the brightness of an image. This makes an image good for human perception.

Formula for HSI

H=ArcTan(√3(G-B)/(R-G)+(R-B)….1

I=(R+G+B)/3………………………2

S=1-(min(R,G,B)/I)…………………3

5.1 Feature extraction phase

The purpose of feature extraction is to reduce the image data by measuring certain features or properties of each segmented regions such as colour shape or texture. This phase consist of two steps viz spot isolation and spot extraction

5.2 Spot isolation

Often, a segmented image consists of a number of spots. In order to extract features from the individual spot, it is necessary to have an algorithm that identify each spot. To identify each spot, we label each spot with unique integer and the largest integer label gives the number of spots in the image. Such identification algorithm is called component labelling. The following fig shows the binary segmented image and the labelled image after applying the component labelling algorithm.[1]

6. Feature extraction

In order to recognise the spot catagory, we measure several number of features in segmented image, to be later use for classification. These features corresponds to colour characteristics of the spots such as:[2]

1) Mean:

Mean of the gray level of the red, green and blue channel of spot. other feature corresponds to morphological characteristics of the spots such as: the length of principal axis, major and minor axis length of spot.

2) Length of principal axes:

Major and minor axes length is major and minor length of the ellipse.

3) Eccentricity:

The ratio of the distance between the foci and major axis length of the ellipse. Its value lies between 0 and 1.The spot whose eccentricity ratio is 0 is a circle while the spot whose eccentricity ratio is 1 is a line. It is given by

2*sqrt(((major/2)^2-(minor/2)^2)/major)

4) Equidiameter:

The diameter of the disk with the same area as spot is calculated as:

Sqrt(4* spot area/pi)

5) Solidity:

Also called as compactness, gas a value between 0 and 1,if the spot has a solidity value equal to 1, i.e. fully compact.

spotArea/convexArea

6. CENTER OF GRAVITY:

For a spot surface described by the function F(x,y) consisting of N pixels center of gravity coordinates (X,Y) can be calculated as:

X=(1/N)*∑∑ x Y=(1/N)*∑∑ y

6.1 Features Database

It is the component used to store the outputs of the feature extraction stage for the later usage by the classifier. The database is relational one, which consists of two tables namely a disorder table which is used to keep the track of disorder that have been processed and feature table, which is used to store the spot features for each disorder.

7. THE CLASSIFIER

An artificial neural network was used to perform our classification task. There are many different types of ANNs. The most widely used is back propagation ANN. This type of ANN is excellent for performing classification task. This configuration includes the number of layers, the number of neurons for each layer and the minimal number of training samples. This configuration is also called as the topology of ANN.

RESULTS

By using this system we successfully detected different types of diseases on a leaf which are stored in database. We compared different parameter values of healthy and disease affected leaf. Since there was very large difference in disease affected leaf parameter values with reference to healthy leaf parameter values, presence of disease was clearly identified. Also we sprinkled various pesticides according to type of disease detected.



Healthy leaf:

Fig 6.(a) healthy image (b)binary image (c)Segmented image

Disease affected leaf:

Fig 7. (a) citrus canker affected leaf image (b)binary image (c)segmented image

Result Table

Comparison table of healthy leaf and disease affected leaf

Parameter Healthy Leaf

Disease Affected Leaf

Leaf area 326.075275 cmsq

301.819010 Cmsq

Spot area 175.727591 cmsq

28.7184613 Cmsq

Major axis 105.83 cm

79.37 cm

Minor axis 79.37 cm 105.83 cm

Centre of gravity

X Y

177.99 177.99

173.46 173.46

Equidiameter 105.51

42.67

Eccentricity 6.804563 0.000000

Solidity 0.15

0.03

Conclusion

We have developed leaf disease detection and diagnosis system with the help of image processing which is capable of diagnosing disorders. A set of features was selected to be

extracted using feature extraction phase, and those features were stored in the feature database, which is designed for this purpose. The captured leaf image parameters were compared with the parameters of healthy leaf and disease was detected. According to disease pesticide control was done.

Reference

1. “An Integrated Image Processing System For Leaf Disease Detection And Diagnosis” - Mohammed E1-Helly, Ahmed Rafea, Salwa E1-Gammal

2. “Feature selection of cotton disease leaves image based on fuzzy feature selection techniques”-Yan-Cheng Zhang, Han Ping Moa.

3. “Remote Area Plant Disease Detection Using Image Processing”-Sabah Bashir, Navdeep Sharma

Prof. Mrs.Seema Deoghare working as Assistant Professor At Pimpri Chinchwad College Of ngg. Nigdi, Pune -44

Pranjali Vinayak Keskar Pursuing B.E (E&TC) Pimpri Chinchwad College Of Engg. Nigdi, Pune -44

Shubhangi Nimba Masare Pursuing B.E (E&TC) Pimpri Chinchwad College Of Engg. Nigdi, Pune -44

Manjusha Suresh Kadam Pursuing B.E (E&TC) Pimpri Chinchwad College Of Engg. Nigdi, Pune -44

Prof. Ashish G. Bajaj, Prof. Amar B. Chavan and Prof. Sachin S. Jadhao 32


Mobile IP Telephony: A solution to Rural Connectivity

Prof. Ashish G. Bajaj, Prof. Amar B. Chavan and Prof. Sachin S. Jadhao

Abstract: With the development of wireless LAN and VoIP technology, economical build-up of infrastructure in the rural areas of developing countries is now emerging as a real possibility. The paper proposes the deployment of WiFi/WiMAX integrated with VoIP as a plausible solution to rural connectivity. Integration of the designed network with the existing cellular network has been suggested to extend the coverage range. Solar power dependency along with remote network management has been proposed to allow undisrupted connectivity. Simulations have been performed on the Network Simulator (NS2) to validate the efficiency of the proposed model. A comparison to other potential solutions to rural connectivity has been drawn to prove the benefits of the model.

1. Introduction

It is widely accepted that communication technology is one of the most important enablers, increasing access to information and thus the standard of living. Recent advances have greatly reduced the cost of telecommunications infrastructure and worldwide mobile phone penetration has increased greatly. However, most of the gains of the telecommunications revolution have been restricted to the industrialized countries. The central issue is shifting from disparity between developed and developing countries to between urban and rural areas of within developing countries.

Telecommunications carriers around the world have already introduced IP into their networks because it provides economic benefits over traditional telecommunications networks. Technologies that use the Internet and Internet protocol networks to deliver voice communications have the potential to reduce costs, support innovation, and improve access to communications services within developing countries and around the world. We have proposed the integration of WiMAX with VoIP to provide coverage to a large customer base.

We start by giving an overview of VoIP technology and WiMax. We then present a design of the model to be deployed. We continue by comparing of the proposedtechnology with the other viable solutions and how mobile IP telephony proves to be the most plausible option.

2. Overview of VoIP

The Public Switched Telephone Network (PSTN) is the collection of all the switching and networking equipment that belongs to the carriers that are involved in providing

telephone service. In this context, the PSTN is primarily the wired telephone network and its access points to wireless networks, such as cellular. The overall technology requirements of an Internet Protocol (IP) telephony solution can be split into four categories: signaling, encoding, transport and gateway control. The purpose of the signaling protocol is to create and manage connections between endpoints, as well as the calls themselves. Next, when the conversation commences, the analog signal produced by the human voice needs to be encoded in a digital format suitable for transmission across an IP network. The IP network itself must then ensure that the real-time conversation is transported across the available media in a manner that produces acceptable voice quality. Finally, it may be necessary for the IP telephony system to be converted by a gateway to another format-either for interoperation with a different IP-based multimedia scheme or because the call is being placed onto the PSTN.

An IP network does not have the same limitations as the

traditional telephone system as far as routing is concerned. A circuit switched network creates a dedicated connection for an entire call, and therefore guarantees a constant bandwidth and satisfactory quality for the entire speech transmission. A packet switched network like the Internet splits the voice data into packets that are routed independently along the most efficient path in the network on the way to their final destination.

SS7Once a user dials a telephone number signaling is required to determine the status of the called party— available or busy—and to establish the call. Signaling System 7 (SS7) is the set of protocols (standards for signaling) used for call setup, teardown, and maintenance in the Public Switched Telephone Network (PSTN).SS7 is implemented as a packet-switched network and typically uses dedicated links, nodes and facilities. In general, it is a non-associated, common channel out-of-band signaling network allowing switches to communicate during a call. The integration of SS7 and IP will provide significant benefits. Figure1 depicts a type of VoIP network utilizing an SS7-to-IP gateway. SS7 provides the call control on either side of the traditional PSTN, while H.323/Session Initiation Protocol (SIP) provides call control in the IP network. The media gateway provides circuit-to-voice conversion.



Figure1. SS7 based VoIP Network H.323H.323, ratified by the International Telecommunication Union-Telecommunication (ITU-T) is a set of protocols for voice, video, and data conferencing over packet-based networks, such as the Internet. The H.323 protocol stack is designed to operate above the transport layer of the underlying network. The scope of H.323, however, is much broader and encompasses networking multipoint conferencing among terminals that support not only audio but also video and data communications. In a general H.323 implementation, three logical entities are required: gateways, gatekeepers and multipoint control units (MCUs). Figure2. VoIP Network Components SIP Session Initiation Protocol, SIP, defined by the Internet Engineering Task Force (IETF), is a signaling protocol for telephone calls over IP. Unlike H.323, however, SIP was designed specifically for the Internet. It exploits the manageability of IP and makes developing a telephony application relatively simple. SIP is an application-layer control (signaling) protocol for creating, modifying and terminating sessions with one or more participants. The facilities of SIP enable personal mobility-the ability of end users to originate and receive calls and access subscribed telecommunication services on any terminal in any location. This mobility can be augmented via wireless VoIP. Voice coders An efficient voice encoding and decoding mechanism is vital for using the packet-switched

technology. The purpose of a voice coder (vocoder)-also referred to as a codec (coding/decoding)-is to use the analog signal (human speech) and transform and compress it into digital data. A number of factors must be taken into account including bandwidth usage, silence compression, intellectual property, look-ahead and frame size, resilience to loss, layered coding, and fixed-point vs. floating point digital signal processor (DSPs). The bit-rate of available narrowband vocoders ranges from 1.2 to 64 kbps. Transport Once signaling and encoding occur, Real-time Transport Protocol (RTP) and R e a l - T i m e Control Protocol (RTCP) are utilized to move the voice packets. Media streams are p a c k e t i z e d according to a predefined format. RTP provides delivery monitoring of its payload types through sequencing and time stamping. RTCP offers insight on the performance and behavior of the media stream, such as voice stream jitter. RTP and RTCP are intended to be independent of the signaling protocol, encoding schemes, and network layers implemented. Gateway In VoIP systems gateways function as the interconnection between the Internet and the PSTN or the H.323 and the non-H.323 network. On one side it connects to traditional voice signals, and on the other side it connects to packet-based devices. The gateway translates signaling messages between the two sides with a CODEC function and can also function as a compressor and decompressor.

3. WiMAX

WiMAX (Worldwide Interoperability for Microwave Access) is an upcoming new technology that delivers high-speed, wireless broadband at a much lower cost than cellular and over a much greater range than WiFi. WiMAX will not only deliver significant improvements in speed, throughput and capacity but will also enable portable and mobile services to laptops and handheld devices over a wider area of coverage making them more “mobile”. The greater operational range of WiMAX provides our model significant advantages over the traditional wireless networks and the Wifi networks since operation on the widespread rural geography is primarily governed by the cost and coverage factors. The greater speed capability of the WiMAX network enhances the service quality of the VoIP phones which is one of the key issues wile evaluating VoIP system performance . Along with the support for high speed broadband , WiMAX offers the best possible combination of services that are needed for a rural setup ranging over large physical areas and hence is our choice in the proposed system . 4. Proposed Model for the Rural Connectivity The figure 3 reflects a design of the model to be implemented in the rural areas to provide connectivity



within the community as well as outside the community. The core technologies for the proposed Community Telecommunications network are primarily; 1) an Internet Protocol (IP) network in lieu of a circuit switched network 2) Voice services that are provided through Voice over IP (VoIP) in lieu of custom hardware-based switching 3) Wireless distribution, be it WiFi and/or WiMAX in lieu of terrestrial land lines. Together these newer technologies provide a unique opportunity that is just now capable of being realized, for expanding communications into the most remote areas of any country in the world. Further, these off-the-shelf technologies allow this to be done at a cost that is literally pennies-on-the-dollar for what has been possible in the past. Figure 3. Model of the Rural Connectivity Local Wireless Network/WiMAX As conceived and tested, the local community wireless network is comprised of a switch (or access to a central switch) a single router, a series of wireless antennas and repeaters, and VoIP phones, and in most cases, WiFi phones. The type, number, and placement of the antennas is a factor of the local environment, and may include WiMAX for distribution and WiFi for access, or may include a pure WiFi-only network, possibly a mesh. VoIP Switching/Gateway This component is the actual VoIP switching that allows for calls to be routed between the user communities, whether they are within the local community or with those residing on other networks including other similar IP-based community networks, mobile users, or PSTN users. As proposed, the configuration is such that a single VoIP switch can provide support to hundreds, if not thousands of local community phone systems/customers. In fact, as conceived, a single soft switch can provide the needed switching for hundreds, even thousands of community phone systems located in dozens of different countries. It is equally feasible for each country to set up their own central VoIP switch to handle the local community networks within each specific country. Siemens offers its communications systems

solutions, HiPath which is currently being used in smaller networks to facilitate VoIP and WiFi.

VoWiFi Phones With the growing populating of VoIP switching and WiFi networks, the most recent technological development has been SIP-based VoIP/WiFi phones. These look very similar in size to a mobile phone offered through any number of commercial wireless carriers. In fact, one of the current dynamics within the cellular marketplace is the dual-mode handsets that provide digital cellular service as well as VoWiFi capabilities, including switching between the two networks while retaining a call. The advantage is that they can be powered by solar where needed, and can be operated directly off of the community WiFi network. Figure 4. Integration of Cellular and WiMAX Network Integration of cellular and Wi-Fi networks Figure 4 shows the method where wireless IP phone is assigned a cellular number, and when it is outside cellular coverage area, it is connected through fixed IP network. This enables maintenance of the connection while moving out of the coverage of the cellular region into the rural region with WiFi coverage. In cellular network, HLR (Home Location Register) keeps the area where each subscriber is located (the location area). When the subscriber moves and the area changes, the HLR is also updated to a new area code. As one of these location areas, “home Wi-Fi area” is added With this system, when in the ‘hot spots’, connection via VoIP is possible. Outside, it is connected via existing cellular network. When the terminal detects Wi-Fi radio signal over certain threshold, it notifies the cellular network through IP network that it is located in its own “home Wi-Fi area.” GW in Fig.3 converts the telephone number to IP address, and connects to a designated access point. Securing power source Commercial power supply is pre-requisite for location of Gateway (IP-PBX), but location of access points in Wi-Fi needs to anticipate the possibility of no power, these do not require high power like traditional telephone switching systems did. In places without power, solar power with simple solar panel or small, light-weight Manganese Lithium-ion type batteries can be used. For the



VoWiFi phones, portable solar power charger is commercially available. Remote maintenance capability Since it is rural area, remote monitoring and control function is indispensable. The local systems from all the communities can be connected to central control centre via Internet VPN, in order to collect data on operation to be able to cope with problems if they arise. When large-scale WiFi network or WiMAX is implemented in rural areas and they are connected to public cellular and fixed networks, an integrated network management system will be needed. For this type of network management, SNMP (Simple Network Management Protocol) may be applied to wireless LAN devices such as access points, thereby enabling build-up of a management system easily in a short period of time.

5. Simulation Results To test the efficiency of the proposed communication model we simulated the same on the Network Simulator (NS2) and arrived at the following results. The capacity of the two different codes G.711 and G.723 are compared and it is concluded that 802.16 (WiMax) protocol can support can support fourteen to eighteen simultaneous VoIP sessions using the G.723.1 codec.

The packet loss has been reduced by increasing the que length which though increases the packet arrival rate by some amount. Future work is to optimize the packet arrival rate and also reduce the packet loss.

6. Potential limitations of IP Telephony Despite its several benefits there are a few potentials limitations to the delivery of voice over packets. Some of them are discussed here. Delay also called the latency is the time taken for a packet to arrive at its destination from the sending endpoint. The IP network delay is the sum of the packet capture delay, the switching/routing delay, and the queuing time. Jitter Packet delay variation is called jitter and is defined as the variation of packet inter-arrival time at the receiving side of the network. In VoIP systems, jitter is also produced when packets are sent over different paths through the network. Some packets may therefore arrive in a different order compared to how they were sent. Jitter is a more or less unavoidable factor in networks dealing with multimedia services. Packet loss corresponds to the percentage of the total amount speech frames that do not reach their point of destination. It occurs frequently in IP connections and can have many different origins. Packet loss may be caused by physical media errors as well as an overloaded router that intentionally discard packets to relieve congestion in the connection. A packet can also arrive too late to be involved in the reconstruction of the voice signal and therefore get dropped. Packet loss can in turn create impairments like dropouts and time clipping. Echo : Echo is caused by the leakage of the talkers voice signal between the transmit path and the receiving path, often caused by a mismatch between the analogue telephone device and the transmission media. Another reason is acoustic coupling problems between a telephones microphone and its loudspeaker.

7. Comparison to CDMA450 CDMA 450MHz is often proposed as a rural WLL solution, based on the idea that propagation at 450MHz is superior; therefore coverage using this technology can be achieved very economically in rural areas. However, it is critical, for operators evaluating this technology, to understand that range in CDMA systems is limited by noise and mutual



interference, not by propagation and path loss. CDMA 450MHz can achieve 50km range, but in single-user conditions, or under very light system loading. When the base stations are sufficiently loaded to amortize their cost, the achievable range will be much less. Typically, one base station must be installed in each served community, even if the network operates at 450MHz. Moreover, being a mobile network, CDMA-450 requires a complex core network mandated by mobility standards. Operators of fixed rural CDMA networks will find that they have to: • Over-invest in the CDMA core network • Integrate mobile network nodes into their fixed line networks • Build extensive, high-performance backhaul networks • Deploy an excessive number of base stations • Use dedicated, high-power phones and directional antennas for remote subscribers The result is that a rural CDMA-450 network can be much more expensive than operators would expect based on the nominal traffic capacity required by the network. Mobile IP telephony systems like the one which we proposed are much more economical to deploy in rural areas, and are particularly more cost-efficient to expand, because of their stable coverage under increasing traffic conditions.

8. Conclusion

We have made a proposal for a rural telecommunication system targeted at expansion of telecom infrastructure in rural areas of developing countries, utilizing VoIP, WiFi/WiMAX and cellular/Wi-Fi dual terminals. This approach is substantially less costly than reliance on traditional circuit -switched solutions and even cellular networks.

This proposal which integrates cellular and WiFi

networks on VoIP attempts to have the large-scale, nationwide cellular network and local, small-scale wireless LAN collaborate and fuse with each other, and it provides superior convenience. It is possible to implement in a short period of time, and it is provides the capability to cope with localities with no power supply, and remote maintenance. Furthermore, through using the Internet over this infrastructure, people will be able to develop various applications for tourism, environmental protection, education and government services that are needed in each local community.

9. References [1] Uyless Black, “Voice Over IP”, Prentice Hall PTR,

2000 [2] Princy Mehta, Sanjay Udhani, “Voice Over IP”, IEEE

Potentials, 2000

[3]ITU Statistics, http://www.itu.int/ITU-D/ict/statistics/

[4] M. Yavuz et al., “VoIP over CDMA2000 1xEV-DO Revision A,” IEEE Commun. Mag., Feb. 2006. [5]Shridhar Mubaraq Mishra, John Hwang, Dick Filippini, Reza Moazzami, Lakshminarayanan Subramanian and Tom Du , Economic Analysis of Networking Technologies for Rural Developing Regions, IEEE Commun. Mag.

[6]Siemens, HiPath Catalogues and Brochures

Prof. Ashish G Bajaj has graduated in Electronics & Telecommunication Engineering from Dr.BAMU, Aurangabad in 2006 and had lifetime membership for Indian Society for Technical Education. Prof. Amar Chavan was born at Udgir, Maharashtra, India on 1st Nov.’ 1986. Currently, He is working as Assistant Professor. He did his M.tech in

Electronic Design & Technology from DOEACC, Aurangabad. Also he did his B.tech in Electronics and Communication Engineering from Dr. Babasaheb Ambedkar Marathwada University, Aurangabad. His area of interest includes Digital Electronics, Power Electronics,

Instrumentation and system designing. Prof. Sachin Jadhao was born at Buldhana, Maharashtra, India on 29th

June.’ 1985. Currently, He is working as Assistant Professor. He did his M.tech in Electronic Design & Technology from DOEACC, Aurangabad. Also he did his

B.E. in Electronics Engineering from Dr. Babasaheb Ambedkar Marathwada University, Aurangabad. His area of interest includes Embedded Systems, Electronics System Design, DSP Processors.

Nancy, Silky Baghla 37


Performance Evaluation and Comparison of MADM Algorithms for Subjective and Objective

Weights in Heterogeneous Networks

Nancy, Silky Baghla

Abstract: In a fourth generation (4G) wireless environment, the need for an user to be always best connected (ABC) anywhere at any time leads to execute a vertical handoff decision for guaranteeing service continuity and quality of service (QoS). In this paper, Vertical handover decision schemes is compared and Multi Attribute Decision Making (MADM) is used to choose the best network from the available Visitor networks (VTs) for the continuous connection by the mobile terminal. A comparative analysis of these methods including SAW, MEW and TOPSIS illustrated with a numerical simulation, showed the impact of the various importance weights assignment in their performance for different traffic classes and applications such as: voice and data connections, in a 4G wireless system.

Keywords—4G mobile communication, Algorithms, Decision making.

I. INTRODUCTION

Future generation wireless networks (FGWN) are expected to support heterogeneous access technologies than homogeneous wireless networks. In FGWN, heterogeneous network is managed by different operators like WiMax, WiFi, UMTS etc. In this heterogeneous wireless network environment, always best connected (ABC)[1] which requires dynamic selection of the best network and access technologies when multiple options are available simultaneously. The typical scenario of Wifi and WiMax as shown in Fig 1 are: WiFi with high bandwidth, low-cost and short coverage and WiMax with high-speed mobile, fixed internet access to the end users, it provides services for data, voice and video. Handover network has the two types, horizontal handover and vertical handover [2]. A vertical handoff is the process of changing the mobile connection between access points supporting different wireless technologies. Meanwhile, in a horizontal handoff the connection just moves from one base station to another within the same access network. The vertical handoff consists mainly in three phases:

network discovery, handoff decision and handoff execution.

Nancy, Silky Baghla is with J.C.D. College of Engineering Sirsa, Haryana, Email: [email protected]

In the first step, the mobile terminal (MT) discovers its available neighboring networks. In the decision phase, the MT determines whether it has to redirect its connection based on comparing the decision factors offered by the available networks and required by the mobile user, that is, information gathered in the first phase. The last phase is responsible for the establishments and release of the connections according to the vertical handoff decision.

Fig. 1 The scenario of WiFi and WiMax Various Multiple Attribute Decision Making (MADM) [2] methods have been proposed in the literature for vertical handoff, methods such as SAW (simple additive weighting)[3], TOPSIS (technique for order preference by similarity to ideal solution) [3], MEW (multiplicative exponent weighting)[4] and Artificial Hierarchy process(AHP) [5]. The scope of our work is mainly in handover decision phase, as mentioned in the decision phase; decision makers must choose the best network from available networks. . In this paper, we compare SAW (simple additive weighting), TOPSIS (technique for order preference by similarity to ideal solution) and MEW (multiplicative exponent weighting) MADM algorithms which uses the cost, packet delay, packet jitter and available bandwidth of the participating access networks to make handoff decisions for multi-attribute QoS consideration according to the features of the traffic. According to these attributes, the attribute matrix of alternative networks is established. Appropriate weight factor is assigned to each criterion to account for its importance which is determined by Artificial Hierarchy



process (AHP). Considerable amount of research on develop MADM methods for vertical handoff have been conducted, and it is necessary to evaluate their performance under different scenarios in order to provide the best solution for a particular application. In [4], [9], and [10] brief simulation studies are addressed for this purpose, but only including SAW, MEW, and TOPSIS algorithms.

II. RELATED WORK

At present many of the handoff decision algorithms are proposed in the literature. In (4) a comparison done among SAW, Technique for Order Preference by Similarity to Ideal Solution(TOPSIS), Grey Relational Analysis (GRA) and Multiplicative Exponent Weighting (MEW) for vertical handoff decision. In (3) author discuss that the vertical handoff decision algorithm for heterogeneous wireless network, here the problem is formulated as Markov decision process. In (3) the vertical handoff decision is formulated as fuzzy multiple attribute decision making (MADM). In (8) their goal is to reduce the overload and the processing delay in the mobile terminal so they proposed novel vertical handoff decision scheme to avoid the processing delay and power consumption. In (7) a vertical handoff decision scheme DVHD uses the MADM method to avoid the processing delay. In (10) the paper is mainly used to decrease the processing delay and to make a trust handoff decision in a heterogeneous wireless environment using T-DVHD. In (11) a novel distributed vertical handoff decision scheme using the SAW method with a distributed manner to avoid the drawbacks. In (14) the paper provides the four steps integrated strategy for MADM based network selection to solve the problem. All these proposal works are mainly focused on the handoff decision and calculate the handoff decision criteria on the mobile terminal side and the discussed scheme are used to reduce the processing delay by the calculation process using MADM in a distributed manner. In (16) the comparison n analysis shows the SAW, MEW, TOPSIS, VIKOR, GRA and WMC with the numerical simulation of vertical handoff in 4G networks. III. DECISIN MAKERS IN VERTICAL HANDOVER

DECISION SCHEMES

Multiple attribute decision making (MADM) refers to making preference decisions (e.g., evaluation, prioritization, and selection) over the available alternatives that are characterized by multiple, usually conflicting, attributes. The structure of the alternative performance matrix Table 1, where xij is the rating of alternative i with respect to criterion j and wj is the weight of criterion j. Since each criterion has a different meaning, it cannot be assumed that they all have equal weights, and as a result, finding the appropriate weight for each criterion is one the

main points in MADM. Various methods for finding weights can be found in the literature and most of them can be categorized into two groups:

Subjective weights are determined only according to the preference decision makers.

Objective weights determine weights by solving mathematical models without any consideration of the decision maker’s preferences. Table 1. Matrix format of a MADM problem

333231323222121312111

)3(3)2(2)1(1

xxxAxxxAxxxA

wCwCwC

IV. REVIEW OF MADM METHODS

The most known and used MADM algorithms for vertical handoff are Simple Additive Weighting (SAW) [3], Technique for Order Preference by Similarity to Ideal Solution (TOPSIS) [3], and Multiplicative Exponent Weighting (MEW) [4] between others. These algorithms have to evaluate and compare the decision factors for each wireless network, in order to detect and trigger a vertical handover. The factors can be classified as benefical, i.e., the larger, the better, or cost, i.e., the lower, the better. In the following these algorithms are described.

A. Simple Additive Weighting (SAW) Simple Additive Weighting (SAW) which is also referred as weighted linear combination or scoring methods or weighted sum method is a simple and most often used multi attribute decision technique. The method is based on the weighted average. An evaluation score is calculated for each alternative by multiplying the scaled value given to the alternative of that attribute with the weights of relative importance directly assigned by decision maker followed by summing of the products for all criteria. For numerical attributes score are calculated by normalized values to match the standardized scale. The SAW is a comparable scale for all elements in the decision matrix, the comparable scale obtained by rij for benefit criteria Eq. (4.1) and worst criteria Eq. (4.2).

j

ijij x

xV max (4.1)

ij

jij x

xVmin

(4.2)

The SAW method, underlying additive values function and compute as alternatives score Vi = V(Ai) by adding weighting normalized values before eventually ranking



alternatives.

(4.3) For with i{1,…..,n},j={1…..m}; Then the selected network is is:

(4.4)

B. Technique for Order Preference By Similarity To Ideal Solution(TOPSIS)

TOPSIS (15) is a MADM instrument for measuring relative efficiency of alternatives. It determines the preference order on the grounds of the similarity to a positive ideal solution and the worst similarity to a negative solution. The following are the steps of TOPSIS. Construct the normalized decision matrix. Each element rij of the Euclidean normalized decision matrix R can be calculated as follows: for i=1,…,m; j=1,……,n (4.5)

Next the weighted normalized decision matrix is constructed by

(4.6) Then positive ideal and negative ideal solutions are determined by Positive Ideal solution.

} where (4.7)

Negative ideal solution.

where (4.8)

The distance between each alternative and the positive ideal solution is:

i=1,…., m (4.9)

The distance between each alternative and the negative ideal solution is:

i=1,…., m (4.10)

Finally relative closeness to the ideal solution Ci* is

calculated as

0< <1 (4.11)

A set of alternatives can now be preference ranked according to the descending order of . Then the selected network is:

(4.12)

C. Multiplicative Exponential Weighting(MEW) MEW[4] another MADM scoring method. The main difference is that instead of addition usually mathematical operation now there is multiplication. As with all MADM methods, WPM is a finite set of decision alternatives described in terms of several decision criteria. The vertical handover decision problem can be expressed as a matrix form and each row i corresponds to the candidate network I and each column j corresponds to the attributes.

(4.13) Where xij denotes attribute j of candidate network i, wi denotes the weight of attributed j.

V. PERFORMANCE COMPARISON

In order to evaluate the performance of each MADM algorithm, we consider a network selection situation in a 4G environment integrated by three network types as WLAN, UMTS and WiMAX, and there are two networks of each type. In this work, four decision criteria have to be evaluated and compared in order to detect and to trigger a vertical handoff. Including available bandwidth (Mbps), packet delay (ms), packet jitter (ms), and cost per byte. The range of values of the parameters or decision criteria is shown in Table II. For Subjective Weights the values of assigned weights for different services considered in this study are: case 1, all parameters have the same weight, this is the baseline case; case 2, delay and packet jitter have 70% of importance and the rest is equally distributed among the other parameters, this case is suitable for voice connections; and case 3, available and total bandwidth have 70% of importance, this case is suitable for data connections. In each vertical handoff decision point, the attribute values may be the same, increase or decrease within the range shown in Table II. Table II. Values of the networks parameters. Criteria Network

Cost per byte

Packet Delay(ms)

Packet Jitter(ms)

Available Bandwidth

UMTS 60 25-50 5-10 0.1-2 WLAN 10 100-150 10-20 1-11



WIMAX 40 60-100 3-10 1-60 For Objective Weights. The four traffic classes have different QoS requirements [14]. To account for this fact, we assigned different weights for the same attribute between different traffic classes. The AHP matrices for the four traffic classes are shown in Table III. The weights determined by using the method are shown in Table IV. Table III: AHP matrix for each Traffic Class. Conversational Cost Delay Jitter Bandwidth Cost 1 1/9 1/9 1 Delay 9 1 1 9 Jitter 9 1 1 9 Bandwidth 1 1/9 1/9 1 Streaming Cost Delay Jitter Bandwidth Cost 1 1/5 1/9 1/9 Delay 5 1 1/5 1/5 Jitter 9 5 1 1 Bandwidth 9 5 1 1 Interactive Cost Delay Jitter Bandwidth Cost 1 5 9 5 Delay 1/5 1 5 1 Jitter 1/9 1/5 1 1/5 Bandwidth 1/5 1 5 1 Background Cost Delay Jitter Bandwidth Cost 1 9 9 5 Delay 1/9 1 1 1/5 Jitter 1/9 1 1 1/5 Bandwidth 1/5 5 5 1 Table IV: Importance Weights Per Class And Consistency

Ratio(CR). Traffic Class Cost Delay Jitter Bandwidth CR Conversational 0.04998 0.45002 0.45002 0.04998 0.000 Streaming 0.03737 0.11380 0.42441 0.42441 0.049 Interactive 0.63593 0.16051 0.04304 0.16051 0.049 Background 0.66932 0.05546 0.05546 0.21976 0.049

A. Simulation 1 In this simulation, we calculate the ranking order of the alternatives for data application where 70% importance is given to the bandwidth using the SAW, MEW and TOPSIS algorithms. Table V presents the relative closeness to the ideal solution of TOPSIS and overall score of SAW and MEW. The results show that the ranking order of the alternatives is same for both algorithms TOPSIS and SAW. The ranking order of SAW and TOPSIS is Network #3, Network #6, Network #5, Network #4, Network #2 and Network #1. The ranking order of MEW is Network #3, Network #6, Network #5, Network #4, Network #1 and Network #2.

Table V. The Ranking Order of SAW, MEW and TOPSIS.

SAW TOPSIS MEW Network # 1 UMTS 1

0.1335 Rank#6

0.665 Rank#6

0.0945 Rank#5

Network #2 UMTS 2

0.3064 Rank#5

0.1858 Rank#5

0.0372 Rank#6

Network #3 WLAN 1

0.8020 Rank#1

0.8206 Rank#1

0.7088 Rank#1

Network #4 WLAN 2

0.3629 Rank#4

0.3116 Rank#4

0.3209 Rank#4

Network #5 WIMAX 1

0.5088 Rank#3

0.5175 Rank#3

0.4416 Rank#3

Network #6 WIMAX 2

0.6358 Rank#2

0.6384 Rank#2

0.5633 Rank#2

The ranking order of MEW is different from the ranking order of SAW and TOPSIS related to Network #1 and Network #2 because MEW (equation 4.13) penalizes the alternative having more poor attributes than the other alternatives. Note that SAW, MEW and TOPSIS algorithms provide the same best alternative (Network #3) in this case. Similarly for voice application the best alternative is Network#2. For different traffic classes show the similar result according to their weights such as Network #2 is best alternative for Conversational, Interactive and Background traffic and Network #3 for Streaming traffic.

B. Simulation 2 In this simulation, we focus on the ranking abnormality problem. We here remove an alternative (e.g. Network #1) from the alternative candidate list. Table VI presents the relative closeness to the ideal solution of TOPSIS and the overall score of SAW and MEW.

Table VI. The Ranking Order of SAW, MEW and TOPSIS.


------

-----

-----

Network #2 UMTS 2

0.3064 Rank#5

0.1993 Rank#5

0.0372 Rank#5

Network #3 WLAN 1

0.8020 Rank#1

0.6091 Rank#2

0.7088 Rank#1

Network #4 WLAN 2

0.3629 Rank#4

0.3068 Rank#4

0.3209 Rank#4

Network #5 WIMAX 1

0.5088 Rank#3

0.5095 Rank#3

0.4416 Rank#3

Network #6 WIMAX 2

0.6358 Rank#2

0.8288 Rank#1

0.5633 Rank#2

In this simulation, the result show that a removal of an alternative causes a change in the ranking order of TOPSIS. The ranking order of SAW, MEW remains the same. We continue removing an alternative (e.g. Network #2) from the alternative candidate list. The result in Table VII show that the ranking order in SAW and TOPSIS has changed from Network #6 to Network #3. In Table V, all algorithms determine that Network #3 is the best interface since it has the best QoS attribute values and the cost is not very high. Network #1 is the worst interface because it has the worst QoS and cost attribute values.

Table VII. The Ranking Order of SAW, MEW and TOPSIS.


------

-----

-----

Network #2 UMTS 2

------

-----

-----



Network #3 WLAN 1

0.9195 Rank#1

0.8505 Rank#1

0.878 Rank#1

Network #4 WLAN 2

0.4464 Rank#4

0.1495 Rank#4

0.3975 Rank#4

Network #5 WIMAX 1

0.5720 Rank#3

0.3528 Rank#3

0.5469 Rank#3

Network #6 WIMAX 2

0.7335 Rank#2

0.5554 Rank#2

0.6977 Rank#2

When we remove the worst interface out of the list, this does not influence the ranking order of other interfaces for SAW and MEW. However, the best interface in TOPSIS changes from Network #3 to Network #6 in Table VI. When another worst interface (Network #2) is removed, the best interface in TOPSIS also changes (Table VII). The simulation results highlight the ranking abnormality problem of TOPSIS and show that SAW and MEW provide a more effective behavior in every application and traffic class.

C. Simulation 3 In this simulation, we investigate the sensitivity of the assigned weights to the network selection. For conversational and streaming traffic classes, the weight of the jitter is varied from 0 to 0.5. The weights for other criteria are varied in proportion to the values specified in Table IV. For interactive and background traffic classes, the weights of cost is varied accordingly. Fig. 2(a) and (b) show that when the weight of the jitter increases, eventually all three algorithms select Network #2. Fig. 2(c) and 2(d) shows that when the weight of Cost increases, all three algorithms select Network #2 which has the lowest cost value.

Fig. 2 Sensitivity Analysis

VI. CONCLUSIONS

In this paper, we presented the result for the performance comparison between three vertical handoff decision algorithms, namely, SAW (simple additive weighting), TOPSIS (technique for order preference by similarity to ideal solution) and MEW (multiplicative exponent weighting). Results show that SAW, MEW and TOPSIS provide similar performance to all applications and four traffic classes, with different importance. The simulation result showed that TOPSIS suffered from Ranking Abnormalities. Results also showed that all three algorithms depend on the importance weights assigned to parameters.



REFERENCES [1] M. Kassar, B. Kervella, and G. Pujolle, “An overview of

vertical handover decision strategies in heterogeneous wireless networks,” Computer Communications, vol. 31, pp. 2607-2620, June 2008.

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[3] W. Zhang, “Handover Decision Using Fuzzy MADM in Heterogeneous Networks,” in Proc. of IEEE Wireless Communications and Networking Conf., WCNC’04, Atlanta, USA, pp. 653-658.

[4] E. Stevens-Navarro and V. W.S. Wong, “Comparison between Vertical Handoff Decision Algorithms for Heterogeneous Wireless Networks,” in Proc. of 63rd Conf. on Vehicular Technology, IEEE VTC’06-Spring, Melbourne, Australia, pp. 947-951.

[5] J. Fu, J. Wu, J. Zhang, L. Ping, and Z. Li, “ Novel AHP and GRA Based Handover Decision Mechanism in Heterogeneous Wireless Networks”, in Proc. CICLing (2), pp. 213-220, 2010.

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[7] R.Tawil, G.Pujolle and O.Salazar, A Vertical Handoff Decision Schemes In Heterogeneous Wireless Systems, Vehicular Technology Conference, 2008. VTC Spring 2008. IEEE , Singapore , pp. 2626-2630.

[8] R.Tawil, J.Demerjain, G.Pujolle And O.Salazar, Processing-Delay Reduction During The Vertical Handoff Decision In Heterogeneous Wireless System, : International Conference on Computer Systems and Applications, 2008. AICCSA 2008. IEEE/ACS 2008., pp.381-385.

[9] LIU yu, Ye Min-hue and ZHANG Hui-min, The Handoff Schemes in mobile IP, Vehicular Technology Conference, 2003. VTC 2003- Spring. The 57th IEEE Semiannual , pp. 485-489.

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[11] R.Tawil, G.Pujolle and O.Salazar, Vertical Handoff Decision Schemes For The Next Generation Wireless Networks, Wireless Communications and Networking Conference, 2008. WCNC.2008, pp. 2789-2792.

[12] R.Tawil, G.Pujolle and J.Demerjain, Distributed Handoff Decision Scheme Using MIH Function For The Fourth Generation Wireless Networks: 3rd International Conference on Information and Communication Technologies: From Theory to Applications, 2008. ICTTA 2008., pp.1-6.

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[14] Lusheng Wang and David Binet, MADM- Based Network Selection In Heterogeneous Wireless Networks: A Simulation Study, 1st International Conference on Wireless Communication, Vehicular Technology, Information Theory and Aerospace & Electronic Systems Technology 2009. Wireless VITAE 2009, pp. 559-564.

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Magazine, IEEE , 44(2006), pp. 96-103, doi:10.1109/MCOM.2006.1710420

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PreetiDhiman, Noble Tawra, Rakesh Nagar, Rishab Singh and Varun Kaushik 43


Voice Operated Intelligent Fire Extinguisher Vehicle

PreetiDhiman, Noble Tawra, Rakesh Nagar, Rishab Singh and Varun Kaushik Abstract-This paper demonstrates the research and implementation of voice automated fire extinguisher vehicle. The vehicle is controlled through connected speech input. The language input allows a user to interact with the robot which is familiar to most of the people. The advantages of speech activated robots are hands-free and fast data input operations. The speech recognition system is trained in such a way that it recognizes defined commands and the designed robot navigates based on the instruction through the Speech Commands. The medium of interaction between humans and computers is on the processing of speech. The complete system consists of three subsystems, the speech recognition system, transmitter section and the receiver section (on vehicle) .We have studied the various factors such as noise which interferes speech recognition and distance factor. The results prove that proposed robot is capable of controlling fire, avoiding obstacles and understanding the meaning of speech commands. Keywords-Transmitter, Receiver, Speech recognition system, Visual Basic, Microsoft speech SDK 5.1.

I. INTRODUCTION

The project aims at designing an intelligent voice operated fire extinguishing robotic vehicle which can be controlled wirelessly through RF communication. The Robotic vehicle has a camera mounted on it whose direction can also be controlled using voice commands. The proposed vehicle has a water jet spray which is capable of sprinkling water. The sprinkler can be moved towards the required direction.

A lot of work has been done earlier in the field of word recognition.Using a traditional recognizer an accuracy of around 60% has previously been obtained for both a 156 town name task and 1108 road name task. Techniques presented in [Azzopardi/Semnani_et_al:1998]has resulted in an accuracy of 90% for an automated corporate directory system with 120,000 entries. As an input method for rapidly spreading small portable information devices, and advanced robotics applications, development of speaker independent speech recognition technology which can be embedded on a single DSP chip has been developed by [Hoshimi/Yamada_et_al:1998].

preetiDhiman is working as Assistant professor, Galgotias College of Engineering &Technology, Greater Noida, Email: [email protected] and Noble Tawra, Rakesh Nagar, Rishab Singh, Varun Kaushik are Students, Galgotias College of Engineering & Technology, Greater Noida, India, Emails: [email protected], [email protected], [email protected], [email protected]

When the newly proposed noise robustness method was tested with 100 isolated word vocabulary speech of 50 subjects, recognition accuracy of 94.7% was obtained under various noisy environments. Software engineering for research and development in the area of signal processing is by no means unimportant. A programming paradigm which allows software components to be advantageously combined witheach other in a way that recalls the concept of hardware plug-and-play, without the need for incorporating complex schedulers to control data flows has been developed by [Dutoit/Shroeter:1998].Earlier similar work in a limited input domain was done using wireless for e.g. remote control of electrical switches (this is currently one of the ingenuity problems). We read a newspaper report about an year ago (TheHindu - Thursday Science & Technology Section) about such a project. A suggested application was for hospitalized patients who usually are dependent on someone else for to switch on/off the lights,fan, etc. But what if the patient's hands are broken. Obviously a voice based system ought to be used in such a case.

A voice recognition unit built around a high speed processor that ensures various operations of the system to be performed by voice command. The Program of the project is written in Visual basic language for controlling robot motor from the PC’s parallel port termed as printer port (LPT). The Program accepts the input in decimal numbers and outputs at the data output pins of the PC’s parallel port for controlling the connected devices. Our project controls left, right, forward and backward movement of robot wirelessly within 500m range using 433 MHz RF frequency. The special feature of our project is that our visual basic program control window based voice recognizing software. So for controlling any movement of robot we have to just speak name of movement. The voice recognizing software compare our voice with already stored voice, if match found robot start executing command according to voice command, otherwise it give error massage. At the receiver side of robot 8051 microcontroller is also used. The microcontroller takes command wirelessly transmitted by PC. The role of microcontroller is to drive 7 segments, drive DC motor, take input from temperature sensor and night light sensor and drive relays.

II.IMPLEMENTATION FRAMEWORK The controlling devices of the whole system are

Microcontrollers. Speechrecognition module, wireless transceiver modules, obstacle detector, lamp, waterjetspray, DC motors and buzzer are interfaced to Microcontroller. When the user fed the voice commands to the speech recognition module, the microcontroller interfaced to itreads



the command and sends relevant data of that command wirelessly using transceiver module. This data is received by the transceiver module on the robotic vehicle and feds it to

microcontroller which acts accordingly on motors, pump and lamp. The vehicle is mounted with a camera which helps in viewing the live images on TV.

Figure.1 Functional flow chart

A. TRANSMITTER SECTION

Optocouplers are used which consists of an infrared light-emitting diode (LED) and an npn phototransistor. When a high going pulse is available on the data pin, the internal LED drives the phototransistor of optocoupler MCT2E and it provides an enable pulse to HT12E encoder. All address pins of HT12E is grounded. Thus the data encoded by HT12E will be 0111. This encoded data is available at pin 17 of HT12E. The RF transmitter frequency modulate data signal and transmits using antenna. For RF transmission purposed it is needed to encode the signal generated at computer parallel port with the help visual basic code. B.RECEIVER SECTION

HT 12D Receive and decode 12 bit encoded data transmitted by HT12E, for further processing. The HT12D is 12 bit decoders are a series of CMOS LSIs for remote control system applications. They are paired with Holtek’s 2^12 series of encoders. For proper operation, a pair of encoder/decoder with the same number of addresses and data format should be chosen. The decoders receive serial addresses and data from a programmed 2^12 series of encoders that are transmitted by a carrier using an RF transmission medium. They compare the serial input data three times continuously with their local addresses. If no error or unmatched codes are found, the input data codes are

decoded and then transferred to the output pins. The VT pin also goes high to indicate a valid transmission. The 2^12 series of decoders are capable of decoding information that consist of N bits of address and 12_N bits of data. Of this series, the HT12D is arranged to provide 8 address bits and 4 data bits.

Figure.2 Transmitter circuit

Fig.3 Receiver circuit



C.SPEECH RECOGNITION SYSTEM The speech is received by a microphone and

processed on a PC. When a command for the robot is recognized, the PC sends a command message to the robot, built-in computer using RF signals. The robot computer analyzes the message and takes appropriate actions. For the speech processing we will focus on Microsoft SDK5.1 for VISUAL BASIC 6.

Fig.4 PC-Robot interface

D.VOICE CAPABILITIES IN VISUAL BASIC

I.Text-to-Speech Capabilities

One feature of the voice engine, with immediate application for experimental procedures, is the capability it provides to program a computer to read text aloud. What follows is a step-by-step example that illustrates how straightforward it is to implement this capability using the Speech SDK within Visual Basic.

II.Voice Recognition Capabilities Apart from the text-to-speech capabilities described

above, the Speech SDK offers a powerful human speech recognition system. Although a simple example may readily be built using Visual Basic, its use is more complex than the Text-To-Speech capability, and thus some knowledge of Visual Basic programming is required to fully understand the example.

Fig.5Visual Basic environment

E.80S51 MICROCONTROLLER We are using 8 bit microcontroller but our data is 4

bit so thelower nibble of port ie P 1.0-P 1.3 are connected to D0-D3 and in higher nibble of port i.e. P1.4 –P1.7 all bit are

CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system tocontinue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip.

F.OBSTACLE SENSOR The infrared intruder sensor is used to sense some unknown person like thief entering in your house without your permission. The board can be used in two modes – as an obstacle sensor and in the other as an IR signal receiver and transmitter. The two modes can be selected with the mode selector jumper. Putting the jumper in one position (SNS) will make the sensor work as an obstacle sensor and putting it in the other position (Tx) will put the sensor in the IR signal receiving and transmitting mode.

Fig.6Obstacle sensor

G.7 SEGMENTDISPLAY

The seven segment display is used to display the code received by receiver. Different codes are being used for different operations, so the user finds it easy to tele the code on display for correct operation.



Fig.7 Seven segment display

H.FIRE SENSOR Here thermistor is used as fire sensor. Usually the

temperature sensor produces a voltage signal that increases as the temperature increases. The inverted temperature sensor (cold sensor) produces a voltage signal that increases as the temperature decreases. If the temperature sensor is being used with a digital process unit then it needs to be followed by a comparator or Schmitt inverter to give a sharp change of signal from low to high. The temperature sensing circuit uses an NTC (negative-temperature coefficient) thermistor to monitor temperature. The resistance of a NTC thermistor falls as its temperature increases.

Fig.8Fire sensor

III. APPLICATIONS 1. It guides the blind persons to reach a particular

destination by using the voice feature. 2. It is used in hazardous places. 3. The photo electric sensor in the robot will sense the

obstacles and it will make decisions according to the obstacles it encounters.

4. It warns the person against the intruders. 5. Useful in controlling fire at extreme places where human

being cannot reach. 6. Live images of the incident can be seen through wireless

camera.

IV.FUTURE SCOPE Some of interfacing applications which can be made

are controlling home appliances, robotics movements, Speech Assisted technologies etc.

By making it GPS enabled, robot can be controlled from remote station also.

A CO2 booster can be attached to make it powerful extinguisher.

V. LIMITATIONS Speech has difficulties to be recognized by an

application. Because speech is different for every speaker, May be fast, slow, or varying in speed. May have high pitch, low pitch, or be whispered. Have widely-varying types of environmental noise. Can occur over any number of channels .Changes depending on sequence of phonemes, May not have distinct boundaries between units (phonemes), Boundaries may be more or less distinct depending on speaker style and types of phonemes,. Changes depending on the semantics of the utterance, has an unlimited number of words, has phonemes that can be modified, inserted, or deleted.

VI. CONCLUSION Based on the design principles and requirement, a

prototype of the system for Voice Operated Fire Extinguisher Robot has been developed.

REFERENCES 1. GuiseppeRiccardi, “active learning: theory and applications to

automatic Speech Recognition”,IEEE transaction of speech and audio Processing, vol. 13,No. 4, july 2005 .

2. ShantanuChakrabarthy “Robust speech feature extraction by growthTransformation in reproducing kernel Hillbert space”, IEEE Transactions on audio speech and language processing, vol.15,No 6,june2007 .

3. T. Aprille and T. Trick., “ Steady-state analysis of nonlinear circuits with periodic inputs”, Proceedings of the IEEE, vol. 60, no. 1, pp. 108-114, January 1972.

4. J. Chen, D. Feng, J. Phillips, and K. Kundert, “ Simulation and modeling of intermodulationdistortion in communication circuits”, Proceedings of the 1999 IEEECustom Integrated Circuits Conference, May 1999.

5. X. Huang, F. Alleva, M.Y. Hwang, and R. Rosenfeld, “ An overview of the sphinx-iispeech recognition system. InProceedings of the workshop on Human Language Technology” pages 81{86. Association for Computational Linguistics, 1993.

6. D. Huggins-Daines, M. Kumar, A. Chan, A.W. Black, M. Ravishankar, and A.I.Rudnicky, “PocketSphinx: A free, real-time continuous speech recognition system forhand-held devices”. In Acoustics, Speech and Signal Processing, 2006. ICASSP 2006Proceedings. 2006 IEEE International Conference on, volume 1, pages I-I. IEEE,2006.

PreetiDhiman received B.Tech Degree in 2003 with Honors and M.Tech. Degree in 2007 in Instrumentation & Control. She is currently working as Assistant Professor in Electronics & Instrumentation Department, Galgotias College of Engg. & Technology, Greater Noida. Her research interest includes Fuzzy Control, Intelligent Control and Evolution Algorithm.



Nobel Tawra is pursuing B-tech from Galgotias College of Engineering &Technology, Greater Noida in Electronics& Instrumentation .he is a Final year student

Rakesh Nagar is pursuing B-tech from Galgotias College of Engineering &Technology, Greaeter Noida in Electronics &Instrumentation. he is a Final year student

Rishab Singh is pursuing B-tech from Galgotias College of Engineering &Technology,Greaeter Noida in Electronics & Instrumentation. he is a Final year student

Varun Kumar Kaushik had done 3yr diploma in Electronics Engineering from Board of Technical Education (Delhi) ,now he is pursuing B-tech from Galgotias College of Engineering &Technology,Greaeter Noida in Electronics &Instrumentation. he is a Final year student

Bhavesh Bhatt, Chirag Gudkha, Avinash Khedekar and Prashant Mistry. 48


Braiile Calculator

Bhavesh Bhatt, Chirag Gudkha, Avinash Khedekar and Prashant Mistry.

Abstract---This paper describes a novel Braille calculator system developed in a single low cost unit. 15 million blind out of 37 million population around the globe can make use of its special feature of producing output in Braille, Audio as well as in LCD display. Calculators with smooth input keys and LCD outputs which are available in market are useless for blind person. With the implementation of Braille keys and Braille output along with a speaker, it becomes a boon to blind person for computation purpose. Due to presence of such a calculator and affordability of this one, it will boost the calculation capability of visually impaired people. The system performance has been evaluated and shown encouraging results. Keywords---Braille, Braille literature survey, Braille system design, embossing of keypad, future enhancement.

1. INTRODUCTION Technology has removed barriers to educate and employ

people with visual impairment. Now these people can also compete with the normal people with the advanced technology. Calculators are one of the most common required tool at home, school, and work. However, people with various disabilities cannot use standard calculators. But For blinds, we have the Braille calculator coming up. Various statics have shown that the blind people often have hearing problems as well. So , to deal with those , we even have solution for this in form of audio output. The Braille system is a method that is widely used by blind people to read and write. The basic idea is to rotate stepper motor according to the answer, whose shaft will hold wheels on which Braille characters (0 to 9) would have been embossed. The keys of keypads will also be embossed in Braille language. The idea was inspired from old mechanical calculators as shown in fig. These devices were motor-driven, and had movable carriages where results of calculations were displayed by dials.

This paper deals with the technology used to Device the

Braille calculator, From the Braille language, Braille literature survey, the block diagram and working, the components used to the applications and future enhancements. Bhavesh Bhatt, Chirag Gudkha, Avinash Khedekar and Prashant Mistry are with Electronics, PVPPCOE (Padmabhushan vasantdada paristhan Patil College of engineering), Mumbai, India, Email: Email ID- [email protected]

Old Mechanical Calculator:

2. BRAILLE

Braille is a tactile writing system by the blind and the visually impaired, and found in books, on menus, signs, elevator buttons, and currency. Braille-users can read computer screens and other electronic supports thanks to refreshable Braille displays. They can write Braille with a slate and stylus or type it on a Braille writer, such as a portable Braille note-taker, or on a computer that prints with a Braille embosser.

Braille characters are small rectangular blocks called cells that contain tiny palpable bumps called raised dots. The number and arrangement of these dots distinguish one character from another. Since the various Braille alphabets originated as transcription codes of printed writing systems, the mappings (sets of character designations) vary from language to language. Furthermore, in English Braille there are three levels of encoding: Grade 1, a letter-by-letter transcription used for basic literacy; Grade 2, an addition of abbreviations and contractions; and Grade 3, various non-standardized personal short hands.

Braille can be seen as the world's first binary encoding

scheme for representing the characters of a writing system. The system as devised by Braille consists of two parts. A character encoding for mapping characters of the French alphabet to tuples of six bits or dots. A way of physically representing six-bit characters as raised dots in a Braille cell.

Braille may be produced by hand using a slate and

stylus in which each dot is created from the back of the page, writing in mirror image, or it may be produced on a braille typewriter or Perkins Brailler. Because braille letters cannot be effectively erased and written over if an error is made, an error is overwritten with all six dots. Interposing refers to braille printing that is offset, so that the paper can be embossed on both sides, with the dots on one side appearing between the divots that form the dots on the other (see the photo in the box at the top of this



article for an example). Braille may also be produced using a computer with braille translation software and a braille embosser or a refreshable braille display.

Braille has been extended to an 8-dot code, particularly for use with braille embossers and refreshable braille displays. In 8-dot braille the additional dots are added at the bottom of the cell, giving matrix 4 dots high by 2 dots wide. The additional dots are given the numbers 7 (for the lower-left dot) and 8 (for the lower-right dot). Eight-dot braille has the advantages that the case of an individual letter is directly coded in the cell containing the letter and that all the printable ASCII characters can be represented in a single cell. All 256 (28) possible combinations of 8 dots are encoded by the Unicode standard. Braille with six dots is frequently stored as braille ASCII.

The first 25 braille letters, up through the first half of the 3rd decade, transcribe a–z (skipping w). In English Braille, the rest of that decade is rounded out with the ligatures and, for, of, the, and with. Omitting dot 3 from these forms the 4th decade, the ligatures ch, gh, sh, th, wh, ed, er, ou, ow and the letter w.

ch sh th

Letters and Numbers in Braille

3. BRAILLE CALULATOR SYSTEM DESIGN 3.1. BLOCK DIAGRAM DESCRIPTION As shown in figure, 5*4 matrix will act as a input of the calculator which will have Braille embossing on it . user will give the input as number and operation viz. addition , subtraction , multiplication, division to be performed using keypad. Micro-controller P89V51RD2 will carry out the particular operation on user entered numbers and will give the result for further processing.. Micro-controller P89V51RD2 will process the answer of the calculator to rotate the wheels of the braille display to produce the output in terms of the braille.These wheels will be rotated with the

help of stepper motor which will be driven through the driver ULN-2803. The result will also be serially communicated to the micro-controller AT89C2051 which will operate audio-processing and playback IC APR6016 to announce the answer of the calculator on the loudspeaker

WORKING The project will serve as calculator for blind people. The user will input a number through keyboard. The number will be stored in microcontroller . When the user will press any operation key such as ‘+’,’-‘,’*’,’\’, the microcontroller will ask for another number as input from user. On pressing’=’ key, the microcontroller will calculate the result and will display the result on Braille display unit. The four stepper motor in display unit will rotate according to result. After rotation of each stepper motor through one step angle, the corresponding memory location in Serial Memory (24C64) is incremented and stored. As this memory is non-volatile, in case of power failure or when reset button is pressed, the display will rotate back to (0000) position. We are also serially sending the answer to AT89C2051 and communicating with APR6016 to announce the result on loud speaker 3.2 COMPONENTS 3.2.1 MATRIX KEYPAD This is nothing but push-button keys arranged in matrix manner. User will input the numbers to be manipulated and corresponding manipulations to the system. These keys will be attached with the Braille embossed digits and arithmetic signs as shown in figure 4. It will have symbols for letters from 0 to 9 and signs for +,-,\,*,=. The keyboard will be as shown in figure below. Keyboards are organized as a matrix of rows and columns; two side of this matrix are connected to Vcc through resistors while the third side is connected to the microcontroller port and configured as an output; and the last side is connected to the microcontroller port and configured as an input as shown in figure



3.2.2MICROCONTROLER 89S52RD2

The P89V51RD2 is an 80C51 microcontroller with 64 kB Flash and 1024 bytes of Data RAM.A key feature of the P89V51RD2 is its X2 mode option. The design engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or select the X2 mode (6 clocks per machine cycle) to achieve twice the throughput at the same clock frequency. Another way to benefit from this feature is to keep the same performance by reducing the clock frequency by half, thus dramatically reducing the EMI. The Flash program memory supports both parallel programming and in serial In-System Programming (ISP). In-System Programming is performed without removing the microcontroller from the system. The In-System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89V51RD2 through the serial port. This firmware is provided by Philips and embedded within each P89V51RD2 device. The Philips In-System Programming facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (VDD,VSS, TxD, RxD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature

3.2.3. DRIVER ULN2803 The eight Pin NPN Darlington connected transistor in this family of array are ideally suited for interfacing between low logic level digital circuitry (such as TTL CMOS or PMOS /NMOS ) and the higher current /voltage requirement of lamp, really ,printer, hammer or other similar loads for a broad range of computer ,industrial and consumer application. All devices featuring open-collector output and freewheeling clamp diode for transient suppression. the ULN2803 in designed to be compatible with standard TTL families while the ULN 2803is optimized for 6to15 volts high level CMOS or PMOS. 3.2.4. AUDIO PROCESSING APR6106. The APR6016 offers non-volatile storage of voice and/or data in advanced Multi-Level Flash memory. Up to 16 minutes of audio recording and playback can be accommodated. A maximum of 30K bits of digital data can be stored. Devices can be cascaded for longer duration recording or greater digital storage. Device control is accomplished through an industry standard SPI interface that allows a microcontroller to manage message recording and playback. This flexible arrangement allows for the widest variety of messaging options. The APR6016 is ideal for use in cellular and cordless phones, telephone answering devices, personal digital assistants, personal voice recorders, and voice pagers. APLUs Integrated achieves this high level of storage capability by using a proprietary analog multi-level storage technology implemented in an advanced non-volatile Flash memory process. Each memory cell can typically store 256 voltage levels. This allows the APR6008 voice to reproduce audio signals in their natural form,

eliminating the need for encoding and compression which can introduce distortion. 3.2.5 BRAILLE OUTPUT DISPLAY This is going to be the output unit of the calculator. For this purpose, we will be carrying out embossing of the braille digits on the rubber band. This rubber band will be mounted on the circumference of robotic wheel as shown in figure. Accordingly there will be four wheels to display 4-digit output of the calculator. The rotation of all these wheels will be carried out with the stepper motor. Once the micro-controller has calculated the result of arithmetic operations entered by user, each motor will rotate according to the value at each digit position of the answer. Each of this rotation will be with respect to reset position (ANS-0000 position)

4.OUTPUT CALCULATON

1) The output is 4 digit so we are using four stepper motors one for each digit display. Each stepper motor has 11 braille digits 0 to 9 and point (.) embossed on it. 2) The diameter of our wheel is 7cm.So the circumference = pi*d = 22cm.This 22cm corresponds to 360 degrees. 3) We are rotating the stepper motor by 27 degrees for one digit which will correspond to 1.65cm of circumference. Therefore one Braille digit has length of 1.65 cm. 4) To rotate stepper motor 27 degrees i.e. to display one we have to send entire sequence (A,9,5,6) 3 times(3*7.2=21.6) and 3 more steps i.e. (3*1.8=5.4) the total sequence giving 27 degrees(21.6+5.4=27). 5) Similarly to display 2 we have to rotate the stepper motor by 54 degrees and so on for other digits

5. CONCLUSION The stepper motor will rotate in steps according to the angle calculated by microcontroller after the input keys are pressed which are in Braille. The stepper motor stops rotating after the angle of rotation is completed and the blind person can read the output in Braille with their sense to touch. The output is also available in audio form so that it becomes easier to use. The designed Braille calculator currently works for 4 digits. With some improvements the calculator can be incorporated with more features. Furthermore improvements would include a list of possible things-



1. As our display of Braille calculator has limitation of display up to 4 digits, it can be extended up to 8 digits with further sophistication needed.

2. It can be extended to operate on floating point numbers. 3. As nowadays calculators are available with scientific

functions, it may be possible to incorporate them in Braille calculator

4. An increased number of cells on our display, the ability to read more than 100 character longer lasting battery Also, we would like to make our device thinner. Although increasing the number of cells would make our device larger, we might be able make our device wider, which would allow us to make it thinner and still increase the display size

With these possible enhancements implemented

correctly and shown good results , It can have applications like- 1. Assistive technology programs that run on off-the-shelf

computers can speak the text on the screen or magnify the text in a word processor, web browser, e-mail program or other application.

2 Stand-alone products designed specifically for people who are blind or visually impaired, including personal digital assistants (PDAs) and electronic book players provide portable access to books, phone numbers, appointment calendars, and more.

3. Optical character recognition systems scan printed material and speak the text. Braille embossers turn text files into hard-copy Braille.

6. REFERNCES 1. Portable Braille e-Reader By Heajin Hur Nick

Rosenwinkel Sungjin Park ECE 445, SENIOR DESIGN PROJECT FALL 2011.

2. A Portable Device for the Translation of Braille to Literary Text- Iain Murray, Department of Electrical and Computer Engineering Curtin University of Technology Perth, Western Australia.

3. Andrew Pasquale Department of Electrical and Computer Engineering Curtin University of Technology Perth, Western Australia.

Mital Mungra and Assi. Prof. Vishal S.Vora 52


Design Incrementing Burst Data Transfer Operation for AMBA-Advanced High

Performance Bus

Mital Mungra and Assi. Prof. Vishal S.Vora Abstract: The rapid development in the field of mobile communication, digital signal processing motivated the design engineer to integrate the complex systems of multimillion transistors in a single chip. The design of an AMBA advanced high performance bus (AHB) protocol basic block is presented. Operations like simple read write and burst read write and out of order read write are mentioned. The AHB (Advanced High-performance Bus) is a high-performance bus in AMBA (Advanced Microcontroller Bus Architecture) family. This AHB can be used in high clock frequency system modules. The design of the AHB Protocol is simulated using Modelsim which has the basic blocks such as Master and Slave. The arbitration mechanism is used to ensure that only one Master has access to the bus at any one time and the AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer .It can be coded using VHDL. Keywords: AHB bus matrix, arbiter, system on chip, FSM for master and slave, master and slave side arbitration, IP, VHDL..

I. INTRODUCTION

In recent days, the development of SOC chips and the reusable IP cores are given higher priority because of its less cost and reduction in Time to market. So this enables the major and very sensitive issue such as interfacing of these IP cores. These interfaces play a vital role in SOC and should be taken care because of the communication between the IP cores properly. The communication between the different IP cores should have a lossless data flow and should be flexible to the any SOC designer too. Hence to resolve this issue, the standard protocol buses are used in or order to interface the two IP cores. There are many bus interfaces are available in the market. Most of the IP cores from ARM use the AMBA (Advanced Microcontroller Bus Architecture) which has AHB (Advanced High-Performance Bus).

Mital Mungra is working in Department of electronics & communication, Gujarat technical university, Ahmadabad, Gujarat, and Assi. Prof. Vishal S.Vora is working in Department of electronics & communication, Atmiya institute of technology & science, Rajkot.Gujarat., Emails: [email protected] , [email protected]

The purpose of this work is to implement different operation of data transfer for a SOC bus for Open Cores that we would adopt and use in any core development. There exist many bus interfaces AMBA, CORECONNECT, WISHBONE, AVALON are well known and well used bus architectures. AMBA offers advantage compared to all other buses.It can be coded using any hardware description language like VHDL and VERILOG, and it takes the shapes of simple logic gates supported by most of FPGAs and ASIC devices.

AMBA bus which can support up to 16 Master and 16 Slave .The benefits of the SOC approaches are numerous, including improvements in system performance, cost, size and power dissipation. This bus has its own advantages and flexibilities. A full AHB interface is used for the following.

Bus Masters

On-chip memory blocks

External memory interfaces

High-bandwidth peripherals with FIFO interfaces

DMA slave peripherals

II. AMBA-AHB PROTOCOL

A. Objective of the AMBA-AHB

1. It gives Facility to right-first-time development of embedded microcontroller products with one or more CPUs, GPUs or signal processors.

2. It is technology independent, to allow reuse of IP cores, peripheral and system macro cells across diverse IC processes

3. It encourages modular system design to improve processor independence, and the development of reusable peripheral and system IP libraries.

4. It minimize silicon infrastructure while supporting high performance and low power on-chip communication.

B. A Typical AMBA based architecture

The Figure I shows the typical AMBA based Microcontroller system. The Advanced Microprocessor Bus



Architecture (AMBA) defined by ARM is a widely used open standard for an on-chip bus system. An AMBA-based microcontroller typically consists of a high-performance system backbone bus (AMBA AHB or AMBA ASB), able to sustain the external memory bandwidth, on which the CPU, on-chip memory and other Direct Memory Access (DMA) devices reside. In older version it used ASB as a backbone bus or in new version it used AHB as backbone bus. This bus provides a high-bandwidth interface between the elements that are involved in the majority of transfers. The system busses ASB and AHB are designed for high performance connection of processors, dedicated hardware and on chip memory. They allow following things :

1. Multiple bus Masters

2. Pipelined operation

3. Burst transfers

4. Split transactions

5. High performance

Figure I : A typical AMBA based architecture

The main aim of this to make ease the component design ,by allowing the combination of interchangeable components in the SOC design. It promotes the reuse of intellectual property components, so that at least a part of the SOC design can become a composition, rather than a complete rewrite every time. By referring The Advanced Microcontroller Bus Architecture (AMBA) specification 2.0, it defines an on chip communications standard for designing high-performance embedded microcontrollers. Three distinct buses are defined within the AMBA specification:

1. The Advanced High-performance Bus (AHB)

2. The Advanced System Bus (ASB)

3. The Advanced Peripheral Bus (APB)

1. Advanced High-performance Bus (AHB) The AMBA AHB is for high-performance, high clock

frequency system modules. The AHB acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macro cell functions. AHB is also specified to ensure ease of use in an efficient design flow using synthesis and automated test techniques.

2. Advanced System Bus (ASB)

The AMBA ASB is for high-performance system modules. AMBA ASB is an alternative system bus suitable for use where the high-performance features of AHB are not required. ASB also supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macro cell functions.

3. Advanced Peripheral Bus (APB)

The AMBA APB is for low-power peripherals. AMBA APB is optimized for minimal power consumption and reduced interface complexity to support peripheral functions. APB can be used in conjunction with either version of the system bus.

C. Choice of system bus

Both AMBA AHB and ASB are available for use as the main system bus. Typically the choice of system bus will depend on the interface provided by the system modules required. The AHB is recommended for all new designs, not only because it provides a higher bandwidth solution, but also because the single-clock-edge protocol results in a smoother integration with design automation tools used during a typical ASIC Development. It also have features that is not available with ASB

A full AHB or ASB interface is used whenever we want to implement or need to connect the components described below.

Bus Masters

On-chip memory blocks

External memory interfaces

High-bandwidth peripherals with FIFO interfaces

DMA slave peripherals.

A simple APB interface is used whenever we want to implement or need to connect the components described below.

Simple register-mapped slave devices

Very low power interfaces where clocks cannot be globally routed



Grouping narrow-bus peripherals to avoid loading the system bus.

D. Terminology

The following terms are used throughout this specification: 1. Bus Cycle:

A bus cycle is a basic unit of one bus clock period and for the purpose of AMBA AHB or APB protocol descriptions is defined from rising-edge to rising-edge transitions. An ASB bus cycle is defined from falling-edge to falling-edge transitions. Bus signal timing is referenced to the bus cycle clock.

2. Bus Transfer:

An AMBA AHB bus transfer is a read or write operation of a data object, which may take one or more bus cycles. The bus transfer is terminated by a completion response from the addressed slave. The transfer sizes supported by AMBA AHB include byte (8-bit), half word (16-bit) and word (32-bit).

3. Burst Operation : A burst operation is defined as one or more data transactions, initiated by a bus master, which have a consistent width of transaction to an incremental region of address space. The increment step per transaction is determined by the width of transfer (byte, half word and word).

E. Features High performance Burst transfers Split transactions Single edge clock operation SEQ, NONSEQ, BUSY, and IDLE Transfer Types Programmable number of idle cycles Large Data bus-widths - 32, 64, 128 and 256 bits wide Address Decoding with Configurable Memory Map

III. MERITS AND DEMERITS

A. Merits ; AHB offers a fairly low cost (in area), low power

(based on I/O) bus with a moderate amount of complexity and it can achieve higher frequencies when compared to others because this protocol separates the address and data phases.

AHB can use the higher frequency along with separate data buses that can be defined to 128-bit and above to achieve the bandwidth required for high-performance bus applications.

AHB can access other protocols through the proper bridging converter. Hence it supports the bridge configuration for data transfer.

AHB allows slaves with significant latency to respond to read with an HRESP of “SPLIT”. The slave will then request the bus on behalf of the master when the

read data is available. This enables better bus utilization.

AHB offers burst capability by defining incrementing bursts of specified length and it supports both incrementing and wrapping. Although AHB requires that an address phase be provided for each beat of data, the slave can still use the burst information to make the proper request on the other side. This helps to mask the latency of the slave.

AHB is defined with a choice of several bus widths, from 8-bit to 1024-bit. The most common implementation has been 32-bit, but higher bandwidth requirements may be satisfied by using 64 or 128-bit buses.

AHB used the HRESP signals driven by the slaves to indicate when an error has occurred.

AHB also offers a large selection of verification IP from several different suppliers. The solutions offered support several different languages and run in a choice of environments.

Access to the target device is controlled through a MUX, thereby admitting bus-access to one bus-master at a time.

AHB Masters, Slaves and Arbiters support Early Burst Termination. Bursts can be early terminated either as a result of the Arbiter removing the HGRANT to a master part way through a burst or after a slave returns a non-OKAY response to any beat of a burst. However that a master cannot decide to terminate a defined length burst unless prompted to do so by the Arbiter or Slave responses.

Any slave which does not use SPLIT responses can be connected directly to an AHB master. If the slave does use SPLIT responses then a simplified version of the arbiter is also required.

B. Demerits : AHB cannot achieve full data bus utilization and

bandwidth if some slaves have a relatively high latency.

AHB defines transfer sizes of 1, 2, 4, 8, and 16 bytes. Because byte enables are not defined, there are cases where multiple transfers must be made inside a single quadword.

AHB defines timing parameters for many of the relationships between signals on the bus. However, these are not associated with requirements relative to a clock cycle. Therefore, SoC developers must integrate AHB cores and run chip level static timing analysis to judge how compatible AHB masters and slaves are with one another.

Power-based SoCs cover a wide range of applications, and there is a corresponding wide range of address map requirements. Having the address decodes for all AHB slaves reside within the interconnect means having to support the most complex split address ranges, even for the simplest of slaves



IV. BLOCK DIAGRAM OF AMBA_AHB

A. Component of the block diagram :

Totally this block diagram comprises of four components. Arbiter Master Slave Decoder

.

Figure II : block diagram of AMBA-AHB

1. Arbiter : The arbitration mechanism is used to ensure that only one master has access to the bus at any one time. The arbiter performs this function by observing a number of different requests to use the bus and deciding which is currently the highest priority master requesting the bus.

2. Master : A bus master is able to initiate read and write information by providing address and control information. Only one bus master can use the bus at the same time An AHB bus master has the most complex bus interface in an AMBA system. Typically an AMBA system designer would use predesigned bus masters and therefore would not need to be concerned with the detail of the bus master interface. No provision is

made within the AHB specification for a bus master to cancel a transfer once it has commenced.

3. Slave :

After a master has started a transfer, the slave then determines how the transfer should Progress the transfer should progress. Whenever a slave is accessed it must provide a response which indicates the status of the transfer. The HREADY signal is used to extend the transfer and this works in combination with the response signal HRESP which provide the status of the transfer. The slave can complete the transfer in a number of ways. It can:

Complete the transfer immediately Signal an error to indicate that the transfer has failed Delay the completion of the transfer, but allow the

master and slave to back off the bus, leaving it available for other transfers.

4. Decoder : The AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer. A central address decoder is used to provide a select signal ‘HSELx’ for each slave on the bus. The select signal is a combinatorial decode of the high-order address signals. A slave must only sample the address and control signals and HSELx is asserted when HREADY is HIGH, indicating that the current transfer is completing.

B. Working : The AMBA AHB bus protocol is designed with a central multiplexor interconnection scheme. Using this scheme all bus masters drive out the address and control signals indicating the transfer, they wish to perform and the arbiter determines which master has its address and control signals routed to all of the slaves. Before which initially the master who needs to perform the operation should give the request signal to the arbiter and the arbiter will give the grant signal to the master for further proceedings. Similarly, a decoder is used to select the slave which has to be active during the operation based on the address given by the master. A central decoder is also required to control the read data and response signal multiplexor, which selects the appropriate signals from the slave that is involved in the transfer. These make the read and write operation smoothly.

C. AMBA-AHB Signal : All signals are prefixed with the letter H, ensuring that the AHB signals are differentiated from other similarly named signals in a system design. The signals involved in designing the AMBA AHB are listed in the Table I which also gives the specification of each signal.



Table I : AHB signal list

S.No. NAME WIDTH DRIVER FUNCTION

1 HCLK 1 Clock Source

This clock times all bus transfers at the rising edge of HCLK

2 HADDR 32 Master

The system address bus of width 32-bit

3 HTRANS 2 Master

Indicates the type of the current transfer happening

4 HWRITE 1 Master

When HIGH this signal indicates a write transfer and when LOW a read transfer

5 HSIZE 3 Master Indicates the size of the transfer

6 HBURST 3 Master

Indicates if the transfer forms part of a burst.

7 HWDATA 8 Master

The write data bus is used to transfer data from the master to the bus slaves during write operations.

8 HSELx 1 Decoder

Each AHB slave has its own slave select signal and this signal indicates that the current transfer is intended for the selected slave.

9 HRDATA 8 Slave

The read data bus is used to transfer data from bus slaves to the bus master during read operations.

10 HREADY 1 Slave

When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal may be driven LOW to extend a transfer.

11 HRESP 2 Slave

The transfer response provides additional information on the status of a transfer

V. APPLICATIONS

AMBA-AHB can be used in the different application and also it is technology independent.

ARM Controllers are designed according to the specifications of AMBA.

In the present technology, high performance and speed are required which are convincingly met by AMBA-AHB

Compared to the other architectures AMBA-AHB is far more advanced and efficient.

To minimize the silicon infrastructure to support on-chip and off-chip communications.

Any embedded project which involve in ARM processors or Microcontroller must always make use of this AMBA-AHB as the common bus throughout the project.



VI. RESULTS

A. Simulation result of Decoder :

B. Simulation result of Multiplexer :

C. Simulation result of Highest priority algoritham :

D. Simulation result of Master :

E. Simulation result of Slave :



VII. CONCLUSION The AMBA advanced Microcontroller bus architecture specification defines an On-Chip Communications standard for designing high performance embedded microcontrollers. I have designed the intellectual properties of the Master and Slave depending upon the specifications, data transfer and various transfer modes that are supported by AMBA-AHB architecture. All of the commands and data are successfully transferred from one IP core to the other IP core using AMBA-AHB protocol. There is no loss of data or control information. The main goal of this work is to design algorithms for arbiter which is useful to granting the Master. The design of decoder is also completed which is generating the select signal for the slave. Also different operation of data transfer is also mentioned

APPENDIX AMBA – Advanced Microcontroller Based Architecture. AHB – Advanced High performance Bus. ASB – Advanced System Bus. APB – Advanced Peripheral Bus. SOC – System On Chip. IP – Intellectual Property VHDL – Very high speed integrated circuit Hardware

Descriptive Language.

ACKNOWLEDGMENT we have taken efforts in this paper. However, it would not

have been possible without the kind support and help of many individuals. we are highly indebted to Prof. K.B.Sheth, AITS, Rajkot for his guidance and constant supervision as well as for providing necessary information regarding the paper. we would like to express our gratitude towards him for their kind co-operation and encouragement which help us in completion of this paper.

REFERENCES

[1] Rishabh Singh Kurmi and Miss.Shruti Bhargava, “Implementation of an

AMBA Advanced High Performance Bus protocol IP block” , International Journal of Electronics Communication and Computer Engineering (IJECCE) vol.1 Issue.1 01/06/2011.

[2] MS. Usha A. Jadhava and Prof.M.M.Jadhava , “ High Throughput AMBA AHB Protocol” , International Journal of Engineering Science and Technology,Vol. 2(5), 2010, 1233-1241.

[3] Varsha vishwarkama, Abhishek choubey and Arvind Sahu , “Implementation of AMBA AHB protocol for high capacity memory management using VHDL” , International Journal on Computer Science and Engineering (IJCSE).

[4] Anurag Shrivastava , Amit Kant Pandit , Vipan Kakkar and GS Tomar , “Trends and Trade-offs in Designing and Performance Evaluation of Different On-Chip AMBA Bus“ , International Journal of Engineering Sciences & Management,Jan-Mar,2012.

[5] Mohandeep Sharma and Dilip Kumar, “Wishbone Bus Architecture – A Survey And Comparison”, International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012.

[6] Mrs.Bhavana L. Mahajan, Prof. Sampada Pimpale and Ms.Kshitija S. Patil ,” FPGA Implemented AHB Protocol” International Journal Of Electronics And Communication Engineering & Technology (IJECET), Volume 3, Issue 3, October- December (2012).

[7] Priya Bangal “An Experimental Investigation Of An On-Chip Interconnect Fabric Using A Multiprocessor System-On-Chip Architecture”.

[8] Ankita Sharma and R.H. Talwekar,” Low complex architecture for AHB-APB interface to DMA controller using Verilog”, International Journal of Digital Application & Contemporary research, Volume 1, Issue 3, October, 2012, ISSN: 2319-4863.

[9] http://informatik.uibk.ac.at/teaching/ws2007/esd/socslides.pd

Mital Mungra pursuing M.E. in Electronics & communication from Atmiya institute of technology & science, Rajkot.. Her research interest includes Embedded Systems and VLSI.

Vishal S. Vora has pursuing Ph.D (Embedded

system).he is right now working as an assistant professor in department of Electronics & Communication at Atmiya Institute of Technology & Science, Rajkot, Gujarat . He had published more than 10 papers in reputed national or international journal and conference. He had attended and

delivered expert talk in many workshop, STTPS and seminars of embedded system

Mrs. Ashutosh 59


Introduction of SOA in Cloud computing for facilitating new services

Mrs. Ashutosh

Abstract :SOA is an Architectural principle that positions IT services as the primary means through which Business services are offered by the organization to its ecosystem therefore SOA offers the prospect of better alignment of academic and administrative goals to It solution in Education organization also it is a method for publishing services hosted by computer systems for the use of other computer systems. On other hand, cloud computing depict wide ranging advancement towards the operation of wide area networks such as the internet to facilitate interface between IT service supplier and clients. Cloud computing has a numeral profits and threats that should be looked at by any higher ranking guidance group taking into account the relocation of its enterprise computing IT portfolio.

SOA and Cloud computing are complementary activity and both will play important role in IT services. The aim of this paper is to Merge SOA in cloud computing to provide an organization with aspect to select common standard for network Accessible capabilities while the concept share many common characteristics they are not synonymous and can be perused either independently or as concurrent activities

1. Introduction: Software engineering is a systematic approach of development, operation and maintenance of software. In software engineering Service-Oriented Architecture, different method which is used for software development with the help of services and these services may communicate with other services also. Service-Oriented Architectures (SOA) is becoming increasingly widespread in a variety of computing domains such as enterprise and e-commerce systems, which continue to grow in size and complexity. These systems are expected to adapt not only to the fluctuating execution environments but also to changes in their operational requirements. SOA is a collection of different services and these services can communicate to each other using message passing (message passing include simple data passing or coordination of different activates). Software architecture describes the system’s components and their interaction at the high level. These components are not distributed objects and work as a module which is deployed onto a server as a single unit along with other components and the interaction between the components is called “connecters”. Mrs. Ashutosh is working in Gautam Buddha university, Greater Noida, Email: [email protected]

Using Service-oriented Architecture, Software quality can be improved as well as cost will reduce with more reusable component in software engineering. Reusable components are designed to perform specific functions. These are independent and pre-built pieces of programming code. Therefore, it is important and productive to conduct research on how to develop software with service –oriented computing technology. There is not enough research and practices to implement “register, find, bind and execute” paradigm and make practical and cost-effective. So we need to analyze this process deeply to provide practical architectures and methodologies for reusable services. The impact of reusability in SOA is innovative. The component development for providing various services is difficult task for a Service Oriented System. It is not efficient to develop a new component for a new service every time as it would not be economical and also it is difficult to integrate it with the Legacy System. Today as per change in environment software also change according to that new requirements are added as old one are deleted from software but any software model do not include this feature so service oriented architecture uses services for contraction of low cost, secure and reliable applications with the help of WSDL web service description language services are designed for how they look or work and in one service many services can be combined together. new service every time as it would not be economical and also it is difficult to integrate it with the Legacy System. There has also been an emergence of a dynamic understanding and need to control what how and when the cloud provides services to the consumers of those services.

2. New Service Introduction to SOA This paper proposes a combined model for service discovery and negotiation of new service. In the paper the discovery method and new service negotiation method is discussed with different process. Service requesters can be either arbitrary application developers or other service providers. A service provider needs to register its services with a service registry and provide services directly to interested parties. Each service may have multiple service interfaces to meet the needs of different requesters, and requesters can dynamically discover the interfaces they require. Making discovery-based service abstraction is challenging. Step 1: In this model first of all service and negotiation thread is discovered, and specifications are searched.

Mrs. Ashutosh 60


Step 2: If specifications are exactly matched then available service is searched and provides the service. If specification is not matched then request gets rejected and will search for new service. Now it will check the interface with matching parts and send request for the same.

Step 3: If request is served then prepare the contract document otherwise search for new one.

Step 4: the new search checks whether the new service is posted and prepare the contract otherwise negotiation is done for the provided service. If service is not negotiable then customer can exit from the process.

Step 5: In this model modification can be done in the new service before or after negotiation, then bind and execute.

Step 6: After contract documents are sent to the requestor the service is bind and executed, and specifications are sent to the registry.

Fig1: flow chart for negotiation and new service thread

3. Cloud computing over SOA

a. Network Reliance: SOA is basically reliant on the network to unite the service supplier with the buyer. For Example, Web service protocols are used on internet protocols to cite software role spread transversely on the network. Underperforming networks can instill a huge brunt on the accessibility of web services to the customer.

b. Supplier Overhead: Actualizing all-purpose

reclaimable software constituent for wide recipients utilizes more imaginations than evolving a smaller amount of general elucidation. The cost of regaining, therefore, swings to the service contributors, which repays it to the customers.

c. Business Measures: When several constituents are

being formulated at the same time by individualist teams, it becomes substantial for the interface of a suppliers service to affirm to the terms of a consumer. Likewise, it aids everybody involved, if the interfaces alongside services have a little solidity in configuration and security access procedures. Selecting and transmitting a complete band of business measures is a reliable in coming near to help in business SOA assimilation.

d. Organizational Agility: It relates to SOA, where

we are often pertaining to organizational agility, or the cognition to more rapidly getting used to a centralized organization’s supplements to match their up to date necessities. An organization’s demands of IT might alter over time for numerous factors, including alterations in the enterprise or organization, modifications in enterprise-wide describing requirements, adaptations in the ordinances, novel technologies in the lucrative business enterprise, endeavors to unite varied data accumulation resources, to meliorate the organization’s functional impression, and several other rationalities.

3.1 Characteristics Cloud computing has a variety of characteristics, with the main ones being:

Shared Infrastructure — Uses a virtualized software model, enabling the sharing of physical services, storage, and networking capabilities. The cloud infrastructure, regardless of deployment model, seeks to make the most of the available infrastructure across a number of users.

Dynamic Provisioning — Allows for the provision of services based on current demand requirements. This is done automatically using software automation, enabling the expansion and contraction of service capability, as needed. This dynamic scaling needs to be done while maintaining high levels of reliability and security.

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Mrs. Ashutosh 61


Network Access — Needs to be accessed across the internet from a broad range of devices such as PCs, laptops, and mobile devices, using standards-based APIs (for example, ones based on HTTP). Deployments of services in the cloud include everything from using business applications to the latest application on the newest smart phones.

Managed Metering — Uses metering for managing and optimizing the service and to provide reporting and billing information. In this way, consumers are billed for services according to how much they have actually used during the billing period.

In short, cloud computing allows for the sharing and scalable deployment of services, as needed, from almost any location, and for which the customer can be billed based on actual usage.

4. Convergence of SOA and Cloud Computing The shift towards services willalso leads to standardization. Thus, the components of software services can be tied together and carried out on several platforms over the network business purpose. The several functions involved are:

Network Dependence: Both cloud computing and SOA count on a robust network to unite consumers and producers and in that sense, both have the identical initial morphological blemishes, when the network is not operating or is unavailable. A researcher has intricate on this concern by mentioning that “with gigabit Ethernet connections in local area networks, and progressively quick internet services; network operation has bettered to the extent where cloud computing looks like a feasible forgoing [1].

Forms of Outsourcing: Both constructs require forms of contractual kinship and belief between service benefactors and service enjoyers. Reuse of an SOA service by a group of other systems is in effect an “outsourcing” of that capability to another organization. With cloud computing, the outsourcing is more conspicuous and frequently has a fully fruitful gusto. Storage, platforms, and servers are acquired from business benefactors who have economies of degree in providing those cater to vast addressees. Cloud computing allows the customer organization to leave the detailed IT administration issues to the service benefactors.

Standards: Both cloud computing and SOA provide an organization with aspect to select common standards for network accessible capabilities. SOA has a rather constituted set of principles, with which to implement software services, such as representational state transfer (REST), simple-object access protocol (SOAP) and web services description language (WSDL), among many others. Cloud computing is not as mature, and many of the interfaces offered are unique to a

particular vendor, thus raising the risk of vendor lock-in.

5. Service Models Once a cloud is established, how its cloud computing services are deployed in terms of business models can differ depending on requirements. The primary service models being deployed are commonly known as: 5.1 Software as a Service (SaaS) — Consumers purchase the ability to access and use an application or service that is hosted in the cloud. A benchmark example of this is Salesforce.com, as discussed previously, where necessary information for the interaction between the consumer and the service is hosted as part of the service in the cloud. Also, Microsoft is expanding its involvement in this area, and as part of the cloud computing option for Microsoft® Office 2010, its Office Web Apps are available to Office volume licensing customers and Office Web App subscriptions through its cloud-based Online Services. 5.2 Platform as a Service (PaaS) — Consumers purchase access to the platforms, enabling them to deploy their own software and applications in the cloud. The operating systems and network access are not managed by the consumer, and there might be constraints as to which applications can be deployed. 5.3 Infrastructure as a Service (IaaS) — Consumers control and manage the systems in terms of the operating systems, applications, storage, and network connectivity, but do not themselves control the cloud infrastructure. Also known are the various subsets of these models that may be related to a particular industry or market. Communications as a Service (CaaS) is one such subset model used to describe hosted IP telephony services. Along with the move to CaaS is a shift to more IP-centric communications and more SIP trucking deployments. With IP and SIP in place, it can be as easy to have the PBX in the cloud as it is to have it on the premise. In this context, CaaS could be seen as a subset of SaaS. Traditionally a user needed to rest share some resources before he or she could be granted access to a larger pool of shared resources, a cloud computing user need only pay for the computing services. With cloud computing, new Internet services can be developed and deployed without capital acquisitions of hardware or large human integration expenses. Amazon launched its cloud offering back in 2006, known as the Elastic Computing Cloud or EC2 (see http://aws.amazon.com/ec2). Other companies, such as Google’s App Engine (http://code.google.com/app engine) and Microsoft’s Azure Platform (www.microsoft.com/windows azure), released their cloud platforms later in 2008.Open source cloud computing infrastructure systems have also been developed from university research groups, such as Eucalyptus.6 These cloud computing offerings provide different levels of abstraction and services to cloud users. Cloud computing

Mrs. Ashutosh 62


environments offer three major types of services: infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS).7 For example, by leveraging IaaS, Amazon EC2 provides a computing unit that looks much like physical hardware. Users can control the entire software stack. On the other hand, while leveraging SaaS, Google App Engine requires strict restrictions on application architectures as it attempts to improve scalability and performance. A single aspect of SOA is message passing. In realizing a workflow of services, messages are passed between services or between services and the service container. An issue related to security is the threat to the privacy of proprietary information. Not only is there a risk that messages could be intercepted, but there’s also the threat that competitors might be able to infer business operations from message traffic. Cloud environments suffer the same problems with privacy.

6. Conclusion: With the help of this new computing technique many organization develop distributive software system by combing or assembling basic services and these services come from different service providers , XML language is used for taking information and data from these providers service-oriented and cloud computing combined will indeed begin to challenge the way in which we think about enterprise computing. However, the potential for sharing could not only remove historical barriers but also encourage organizations to think more collaboratively. In cloud computing user only need to pay for the computing services. With it if a user wants to develop or deploy any internet services than he/she can do that without any capital acquisition of hardware and or large human integration expense. As in SOA services provided for user or services are created for providers also but these services are controlled in cloud computing. Cloud computing does an emergence of a dynamic understand and need to control what and how clouds provides the service to consumers of these services. References: [1] John Naughton, “Holes in the net make „cloud

computing‟ pie in the sky http://www.guardian.co.uk/technology/2008/mar/02/securit y.internetphonesbroadband.

[2] John Foley, “A Definition of Cloud Computing”http://www.informationweek.com/cloudcomputing /blogarchives/2008/09 /a_defi nition_of.html

[3] Simon Wardley, “Cloud Recap….. The CloudToday”http://blog.gardeviance.org/2008/10/cloudrecap. html.

[4] Dr. Vinay Goyal, Amit Jain “Service-Oriented Architecture & Its Concept - Unleashed”, published in Proceedings of International Conference on Advances in Modeling, Optimization & Computing (AMOC-

2011), at Indian Institute of Technology (IIT), Roorkee.

[5] GDS InfoCentre, Roman Bradley, “Agile Infrastructures”http://gdsinternational.com/infocentre/artsum.asp?mag=184&iss=150&art=25901&lang=en 28 March 2008.

[6] M.B. Blake, “Decomposing Composition:Service-Oriented Software Engineers,” IEEE Software, vol. 24, no. 6, 2007, pp. 68–77.

[7]. M.P. Papazoglou et al., “Service-Oriented Computing: A Research Roadmap,” Int’l J. Cooperative Information Systems, vol. 17, no. 2, 2008, pp. 223–255.

Swapnil Shringarpure, Pranjal Upadhyay, Abhishek Bhalotia and Dhiraj Sambhwani 63


AUTOMATED BICYCLE

Swapnil Shringarpure, Pranjal Upadhyay, Abhishek Bhalotia and Dhiraj Sambhwani

ABSTRACT: The paper deals with the research and development of electric bicycles which can be implemented as an alternative to the two wheelers consuming large amount of fuel and polluting the environment. In order to cope with the lightning speed of life these days quick transportation has been one of the important factor, in one way the fast transport provide us with the modern needs of life, but on the other side the it has resulted in increased consumption of fuels and also played a crucial role in increasing pollution. This research deals with these problems efficiently as energy is generated utilizing the mechanical energy of the rider.The state of the art, general calculus and future developments are shown.

1. INTRODUCTION

This research is to implement an electric cycle powered by energy generated during pedalling to save non-renewable sources of energy that are used at an alarming rate. The pie-chart given shows a regular increase in the use of 2 wheelers, as there is a regular rise in the prices of petrol, travelling has become more and more costly as well as alarming for the mankind. The self powered electric cycle makes use of dynamo to generate electricity and motor to utilize the same.

Fig 1: Pie chart depicting the use of various transports in India Swapnil Shringarpure , Pranjal Upadhyay, Abhishek Bhalotia and Dhiraj Sambhwani are with Electronics Department,PVPPCOE, Emails: [email protected] , [email protected], [email protected] , [email protected]

2. EVALUATION OF THE STATE OF THE ART The basic configuration of an electric bicycle consists of a control switch that controls whether the power flow is from the dynamo to battery or from battery to the electric motor. The rider of an electric bicycle can choose to

Rely on the motor completely. Pedal and use the motor at the same time. Pedal only (use as a conventional bicycle).

Aspects Favouring the Use of Electric Bicycles A number of aspects favour the use of electric bicycles indifferent situations. These include lower energy cost per distance travelled (1–2% of going by car when going by electric bicycle) for a single rider; savings in other costs such as insurance, licenses, registration, parking, improvement of the traffic flow; environmental friendliness; and the health benefit for the rider (Table 1).[1] Table 1: Aspects favouring use of electric bicycles

2.1 BLOCK DIAGRAM

Fig 2: Block diagram



3. COMPONENTS USED

3.1 DC MOTOR WITH SPROCKET

Fig 3: DC motor with sprocket

A sprocket that is fabricated is attached to the shaft of a DC motor (12V, 100 rpm) which rotates over the chain generating electricity. It generates a voltage of about 30V and a current of 1A at its highest speed. 3.2 PROTECTION CIRCUIT A protection circuit or a regulator circuit containing adjustable voltage regulator IC LM 371 is used so as to protect the battery from extra charge. 3.3 CONTROLLING CIRCUIT A circuit controlling the flow of power using switches is used. While charging the rectified power of the dynamo is stored in the batteries and so the switch between motor and batteries is OFF whereas that between dynamo and batteries is ON. When the rider is exhausted the switch for discharging is turned ON and so the batteries provide the power stored in them to the motor which has its shaft connected to the axel of the wheel. The rotation of the shaft causes rotation of the wheel. 3.3 MOTOR

Fig 4: DC motor for discharging

For discharging the motor used is a Johnson’s motor (12V, 60rpm). 3.4 BATTERIES The energy storage source of an electric bicycle is the rechargeable battery. At present, there are 4 battery chemistries that are observed in use. The Lead Acid (PbA) battery is by far the most common, while Nickel Cadmium (NiCad) is occasionally seen, and Nickel Metal-Hydride

(NiMH) and Lithium Ion (Li-ion) batteries are both making headway as the choice for the future. [2] In this paper we are considering use of Lead Acid batteries. Recharging of these storage batteries is obtained by connecting the battery terminals to a dc voltage source that has a voltage that is greater than the battery voltage. This voltage difference will cause a charging current to flow through the battery and reverse the chemical reaction that occurred during discharge. The charging current decreases as the voltage difference between the charging voltage and the battery voltage decreases. Typically, the selected charging voltage is greater than the nominal battery voltage in order to cause a slight overcharge of the battery. The battery is deemed to be "charged" when the batteries will accept no additional current.

4. GENERAL CALCULUS 4.1 Torque equation 푇표푟푞푢푒 = 푀 × 푎 × 푟 Where M = mass of the cycle a = acceleration r = radius of wheel 4.2 Power and Torque Relation

푃표푤푒푟 =푇표푟푞푢푒 × 2휋 × (푟표푡푎푡푖표푛푎푙푠푝푒푒푑)

60000

5. APPLICATIONS THAT IT CAN RUN The electric bicycle can be used for saving some amount of electricity that can be used in our day to day lives such as charging of cell phones, laptop charging and also for lighting a small led.

Fig 5: LED lightning using a dynamo



Fig 6: Laptop charging using pedalling

Fig 7: Charging of a mobile using pedalling

6. FUTURE DEVELOPMENTS Since the research done in this paper is limited to making a prototype of electric bicycle the same can concept can be applied to a bigger cycle with taking many factors into consideration and keeping the basic logic same.

7. ACKNOWLEDGEMENTS We would like to thank our project guide, Mrs.Leena Govekar and our project co-ordinator, Mrs.Nilima.Zade for their continuous guidance in carrying out this research.

REFERENCES [1] Annete muetze, Electric Bicycles – A performance

evaluation Institute of Technology, USA. [2] Justin Lemire-Elmore, the Energy Cost of Electric and

Human-Powered Bicycles Term Paper 81781999, April 13, 2004.

E.Angel Anna Prathiba and B.Saravanan 66


HASBE for Access Control by Separate Encryption/Decryption in Cloud Computing

E.Angel Anna Prathiba and B.Saravanan

. Abstract— Cloud computing has emerged as one of the most influential paradigms in the IT industry. In such area the data confidentiality, flexibility and access control are to be considered in the research area. Data owners and service providers are not in the same trusted domain in cloud computing. Enterprises usually store data in internal storage and install firewalls to protect against intruders. The data will be stored in storage provided by service providers. Service providers should not be a trusted one anyhow they are all third party. Propose a novel technique to Hierarchical Attribute Set Based Encryption (HASBE) , it is driven by the Cipher Policy attribute-based encryption (CP-ABE) with a hierarchical structure of cloud users. It achieves both flexibility and fine-grained access control to support compound attributes of ASBE. Storing the data in encrypted form is a common method of information privacy protection. If a cloud system is responsible for both tasks on storage and encryption/decryption of data, the system administrators may simultaneously obtain encrypted data and decryption keys. This allows them to access information without authorization and thus poses a risk to information privacy. The proposes of business model for cloud computing based on the concept of separating the encryption and decryption service from the storage service. Customer Relationship Management for business model that is driven by the category of Software as a Service method in cloud. Implement the scheme and show that it is both efficient and flexible in dealing with access control for outsourced data and encryption/decryption operations shows high secure and effective way for accessing data in cloud environment. Keywords- cloud computing; service level agreements; encryption and decryption cloud service; data privacy protection

I. INTRODUCTION

Cloud computing is the delivery of computing as a service rather than a product, whereby shared resources, software, and information are provided to computers and other devices as a metered service over a network (typically the Internet).Cloud computing provides computation, software, data access, and storage resources without requiring cloud users to know the location and other details of the computing infrastructure.

End users access cloud based applications through a web browser or a light weight desktop or mobile app while the business software and data are stored on servers at a remote location.

E.Angel Anna Prathiba is a PG scholar and ,B.Saravanan is working as Assistant Professor, Department of Computer Science and Engineering, Angel College of Engineering and Technology, Tirupur, Tamilnadu, India. [email protected],[email protected]

Cloud application providers strive to give the same or better service and performance as if the software programs were installed locally on end-user computers Service providers follow specific policies and practices to protect their users’ data, and these policies are usually stated in the service contract. Most current network application services have the same practice.The content of the service contract covers definitions of service items, service scope, service change notification, scope of privacy protection, regulations on user data collection, use, sharing and release, and statements regarding user responsibilities. In a cloud computing environment, the service content offered by service providers can be adjusted according to the needs of the user. For example, the applicant can request different amounts of storage, transmission speeds, levels of data encryption and other service application service, and agrees with the provider’s data privacy and protection policies.A common approach to protect user data is that user data is encrypted before it is stored. In a cloud computing environment, a user’s data can also be stored following additional encryption, but if the storage and encryption of a given user’s data is performed by the same service provider, the service provider’s internal staff (e.g., system administrators and authorized staff) can use their decryption keys and internal access privileges to access user data. From the user’s perspective, this could put his stored data at risk of unauthorized disclosure.

Creating user trust through the protection of user’s data

content is the key to the widespread acceptance of the cloud computing. This study proposes a business model for cloud computing based on the concept of using a separate encryption and decryption service. In the model, data storage and decryption of user data are provided separately by two distinct providers. In addition, those working with the data storage system will have no access to decrypted user data, and those working with user data encryption and decryption will delete all encrypted and decrypted user data after transferring the encrypted data to the system of the data storage service provider.

Given that encryption is an independent cloud

computing service, a unique feature of the business model is that different services are provided by multiple operators. system with effective data protection. This study provides a draft SLA for this type of business model of combining multiple providers in a single servicewhich can establish the cooperation model between operators and the division of responsibility for the services they jointly provide to the user.

,



II. RELATED WORK

A. Origin of cloud computing Cloud computing services use the Internet as a

transmission medium and transform information technology resources into services for end-users, including software services, computing platform services,development platform services, and basic infrastructure leasing.

As a concept, cloud computing’s primary significance lies in allowing the end user to access computation resources through the Internet, as shown in Fig. 1. Some scholars find cloud computing similar to grid computing [3], but some also find similarities to utilities such as water and electrical power and refer to it as utility computing [2]. Because the use of resources can be independently adjusted, it is also sometimes referred to as autonomic computing [5]

Figure 1. Cloud computing concept map

The literature contains many explanations of cloud

computing [6]. After compiling scholarly definitions of cloud computing, Vaquero, Rodero-Merino, Caceres, and Lindner suggested that cloud computing could be defined as the integration of virtual resources according to user requirements, flexibly combining resources including hardware, development platforms and various applications to create services[7]. The special features of cloud computing include the storage of user data in the cloud and the lack of any need for software installation on the client side. As long as the user is able to connect to the Internet, all of the hardware resources in the cloud can be used as client-side infrastructure. Generally speaking, cloud computing applications are demand-driven, providing various services according to user requirements, and service providers charge by metered time, instances of use, or defined period. B. Cloud computing business models

The hardware and architecture required for providing cloud computing environment services is similar to most computer hardware and software systems. The hardware in a modern personal computer (i.e., CPU, HDD, optical drive, etc.) performs basic functions such as performing calculations and storing data. The operating system (e.g., Windows XP) is the platform for the operations of the basic infrastructure, and text processing software such as MSWord and Excel are application services which run on the platform.

The architecture of cloud services can be divided into

three levels: infrastructure, platform, and application software [7]. Application software constructs the user interface and presents the application system’s functions. Through the functions of the operations platform, the application can use the CPU and other hardware resources to execute calculations and access storage media and other equipment to store data.

Building a cloud computing application as a service requires infrastructure, platform and application software which can be obtained from a single provider or from different service providers. If the revenue for cloud services primarily comes from charging for infrastructure, this business model can be referred to as Infrastructure as a Service (IaaS). If revenue comes primarily from charging for the platform, the business model can be referred to as Platform as a Service (PaaS). If revenue primarily comes from charging for applications or an operating system, the business model can be referred to as Software as a Service (SaaS).

proposed a holistic business model framework [8], as shown in Fig. 2.

Fig. 2 presents a hierarchical structure, with Platform as

a Service as the value-added infrastructure service. The Application is built on the infrastructure and computing platform, and requires a specific user interface.

C. Data confidentiality for clients

In a cloud computing environment, the equipment used for business operations can be leased from a single service provider along with the application, and the related business data can be stored on equipment provided by the same service provider.

Figure 2. Hierarchical structure of system model for data access in cloud

Trusted authority

Domain authorit

Domain authorit

Domain authorit

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Authorize by trusted authority

Data owner Data customer

Manage data by its owner Authorize by domain authority

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Data file Key to decrypt

the data file

Cloud service provider

Tree access policy

Cloud



This type of arrangement can help a company save on hardware and software infrastructure costs, but storing the company’s data on the service provider’s equipment raises the possibility that important business information may be improperly disclosed to others[9].

Some researchers have suggested that user data stored on a service-provider’s equipment must be encrypted [10]. Encrypting data prior to storage is a common method of data protection, and service providers may be able to build firewalls to ensure that the decryption keys associated with encrypted user data are not disclosed to outsiders. However, if the decryption key and the encrypted data are held by the same service provider, it raises the possibility that high-level administrators within the service provider would have access to both the decryption key and the encrypted data, thus presenting a risk for the unauthorized disclosure of the user data. D. Secured data storage in existence

Common methods for protecting user data include encryption prior to storage, user authentication procedures prior to storage or retrieval, and building secure channels for data transmission. These protection methods normally require cryptography algorithms and digital signature techniques, as explained below:

Common data encryption methods include symmetric and asymmetric cryptography algorithms.Generally speaking, symmetric cryptography is more efficient, and is suitable for encrypting large volumes of data. Asymmetric cryptography requires more computation time and is used for the decryption keys required for symmetric cryptography.

The use of passwords as an authentication process is more familiar to general users, but messages sent by the user are vulnerable to surreptitious recording by hackers who can then use the data in the message to log into the service as the user. In more advanced authentication systems, the system side will generate a random number to send the user a challenge message, requesting the user to transmit an encrypted response message in reply to the challenge message, thus authenticating that the user has the correct encryption key. Without this key, the user will not be allowed access. In the process of challenge and response the client’s encrypted key uses the client’s password to convert a derived value and. In this program, each communication between the client and server is unique, and a hacker using an old message would fail to access the system. In addition, the One-Time Password (OTP) authentication system differs from most peoples’ conception of a password[13]. Most people understand a password to be a password chosen by the user to be meaningful, and can be used again and again. The emphasis of OTP, however is the single-use nature of the password.

After receiving authentication from the user, the system side must create a secure transmission channel to exchange information with the user. The Secure Sockets Layer (SSL) is a common method of building secure channels[14], primarily using RSA encryption to transmit the secret keys needed for the both sides to encrypt and decrypt data transmitted between them.

When using cryptographic technology to protect user

data, the keys used for encryption and decryption of that data must be securely stored. In particular, cloud computing service providers must have specific methods for constraining internal system management personnel to prevent them from obtaining both encrypted data and their decryption keys – this is critical to protecting user data. Operator policies for protecting user data must be clearly laid out in the Service Level Agreement (SLA) and must explain how special privilege users are prevented from improperly accessing user data.

Kandukuri, Paturi and Rakshit offer six recommendations for SLA content[4], including (1) special privilege user data access must be controlled to prevent unauthorized storage or retrieval, (2) cloud computing services must comply with relevant laws, (3) user data must be properly stored and encrypted, (4) a reset mechanism must be provided in case of service disruption or system crash, (5) service must be sustainable and guaranteed against service discontinuation due to change or dissolution of the provider and (6) if cloud computing services are used for illegal purposes, the provider must be able to provide records to assist with investigations.

III A BUSINESS MODEL SEPARATE ENCRYPTION

AND DECRYPTION SERVICE A. Concepts

This study proposes a Business Model for Cloud Computing Based on a Separate Encryption and Decryption Service. The concept is based on separating the storage and encryption/decryption of user data, as shown in Fig. 3. In this business model, Encryption/Decryption as a Service and Storage as a Service (SaaS) are not provided by a single operator. In addition, the SaaS provider may not store unencrypted user data and, once the provider of Encryption/Decryption as a Service has finished encrypting the user data and handed it off to an application (e.g. a CRM system), the encryption/decryption system must delete all encrypted and decrypted user data.

Figure 3. Encryption/Decryption as an independent service

The concept of dividing authority is often applied in

business management. For example, responsibility for a company’s finances is divided between the accountant and cashier. In business operations, the accountant is responsible for keeping accounts, while the cashier is responsible for making payments. By keeping these two functions separate, the company can prevent the accountant from falsifying accounts and embezzling corporate funds. Official documents frequently need to be stamped with two seals (i.e., the corporate seal and the legal representative’s seal), thus preventing a staff member from abusing his position to issue fake documents, and these seals are normally entrusted to two different people. These examples of the division of



authority are designed to avoid a concentration of power which could raise operational risks.

In a cloud computing environment, the user normally uses cloud services with specific functions, e.g., Salesforce.com’s CRM service [14], SAP’s ERP services [16], etc. Data generated while using these services is then stored on storage facilities on the cloud service. This study emphasizes the addition of an independent encryption/decryption cloud service to this type of business model, with the result that two service providers split responsibility for data storage and data encryption/decryption.

To illustrate the concept of our proposed business model, Fig. 4 presents an example in which the user uses separate cloud services for CRM, storage and encryption/decryption. According to the user’s needs, CRM Cloud Services could be swapped for other function-specific application services (e.g., ERP Cloud Services, Account Software Cloud Services, Investment Portfolio Selection and Financial Operations Cloud Services).

Figure 4. Business model concept integrate separate

cloud services for data encryption/decryption, CRM and storage

Prior to the emergence of an emphasis on the independence of encryption/decryption services, CRM, ERP and other cloud services would simultaneously provide their users with storage services. This study emphasizes that Encryption/Decryption Cloud Services must be provided independently by a separate provider. B. Examples of the Encryption/Decryption as a Separate

Cloud Service Business Model

After the user logs into the CRM system, if the CRM Service System requires any client information, it will execute a Data Retrieval Program. When this data needs to be saved, it will execute a Data Storage Program. The Data Retrieval Program is illustrated in Fig. 5 and is explained below.

Figure 5. Data retrieval diagram

When a user wants to access the CRM Cloud Service, he

must first execute the Login Program as shown in Step 1. This step can use current e-commerce or other services which have already securely verified the user’s registration, such as symmetric key-based challenge and reply login verification, or through a One-Time Password.

After the user’s login has been successfully verified, if the CRM Service System requires client information from the user, it sends a request for information to the Storage Service System, as shown in Step 2. In this step, the CRM Service System transmits the user ID to the Storage Service System where it searches for the user’s data. This data is encrypted so, once found, a request must be sent to the Encryption/Decryption Service System along with the user ID. Step 3 shows the Storage Service System executing the transmission of encrypted client data and the user ID to the Encryption/Decryption Service System.

Since the Encryption/Decryption Service System can serve multiple users and the encryption/decryption for each user’s data requires a different key, therefore each user’s unique ID and keys are stored together. Therefore, in Step 4, the Encryption/Decryption Service System uses the received user ID to index the user’s data decryption key, which is then used to decrypt the received data. Using the correct decryption key to decrypt the data is critical to restoring the data to its original state.

After the Encryption/Decryption Service System has decrypted the client’s data, in Step 5 the decrypted client data is provided to the CRM Service System which then displays the client data to the user in Step 6, completing the Data Retrieval Program. Prior to sending the decrypted client data, the Encryption/Decryption Service System and the CRM Service System can establish a secure data transmission channel (e.g., a Secure Sockets Layer connection) to securely transmit the decrypted client data. After the decrypted client data is sent, the Encryption/Decryption Service System is not allowed to retain the decrypted data and any unencrypted data must be deleted to prevent the encrypted data and the decryption key from being stored in the same system. This is a critical factor in ensuring the privacy of user data. Next,the Data Storage Program, as shown in Fig. 6. This program also involves the collaboration of three cloud service systems: CRM Service System, Encryption/Decryption Service System, and Storage Service System.

Figure 6. Data storage diagram



Step 1 of Fig. 6 shows the client sending a Data Storage Request to the CRM Service System which then initiates the Data Storage Program, requesting data encryption from the Encryption/Decryption Service System as shown in Step 2. In Step 2, the CRM Service System and the Encryption/Decryption Service System establish a secure data transfer channel to transmit the user ID and the data requiring storage from the CRM Service System to the Encryption/Decryption Service System.

As the encryption of data from different users requires different keys, in Step 3 the Encryption/Decryption Service System initiates data encryption, which involves using the received user ID to index the user’s encryption key which is then used to encrypt the received data.

Following this study’s emphasis on the principle of divided authority, once the client data is encrypted by the Encryption/Decryption Service System it must be transferred to the Storage Service System where the user ID and encrypted data are stored together. Therefore, when the Encryption/Decryption Service System executes Step 4, it must transfer the user ID and encrypted client data to the Storage Service System. Step 5 shows the Storage Service System receiving the user ID paired with the data for storage. In this business model, the following the completion of Step 4 at the Encryption/Decryption Service System, all unencrypted and decrypted user data must be deleted.

Step 6, the final step of the Data Storage Program, transmits a Data Storage Complete message from the Storage Service System to the CRM Service System, at which point the CRM Service System may confirm that the client data has been stored. If it doesn’t receive a Data Storage Complete message,it can re-initiate the Data Storage Program or, after a given period of time, proceed with exceptional situation handling.

In the above example, the user’s goal in logging into the CRM Service System is possibly to maintain part of the client data, thus the system design must take data maintenance into consideration. Feasible design methods include matching the encrypted client data with the corresponding user ID and client ID, thus allowing for the indexing of the user ID to obtain the corresponding client data. Then the client ID can be used to index the client data the user wishes to maintain. Considering the massive amount of client data, search efficiency could be improved by combining the user ID and client ID to form a combined ID used for searching for a specific client’s data.

In the new business model, multiple cloud service operators jointly serve their clients through existing information technologies including various application systems such as ERP, accounting software, portfolio selection and financial operations which may require the user ID to be combined with other IDs for indexing stored or retrieved data. In addition, the foregoing description of the two systems can use Web Service related technology to achieve operational synergies and data exchange goals. These technologies can consider open international standards including the World Wide Web Consortium’s (W3C) published Web Service, UDDI, WSDL and SOAP standard documentation. C. Service Level Agreement Content

The above-mentioned example has multiple service operators coordinating to provide a CRM Cloud Service. Unlike conventional Service Level Agreements (SLA), any SLA between the user and the service provider must consider the rights and obligations of the collaborating operators, and operators should sign contracts between themselves to establish the division of responsibilities and cooperation model for providing common services to clients.

The proposed example of a CRM Cloud Service includes a template for a multi-party SLA for the user, CRM operator, encryption/decryption service operator, storage service operator. The content is based on policies for ensuring data privacy, as shown in Fig. 7.

Figure 7. Cloud services SLA template (based on policies to ensure data privacy)

IV. CONCLUSION Cloud computing environments include three types of

services: infrastructure, platform and software. To the user, cloud computing virtualizes resources and, to access services, the user only requires a means of accessing the Internet, example a smart phone or PDA, or even a Smart Card or other active smart chip, thus reducing purchasing and maintenance costs for software and hardware. Because key industrial data is stored on the service provider’s equipment, the service provider must protect the user’s data, for example by encrypting the user’s data prior to storage. However, this leaves the service provider’s high-privilege internal staff (e.g., system administrators) with access to both the Decryption Key and the user’s encrypted data, exposing the user’s data to risk of potential disclosure.

For cloud computing to spread, users must have a high level of trust in the methods by which service providers protect their data. This study proposes a Business Model for Cloud Computing Based on a Separate Encryption and Decryption Service, emphasizing that authorization for the storage and encryption/decryption of user data must be vested with two different service providers. The privileges of Storage as Service provider include storing user data which has already been encrypted through an Encryption/Decryption Service System, but does not allow this service provider access to the Decryption Key or allow for the storage of decrypted data. Furthermore, the privileges of the Encryption/Decryption as Service provider includes management of the key required for the encryption/decryption of user data, but not the storage of decrypted or encrypted user data. In this new business model, user data in the Storage Service System is all saved



encrypted.Without the decryption key, there is no way for the service provider to access the user data. Within the Encryption/Decryption Service System there is no stored user data, thus eliminating the possibility that user data might be improperly disclosed.

After establishing “Separate Encryption/Decryption Services” in cloud computing environments, users of cloud computing services (e.g., CRM, ERP, etc.) will use the services of at least two cloud computing service providers, so agreements between these service providers are required to establish a model for cooperation and division of responsibilities in providing a common service to clients. This study provides a draft of a multi-signatory Service Level Agreement (SLA) in which the signatories can include cloud computing rental users, application service providers, encryption/decryption service providers, storage service providers, etc., with content including the rights and obligations between operators and also includes data security policies between each operator and clients.

The concept of this is consistent with division of management authority to reduce operational risk, thus avoiding the risk of wrongful disclosure of user data.

V. REFERENCES

[1] R. Buyya, C. ShinYeo, J. Broberg, and I. Brandic, “Cloud computing and emerging it platforms: Vision, hype, and reality for delivering computing as the 5th utility,” Future Generation Comput. Syst., vol. 25, pp.599–616, 2009.

[2] K. Barlow and J. Lane, “Like technology from an advanced alien culture: Google apps for education at ASU,” in Proc. ACM SIGUCCS User Services Conf., Orlando, FL, 2007.

[3] B. Barbara, “Salesforce.com: Raising the level of networking,” Inf.Today, vol. 27, pp. 45–45, 2010.

[4] J. Bell, Hosting EnterpriseData in the Cloud—Part 9: InvestmentValue Zetta, Tech. Rep., 2010.

[5] A. Ross, “Technical perspective: A chilly sense of security,” Commun.ACM, vol. 52, pp. 90–90, 2009.

[6] D. E. Bell and L. J. LaPadula, Secure Computer Systems: Unified Exposition and Multics Interpretation The MITRE Corporation, Tech.Rep., 1976.

[7] K. J. Biba, Integrity Considerations for Secure Computer Sytems The MITRE Corporation, Tech. Rep., 1977.

[8] H. Harney, A. Colgrove, and P. D. McDaniel, “Principles of policy in secure groups,” in Proc. NDSS, San Diego, CA, 2001.

[9] P. D. McDaniel and A. Prakash, “Methods and limitations of security policy reconciliation,” in Proc. IEEE Symp. Security and Privacy,Berkeley, CA, 2002.

[10] T. Yu and M. Winslett, “A unified scheme for resource protection in automated trust negotiation,” in Proc. IEEE Symp. Security and Privacy, Berkeley, CA, 2003.

[11] J. Li, N. Li, and W. H. Winsborough, “Automated trust negotiation using cryptographic credentials,” in Proc. ACM Conf. Computer and Communications Security (CCS), Alexandria, VA, 2005.

[12] V. Goyal, O. Pandey, A. Sahai, and B.Waters, “Attibute-based encryption for fine-grained access control of encrypted data,” in Proc. ACM Conf. Computer and Communications Security (ACM CCS), Alexandria,VA, 2006.

[13] S. Yu, C. Wang, K. Ren, and W. Lou, “Achiving secure, scalable, and fine-grained data access control in cloud computing,” in Proc. IEEE INFOCOM 2010, 2010, pp. 534–542.

[14] J. Bethencourt, A. Sahai, and B. Waters, “Ciphertext-policy attributebased encryption,” in Proc. IEEE Symp. Security and Privacy, Oakland,CA, 2007.

The Author, Angel Anna Prathiba.E is a final year student doing Master of Engineering in Computer Science at Angel College of Engineering and Technology, Tirupur and received Bachelor of Technology degree in Information Technology from Angel College of Engineering and Technology, Tirupur in the year 2011. Her area of interest is Cloud Computing. She has published paper in International Journal. She has also presented over 3 papers in National Conferences.

The Author, Saravanan.B has one year experience in Industry. He has presented two papers in International Conferences. He attended three workshops and one seminar. He had published a paper in International Journal. His area of interest is Image processing, Operating Systems, Cloud computing and Object Oriented Programming. Currently he is working as Assistant Professor in Angel College of Engineering and Technology,Tirupur.

Anuja A. Khot and Ravindra G. Patil 72


Hydraulic Pressure Test on Insulator Using PLC

Anuja A. Khot and Ravindra G. Patil Abstract: This paper describes the use of advanced Programmable Logic Controller (PLC) over relay controller for disc insulator testing under certain pressure using Hydraulic pressure testing machine. The PLC used in this paper is micro PLC of the MITSUBSHI Company’s FX3U. The inputs and outputs of PLC differ from one to another. PLC logic control system is the advanced technology. The speed of work done in case of PLC logic is more when compared to relay logic. Circuit connection can be changed simply by changing the program as per the requirement of the user with respect to number of inputs and outputs of PLC. The space occupied by the relay logic system is more when compared to PLC logic system because of circuit connections. Hence, the space used for the system installation can be reduced in case of PLC. The study of basic principles of relay and PLC logic is done, hence got inferred that PLC will decrease the complexity compared to relay logic and PLC appears to be an excellent solution for many different problems which will improve the status of production.

Keywords: Hydraulic Pressure Test Machine, Ladder Logic Diagram (LLD), Programmable Logic Controller (PLC), Relay.

I. INTRODUCTION Industry has begun to recognize the need for quality

improvement and increase in productivity in the sixties and seventies. Flexibility also became a major concern (ability to change a process quickly became very important in order to satisfy consumer needs). Try to imagine automated industrial production line in the sixties and seventies. There was always a huge electrical board for system controls, and not infrequently it covered an entire wall. Within this board there were a great number of interconnected electromechanical relays to make the whole system work. By word "connected" it was understood that electrician had to connect all relays manually using wires. An engineer would design logic for a system, and it would receive a schematic outline of logic that had to implement with relays.

Anuja A. Khot is a M.Tech (PES) student, EEED, BEC, Bagalkot and Ravindra G. Patil is working as Associate Professor EEED, BEC, Bagalkot, Emails: [email protected], [email protected]

These relay schemas often contained hundreds of relays. The plan that was given was called "ladder schematic". Ladder displayed all switches, sensors, motors, valves, relays, etc. found in the system. One of the problems with this type of control was that it was based on mechanical relays. Mechanical instruments were usually the weakest connection in the system due to their moveable parts that could wear out. If one relay stopped working, it would have to examine an entire system and it would be out until a cause of the problem was found and corrected. The other problem with this type of control was in the system's break period when a system had to be turned off, so connections could be made on the electrical board. If a firm decided to change the order of operations or to make even a small change, it would turn out to be a major expense and a loss of production time until a system was functional again.

The PLC acts as a total replacement for hard wired relay

logic with an effective reduction in wiring and panel size with increase in flexibility and reliability. Since their development in early 1970’s, Programmable Logic Controllers (PLC) have evolved to challenge not only relays but other control devices such as, stepping switches, drum sequencers etc. The simplicity of reprogramming a PLC, when modifications were required in the existing control, as compared to the cumbersome process of rewiring a hardwired control panel has been widely accepted. The comparatively small size of the PLC accompanied with less hardwired interlocks reduces the panel size considerably. The use of solid state devices make PLC very reliable as compared to the electromechanical devices used in hardwired control panels.

It is experienced that, in a system using PLC’s, about 90%

of the faults that occur, are due to causes external to PLC. Malfunctioning of limit switches, opening of wires due to loose connections, wire breakage etc. contributes to major causes of breakdowns. In a system using PLC’s, apart from carrying out the logical decisions, the troubleshooting is considerably simplified.

The process status, timer values, counter values, process

parameters like temperature, pressure etc. can be displayed on an alphanumeric display of a seven segment display. The fault code for a corresponding fault can be displayed to pinpoint the fault, resulting in fast diagnosis. Thus the duration of machine stoppage and down time are considerably reduced due to efficient man-machine communication.



II. HYDRAULIC PRESSURE TEST MACHINE PROFILE

A. Machine Profile The hydraulic press is one of the oldest of the basic machine tools. They present a price and weight benefit over the equivalent electro-mechanical systems needed to generate the same force or torque. Hydraulically actuated systems are used in a wide range of industrial applications, and continue to be a popular and relatively inexpensive power source and modern hydraulic presses offer good performance and reliability. The machine used in this paper is Hydraulic Pressure testing machine. It is used to test the disc insulators of different sizes and the machine is capable to generate up to 300bars of pressure. The press has two hydraulic servomechanisms: a hydraulic cylinder, driven by a servo-solenoid flow control valve, to support the punch tool; a hydraulic cylinder, where the chamber pressure is controlled by a servo-solenoid pressure control valve, to support the operations of loading and unloading of the press blank holder [1]. Disc insulators of various rating of 70KN to 420KN can be tested here at specific pressure to check mechanical strength. Machine is working with Hydraulic Pressure system i.e all the operations are hydraulically operated as shown in fig.1 and the hydraulic circuit for Hydraulic Pressure Test Machine as show in fig.2.

B. Existing control system 1. Machine is controlled by electrical panel 2. Relay logic has been used for electrical system 3. 415V, 3 phase from main panel and stepped down to

230V, 1 phase to control panel 4. Here disc insulators are tested under 200 Kg/cm2 of

pressure.

C. Working Principle

The hydraulic press depends on Pascal's principle: the pressure throughout a closed system is constant. At one end of the system is a piston with a small cross-sectional area driven by a lever to increase the force. Small-diameter tubing leads to the other end of the system. A fluid, such as oil, is displaced when either piston is pushed inward. The small piston, for a given distance of movement, displaces a smaller amount of volume than the large piston, which is proportional to the ratio of areas of the heads of the pistons. Therefore, the small piston must be moved a large distance to get the large piston to move significantly. The distance the large piston will move is the distance that the small piston is moved divided by the ratio of the areas of the heads of the pistons.

Fig. 1: Hydraulic Pressure testing machine

Fig. 2: Hydraulic circuit for Hydraulic Pressure Test Machine

III. SWITCHGEAR ELEMENTS

A. Relays The relays are devices that monitor various parameters in

various ways. The types of relays can be broadly classified as electromechanical relays and static relays (analog and digital). The electromechanical relays have been dominating the electrical protection field until the use of silicon semiconductor devices became more common. Because a relay is able to control an output circuit of higher power than the input circuit, it can be considered, in a broad sense, to be a form of an electrical amplifier.

Operating Principle: When a current flows through the coil, the resulting magnetic field attracts an armature that is mechanically linked to a moving contact. The movement either makes or breaks a connection with a fixed contact. When the current to the coil is switched off, the armature is returned by a force approximately half as strong as the magnetic force to its relaxed position. Usually this is a spring, but gravity is also used commonly in industrial motor starters. Most relays are manufactured to operate quickly. In a low



voltage application, this is to reduce noise. In a high voltage or high current application, this is to reduce arcing.

B. Contactor A contactor is an electrical device used for switching a power circuit. A contactor is activated by a control input which is a lower voltage / current than that which the contactor is switching. Contactors come in many forms with varying capacities and features. Unlike a circuit breaker a contactor is not intended to interrupt a short circuit current. Operating Principle: When current passes through the electromagnet, a magnetic field is produced which attracts ferrous objects, in this case the moving core of the contactor is attracted to the stationary core. Since there is an air gap initially, the electromagnet coil draws more current initially until the cores meet and reduce the gap, increasing the inductive impedance of the circuit. For contactors energized with alternating current, a small part of the core is surrounded with a shading coil, which slightly delays the magnetic flux in the core. The effect is to average out the alternating pull of the magnetic field and so prevent the core from buzzing at twice line frequency.

C. Circuit Breaker

A circuit breaker is an automatically-operated electrical switch designed to protect an electrical circuit from damage caused by overload or short circuit. Unlike a fuse, which operates once and then has to be replaced, a circuit breaker can be reset (either manually or automatically) to resume normal operation. Circuit breakers are made in varying sizes, from small devices that protect an individual household appliance up to large switchgear designed to protect high voltage circuits feeding an entire city.

Operating Principle: Magnetic circuit breakers are implemented using a solenoid (electromagnet) that’s pulling force increases with the current. The circuit breaker's contacts are held closed by a latch and, as the current in the solenoid increases beyond the rating of the circuit breaker, the solenoid's pull releases the latch which then allows the contacts to open by spring action. During an overload, the solenoid pulls the core through the fluid to close the magnetic circuit, which then provides sufficient force to release the latch. The delay permits brief current surges beyond normal running current for motor starting, energizing equipment, etc. Short circuit currents provide sufficient solenoid force to release the latch regardless of core position thus bypassing the delay feature. Ambient temperature affects the time delay but does not affect the current rating of a magnetic breaker.

IV. PROGRAMMABLE LOGIC CONTROLLER (PLC)

A. Introduction A Programmable Logic Controller (PLC) preferred in this paper is of the MITSUBISHI Company’s FX3U and it is microprocessor-based control system that can be programmed

to sense, activate and control industrial equipment and therefore incorporates a number of input/output terminals for interfacing to an industrial process as shown in the fig. 3. A control program stored in the PLC memory determines the relationship between the inputs and outputs of the PLC [2].

Fig.3. Mitsubishi FX3U PLC with the expansion block

B. History In 1960’s PLC were first developed to replace relays and relay control system. Relays, while very useful in some applications, also have some problems. The main problems are the fact that they are mechanically. This means that they wear down and have to be replaced every so often. Also relays take up a quite a bit of space. These along with other considerations led to the development of PLC’s. More improvement of PLC’s occurred in the 70’s.

In 1973 the ability to communicate between PLC’s was added. This also made it possible to have the controlling circuit quite a ways away from the machines it was controlling. However at this time the lack of standardization in PLC’s created other problems. This was improved in 1980’s. The size of PLC’s was also reduced then, thus using space even more efficiently. The 90’s increased the collection of ways in which a PLC could be programmed (block diagram, instruction list, C etc) [4].

C. Block Diagram

The block diagram of the PLC is as shown in the fig. 4. The processor is a solid state device designed to replace relays, timers, counters etc. The necessary voltage and current requirements for the internal working of the PLC is generated by the power supply.

The field elements dare interfaced to the input or the output sections. Typical input elements are push buttons, limit switches, proximity switches, relay contacts, selector switches, thumbwheels etc. Typical output elements are solenoid valves, relay coils, indicator lights, LED display etc. These field elements are selected by the end user. The necessary power supply for the input and output elements is built external to the PLC.



Fig.4. Block diagram of Programmable Logic Controller

The PLC power supply is designed and rated only to operate the internal structure and dot the field elements. The processor is programmed in a similar way as the hardwired control panels, known as ladder diagrams.

The programming device is the device where, by the programmer or operator can enter or edit program instructions or data. The programmer can be handheld unit that is a personal computer, or an industrial computer-programming terminal.

V. LADDER LOGIC DIAGRAM (LLD)

A. Ladder Logic The main modeling language of the PLC is based on the so-called Ladder Logic Diagram (LLD). This graphical symbolic language is widely used in the design of PLC for industrial automation. LLD models the actual combination of relay contacts. The term “ladder” derives from the appearance of the diagram [3]. The ladder diagram is to be read left to right, then top to bottom. A relay contact or a step in LLD is either (a) normally closed (NC), represented symbol by -| / |- or (b) normally open (NO), represented by the symbol -| |-. They are controlled by logical inputs and state variables which are represented by the labels (e.g. alarm, stop). When an input triggers the step, the corresponding relay state changes to the opposite state, that is, the NC step is turned ON while the NO step is turned OFF. A PLC ladder program consists of N/O contacts are and N/C. The relays coils are represented by the symbol - ( )- [5]. These symbols are associated with the determined OP (operation) codes which instruct the CPU to take specific action while executing the ladder. The ladder is the combination of the above symbols interconnected with each other in a sequence and in a predetermined syntax. One branch of such a ladder is known as a “RUNG”.

B. Ladder Structure The ladder program is arranged in a set of ladder rungs. The structure of each ladder rung allows to program.

Maximum 9 contacts and one output coil in series (columns)

Maximum 6 contacts / coils in parallel ( rows) The rungs are numbered serially by the programming

devices and are executed sequentially. Each rung is identified

by a unique number from 000 to 999. Insertion / deletion of rungs results in renumbering of all the succeeding rungs i.e. if rung number 0,1,2,3 are existing in the ladder and if rung number 1 is deleted then rung number 2 will become rung number 1, rung number 3 will become rung number 2 whereas rung number 0 will remain as it is. Similarly if a new rung is inserted in between two rungs the addresses of the succeeding rungs to the new rung is shifted by 1.

C. Ladder Execution The PLC performs its task in a definite cycle. This is called

as the PLC Scan the definite cycle of PLC scan is as shown in fig. 5. PLC Scan means that contribute the input processing, program processing and output processing together.

Fig.5. PLC scan process

When the PLC is performing these scan it is said to be in the RUN mode, otherwise it is said to be in STOP mode. The PLC reads the status of all the inputs and updates their images in the memory. This is called as input scan. Depending upon the status of inputs read in input scan the PLC solves the logic written by the user in User Memory Cassette (UMC). This is called as logic scan. The status of the outputs generated in the logic scan is transferred on to the output module in the output scan.

One input scan followed by one logic scan followed by one

output scan together contributes to one PLC scan. As soon as PLC processor completes a scan it immediately starts another scan forming continuous loops.

In the logic scan the rungs programmed in UMC are

executed in the sequence in which they are entered. It is important to note that the execution of complex ladder rung having multiple coils will follow the thumb rules as below.

The PLC will evaluate the status of all the coils in a rung sequentially from top to bottom. This will be done considering all the different paths controlling that coil. Each path will be traversed from left to the right only. No contact or link will conduct from right to left.

The status of those node points required to evaluate the status of the first coil considering all its paths are decided. The node points are those points where one or more parallel paths being or end. Using this status of node points the status of the first coil is evaluated.

In evaluating the status of subsequent coils and nodes within that rung, the status of previously evaluated coils and nodes are used again, without reevaluating them.



VI. EXPERIMENTAL SETUP

A. Electrical Wring Diagram of Hydraulic Pressure Test Machine

Fig.6. Electrical wiring diagram of Hydraulic Pressure Test Machine

B. Working Sequence of Hydraulic Test Machine Initial Condition:

Main paper should be switched ON. Hydraulic motor should be switched ON. Clam should be in UP position.

Auto mode and Manual mode: Auto ready should be on. Any of the carriage moment (forward or

backward) should move to the center. Once carriage comes to the center cylinder

should be declamp and should start coming down.

Once seal get fixed to the insulator a pressure of 200 Kg/cm2 is created.

When the pressure attains 200 Kg/cm2 and after a permitted time cylinder moves upward and stops.

The cylinder touches the clamp top limit cylinder will stop and auto cycle will be completed.

The flow chart of the working sequence of the Hydraulic Pressure Test Machine is as shown in the fig. 7.

. Fig.7. Flow chart of the working sequence of Hydraulic Pressure Test

Machine

C. Advantages of PLC over Relay Electrical system including motors, switch gear

elements, cables, transformers etc. were more than 20 years old. So the system will be giving frequent problems. Old system has balanced with PLC, switch gear elements etc. which increase the life of machine

Circuit alteration in the new PLC system becomes easier by changing the PLC program, the circuit can be altered. Contrary, to this relay logic it is very difficult to change the circuit because it requires lots of hardware alterations which is the time consuming and prone to errors.

Ideal planner size was very big because lot of relays and contactors were required for interlocking circuits. Now, the panel size is reduced to 50% because very few relays are required for field input,

Move the bed in Forward/ Reverse direction

Move the clamp down

Move the clamp UP

Stop

Machine control on

Clamp should be Upside

Place the insulator

Apply the pressure for given time

Move the bed in reverse /forward

direction

Start



output. Interlocking circuit can be written through the PLC program.

The new PLC system will reduce the breakdown time and increase the availability of time which will increase the production statistics.

VII. CONCLUSION Replacing the relay control system with PLC makes more efficient and effective control system. The very nature of PLC design as well as its application, offers numerous benefits to industrial users to control and troubleshoot the faults. Testing of the disc insulators under certain pressure using PLC logic is possible, which decreases the complexity in operation compared to relay logic. So, PLC appears to be an excellent solution for many different problems which improves the status of production.

REFERENCES

[1] J. A. Ferreira, P. Sun and J. J. Grácio, “Design and control of a hydraulic press”, Proceedings of the 2006 IEEE Conference on Computer Aided Control Systems Design Munich, Germany, October 4-6, 2006.

[2] Mitsubishi FX3U MELSEC PLC manual. [3] W. Bolton “Ladder and Functional Block Programming”, the

first edition of the book was published in 1996. [4] Madhuchandan Mitra, Samarijit Sen Gupta, “Programming

Logic Controllers and Industrial Automation- An Introduction”. June 17, 2007.

[5] Zulfakar Aspar and Mohamed Khalil-Hani, “Modeling of a Ladder Logic Processor for High Performance Programmable Logic Controller”, 2009. Third Asia International Conference on Modeling & Simulation.

Anuja A. Khot was born in Sangli, Maharashtra, India on 07 January 1990. She obtained B.E (Electrical and Electronics) from Visvesvaraya Technological University (Autonomous), Karnataka., India. She is currently perusing M.Tech Degree in Power and Energy Systems in Electrical and Electronics Engineering, Basaveshwar Engineering College, Bagalkot, India.

Ravindra G. Patil was born in Hampiholi of Ramdurg Tal, Karnataka, India on 1st April 1961. He obtained B.E (Electrical and Electronics) from Karnataka University, Dharwad, Karnataka India in 1984 and M.E from Jadhavpur University, Kolkata, West Bengal, India in 1993. His areas of interest include Power Electronics, Machines and Drives. Presently he is working as Associate Professor in the Department of Electrical & Electronics

Engineering at Basaveshwar Engineering College, Bagalkot, India.

Rutika J. Upadhyay, Ashish B. Makwana and Aslam Durvesh 78


BER Comparison of Linear and Non linear MIMO Detectors in AWGN, Rician Fading and

Rayleigh Fading channel

Rutika J. Upadhyay, Ashish B. Makwana and Aslam Durvesh

Abstract—With the integration of Internet and multimedia applications in next generation wireless communications, the demand for wide-band high data rate communication services is growing. As the available radio spectrum is limited, higher data rates can be achieved only by designing more efficient signaling techniques. Multiple Input Multiple Output (MIMO) technology is one of the most promising wireless technologies that can efficiently boost the data transmission rate, improve system coverage, and enhance link reliability. By employing multiple antennas at transmitter and receiver sides, MIMO techniques enable a new dimension– the spatial dimension – that can be utilized in different ways to combat the impairments of wireless channels. While using MIMO techniques, there is intersymbol interference present between the symbols. Detection is a well known technique for combating intersymbol interference. This paper will focus on linear and Non linear Detection techniques in the AWGN (Additive White Gaussian Noise) channel, Rician Fading channel and the Rayleigh fading channel. This paper discusses different types of Detectors like Zero Forcing (ZF), Minimum Mean Square Error (MMSE), Maximum likelihood (ML) and Successive interference cancellation (SIC) and concludes that ML has better performance over other all. A simulation results shows in which fading channel getting better performance in terms of BER v/s SNR. Keywords— AWGN channel, Rayleigh fading channel , BER, SNR, Intersymbol Interference (ISI), Multiple Input Multiple Output (MIMO), Minimum Mean Square Error (MMSE) and Zero Forcing (ZF).

I) INTRODUCTION In broad sense, the term communications refers to the

sending, receiving and processing of information by electronic means. It is the technique of transmitting a message, from one point to another, knowing how much information, if any, is likely to be lost in the process [1-2]. Hence, the term “communication” is covered all forms of distance communications including radio, telegraphy, television, telephony, data communication and computer networking. Communications started with wire telegraphy in the eighteen forties, developing with telephony some decades later and radio at the beginning of this century. Rutika J. Upadhyay is a PG Student, Parul Institute of Engineering and Technology, GTU, Limba., Ashish B. Makwana is working as a Assistant Professor, V.V.P. college, Rajkot and Aslam Durvesh is working as Assistant professor, EC department, Parul Institute of Engineering and Technology, Limba. Emails: [email protected], [email protected], [email protected]

More recently, the use of satellites and fiber optics has made communications even more widespread, with an increasing emphasis on computer and other data communications [1],[3]. A modern communications system is first concerned with the sorting, processing and sometimes storing of information before its transmission. The actual transmission then follows, with further processing and filtering of noise. Finally it come reception, which may include processing steps such as decoding, storage and interpretation [4]. Demands for capacity in wireless Communications, driven by Cellular mobile, Internet and Multimedia services have been rapidly increasing worldwide. On the other hand available radio spectrum is limited and the Communication capacity needs cannot be met without a significant increase in communication spectral efficiency. Advances in coding, such as Turbo codes, Low density parity check codes and Space time codes [1],[5] made it feasible to approach the Shannon capacity limit in system with a single antenna link. Significant further advances in spectral efficiency are available though increasing the number of antennas at both transmitter and the receiver which is as MIMO technology. It is one of several forms of smart antenna technology. In fact, the MIMO concept is much more general and embraces many other scenarios such as wire line digital subscriber line (DSL) systems [6] and single-antenna frequency-selective channels [2-3]. MIMO technology has attracted attention in wireless communications, because it offers significant increases in data throughput and link range without additional bandwidth or transmit power. It is achieved by higher spectral efficiency (more bits per second per hertz of bandwidth) and link reliability or diversity (reduced fading). Because of these properties, MIMO is an important part of modern wireless communication standards such as IEEE 802.11n (Wifi), 4G, 3GPP Long Term Evolution, WiMAX and HSPA+.

II) THE MIMO SYSTEM MODEL

Spatial Multiplexing (SM) has been utilized in MIMO systems to provide higher transmission rate without allocating additional bandwidth or increasing the transmit power [7]. The VBLAST was the practical implementation approach of spatial multiplexing technique. Spatial multiplexing involves deploying multiple antennas at both transmitter and receiver ends as shown in Figure 1. Input data streams can be divided into different independent sub streams and then transmitted simultaneously via sufficiently-



separated antennas (λ / 2 or more, to obtain highly uncorrelated and independent signal). It has been shown in [8] that utilizing spatial multiplexing schemes under certain conditions and assumptions, can linearly increases capacity with relation to the minimum of the number of transmit antennas and the number of receive antennas. In this system received signal is given by

푦 = 퐻푥 + 푛

Where, 퐻 = ℎ ℎℎ ℎ

Figure 1 2x2 MIMO Channel

III. MIMO CHANNEL MODEL A. AWGN Channel For an AWGN (Additive White Gaussian Noise) channel,

‘θ’ is a constant and is equivalent to the AoA of the LoS propagation path. In this case, we use the so-called narrowband data model to model the received signal at the antenna arrays. The narrowband data model assumes that the envelope of the signal wave front propagating across the antenna array essentially remains constant. This model is valid when the signals or the antennas have a bandwidth that is much smaller than the carrier frequency fc. Under the above assumptions, the vector from of the baseband complex equivalent received signal can be written as,

푌(푛) = 푉(휃)푠(푛) + 퐺(푛) Where, V(θ) is the array manifold vector and G(n) is

AWGN with zero mean and two-sided power spectral density given by No/2. This is simply a plane-wave model.

B. Rayleigh Fading Channel

In wireless telecommunications, multipath is the propagation phenomenon that results in radio signals reaching the receiving antenna by two or more paths. Causes of multipath include atmospheric ducting, ionosphere reflection and refraction, and reflection from water bodies and terrestrial objects such as mountains and buildings.

The effects of multipath include constructive and destructive interference, and phase shifting of the signal. This causes Rayleigh fading. The standard statistical model of this gives a distribution known as the Rayleigh distribution. Rayleigh fading is a term used when there is no direct component, and all signals reaching the receiver are reflected. Mathematically, the multipath Rayleigh fading wireless channels modeled by the channel impulse response (CIR)

ℎ(푡) = ∝ 휕(푡 − 휏 )

Where, 퐿푝 is the number of channel paths, ∝ and 휏 are the complex value and delay of path l, respectively. The paths are assumed to be statistically independent, with normalized average power.

C. Rician Channel A Rician model is obtained in a system with LOS propagation and scattering. The model is characterized by the Rician factor, denoted by K and defined as the ratio of the line of sight and the scatter power components. The pdf for a Rician random variable x is given by

푝(푥) = 2푥(1 + 푘)푒 ( ) 퐼 (2푥 푘(푘 + 1)),푥 ≥ 0 Where

퐾 = 퐷

2휎

And D2 and 2σr2 are the powers of the LoS and scattered

components, respectively. The powers are normalized such that D2 + 2σr

2 = 1 The channel matrix for a Rician MIMO model can be

decomposed as, 퐻 = 퐷퐻 + √2휎 퐻

Where, HLOS is the channel matrix for the LoS propagation with no scattering and HRAYL is the channel matrix for the case with scattering only.

III) MIMO DETECTORS

A. Zero Forcing(ZF) A zero-forcing equalizer uses an inverse filter to compensate for the channel response function. In other words, at the output of the equalizer, it has an overall response function equal to one for the symbol that is being detected and an overall zero response for other symbols. If possible, this results in the removal of the interference from all other symbols in the absence of the noise. Zero forcing is a linear equalization method that does not consider the effects of noise. In fact, the noise may be enhanced in the process of eliminating the interference[9]. To solve for 푥 in equation (1), we know that we need to find a matrix WZF which satisfies WZF H =1. The Zero forcing linear detectors for meeting this constraint is given by:

푊 = (퐻 퐻) 퐻 In other words, it inverts the effect of channel as

푋 = 푊 + 푦 = 푥 + (퐻 퐻) 푛

B. MINIMUM MEAN SQUARE ERROR (MMSE)

If the mean square error between the transmitted symbols and the outputs of the detected symbols, or equivalently, the received SNR is taken as the performance criteria, the MMSE detector is the optimal detection that seeks to balance between cancelation of the interference and reduction of noise enhancement. The 푊 that maximizes the SNR and minimizes the mean square error which is given by:

퐸[(푥 −푊 푦) (푥 −푊 푦)] To solve for 푥 in equation (1), we know that we need to find a matrix 푊 . The MMSE linear detector for meeting this constraint is given by:

푊 = (퐻 퐻 + 휎 퐼) 퐻

(1)



When comparing to the equation in Zero Forcing equalizer, apart from the σ2

n term both the equations are comparable. In fact, when the noise term is zero, the MMSE equalizer reduces to Zero Forcing equalizer at high SNR [9].

C. Successive Interference Cancelation(SIC) When signals are detected successively, the outputs of previous detectors can be used to aid the operations of next ones which leads to the decision directed detection algorithms including SIC, Parallel Interference cancelation (PIC), and multistage detection. ZF SIC with optimal ordering, and MMSE-SIC with equal power allocation approaches the capacity of the i.i.d. Rayleigh fading channel [10]. After the first bit is detected by the decorrelator the result is used to cancel the interference from the received signal vector assuming the decision of the first stream is correct [11]. For the ZF-SIC, since the interference is already nulled, the significance of SIC is to reduce the noise amplification by the nulling vector. The nulling vector w1 filters the received vector y as:

푥 = 푠푔푛[푤 푦]

Assuming 푥 = 푥 , by substituting x1 from the received vector y , we obtain a modified received vector y1 given by:

푦 = 푦 − 푥 (퐻)

Where (H)1 denotes the first column of H. We then repeat this operation until all MT bits are detected. Once the first stream is detected, the first row of H is useless and will be eliminated. Therefore after the first cancelation the nulling vector for the second stream need only Mr -1 dimensions. For the MMSE detector the significance of SIC is not only to minimize the amplification of noise but also the cancelation of the interference from other antennas. In addition, there is another opportunity to improve the performance by optimal ordering the SIC process. The ordering is based on the norm of the nulling vector. At each stage of cancelation, instead of randomly selecting the stream to detect, we choose the nulling vector that has the smallest norm to detect the corresponding data stream. This scheme is proved to be the globally optimum ordering more complex.

D. Maximum Likelihood (ML)

The Linear detection method and SIC detection methods require much lower complexity than the optimal ML detection, but their performance is significantly inferior to the ML detection [24]. Maximum likelihood detection calculates the Euclidean distance between received signal vector and the product of all possible transmitted signal vectors with the given channel H, and finds the one with minimum distance. Let C and NT denote a set of signal constellation symbol points and a number of transmit antennas, respectively. Then, ML detection determines the estimate transmitted signal vector x as:

푥 = 푎푟푔 min∈

‖푦 −퐻푥‖

Where:‖푦 −퐻푥‖ corresponds to the ML metric. The ML method achieves the optimal performance as the maximum a posterior detection when all the transmitted vectors are likely. However, its complexity increases exponentially as modulation order N and/or the number of transmit antennas increases [4], the requires number of ML matrix calculation is |퐶| , that is the complexity of metric calculation exponentially increases with the number of antennas. The ML receiver performs optimum vector decoding and is optimal in the sense of minimizing the error probability. ML receiver is a method that compares the received signals with all possible transmitted signal vectors which is modified by channel matrix H and estimates transmit symbol vector 푐̂ according to the Maximum Likelihood principle, which is shown as:

푐̂ = min arg⟦푦 − 푐̀퐻⟧

where F is the Frobenius norm. Expanding the cost function using Frobenius norm given by

푐̂ = min arg 푇푟⌈(푦 − 푐̀퐻) ∗ (푦 − 푐̀퐻)⌉

푐̂ = min arg 푇푟 푦 .푦 +퐻 . 푐′ . 푐′.퐻 −퐻 . 푐′ .푦

− 푦 . 푐′.퐻

Considering rH.r is independent of the transmitted codeword so can be rewritten as

푐̂ = min arg⌈푇푟⌈(푦 − 푐̀퐻) ∗ (푦 − 푐̀퐻)⌉− 2.푅푒푎푙(푇푟[퐻 . 푐̀ .푦])⌉

where .H is a Hermition operator. Although ML detection offers optimal error performance, it suffers from complexity issues.

IV) SIMULATION RESULTS

A. Simulation Setup TABLE I

SIMULATION PARAMETERS

NTx 2

NRx 2

Symbols 1000000(106)

Noise Gaussian noise

Channel AWGN channel, Rician fading channel and Rayleigh flat fading channel



SNR 0 to 25

Modulation BPSK

Detector ZF, MMSE, ZF-SIC, MMSE-SIC, ZF-OSIC, MMSE-OSIC,ML

B. RESULTS

For ZF detection technique, In Figure.3 BER of 10 is achieved for the SNR value of 11 dB at AWGN channel, whereas the same BER is achieved for the SNR value of 14 dB at Rayleigh channel in Figure.2. For MMSE detection technique, In Figure.3 BER of 10 is achieved for the SNR value of 8.5 dB at AWGN channel, whereas the same BER is achieved for the SNR value of 11 dB at Rayleigh channel in Figure.2. For ZF-SIC detection technique, In Figure.3 BER of 10 is achieved for the SNR value of 9 dB at AWGN channel, whereas the same BER is achieved for the SNR value of 11.5 dB at Rayleigh channel in Figure.2.

Figure 2 MIMO All EQUALIZERS IN RAYLEIGH

CHANNEL

Figure 3 MIMO All EQUALIZERS IN AWGN Channel

For ZF-OSIC detection technique, In Figure.3 BER of 10 is achieved for the SNR value of 7 dB at AWGN

channel, whereas the same BER is achieved for the SNR value of 10 dB at Rayleigh channel in Figure.2.

For MMSE-OSIC detection technique, In Figure.3 BER of 10 is achieved for the SNR value of 4 dB at AWGN channel, whereas the same BER is achieved for the SNR value of 6.5 dB at Rayleigh channel in Figure.2.

For ML detection technique, In Figure.3 BER of 10 is achieved for the SNR value of 3.6 dB at AWGN channel, whereas the same BER is achieved for the SNR value of 6 dB at Rayleigh channel in Figure.2.

Figure 4 MIMO All EQUALIZERS IN Rician fading Channel (K=12db)


For RICIAN FADING channel at ZF detection technique, In Figure.4 BER of 10 is achieved for the SNR value of 23 dB at K=12, whereas the same BER is achieved for the SNR value of 16.5 dB at K=4 in Figure.5.and BER is achieved for the SNR value of 20 dB at K=8 in Figure.6.

For MMSE detection technique, In Figure.4 BER of 10 is achieved for the SNR value of 20 dB at K=12, whereas the same BER is achieved for the SNR value of 14.2 dB at K=4 in Figure.5.and BER is achieved for the SNR value of 16.2 dB at K=8 in Figure.6.

0 5 10 15 20 2510

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10-4

10-3

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Average Eb/No,dB

Bit

Erro

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BER for BPSK modulation with 2x2 MIMO and all equalizer (Rayleigh channel)

zfmmsemlzf-sicmmse-siczf-osicmmse-osic

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BER for BPSK modulation with 2x2 MIMO and all equalizer (AWGN channel)


0 5 10 15 20 2510

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BER for BPSK modulation with 2x2 MIMO and all equalizer for K=12 (Rician channel)


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Err

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For ZF-SIC detection technique, In Figure.4 BER of 10 is achieved for the SNR value of 22 dB at K=12, whereas the same BER is achieved for the SNR value of 15 dB at K=4 in Figure.5.and BER is achieved for the SNR value of 19 dB at K=8 in Figure.6.


For MMSE-SIC detection technique, In Figure.4 BER of 10 is achieved for the SNR value of 19 dB at K=12, whereas the same BER is achieved for the SNR value of 14 dB at K=4 in Figure.5.and BER is achieved for the SNR value of 16 dB at K=8 in Figure.6.

For ZF-OSIC detection technique, In Figure.4 BER of 10 is achieved for the SNR value of 21 dB at K=12, whereas the same BER is achieved for the SNR value of 13.5 dB at K=4 in Figure.5.and BER is achieved for the SNR value of 18.5 dB at K=8 in Figure.6.

For MMSE-OSIC detection technique, In Figure.4 BER of 10 is achieved for the SNR value of 16 dB at K=12, whereas the same BER is achieved for the SNR value of 8.5 dB at K=4 in Figure.5.and BER is achieved for the SNR value of 11.2 dB at K=8 in Figure.6.

For ML detection technique, In Figure.4 BER of 10 is achieved for the SNR value of 12 dB at K=12, whereas the same BER is achieved for the SNR value of 7 dB at K=4 in Figure.5.and BER is achieved for the SNR value of 9 dB at K=8 in Figure.6.

From the simulation results it is observed that the

performances of the all receivers in AWGN channel are all most 3dB improved over Rayleigh fading channel. Compared to Rician fading channel for all fading factor of K, all receivers in AWGN channel are better. When comparing all receivers performance at each channel the performance of ML detector is best than all other detector and comparing this detectors performance in ascending order it’s goes from most efficient ML detector to some what moderated MMSE-OSIC than ZF-OSIC, MMSE-SIC, ZF-SIC, MMSE and ZF detector. ML uses the Euclidean distance method to detect the received signal where as MMSE detector removes effect of channel and noise by minimizing mean square error

between transmitted and received symbols whereas ZF detectors removes only effect of channel.

Performance of all detect is better in AWGN channel due

to AWGN is a channel model in which the only impairment to communication is a linear addition of wideband or white noise with a constant spectral density (expressed as watts per hertz of bandwidth) and a Gaussian distribution of amplitude. The model does not account for fading, frequency selectivity, interference, nonlinearity or dispersion. However, it produces simple and tractable mathematical models which are useful for gaining insight into the underlying behaviour of a system before these other phenomena are considered. In Rayleigh channel, performance of MIMO with linear and non linear detectors degrades as compared to AWGN channel. Rayleigh fading is the specialised model for stochastic fading when there is no line of sight signal, and is sometimes considered as a special case of the more generalised concept of Rician fading. Rician fading is a stochastic model for radio propagation anomaly caused by partial cancellation of a radio signal by itself — the signal arrives at the receiver by several different paths (hence exhibiting multipath interference), and at least one of the paths is changing (lengthening or shortening). Rician fading occurs when one of the paths, typically a line of sight signal, is much stronger than the others. In Rician fading, by increasing value of K from 4 to 12 dB performance of MIMO system degrades, where K is the ratio between the power in the direct path and the power in the other, scattered paths.

V) CONCLUSION

In this paper, MIMO system analysed with linear and non linear detection schemes under AWGN, Flat Fading Rayleigh channel and Rician fading channel. Further this system is compared with different channel models and system gets better result in AWGN channel and worst result in Rician channel. Performance of MIMO system is better in AWGN because AWGN does not account for fading, frequency selectivity, interference, nonlinearity or dispersion. Performance of MIMO system is degraded in Rayleigh channel due to consideration of multipath. In Rician channel by increasing value of K performance of MIMO system degrades. This paper also investigated example of different types of receivers utilized within a wireless communication system. From the simulation it is clear that ML detector out performed than other detectors and MMSE,MMSE-SIC,MMSE-OSIC detectors are better than ZF,Zf-SIC,ZF-OSIC detectors because of MMSE detectors removes effect of channel and noise whereas ZF detectors removes only effect of channel.

REFERENCES [1] Muhammad Sana Ullah and Mohammed Jashim Uddin,

“Performance Analysis of Wireless MIMO System by Using Alamouti’s Scheme and Maximum Ratio Combining Technique”, International Journal of Advanced Engineering Sciences and Technologies, Vol No. 8, Issue No. 1, 019 - 024

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Bit

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e





[2] B. Vucetic and J. Yuan, “Space-Time Coding”, England, Wiley, 2003

[3] D. Tse and P. Viswanath, “Fundamentals of Wireless Communication”, Cambridge University Press, USA, 2005.

[4] W. H. Tranter, K. S. Shanmugan, T. S. Rappaport and K. L. Kosber, “Principles of Communication Systems Simulation with Wireless Applications”, Prentice Hall, USA, 2003.

[5] V. Tarokh, H. Jafarkhami, and A.R. Calderbank, "Space-time block codes for wireless communications: Performance results", IEEE Journal on Selected Areas in Communications, Vol. 17, No. 3, pp. 451-460, March 1999.

[6] M. L. Honig, K. Steiglitz and B. Gopinath, “Multichannel Signal processing for data communications in the presence of crosstalk”, IEEE Transactions on communication, Vol. 38, No. 4, pp. 551-558, April 1990.

[7] E. Telatar, “Capacity of multi-antenna Gaussian channels” European Trans. on Telecommunications, vol. 10, pp. 585-595, Dec. 1999.

[8] G.J.Foschini. and M.J.Gans, “On the Limits of Wireless Communication in a Fading Environment When Using Multiple Antennas” Wireless Personal Communications, vol. 6, no. 3, pp. 311-355, 1998.

[9] Rohit Gupta and Amit Grover, “BER Performance Analysis of MIMO Systems Using Equalization Techniques” Innovative Systems Design and Engineering Vol 3, No 10, 2012.

[10] T. S. Rappaport, “Wireless Communications”, Second Edition, Pearson Education, India, 2002.

[11] B. Sklar, “Digital Communications Fundamentals and Applications”, Second Edition, Pearson Education, India, 2003.

First Author UPADHYAY RUTIKA JANAKKUMAR M.E. Degree in Digital Communication from PIET Limba 2013, working in the field of Communication. B.E. degree Electronics and Communication

Engineering in GEC, Rajkot 2009 from Saurashtra University Rajkot.

Second Author MAKWANA ASHISH BHARATBHAI MTECH degree in Electronics & Comunication Systems from DDIT Nadiad 2011, working as an assistant professor in Electronics and Communication Engineering department in V.V.P.

Engineering college Rajkot 2011 from Gujarat Technological University Chandkheda.

Third Author ASLAM DURVESH received the BE degree in Electronics and Communication Engineering from the SVIT, Vasad in 2005 and ME degree in Communication Engineering from the GCET, V V Nagar in 2009 From July 2005 to jun 2006 he was a

lecturer at Valia Institute of Technology, Valia. He was an Assistant professor from July 2006 to july 2007 at PIET, Limda. From July 2007 to July 2012 he was a Assistant Professor at GCET, V V Nagar.Since August 2012 he has been as Assistant Professor, Department of Electronics and Communication. His current research interests are in communication systems and Digital Communication, with current emphasis in wireless communications and high-speed networks.He was Awarded the Ranked 1st, ME student in ME (Communication Engineering), SP University, May „2009, V V Nagar.

K.N Varaprasad, Dr.Nisha Sarwade and Ch. M Krishna 84


Low Power Multiplier-Accumulator

K.N Varaprasad, Dr.Nisha Sarwade and Ch. M Krishna

ABSTRACT: Power dissipation is recognized as a critical parameter in modern VLSI design field. To satisfy MOORE’S law and to produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary. High speed and low power Multiplier-Accumulator(MAC) units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. The core of every microprocessor, DSP, and data-processing ASIC is its data path. Statistics showed that more than 70% of the instructions perform additions and multiplications in the data path of RISC machines. At the heart of data-path and addressing units in turn are arithmetic units, such as comparators, adders, and multipliers. Digital multipliers are the most commonly used components in any digital circuit design. Multiplication based operations such as Multiply and Accumulate and inner product are among some of the frequently used Computation-Intensive Arithmetic Functions, currently implemented in many DSP applications such as convolution, fast Fourier transform, filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of low power and high speed multiplier. A review of recent trends in MAC are presented here. Keywords—MAC, Partially Guarded Computation(PGC), Spurious-Power Suppression Technique(SPST).

I. INTRODUCTION: ONE OF THE accompanying challenges in designing ICs

for portable electrical devices is lowering down the power consumption to prolong the operating time on the basis of given limited energy supply from batteries. with the recent rapid development in multimedia and communication systems, digital signal processing are increasingly being demanded. The multiplier and multiplier-and-accumulator (MAC)[1] are the essential elements of the digital signal processing such as filtering, convolution, and inner products. Most digital signal processing methods use nonlinear functions such as discrete cosine transform (DCT)[2] or discrete wavelet transform (DWT). Because they are basically accomplished by repetitive application of multiplication and addition, Multiplication is an important operation in digital signal processing algorithms. It should be small in area, and consumes minimum power. Therefore, there is need of designing low power high speed multiplier.

K.N Varaprasad and ,Dr.Nisha Sarwade are with Department of Electrical Engineering, VJTI, Mumbai, Maharashtra, INDIA. And Ch. M Krishna is with Department of Electronics Engineering, COEP ,Pune, Maharashtra, INDIA, Emails: [email protected], [email protected], [email protected]

Extensive research has been carried out on low power and high speed multipliers at technology, physical, circuit and logic levels. These low-level techniques are not unique to multiplier modules and they are generally applicable to other types of modules. Moreover, power consumption is directly related to data switching patterns. However, it is difficult to consider application-specific data characteristics in low-level power optimization. Various techniques have been developed for reducing the power consumption of VLSI designs, including voltage scaling, switched-capacitance reduction, clock gating, power-down techniques, threshold-voltage controlling, multiple supply voltages, and dynamic voltage frequency scaling . These low-power techniques have been proven to be efficient at certain expense and are applicable to multimedia/DSP designs. Among these low-power techniques, a promising direction for significantly reducing power consumption is reducing the dynamic power which dominates total power dissipation.

Fig. 1. Example speech data and associated range. This paper presents a review of Low power MACs. The organization of this paper is as follows Section II gives Architecture of Mac followed by Section III which provides a review of recent trends of Low power Mac concluded by Section IV.

II. MAC ARCHITECTURE: This chapter introduces the basics of binary multiplication, partial product generation, reduction and techniques to make the multiplication process faster. The multiplication and accumulation is the main computational kernel in Digital Signal Processing architectures. The MAC unit determines the speed of overall system as it is always lies in the critical path. Developing high speed MAC is crucial for real time DSP application. In order to improve the speed of the MAC unit, there are two major bottlenecks that need to be considered. The first one is the fast multiplication network and the second one is the accumulator. Both of these stages require addition of large operands that involve long paths for carry propagation. In recent Mac accumulation and addition are merge to save the time and power. The MAC unit basically do the multiplication of two umbers multiplier and



multiplicand and add that product in result stored in the accumulator.

Figure 2: Basic arithmetic steps of multiplication and accumulation The Fig.2 shows Basic arithmetic steps of multiplication and accumulation. The general construction of the MAC operation can be represented by this equation: Z = X *Y + Z Where the multiplier A and multiplicand B are assumed to have n bits each and the addend Z has (2n+1) bits. A basic MAC unit can be divided into two main blocks . 1.Multiplier 2.Accumulator A Fast Multiplication process consists of three steps

Partial Product Generation. Partial Product Reduction. Final stage Carry Propagate Adder.

To generate the number of partial product Radix-4 Modified booth encoding techniques have been used. The Modified Booth Encoding (MBE) or Modified Booth’s Algorithm (MBA) was proposed by O. L. Macsorley in 1961 . Booth's radix-4 algorithm is widely used to reduce the area of multiplier and to increase the speed. The booth encoding algorithm is a bit-pair encoding algorithm that generates partial products which are multiples of the multiplicand. The booth algorithm shifts and/or complements the multiplicand (X operand) based on the bit patterns of the multiplier (Y operand). Essentially, three multiplier bits [Y (i+1) ,Y (i) and Y (i-1) ] are encoded into eight bits that are used to select multiples of the multiplicand [-2X,-X,0,+X,+2X]. The three multiplier bits consist of a new bit pair [Y (i+1) and Y (i)] and the leftmost bit from the previously encoded bit pair [Y (i-1)]. Grouping the three bits of multiplier with overlapping has half partial products which improve the system speed Multiplier require high amount of power and delay during the partial products addition. At this stage, most of the multipliers are designed with different kind of multi operands adders that are capable to add more than two input operands and results in two outputs, sum and carry. The number of adders will be minimized by Wallace Tree.

Figure 3: Block Diagram of 4:2 Compressor In addition stage 4-2 compressors are used as carry save adders. The 4-2 and 5-2 compressors have been widely employed in the high speed multipliers to lower the latency of the partial product accumulation stage. Owing to its regular interconnection, the 4-2 compressor is ideal for the partial products addition stage. The 4:2 compressor structure actually compresses five partial products bits into three. The architecture is connected in such a way that four of the inputs are coming from the same bit position of the weight j while one bit is fed from the neighbouring position j-1(known as carry-in). The outputs of 4:2 compressor consists of one bit in the position j and two bits in the position j+1.This structure is called compressor since it compresses four partial products into two parts. A 4-2 compressor can also be built using 3-2 compressors. It consists of two 3-2 compressors (full adders) in series and involves a critical path of 4 XOR delays. The output Cout, being independent of the input Cin accelerates the carry save summation of the partial products. Fig.3 shows Hardware Architecture of general MAC Array Multiplier. Fig.3 shows the block diagram of 4:2 compressor and compressor with full adder.

Figure 3: Hardware Architecture of general MAC Array Multiplier

III.POWER OPTIMAZATION:

Power dissipation has emerged as an important design parameter in the design of microelectronic circuits, especially in portable computing and personal communication applications. Addition is very important operation in any digital design. If we can make adder to work with minimum delay and minimum power it will reflect on final design. Many adders are introduced but there is lot to be implanted in addition. If we use ripple carry adder delay will be propagated through-out the process of addition which is undesirable. The delay is proportional to width of operand which is undesirable. Carry Look ahead



Adder(CLA) which somewhat better compared to RCA. If the length of operand is very high CLA is also not recommended because of its complex structure due to which there is large area overhead and power consumption. So later some of adders like Carry skip adder, Carry save adder and Carry select adders were introduced. But each of adder has its advantages and drawbacks. But according our requirement we are going to use these adders in our design. Since core power consumption must be dissipated through the packaging, increasingly expensive packaging and cooling strategies are required as chip power consumption increases. In addition to cost, there is the issue of reliability. High power systems often run hot, and high temperature tends to exacerbate several silicon failure mechanisms. Another crucial driving factor is that excessive power consumption is becoming the limiting factor in integrating more transistors on a single chip or on a multiple-chip module.

(A)SOURCES OF POWER DISSIPATION:Power dissipation in CMOS circuits is caused by three sources: 1) the leakage current which is primarily determined by the fabrication technology, consists of reverse bias current in the parasitic diodes formed between source and drain diffusions and the bulk region in a MOS transistor as well as the sub-threshold current that arises from the inversion charge that exists at the gate voltages below the threshold voltage, 2) the short-circuit current which is due to the DC path between the supply rails during output transitions and 3) the charging and discharging of capacitive loads during logic changes.

(B)LOW POWER DESIGN SPACE: The previous section revealed the three degrees of freedom inherent in the low-power design space are voltage, physical capacitance, and data activity. Optimizing for power entails an attempt to reduce one or more of these factors. But we are going to discuss more about switching activity in this paper switching activity also influences dynamic power consumption. A chip may contain an enormous amount of physical capacitance, but if there is no switching in the circuit, then no dynamic power will be consumed. The data activity determines how often this switching occurs. There are two components to switching activity: fclk which determines the average periodicity of data arrivals and E(sw) which determines how many transitions each arrival will generate. For circuits that do not experience glitching, E(sw) can be interpreted as the probability that a power consuming transition will occur during a single data period. Even for these circuits, calculation of E(sw) is difficult as it depends not only on the switching activities of the circuit inputs and the logic function computed by the circuit, but also on the spatial and temporal correlations among the circuit inputs. The data activity inside a 16-bit multiplier may change by as much as one order of magnitude as a function of input correlations For certain logic styles, however, glitching can be an important source of signal activity and, therefore, deserves some mention here. Glitching refers to spurious and unwanted transitions that occur before a node settles down to its final steady-state value. Glitching often arises when paths with unbalanced propagation delays converge at the same point in the circuit. Since glitching can cause a node to make several power consuming transitions, it should be avoided whenever possible. The data activity E(sw) can be combined

with the physical capacitance C to obtain switched capacitance, Csw=C.E(sw), which describes the average capacitance charged during each data period 1/fclk. It should be noted that it is the switched capacitance that determines the power consumed by a CMOS circuit. In high-level synthesis domain, there have been quite a few studies devoted to minimize transitions in functional units, registers, multiplexers, and buses [3 - 11]. Many of them focus on minimizing transition activity in functional units because they are the main source of power dissipation in data dominated applications [3 - 8]. The most effective method to reduce the number of transitions in functional units is increasing the correlation of input data. Therefore, many of the previous work focus on increasing input data correlation by changing operation binding [3],[8] loop pipelining [7], loop interchange, operand reordering, operand sharing, unrolling [5], and guarded evaluation[11].The existing works that reduce the dynamic power consumption by minimizing the switched capacitance include the designs in [13]–[18]. The design in [13] proposes a concept called partially guarded computation (PGC), which divides the arithmetic units, e.g., adders and multipliers, into two parts and turns off the unused part to minimize the power consumption. The reported results show that the PGC can reduce power consumption by 10%–44% in an array multiplier with 30%–36% area overheads in speech-related applications. However, the PGC technique cannot gain any power reduction when applied on adders because of the overhead-augmented circuitry. The design in [14] proposes a 32-bit 2’s complement adder equipping a two-stage (master and slave stages) flip-flop at each of the two inputs, a dynamic-range determination (DRD) unit and a sign-extension (SE) unit, which tends to reduce the power dissipation of conventional adders for multimedia applications. Additionally, the design in [15] presents a multiplier using the DRD unit to select the input operand with a smaller effective dynamic range to yield the Booth codes. However, the DRD unit induces additional delay and area overheads. Besides, the input data flows are also frequently switched if the input operands with a smaller effective dynamic range often change between operands A and B, and vice versa. In such cases, the power dissipation of the designs in [14] and [15] is increased rather than decreased. The design in [16] incorporates a technique for glitching power minimization by replacing some existing gates with functionally equivalent ones that can be frozen by asserting a control signal. This technique can be applied to replace layout-level descriptions and guarantees predictable results. However, it can only achieve savings of 6.3% in total power dissipation, since it operates in the layout-level environment which is tightly restricted. One of the most advanced types of MAC for general-purpose digital signal processing has been proposed by Elguibaly [19]. It is an architecture in which accumulation has been combined with the carry save adder (CSA) tree that compresses partial products. In the architecture proposed in [12], the critical path was reduced by eliminating the adder for accumulation and decreasing the number of input bits in the final adder. While it has a better performance because of the reduced



critical path compared to the previous MAC architectures

Table.1: Comparison of power consumption in multipliers Table 1 gives the brief history of power reduction by using PGC. There is a need to improve the output rate due to the use of the final adder results for accumulation. Architecture to merge the adder block to the accumulator register in the MAC operator was proposed in [19] to provide the possibility of using two separate N/2-bit adders instead of one -bit adder to accumulate the N–bit MAC results.

Table.2: performance comparison of existing multipliers and spst. Recently, Zicari proposed an architecture that took a merging technique to fully utilize the 4–2 compressor [20]. It also took this compressor as the basic building blocks for multiplication circuit. There are several techniques in reducing power using techniques like increasing the correlation of input data, Partially Guarded Computation and Spurious power suppression technique. But each of these techniques have their advantages and drawbacks. But depending on our application requirement we should choose our suitable technique to reduce power.

IV.CONCLUSION: By using the PGC technique we can reduce power consumption in an array multiplier by about 10 to 44%. This method can effectively reduce power consumption even after minimization of power by using high-level power

minimization technique. However, the PGC technique cannot gain any power reduction when applied on adders because of the overhead-augmented circuitry. Equipping the SPST can save 24% power dissipation at the cost of only 15% area increment, which is a valuable trade-off especially for modem CMOS technologies. We can still reduce the power by using different adders in accumulation stage and innovative multiplication algorithms. Reduction of power is possible by using more than 2 stages of SPST functional block with some increase in area. REFERENCES: [1] J. J. F. Cavanagh, Digital Computer Arithmetic. New York:

McGraw-Hill, 1984. [2] Information Technology-Coding of Moving Picture and

AssociatedAutio, MPEG-2 Draft International Standard, ISO/IEC 13818-1, 2, 3,1994.

[3] A. Raghunathan and N. K. Jha, “Behavioral synthesis for low power,” Proceedings of International Conference on ComputerDesign, pp. 318-322, Oct. 1994.

[4] A. Raghunathan, S. Dey, N. K. Jha, “Controller re-specification to minimize switching activity in controller/data path circuits,” Proceedings of International Symposium on Low Power Electronics and Design, pp. 301-304, Aug. 1996.

[5] E. Musoll and J. Cortadella, “High-level synthesis techniques for reducing the activity of functional units,” Proceedings of International Symposium on Low Power Design, pp. 99-104, Nov. 1995.

[6] L. Benini, P. Vuillod, G. D. Micheli, and C. Coelho, “Synthesis of low power selectively-clock systems from high-level specification,” Proceedings of International Symposium on System Synthesis, pp. 57-63, Nov. 1996.

[7] D. Kim and K. Choi, “Power conscious high level synthesis using loop folding,” Proceedings of Design Automation Conference, pp.441-445, 1997.

[8] D. Shin and K. Choi, “Lower power high level synthesis by increasing data correlation,” Proceedings of International Symposium on Low Power Electronics and Design, Aug. pp. 441-445, Aug. 1997.

[9] R. Mehra, L. M. Guerra, and J. Rabaey, “Low-power architectural synthesis and the impact of exploiting locality,” Journal of VLSI Signal Processing, 1996.

[10] A. Dasgupta and R. Karri, “Simultaneous scheduling and binding for power minimization during micro architecture synthesis,” Proceedings of International Symposium on Low Power Design, 1995.

[11] V. Tiwari, S. Malik, and P. Ashar, “Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design,” IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 17, no. 10, pp.1051-1060, Oct. 1998.

[12] Young-Ho Seo and Dong-Wook Kim,“A new VLSI architecture of parallel multiplier-accumulator based on radix-2 modified Booth algorithm”, in IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 2, pp.201-208, February 2010.

[13] J. Choi, J. Jeon, and K. Choi, “Power minimization of functional units by partially guarded computation,” in Proc. IEEE Int. Symp. Low power Electron. Des., 2000, pp. 131–136.

[14] O. Chen, R. Sheen, and S. Wang, “A low-power adder operating on effective dynamic data ranges,” IEEE Trans. Very Large Scale Integr (VLSI) Syst., vol. 10, no. 4, pp. 435–453, Aug. 2002.

[15] O. Chen, S.Wang, and Y. W.Wu, “Minimization of switching activities of partial products for designing low-power



multipliers,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 3, pp. 418–433, Jun.2003.

[16] L. Benini, G. D. Micheli, A. Macii, E. Macii, M. Poncino, and R. Scarsi,“Glitch power minimization by selective gate freezing,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 3, pp. 287–298, Jun.2000.

[17] S. Henzler, G. Georgakos, J. Berthold, and D. Schmitt-Landsiedel,“Fast power-efficient circuit-block switch-off scheme,” Electron. Lett.,vol. 40, no. 2, pp. 103–104, Jan. 2004.

[18] T. Xanthopoulos and A. P. Chandrakasan, “A low-power DCT core using adaptive bit width and arithmetic activity exploiting signal correlations and quantization,” IEEE J. Solid-State Circuits, vol. 35, no. 5,pp. 740–750, May 2000.

[19] F. Elguibaly, “A fast parallel multiplier–accumulator using the modified Booth algorithm”, IEEE Trans. Circuits Syst., vol. 27, no. 9, pp.902–908, September 2000.

[20] A. R. Cooper, “Parallel architecture modified Booth multiplier”,Proc.Inst.Electr.Eng.G, vol.135, pp.125–128, 1988.

[21] Z. Huang and M. D. Ercegovac, “High-performance low-power left-to right array multiplier design,” IEEE Trans. Computers., vol. 54, no. 3, pp.272–283, Mar. 2005.

[22] Y. Liao and D. B. Roberts, “A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction–multiple-data (SIMD) feature,” IEEE J. Solid-State Circuits, vol. 37, no. 7, pp.926–931, Jul. 2002.

[23] J. S.Wang, C. N. Kuo, and T. H. Yang, “Low-power fixed-width array multipliers,” in Proc. IEEE Symp. Low Power Electron. Des., Aug.9–11, 2004, pp. 307–312.

[24] O. Chen, S.Wang, and Y. W.Wu, “Minimization of switching activities of partial products for designing low-power multipliers,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 3, pp. 418–433, Jun.2003.

[25] H. Lee, “A power-aware scalable pipelined Booth multiplier,” in Proc.IEEE Int. SOC Conf., Sep. 2004, pp. 123–126.

[27] S. K. Hsu, S. K. Mathew, M. A. Anders, B. R. Zeydel, V. G. Oklobdzija,R. K. Krishnamurthy, and S. Y. Borkar, “A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS,” IEEE J.Solid-State Circuits, vol. 41, no. 1, pp. 256–264, Jan. 2006.

Author’s Profile: 1.K.N Varaprasad is doing M.Tech in Electronics Engineering from Veermata Jijabai Technological Institute and his area of interests are VLSI and Nanotechnology. 2. Dr.Nisha Sarwade is professor in Department of Electrical Engineering in Veermata Jijabai Technological Institute and her area of interests are VLSI and Nanotechnology. 3. Ch.M Krishna is doing M.Tech in VLSI and Embedded Systems from College of Engineering Pune and his area of interests are VLSI and Embedded Systems.

Ms.Vandana M. Anerao 89


Implementation of Stepped Impedance Microstrip Low Pass Filter

Ms.Vandana M. Anerao

Abstract: Filters are significant RF and Microwave components. Lumped element filters are impractical for compact designs of wireless communications equipment, especially hand-held devices. Distributed element filter design offers a much smaller area and profile. With the advent of advanced substrate materials offering high dielectric constants with low loss, the size reduction with preserved efficiency is greatly enhanced. Transmission line filters can be easy to implement, depending on the type of transmission line used. The aim of this paper is to develop a transmission line filters to do practical work. This paper describes about the design, testing and fabrication of microwave low pass filter by using micro strip layout. The development of the micro strip filters are simulated by using Ansoft designer SV simulator software. The final testing was done by using the RF Network Analyzer. The Microstrip low pass filter has a return loss is -22.41 dB and insertion loss is -1.12 dB for frequency of 1.28GHz. Index Terms- Lowpass, filter, stepped impedance, fr4 substrate, dielectric constant.

I. Introduction

In today’s fast-growing wireless industry, time to market is critical. Smaller and less expensive units are becoming the norm and the use of CAD tools to quickly and accurately simulate the behavior of wireless components becomes more important as designs become more complex and prototyping cycles become shorter. Microwave filters can be divided into two main different types, lumped or distributed. Lumped elements consist of discrete elements, such as inductors and capacitors, while distributed elements use the lengths and widths of transmission lines to create their inductive or capacitive values [3].

Lumped elements are very small compared to the wavelength, while distributed elements usually are in the order of the wavelength. At high frequencies (10’s of GHz or higher) the wavelength is so short that only distributed elements are possible to practically realize, while at low frequencies lumped elements are used due to the fact that distributed elements become too large. Ms..VandanaM.Anerao is with KJSCE, Department of Electronics &Telecommunication Engineering, Mumbai, E-mail: [email protected]

II. Microstrip filter design Steps

Fig1. Microstrip filter design steps

II. Steps to design stepped impedance micro-strip low pass filter are as follow:

1. Determine the number of sections from the specification characteristics for Microstrip low pass filter. Filter Specifications

Topology: Stepped Impedance Passband: Lowpass Order: 3 Passband ripple: 0.5 dB Lower PB corner, fp1: 1.27 GHz Upper PB corner, fp2: 1.29 GHz Source resistance: 50.0 ohms Load resistance: 50.0 ohms Implementation = Stepped Impedance Order = 3 Relative Permittivity of substrate = 4.4 Thickness of substrate = 1.59mm tan δ = 0.023

2. To find Lowpass filter prototype values. g 1 =g3 =L1=L3=1.5963 g2=C2 =1.0967 g4 =RL =1.0



Fig 2 .Lumped element low pass filter prototype 3. Application of Richard’s Transformation. Using Richard’s Transformation, series conductors were converted to their equivalent series stubs and shunt capacitors to their equivalent shunt stubs. The characteristic impedances of series stubs remains inductance L while characteristic impedances of shunt stubs becomes capacitance 1/C. Resultant circuit is displayed in fig. 3

9118.00967.1

115963.1

CZ

LZ

OC

OL

Fig3. Converted stub impedances using Richards Transformation The length l of the stubs is λ/8 at cut off frequency. The normalized stub lengths are l= λ/8 at ω =1 Series stubs are difficult to implement in microstrip form hence it is necessary to use Kuroda’s identity to convert these series stubs into shunt stubs. This is done by first adding unit elements at either end of filter as shown in fig 4.

Fig4. Unit element added to both sides of filter These elements will not affect overall performance of filter as long as they are matched to source and load.

Then Kuroda identity can be applied by using the formula

1

22 1ZZn

Where Z2 is the impedance of series stub and Z1 is the impedance of unit element placed adjacent to it. This will result in the following value of n2

6264.15963.1

11

1

2

2

1

22

n

n

ZZn

The impedance of each stub excluding the centre shunt stub shall be multiplied with this value so that the impedances of stubs are equivalent to those as shown in fig 5.

6264.16264.1*1

5962.25963.1*6264.1

2

202

1

21

ZnZZ

ZZnZ OL

Fig5. Filter Design after applying Kuroda’s Identity 4. Frequency Scaling Lastly the impedances of the segments are scaled by 50Ω and the stub lengths are adjusted to λ/8 at the cut off frequency of 1.28GHz

81.12950*5962.259.4550*9118.0

32.8150*6264.1

2

1

ZZZ

OC

Hence the resulting microstrip filter should thus be similar to fig.5.

5963.11

1

5963.1

1

2

022

21

ZZ

ZnZ

ZnZ

OL



Fig6. Filter design after applying frequency scaling The following calculations are performed to obtain lengths and widths of microstrip stubs.

1116.3

)121

1(2

12

14949.12

74748.02

*83875.2

)11.023.0(11

21

60

32.81

2

0

eff

rreff

A

A

rr

rr

wd

wmmletd

ee

dwA

ZA

Z

6463.52

37750

0

0

BZ

B

Z

r

mml

fc

eff

6083.168

1328.0

mml

fc

wd

wmmletd

dw

BBBdwZ

eff

eff

rreff

rr

r

055.168

12844.0

3295.3

)121

1(2

12

18138.32

9069.1

}]61.039.0)1{ln(2

1)12ln(1[2

50

Similarly all other values of lengths and widths of transmission lines are calculated. Table 1: Lengths and widths of transmission line Impedance Length(mm) Width(mm) 50Ω 16.055 3.8138 45.95Ω 15.953 4.448 81.32Ω 16.6083 1.4949 129.81Ω 17.159 0.38996

III. Ansoft Simulation Results Symbols are used for circuit representation of the filter. In this case the filter is composed of microstrip coupled lines (MSCL).Once the filter is specified we can generate the layout from the circuit representation. The data required by this utility to synthesize the microstrip dimensions are the substrate parameters, in this case fr4 with dielectric constant = 4.4, thickness = 1.59mm, tan δ = 0.0023, 50mil thick, impedance of the lines (50 ohms), Electrical length (180 degrees) , Frequency (1.28GHz). Using the starting dimensions we can draw schematic.We can then perform electromagnetic (EM) analysis over the layout and compare the results.

P=16.055mmW=3.8138mm

P=17.159mmW=0.38996mm

1 23

W1=0.38996mmW2=0.38996mmW3=4.448mm

P=17.159mmW=0.38996mm

1 23

W1=0.38996mmW2=3.8138mmW3=1.4949mm

P=16.055mmW=3.8138mm

1 23

W1=3.8138mmW2=0.38996mmW3=1.4949mm

P=1

6.60

83m

mW

=1.4

949m

m

P=1

5.95

3mm

W=4

.448

mm

P=1

6.60

83m

mW

=1.4

949m

m

Fig7. Schematic of stepped impedance micro strip low pass filter



Fig8. Layout of stepped impedance microstrip lowpass filter

Fig9. Designed hardware for microstrip LPF

III(a). Measurement Results

Fig10. Simulated results for S11 and S12

Fig11. Practical result for S12

Fig12. Practical result for S11 Table 2: Comparision of Simulated and hardware results

Parameter Simulated Result

Hardware Result

Return Loss -25.76 dB -22.41 dB Insertion Loss -0.85 dB -1.123 dB

IV. Conclusion In this paper study of low pass filter based on stepped impedance topology is presented. Third order Stepped impedance Low Pass Filter is fabricated and tested on fr4 substrate. Overall performance of designed filter easily met proposed requirements.In future same design can be modified using fractal technology to get miniaturized dimensions.

V. References [1] Ludwig, Reinhold and Bretchko, Pavel (2000). “RF Circuit

Design - Theory and Application” New Jersey, USA: Prentice-Hall, Inc.

[2] Hong, Jia-Sheng and Lanchester, M.J. (2001). “Microstrip Filters for RF / Microwave Applications” USA: John Wiley & Sons, Inc.

[3] Pozar, DavidM. (1998) “Microwave Engineering” 2nd Edition, USA: John Wiley &Sons, Inc.

Ms.Vandana Anerao working in K.J.Somaiya College of Engineering, Mumbai since 2004.She has completed M.E.in electronics and telecommunication. Her area of interest is RF, Microwaves and antenna. She has published 2 international and 3 national papers. she has completed research project on “Design and fabrication of Microstrip components”

Asha N and Ravindra G. Patil 93


Polymer: Future Material of Insulator

Asha N and Ravindra G. Patil

Abstract: The paper describes the details of the some of the tests are carried on ceramic and polymer insulators to know the performance of the better insulator, and also the comparison of ceramic and polymer insulator are done with the manufacturing process. And finally concluded that polymer is the best insulator than ceramic insulator. In the transmission and distribution of electrical energy, insulators have the important task of creating a barrier between live voltage and the ground, while providing strong mechanical support. Insulators are used at various locations in a power network and their insulation and mechanical characteristics must ensure a long-lasting barrier. Porcelain and glass-type insulators have been in use for over 100 years. More recently, new composite (Polymer) materials were introduced. The insulators are subjected to higher than usual levels of one or more accelerating variables such as voltage, temperature and stress.

Keywords: Polymer, Ceramic, Flash over, Hydropobicity, Tensile strength and Puncture Voltage

1. INTRODUCTION

Electrical insulator is a very important component in the electric power systems such as sub-stations, distribution and transmission lines. It prevents the loss of electric charge or current from conductors in electric power transmission lines. In earlier days, insulators were made of ceramic and glass materials. But now days, polymeric insulator were developed and its improvements in design and manufacturing in the recent years have made them attractive to utilities. An insulator is a material that resists the flow of electric charge. Overhead power transmission lines require both wires to conduct the electricity and insulators to isolate the wires from the steel towers or utility poles by which they are supported.

Insulator is an insulating material in a form designed to support a conductor physically and electrically separate it from another conductor or object. Insulators are used in overhead lines as cap and pin, line posts, long rod, railway insulators, jumper loops and in substations as supports, apparatus bushings, apparatus housing (transformer, surge arresters).

The insulators have conventionally been made of ceramics or glass. These materials have outstanding insulating properties and weather resistance but have the disadvantages of being heavy, easily fractured, and

Asha N and Ravindra G. Patil are withElectrical and electronics, power and energy system Basaveshwara engineering collage, Bagalkot, Karnattaka, India, Emails: [email protected], [email protected];

subject to degradation of their withstand voltage properties when polluted. There was therefore a desire to develop insulators of a new structure using new materials that would overcome these drawbacks. Hence composite insulators were developed.

Three types of insulators are:

i. Porcelain Insulators

ii. Glass Insulators

iii. Composite Insulators

i) Porcelain insulators

Porcelain insulators are made from clay, quartz or alumina and feldspar, and are covered with a smooth glaze to shed water. Insulators made from porcelain rich in alumina are used where high mechanical strength is a criterion. Porcelain has a dielectric strength of about 4–10 kV/mm.

Fig.1. 10kV Porcelain Insulator

ii) Glass insulators

Glass insulators were used to insulate lightning rods and cables from structures. Glass insulators are used in battery rest insulators, thread less insulators etc. Glass has a higher dielectric strength, but it attracts condensation and the thick irregular shapes needed for insulators are difficult to cast without internal strains.

Fig.2. Glass Insulator



iii) Composite insulators

A composite insulator consists of a core material, end fitting, and a rubber insulating housing. The core is of FRP (Fiber Reinforced Plastic) to distribute the tensile load. The reinforcing fibers used in FRP are glass (E or ECR – Epoxy corrosion resistant) and epoxy resin is used for the matrix. The portions of the end-fitting to transmit tension to the cable and towers are of forged steel, malleable cast iron, aluminium etc. The rubber housing provides electrical insulation. It covers the FRP Rod thereby protecting it from corrosion due to atmospheric exposure. Composite insulators are also known as polymeric or non-ceramic insulators.

Silicone rubber has superior electrical characteristics and weather resistance properties over a wide range of temperatures, for use in the housing. It is resistant to oxidation, has low surface energy, and resists degradation from ultraviolet radiation. These properties make silicone rubber a good choice for electrical insulators.

Fig 3 polymer insulator

2. Process Flow Chart of Ceramic and Polymer Insulator

Fig 4 Manufacturing process of polymer insulator

Fig 5 Manufacturing process of ceramic insulator

Manufacturing process of polymer insulators needs less cost, power and also easy compared to ceramic insulators

3. TESTING OF INSULATORS

Objective of testing

To ensure the defect free insulators at the stage of dispatch and if any problem persist then approach method is carried out:

1. Identification of the problems and collection of data.

2. Analysis of data (using pareto analysis).

3. Causes and effect diagrams for the analysis of major defects.

4. Action plan

The testing of insulators is classified as:

i. Type test

ii. Routine test

iii. Acceptance test

Type test are those tests carried out to prove conformity with the design and specification. These are intended to prove the general qualities and design of given type of insulators.

Routine test are carried out on each and every insulators to ensure good quality of insulators.

Acceptance test are carried out on samples taken from a lot for the purpose of acceptance of the lot.

For different insulators, different tests are carried out depending on the application and the service requirement.

.a) Following definitions of terms used in testing of insulators

Flashover: A disruptive discharge external to the insulator, connecting those parts which normally have the operating voltage between them.



Puncture: A disruptive discharge passing through the solid insulating parts of an insulator.

Dry impulse with stand voltage: The specified impulse voltage which the insulator shall with stand, without flashover or puncture. The specified power frequency voltage which the insulator shells withstand under wet conditions

Wet power frequency withstand voltage:The specified power frequency voltage which the insulator shells withstand under wet conditions.

Mechanical failing load: The maximum specified type of mechanical load which can be reached by the insulator.

Electromechanical failing load: The maximum load which can be reached when a string insulator unit is tested under few conditions prescribed under I

Table.1: Ems test reading of ceramic insulator

b) Type test:

i) Electromechanical test (For suspension type): This test is consists of application of tensile stress of 21/2 times the maximum working tensile strength for about one minute along with the voltage. Then after this test the insulator is tested for 75 of dry spark voltage

Statistical Evaluation

Table.2: Test evaluation result

N Sample size 20

X

Mean failing load 484KN

R Rated E-M failing load 420KN

S Standard deviation 5.183KN

(R+3S) Acceptance formula 435.55KN Conclusion: Since X obtained is greater than (R+3S), the result meets the requirements of the specification.

Polymer: Applied voltage=50KV (for 160 KN Insulator)

Table.3: EMS test on polymer insulator

Sample number

Tensile breaking load (KN

Duration(mint)

Failing load(KN)

Remarks

1 28 96 240 Socketside crimp sliped

2 26 103 270 Socketside crimp sliped

Remark: Table 1 and table 2 show the withstanding load of 160 KN polymer insulators is more than 420 KN ceramic insulators.

ii) Impulse frequency flashover test:

The insulator used in the field, must also be tested against the high voltage surges caused by lightning etc. For this test the generator developing lightning voltages is employed, it develops a very high voltage at frequency of several hundred thousand cycles per second. Such a voltage is applied to the insulator and the spark over voltage is applied to the insulator and the spark over voltage is noted.

Ceramic insulator: (120 KN Insulator)

0200400600

160

KN42

0 KN

LOAD

(KN

) CERAMIC INSULATOR

POLYMER INSULATOR

Sample number

Tensile breaking load (KN)

Remarks

Sample number

Tensile breaking load (KN)

Remarks

1 482 Cap broken

11 494 Cap broken

2 486 Cap broken

12 478 Cap broken

3 476 Cap broken

13 486 Cap broken

4 492 Cap broken

14 482 Cap broken

5 480 Cap broken

15 490 Cap broken

6 484 Cap broken

16 480 Cap broken

7 486 Cap broken

17 488 Cap broken

8 479 Cap broken

18 478 Cap broken

9 488 Cap broken

19 484 Cap broken

10 482 Cap broken

20 492 Cap broken



Table.4: Impulse test reading on ceramic insulator polymer insulator:

Test sample number

Test voltage KV (rms)

Remarks

1 85 Withstood

2 85 Withstood

3 85 Withstood

Table.5: Impulse test reading on polymer insulator

Test sample(KN) Test Voltage KV(rms)

Remark

90 185 Withstood

120 190 Withstood

160 200 Withstood

420 380 Withstood

Remark: Table 4 and table 5 shows the withstanding voltage of 120 KN insulator for polymer are more the ceramic.

iii) Wet power frequency voltage withstand test:

Before the commencement of test, the insulator shell be exposed to the artificial rain produced for at least one minute before application of voltage and then throughout the test. A voltage of about 75 % of the test voltage as determined shall be applied and then increased gradually to reach the test voltage in a time not less than 5 seconds. The test voltage shall be maintained at this value for one minute. The insulator shall not flashover or puncture during the application of the test voltage.

Ceramic insulators: (120KN Insulator)

Table.6: Power frequency readings on ceramic insulator

Polymer insulator:

Table.7: Power frequency readings on ceramic insulator

Type of sample(KN)

Test voltage(KV)

Remark

90 80 Flashed over

120 85 Flashed over

160 140 Flashed over

9 ton 150 Flashed over

Remark: Table 6 and table 7 show the power frequency withstanding voltage of 90KN polymer insulator are more than 120KN ceramic insulator.

c) Routine test:

i) Visual examination: visually inspection on both type of insulator are examined like surface finishing, glaze, overall finishing

ii) Mechanical strength test :

In this test, the insulator is mounted on a steel pin and 21/2 times the maximum working load is applied for 1min. this test is also called as bending test

050

100150200250300

120 KN

VOLT

AGE

(KV)

POLYMER INSULATOR

CERAMIC INSULATOR

020406080

100

90 KN 120 KN

VOYT

AGE

(KV)

CERAMIC INSULATOR

POLYMER INSULATOR

Test sample number

Test voltage KV (rms)

Remarks

1 57 Flashed over

2 57 Flashed over

3 57 Flashed over



Ceramic insulator:

Table.8: Mechanical reading on ceramic insulator

Product / item(KN)

Load (KN)

70 42

80 48

90 54

100 60

120 72

125 75

160 96

190 114

210 126

300 180

420 252

Polymer insulator:

Table.9: Mechanical reading on polymer insulator

Product / item(KN) Load (Tonne)

90 5.5

120 7.2

160 9.6

Stay arm insulator 4.9

Bracket insulator 4.9

9 tonne 7.7

Remark: Table 8 and table 9 show the Mechanical withstanding capacities of polymer insulator are more than ceramicinsulator.

iii) Hydraulic pressure test: (for ceramic insulator)

In this test, the insulator is subjected to a pressure of 200 kg/cm2 hydraulically in the head portion for about 2 to 3 seconds and in case of any cracks, the pieces shackles.

Crimping pressure test: (for polymer insulator)

The insulator crimping is subjected to a pressure of 210 kg/cm2 about 2 to 3 seconds

Remark: the polymer insulator as the high pressure withstanding than ceramic insulator

:

iv) Electrical flashover test:

This is done in order to ensure that the insulator does not fail under normal working load with some factor of safety. Here, any puncture in the insulator is detected.

For ceramic insulator: Normally 70 to 80 KV is applied

For polymer insulator: normally 150 KV is applied

Remark: withstanding electrical voltage for polymer insulator are more

d) Sample test:

i) Verification of dimensions (for both type of insulators)

Following physical dimensions shall be checked on 10 samples in accordance with the drawing approved by customer

1. Disc diameter

2. Unit spacing

3. Creepage distance

4. Verification of eccentricity

ii) Verification of locking system:

Locking of clip in the insulators are checked by pushing the clip from minimum to maximum force

195

200

205

210

215

420 KN

Kg/c

m sq

u

CERAMIC INSULATOR

POLYMER INSULATOR

0

500

1000

1500

420 KN

KV

POLYMER INSULATOR

CERAMIC INSULATOR



Ceramic insulators (for 420 KN)

Table.10: locking system readings of ceramic insulator

Sample no F min(N) F max(N) Remark

1 139 590 Satisfactory






Polymer insulator (for 160 KN)

Table.11: locking system readings of ceramic insulator

Sample no F min(N) F max(N) Remark




Remark: Table 10 and table 11 show the locking capacity of 160 KN polymer insulators is more than 420 KN ceramic insulators.

iii) Water absorption (For polymer)

The 30mm cutted samples are dipped in the water first sample is cleaned and weighted and the dipped in water for 3 hr than weighted the difference are measured

Table.12: Water absorption readings of polymer insulator

Sample no

Dry weighted(gm)

Saturating weight, S(gm)

% of water obsortion,T

1 7.5593 7.562 0.036

2 7.3492 7.351 0.033

3 7.3728 7.377 0.033

T=(S-D)/D*100

Water diffusion (for polymer)

The samples are boiled in container for 100 hr in deiodised water 0.1 %, Nacl after boiling the specimen are placed in another container filled with top water at ambient temperature for 15 min with 3 hr specimen removed and

dried each specimen is put between the two electrode, voltage is incensed at 1 KV/S up to 12 V

Temperature cycle test (For ceramic insulator)

The test is conducted to bring out minute irregularities in the shell material, which reduce the mechanical strength. For this test insulator is first heated in water at 70oC for one hour and is then immediately cooled in water at 70C for another hour. The heating and cooling cycle is performed 4 times in succession and the time taken for transfer of insulators must be as small as possible. After such temperature cycles the insulator is dried. It should be noted that after this test the glaze of the insulator should not be damaged.

Remark: The ambient temperature is sufficient for polymer insulator, but ceramic insulator needs more temperature

iv) Porosity test: (for ceramic insulator)

The porosity of material of the insulator can well be determined by the penetration test. In this test, recently fired insulator is broken into pieces. This insulator is dipped in a solution of surgical spirit containing about 1gm/lit of cooling material like fuchsin for 12 hours at a pressure of 150kg/cm2. At the end of 12 hours the samples are removed and examined. After that if any slight porosity of the material is indicated by the deep penetration of the dye into it then the whole is rejected.

Fig 6 (a): Porosity test machine

Fig 6 (b): Penetration of the dye, Fig 6 (c): No penetration

Non-porosity is one of the important properties that an insulator has to posses. Without this, with air gaps amidst the insulation, the dielectric strength of the insulators suffers. Therefore this is the most crucial test of all.

Dye penetration test: (for polymer)

Samples shall be cut of length 10 +/- 0.5 mm specimens are placed vertically on a layer of steel/glass balls of diameter 1 to 2 mm in a vessel, a dye is poured in a vessel time taken



by dye to rise though specimen is measured, time taken should be more than 15 mint, if penetration is appeared that sample is rejected

Remark: penetration test for polymer insulator is easy and duration also less compared to porosity test for ceramic insulator.

vi) Puncture voltage test:

For such test the insulator is suspended in insulating oil and a certain minimum potential is applied. The value of this potential in case of suspension insulator is 1.3 times that of dry flashover voltage. The good insulator should not puncture under this test.

For ceramic insulator (160 KN Insulator)

Table.13: Puncture test reading of ceramic insulator

Sample no Voltage (KV) Remark

1 192 Punctured

2 194 Punctured

3 196 Punctured

4 197 punctured

For polymer insulator (120 KN Insulator)

Table.14: Puncture test reading of polymer insulator

Sample no Voltage (kv) Remark

1 193 Punctured

2 196 Punctured

3 198 Punctured

:

Remark: Table 13 and table 14 shows the punctured voltage for 120 KN polymer insulator are more than 160 KN ceramic insulator.

v) Tensile strength test (for polymer insulators)

Tensile strength test is used to evaluate the tensile (tension) properties of vulcanized thermo-set rubbers and thermoplastic elastomers.

There are two methods that are employed according to ASTM Standards:

Test method A- Dumbbell and Straight Section Specimens

Test method B- Cut Ring Specimens

The method that we have employed is Test method A and Dumbbell specimen is used.

Test procedure:

1 .Measure the thickness and width of the dumbbell rubber sample using Vernier calipers and scale.

2. Place one end of a dumbbell specimen in the upper grip of the testing machine.

3. Attach the lower grip of the machine by means of the gripping mechanism to the dumbbell specimen in the upper grip.

4. Care has to be taken to place the dumbbell specimen symmetrically in the grips of the testing machine so that tension is uniformly distributed over the entire cross-section of the sample.

5. Using the scale measure the initial gap (initial length) between the upper and the lower grip.

6. Provide a particular load or force to the machine in units of Newton.

7. Start the grip separation motor or mechanism for normal testing, and allow it to run.

8. At a particular point i.e. at breaking load, the rubber sample ruptures and breaks apart. Note down all the values indicated in the machine. Immediately stop the grip separation motor.

9. Using a scale measure the gap (elongated length) between the upper and the lower grip when the motor is stopped.

10. using all the parameter values that have been noted, calculate percentage elongation and ultimate tensile strength of the rubber sample using the following formulae.

1. Percentage elongation = (elongated length / initial length) x 100

2. Ultimate tensile strength = breaking load / (width x thickness)

196.5197

197.5198

198.5

120 KN

160 KN

KV

CERAMIC INSULATOR

POLYMER INSULATOR



Fig.7 Tensile strength testing machine

Calculations:

SOLID RUBBER SAMPLE

Thickness of rubber sample before the test is 2.1mm and width is 6mm.

After applying load:

Initial length is 87mm and elongated length is 220mm

Breaking load = 53N

Percentage elongation = (elongated length / initial length) x 100

= (220 / 87) x 100

= 252.87%

Ultimate tensile strength = breaking load / (width x thickness)

= 53 / (2.1 x 6)

= 4.2 N/mm2

Observations:

From the test conducted on the samples and calculations, we can conclude that ultimate tensile strength of Solid rubber material is higher. Hence it is more flexible in nature. So this type of materials can be used for making composite insulators as one is strong.

Table.15 tensile test readings on polymer insulator

vii) Hydrophobicity test (for polymer insulator)

Scope:

The superior electrical performance of composite insulators and coated insulators stems from the hydrophobicity (water-repellency) of their surfaces. The hydrophobicity will change with time due to exposure to the outdoor environment and partial discharges (corona).

Seven classes of the hydrophobicity (HC 1-6) have been defined; HC 1 corresponds to a completely hydrophobic (water-repellent) surface and HC 6 to a completely hydrophilic (easily wetted) surface.

These classes provide a coarse value of the wetting status and are particularly suitable for a fast and easy check of insulators in the field.

Test equipment:

The equipment needed is a common spray bottle and a H.V High Frequency Resonant variable voltage corona generator. The spray bottle is filled with tap water and it produces a fine mist. The water shall not contain any chemicals, as detergents, tensides, and solvents. Complementary equipments which could facilitate the judgment is a magnification glass, a lamp, and a measuring-tape.

Specifications of corona generator:

1. H.V High frequency resonant variable voltage corona Generator with output of 0 to 35 kV AC.

•Input voltage: 230V/ 50Hz

•Phase: Single phase @ 50Hz

•Maximum output voltage: 35kV (Resonant type)

•Maximum current: 5mA

•Resonant frequency: 27 kHz

•Peak RF current: 10A

•Total energy in joules: 100 Joules

•Voltage control: Yes starting from 0 to 35kV

•Grounding: Yes minimum 10 ohms required

•ON duration: maximum 1 hour continuously

2. Low voltage plate of 300mm x 300mm and a 3 static H.V Termination with metallic probes of 25mm x 25m



Test setup:

Fig.8 Hydrophobicity test setup

Test procedure:

1. The surface of selected samples shall be cleaned with isopropyl alcohol. Allow the surface to dry and spray with water. Record the HC classification. Dry the sample surface.

2. Treat the surface with corona discharges to destroy the hydrophobicity. This can be done utilizing a high frequency corona tester. Holding the electrode approximately 3mm from the sample surface slowly move the electrode over an area approximately 1”x 1”. Continue treating this area for 2-3 minutes, operating the tester at maximum output. The sample is placed around 3mm below the corona probe so that corona discharges are clearly visible. Dielectric strength of air is 3kV/mm. The voltage is gradually increased from zero and around 30kV, the corona discharges are visible. The surface of rubber is treated with these corona discharges.

3. Immediately after the corona treatment, spray the surface with water 1 – 2 times per second from a distance of 25cm. The spraying shall continue for 20 – 30 seconds. The judgment of the hydrophobicity class shall be performed within 10 seconds after the spraying has been finished.

4. Record the HC classification as shown in the fig.4.3.8. The surface should be hydrophilic with an HC value of 6. If not, dry the surface and repeat the corona treatment for a longer time until an HC of 6 is obtained. Dry the sample surface.

5. Allow the sample to recover and repeat the hydrophobicity measurement at several time intervals. Silicone rubber should recover to HC 1- HC 2 within 24 to 48 hours, depending on the material and the intensity of the corona treatment.

Criteria:

The actual wetting appearance on the insulator has to be identified with one of the seven hydrophobicity classes (HC), which is a value between 1 and 6. The criteria for the different classes are given in below table. Also the contact angle (θ) between the water drops and the surface must be taken into account. The contact angle is defined in fig. 4.3.7. There exist two different contact angles, the advancing contact angle (θa) and the receding contact angle (θr). A drop exhibits these angles on an inclined surface.

The receding angle is the most important when the wetting properties of an insulator shall be evaluated. The inclination angle of the surface affects the θr.

Fig.9: Contact Angle

a. horizontal plan

b. inclined plane

Where θa = advancing angle

θr = receding angle

Criteria for the Hydrophobicity Classification(HC1-6)

Fig.10 Typical examples of surfaces with HC from 1 to 6

Advantages of hydrophobicity for electrical outdoor insulation:

1. In contrast to hydrophilic materials, hydrophobic surfaces prevent complete wetting due to fog, dew or rain and therefore more isolated droplets are formed.

2. Complete wetting would result in electrically conductive layers, which are the reason for leakage currents. These leakage currents can dry the wet layer and form small



electrical arcs, which can attack/damage the surface and may intensify until a complete flashover. Hydrophobicity reduces leakage currents, which finally lowers the flashover probability. In other words hydrophobicity results in better insulator reliability.

3. Due to the lower discharging activity, the surface is less influenced so that erosion is reduced and life expectancy of the insulator is improved.

Dow corning rubber sample

Fig.11 Sample 1 before test and after treating with corona discharge

Fig.12 Sample 1 after recovery of hydrophobicity

Observations on sample:

The one type of rubber sample tested is of ‘Dow Corning’ make. The hydrophobicity classification is observed to be HC 1 before the test as shown in fig.4.3.9. After treating the samples with corona discharge the hydrophobic property of the silicone rubber is destroyed and the classification is observed to be HC 5 as shown in fig.4.3.9. It is observed that the sample has recovered its hydrophobic property within 24 hours after the test and the classification is observed to be HC 1 or HC 2 as shown in the fig.4.3.10. This sample is found to be suitable for composite insulators

From the above tests conducted on ceramic and polymer insulator, finally concluded that polymer is best insulator

4. Comparison between porcelain and composite insulators

Weight ratio of Porcelain to Silicone Composite insulator for Railway Traction applications is 3:1.

Weight ratio between porcelain insulator and composite long rod insulators for transmission line applications is more than 10:1 making composite insulators an ideal insulator for lines with limited right of way.

Fig.13 Traction and Long Rod Insulators

5. Conclusion

Non-ceramic insulators, particularly silicone composite insulators, are being widely adopted all over the world. This report provides details of the design, manufacturing and the three tests that are carried on composite insulators to evaluate its performance by simulating the environmental conditions. Based on this study, the following conclusions can be drawn and some suggestions made:

Silicone composite insulators have been widely adopted in several countries in different high voltage applications such as insulators for distribution, transmission and traction, bushings, instrument transformers, surge arrestors, etc.

Several advantages of silicone composite insulators have been cited for its increased adoption, such as better pollution performance, lower weight, flexibility, shock resistance, etc.

One of the main advantages cited for silicone polymers is their high hydrophobicity and also retention of this characteristic under hostile environment. This has been the main reason for its increased adoption for housing/shed material in high voltage applications. So finally concluded that polymer is best insulator compared to ceramic insulators.



References

[1] INMR (INSULATOR NEWS & MARKET REPORT)

MAGAZINE:source of information on international developments in transmission & distribution .may – june 2002 editionvol.10 no.

[2] INMR (INSULATOR NEWS & MARKET REPORT) MAGAZINE:source of information on international developments in transmission & distribution issue 69, quarter 3, 2005 edition vol.13 no.3

[3] V.K.Kamaraju and M.S.Naidu ‘’High voltage engineering’’ New Age publishers, New Delhi, 2010. 2.

[4] Soni, Gupta and Bhattnagar ;;A course in electrical power ‘’volm 17,1998

[5] Catalogues of insulators given by BHEL-EPD.

Asha N. was born in Chitradurga, Karnataka, India on 22 March 1990. She obtained B.E (Electrical and Electonics) from Visvesvaraya Technological University, Karnataka., India. She is currently perusing M.Tech Degree in Power and Energy Systems in Electrical and Electronics

Engineering, Basaveshwar Engineering College, Bagalkot, India.

Ravindra G. Patil was born in Hampiholi of Ramdurg Tal, Karnataka, India on 1st April 1961. He obtained B.E (Electrical and Electronics) from Karnataka University, Dharwad, Karnataka India in 1984 and M.E from Jadhavpur University, Kolkata , West

Bengal, India in 1993. His areas of interest include Power Electronics, Machines and Drives. Presently he is working as Assistance Professor in the Department of Electrical & Electronics Engineering at Basaveshwar Engineering College, Bagalkot, India.

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