INTERNAL PRODUCT SPECIFICATION€¦ · Fault Report was Reg 0x79h HEX = 49 28 Reg 0x78h HEX= 49 XX Reg 0x7Ch HEX= 10 XX is Reg 0x79h HEX = 48 38 Reg 0x78h HEX= 48 XX Reg 0x80h HEX

INTERNAL PRODUCT SPECIFICATION

HPS3000-9 MODEL NO.: HPS3000-9 PREPARED/DATE: Rail Montaril / 09/23/2009 DRAWING No. 41966008950 CHECKED/DATE: Mark Guevarra / 09/23/2009 Page 1 of 92

1 REVISION LEVEL

1.1 IPS Revision History

ISSUE ECO #

DATE SECTION REVISION

DESCRIPTION APPROVED

A G20083184A July 31, 2008

Initial Release Louie Cuevas

B G20085440A Dec. 16, 2008

Integrate EEPROM FRU Specification

Update template with correct confidentiality property

Update Output Voltage Calibration Procedure

3.9.2.7 Updated Dynamic Margin Was +/- 3% is +/- 5% .

3.9.9.8 Updated value of maximum Tpson_on_delay was 200mS is 400mS.

5.5 6.5.

Updated Output Loading percentage in Burn-In Test was 80-100% is 80-90% Updated in Line Load Regulation Test

6.5.10 Updated Output Voltage Minimum and Maximum Limits at Transient Response Test

6.5.12 Updated Timing Test 2.2 Set efficiency at Nominal Low-Line to

be > 85%

3.9.1.7 Holdover Storage was 12ms minimum is 10ms minimum.

CONFIDENTIAL

PROPERTY OF EMERSON NETWORK POWER. ALL RIGHTS RESERVED

This document, and the information it contains, are the property of an Emerson Network Power company and are protected by law. Both must be held in strictest confidence at all times. No license or right to copy,

use or disclose either, expressly or by implication is granted. ©Astec International Limited. ALL RIGHTS RESERVED.

RENEEFR

astec

10/5/2009



3.9.2.7 Error for dynamic loading now is +/-5%

3.9.5 Update Load sharing Signal Characteristics

3.9.9.10 Update Over Voltage Requirements 6.5.1 Include New Procedure: ‘Initialization

– Calibration Registers’.

6.5.3 Update Ishare Calibration 6.5.5 Set efficiency at Nominal Low-Line to

be > 85%

6.5.7 Update Line Load Regulation Test 6.5.8 Update Ishare Linearity Test 6.5.12 Update Loading Condition on Timing

Test. Now Load-6 for 110Vac and Load-12 for 200Vac.

6.5.25 Update EEPROM FRU Test Procedure

6.6.3 Include New Tests in Redundant Operation: AC-Hot Plug and PSU-Hot Plug.

6.5.11 Update Transient Response Test. Includes Frequency and Duty of Transient Loading.

6.5 Change E-Load mode for 5Vsb. Was Constant Current is Constant Resistance.

6.5.1 Update Procedure on Initialization – Calibration Registers

6.5.3 Update Procedure on Ishare Calibration. Step #5

6.5.3 Update Ishare limit at step #10 and step #11.

6.5.4 Include Vin/In/Pin/Vout/Iout/Pout Calibration Test

6.5.7 Line/Load Regulation test, change Vin. For Low-Line is 110Vac/63Hz and for High-Line is 200Vac/47Hz

6.5.9 Include PMBus Accuracy Test 6.5.10 Ripple/Noise test, change Vin. For

Low-Line is 110Vac/63Hz and for High-Line is 200Vac/47Hz. Change limit for 5Vsb. Was 100mVpp is 150mVpp.



is 150mVpp. Change Loading Condition.

6.5.11 Transient Response test, change Vin. For Low-Line is 110Vac/63Hz and for High-Line is 200Vac/47Hz

6.5.13 Overshoot/Undershoot test, change Vin. For Low-Line is 110Vac/63Hz and for High-Line is 200Vac/47Hz

6.5.14.3 Low Input Test, change Vin. Is 110Vac/63Hz. Fault LED during step#2 was turn-on is turn-off.

6.5.5 Efficiency and Power Factor Test. Was 90% is 89%.

6.5.10 Ripple/Noise Test. Adjust minimum loading condition to 10% of Full Load.

6.5.14.1 Delete OCP testing for 5Vsb. 6.5.9 Accuracy Test. Update Loading

Conditions

6.5.14.3 Low Input Test. Revised Procedure. 3.5 Set Minimum Load Condition:

51V@1A / [email protected]

6.5 Loading Table: Implement minimum load condition

6.5.7 Regulation. Implement minimum load condition

6.5.14.1 Update OCP Test 6.5.14.2 Update Sckt Test for 5Vsb. 6.5.14.3 Low Input Test. Update PMBus Status

Reporting

6.5.19.1 Signal Integrity for PSON#. Update PMBus Status Reporting

6.5.22 EEPROM. Include Definition Table. 6.5.23 Update EEPROM FRU test procedure 5.5 Update Burn-in Test.

6.5 6.5.1 – 3 6.5.5 – 6 6.5.7 – 8 6.5.10 – 11 6.5.13 6.5.14.1 – 3 6.5.15 – 16

Change Main output regulation from 51V to 48V.



6.5.18 6.5.19.1 – 5 6.5.23 6.5.29 6.6 6.7.3

6.5.22 Update EEPROM Data C G20091312A

Mar 11, 2009 3.9.1 Change Nominal Input For Low Line

Condition; was 110Vac, is 100Vac (default in every test, unless specified)

5.5 Burn-in Test; was based on QP-3326, is based on IPC9592

5.7 Reliability Specification Test; was Bell Core, is Telcordia

6.5 Loading Condition; was 1.413kW/2.827kW (Low Line/ High Line), is 1.5kW/3kW (Low Line/High Line)

6.5.2 Update Output Voltage Calibration; is step 1: Calib via Reg E0h to 51V step 2: Calib via Reg 22h to 48V step 3: Save via Reg 15h

6.5.3 Ishare Calibration; +5Vsb @ 0.5A during Calibration Process

6.5.4 Vin/In/Pin/Vout/Iout/Pout Calibration Test; is using HPS3000-9_Tool_Calibration_v01.04.00 (__;NORMAL;Fix CalibCodeUsage)for Pilot.xls

6.5.8 Ishare Linearity Test; Update Loading Conditions and Limits

6.5.14.1 +48V OCP Fault Report was Reg 0x79h HEX = 51 48 Reg 0x78h HEX= 51 XX Reg 0x7Bh HEX = 80 XX is Reg 0x79h HEX = 50 48 Reg 0x78h HEX= 50 XX Reg 0x7Bh HEX = 80 XX Clear Fault (Reg 0x03h) Command removed

6.5.14.2 +48V Sckt Test Fault Report was



Reg 0x79h HEX = 51 48 Reg 0x78h HEX= 51 XX Reg 0x7Bh HEX = 80 XX is Reg 0x79h HEX = 40 18 Reg 0x78h HEX= 40 XX Reg 0x80h HEX = 20 XX Clear Fault (Reg 0x03h) Command removed +5Vsb Sckt Test Fault Report was Reg 0x79h HEX = 41 18 Reg 0x78h HEX= 41 XX is Reg 0x79h HEX = 40 18 Reg 0x78h HEX= 40 XX Reg 0x80h HEX = 04 XX

6.5.14.3 Low Input Test Procedure for decreasing the input voltage; was abruptly to 80Vac, is gradually to 75Vac. Fault Report was Reg 0x79h HEX = 49 28 Reg 0x78h HEX= 49 XX Reg 0x7Ch HEX= 10 XX is Reg 0x79h HEX = 48 38 Reg 0x78h HEX= 48 XX Reg 0x80h HEX = 10 XX Add steps (procedure) on Vin UV Recovery

6.5.15 PLD Test; Revised the entire procedure.

6.5.18 Missing Cycle Test. Line Voltage Interruption; was 12 ms, is 10 ms

6.5.22 Update EEPROM Definition Table 6.5.29 Update PMBus Test

D G20092599AMay 14, 2009

3.2 Update Mechanical Requirement

3.2.1 Update Mechanical Outline 3.2.2 Update Marking’s and Label 3.2.2.2 Update Model Label Format 3.2.2.3 Update Material of Model Label



3.2.2.4 Model Label size and format 3.2.2.4.1 Section deleted 3.2.2.4.2 Section deleted 3.2.2.3 Update Material of Model Label 3.2.2.4 Model Label size and format 6.5.2 Update Output Voltage Calibration

Procedure step 1: Calib via Reg E0h to 51V step 2: Calib via Reg 21h to 48V step 3: Save via Reg 15h

6.5.3 Update Ishare Calibration 6.5.4 Update Calibration Tool for

Vin/In/Pin/Vout/Iout/Pout Calibration Test

6.5.8 Update Ishare Linearity Test Limits 6.5.9 Update Accuracy Test 6.5.10 Ripple/Noise Test. Change back limit

for 5Vsb ripple to 100mVpp.

6.5.14.2 Update Short Circuit Testing 6.5.14.3 Include Low Input Test at High Line

Condition

6.5.22 Update EEPROM Definition Table 6.5.29 Update PMBus Testing

6.5.1 Update Initialization Values 3.8.1 Update Output Connection Pin

Designation and Illustration

3.8.3 Update Mating Connectors Pin Designation and Illustration

6.5.23 Update EEPROM FRU Test Procedure

4.3.1.1 Update FRU History 4.3.1.2 Update Programmable Devices

01 G20093614A

June 30, 2009 2.2 Output change from 51V to 48V.

Efficiency on High Line from 90% to 89%. Deleted Low Line efficiency specs.

3.5 Change output load setting from 51V to 48V.

3.7 Output was 51V is 48V. 3.9.1 Deleted Input Voltage Range for Low

Line.

3.9.1.1 Max input current was 19A is 17A. Deleted low line nominal VIN.



3.9.1.7 Holdover storage was 10msec is 12msec.

3.9.2 Main output regulation was 51V is 48V.

3.9.2.1 Output voltage was 51V is 48V. Update on Table 6.

3.9.2.2 Output voltage was 51V is 48V. Load was 58.9A is 62.5A. Deleted low line loading condition.

3.9.2.4 Output was 51V is 48V. 3.9.2.5 Output was 51V is 48V. Update on

Table 8.

3.9.2.8 Output was 51V is 48V. Changed capacitive loading on Table 9.

3.9.2.11 Main output was 51V is 48V. 3.9.3 Output was 51V is 48V. Ishare signal

name was 51V Ishare is 48V Ishare.

3.9.4 Main output was 51V is 48V. 3.9.7 Efficiency at 200Vac was 90% is 89%.

Deleted low line specs.

3.9.9.1 Main output was 51V is 48V. 3.9.9.2 Main output was 51V is 48V. Update

on Table 11.

3.9.9.3 Main output was 51V is 48V. Update on Table 12.

3.9.9.5 Logic level max for ACOK# signal was 4.80V is 5.25V.

3.9.9.7 Main output was 51V is 48V. 3.9.9.8 Add Tvstby_rise timing requirement. Main

output was 51V is 48V.

3.9.9.9 Main output was 51V is 48V. 3.9.9.10 Main output was 51V is 48V. OVP

range was 56.1V to 61.2V is 52.8V to 57.6V.

3.9.9.11 Main output was 51V is 48V. 5VSB OCP range was 110% - 125% is 110% - 140%.

3.9.9.12 Main output was 51V is 48V. 3.10.9 Update on Acoustic Requirements. 3.11.2 Application was Nemko is Demko 3.11.3 Application was Nemko is Demko 4.3.1.4 PSU address was A0, A2, A4, A6 is

B0, B2, B4, B6.

5.5 Deleted low line input voltage conditions on Burn-in Test



conditions on Burn-in Test 6.4 Deleted Low Line input operating

conditions.

6.5 Deleted Load Combination A on Table 19.

6.5.1 Add note on using correct PSU address on testing.

6.5.5 Delete efficiency specs for low line. Delete all low line testing.

6.5.7 Deleted all low line testing. 6.5.8 Deleted Ishare test on half load

condition.

6.5.9 Deleted accuracy test when Vin is 110V and 120V. Vin was 140V is 180V.

6.5.10 Deleted all low line testing. 6.5.11 Deleted all low line testing. 6.5.12 Deleted timing test during Vin

110Vac. Tvout_holdup specs was 10msec is 12msec.

6.5.13 Deleted all low line testing. 6.5.14.1 Deleted low line testing during 48V

OCP. 5VSB OCP max limit was 4.1A is 4.3A.

6.5.14.2 Deleted low line testing during 48V Short Circuit.

6.5.14.3 Deleted low input testing during low line condition.

6.5.15 Deleted PLD testing during low line condition.

6.5.16 Deleted Auto-Restart testing during low line condition.

6.5.17 Deleted Brownout testing during low line condition.

6.5.18 Deleted Missing Cycle testing during low line condition.

6.5.19.4 Update levels on ACOK# signal test from low line levels to high line levels.

6.5.22 Update on FRU Content on Registers 083 – 086, 0A5 – 0A6 and on 08D. Checksum also updated.

6.5.23 The Vin setting was 100V is 200V. Load is set to 0.5A.



02

G20094356A Aug 4, 2009

1.2

Add Product Revision History for HPS3000NF-9.

1.4 2.1 2.2

Include HPS3000NF-9

1.4 Include SRN Part numbers for HPS3000NF-9

5.4 6.3.2 6.3.3

Add note on using external fan for HPS3000NF-9. Measurement delay was 10secs is 20secs. 48V regulation was 47.52V to 48.48V is 47.85V to 48.15V. Ishare limits were 7.90V to 8.10V is 7.88V to 8.12V.

6.5.22 6.6.3 6.6.5 6.6.7 6.7.2 6.6.9 6.6.10.1.1

Include HPS3000NF-9 FRU data. 48V regulation was 43.2V to 52.8V is 45.60V to 50.40V. PSU Hot-Plug test for QA Audit Only Change loading condition for 5VSB and 48V output 48V regulation was 43.2V to 52.8V is 45.60V to 50.40V. Delete Undershoot monitoring on the table 48V OCP upper limit was 80.85A is 81.25A

All Update on IPS Format Appendix B Included Assembly Wire Proper

Termination instruction

03 G20095328A Sept 25, 2009

6.3.3 Updated I share limits from 7.88V – 8.12V to 7.9V-8.1V

6.6.7 Updated minimum level of 5Vsb from 4.75V to 4.74V

1.2 Updated Revision Release Version from 01 to 02 due to update in Fan grille rack P/N from 40366121932 to 40366124830



TABLE OF CONTENTS1 REVISION LEVEL 1 1.1 IPS REVISION HISTORY................................................................................................................................................................... 1 1.2 PRODUCT REVISION HISTORY................................................................................................................................................................ 15 1.3 DESIGN AUTHORITY................................................................................................................................................................................ 16 1.4 REFERENCE DESIGN AND MANUFACTURING DOCUMENTS............................................................................................................... 16 1.5 LABEL ........................................................................................................................................................................................................ 16 2 GENERAL DESCRIPTION AND CONTENTS ......................................................................................................................17 2.1 SCOPE............................................................................................................................................................................................... 17 2.2 GENERAL PRODUCT DESCRIPTION............................................................................................................................................... 17 2.3 DEFINITIONS.................................................................................................................................................................................... 17

2.3.1 Terminology......................................................................................................................................................................... 17 2.4 ACRONYMS AND ABBREVIATIONS............................................................................................................................................... 18 3 REQUIREMENTS ...........................................................................................................................................................................19 3.1 APPLICABLE DOCUMENTS – STANDARDS AND SPECIFICATIONS............................................................................................. 19

3.1.1 External regulatory standards and requirements............................................................................................................ 19 3.1.1.1 Safety.......................................................................................................................................................................... 19 3.1.1.2 Electromagnetic compatibility (EMC).................................................................................................................. 20

3.1.2 Internal regulatory standards and requirements ............................................................................................................. 20 3.2 MECHANICAL REQUIREMENTS..................................................................................................................................................... 20

3.2.1 Mechanical outline.............................................................................................................................................................. 20 3.2.2 Marking and labels .............................................................................................................................................................. 20

3.2.2.1 Safety approval marking ......................................................................................................................................... 21 3.2.2.2 Model label format ................................................................................................................................................... 21 3.2.2.3 Material of model label ........................................................................................................................................... 21 3.2.2.4 Model label size and format ................................................................................................................................... 21 3.2.2.5 Voltage range identification ................................................................................................................................... 22 3.2.2.6 Fuse marking............................................................................................................................................................. 22 3.2.2.7 Safety earth marking................................................................................................................................................ 22

3.3 APPROACH TO TESTING................................................................................................................................................................. 22 3.4 INPUT SETTINGS AND DEFAULT ................................................................................................................................................... 22 3.5 OUTPUT LOAD SETTINGS AND DEFAULT ................................................................................................................................... 22 3.6 DEFAULT OUTPUT LOAD CAPACITANCE . ................................................................................................................................... 22 3.7 GENERAL SETTINGS ....................................................................................................................................................................... 22 3.8 CONNECTIONS................................................................................................................................................................................. 23

3.8.1 Output connection............................................................................................................................................................... 23 3.8.2 Input connection definition................................................................................................................................................ 24 3.8.3 Mating connectors............................................................................................................................................................... 25

3.9 ELECTRICAL REQUIREMENTS....................................................................................................................................................... 26 3.9.1 Input....................................................................................................................................................................................... 26

3.9.1.1 Input line current ...................................................................................................................................................... 26 3.9.1.2 Power Factor Correction ......................................................................................................................................... 26 3.9.1.3 Inrush current ............................................................................................................................................................ 26 3.9.1.4 Leakage current......................................................................................................................................................... 26 3.9.1.5 Input fusing................................................................................................................................................................ 26 3.9.1.6 Power line transient protection............................................................................................................................... 26 3.9.1.7 Holdover Storage...................................................................................................................................................... 27 3.9.1.8 AC under voltage tolerance .................................................................................................................................... 27

3.9.2 Output.................................................................................................................................................................................... 27 3.9.2.1 Regulation.................................................................................................................................................................. 27 3.9.2.2 Load range ................................................................................................................................................................. 27 3.9.2.3 No Load Operation................................................................................................................................................... 27 3.9.2.4 Grounding.................................................................................................................................................................. 28 3.9.2.5 Output ripple ............................................................................................................................................................. 28



3.9.2.6 Dynamic load ............................................................................................................................................................ 28 3.9.2.7 Capacitive load.......................................................................................................................................................... 28 3.9.2.8 Remote Sensing ........................................................................................................................................................ 28 3.9.2.9 Hot Swap Requirements (Up to 4 power supplies in Parallel) ......................................................................... 28 3.9.2.10 Output Isolation/ ORing Diode .............................................................................................................................. 29

3.9.3 Forced Load Sharing .......................................................................................................................................................... 29 3.9.4 Load sharing Control .......................................................................................................................................................... 30 3.9.5 Load sharing Signal Characteristics................................................................................................................................. 30 3.9.6 Standby Load Sharing ........................................................................................................................................................ 30 3.9.7 Efficiency ............................................................................................................................................................................. 30 3.9.8 Line Transient Deviation and Response.......................................................................................................................... 30 3.9.9 Housekeeping....................................................................................................................................................................... 30

3.9.9.1 5VSB Standby........................................................................................................................................................... 30 3.9.9.2 Remote ON/OFF (PSON#)..................................................................................................................................... 31 3.9.9.3 Power Good (PWOK#)............................................................................................................................................ 31 3.9.9.4 Power Supply Present Indicator (PRESENT#) .................................................................................................... 32 3.9.9.5 AC Input Present Indicator (ACOK#) .................................................................................................................. 32 3.9.9.6 I2C signal Characteristics ....................................................................................................................................... 32 3.9.9.7 LED Indicators.......................................................................................................................................................... 32 3.9.9.8 Timing or sequence.................................................................................................................................................. 33 3.9.9.9 Protection................................................................................................................................................................... 34 3.9.9.10 Over voltage protection........................................................................................................................................... 34 3.9.9.11 Over current/short circuit protection..................................................................................................................... 35 3.9.9.12 Over temperature protection................................................................................................................................... 35 3.9.9.13 Fan Speed control..................................................................................................................................................... 35 3.9.9.14 I2C Devices ............................................................................................................................................................... 35

3.10 ENVIRONMENTAL ........................................................................................................................................................................... 35 3.10.1 Operating Temperature ................................................................................................................................................. 36 3.10.2 Storage temperature ....................................................................................................................................................... 36 3.10.3 Operating relative humidity ......................................................................................................................................... 36 3.10.4 Storage relative humidity ............................................................................................................................................. 36 3.10.5 Operating altitude .......................................................................................................................................................... 36 3.10.6 Storage altitude............................................................................................................................................................... 36 3.10.7 Cooling ............................................................................................................................................................................ 36 3.10.8 RoHS compliant............................................................................................................................................................. 36 3.10.9 Acoustic requirements................................................................................................................................................... 36 3.10.10 Vibration/Shock............................................................................................................................................................. 36

3.11 SAFETY APPROVAL......................................................................................................................................................................... 36 3.11.1 UL 60950......................................................................................................................................................................... 37 3.11.2 EN60950 Apply for Demko + CB Report ................................................................................................................ 37 3.11.3 EN60950 Deviations Apply for Demko + CB Report............................................................................................. 37 3.11.4 CHINA CCC APPROVAL:......................................................................................................................................... 37 3.11.5 POE Internal Safety Qualification .............................................................................................................................. 37 3.11.6 CSA 22.2 No. 60950 ..................................................................................................................................................... 37 3.11.7 Conducted EMI.............................................................................................................................................................. 37 3.11.8 Radiated EMI.................................................................................................................................................................. 37

3.12 ELECTROMAGNETIC COMPATIBILITY/INPUT TRANSIENTS....................................................................................................... 38 3.13 PACKING AND SHIPPING................................................................................................................................................................. 38 3.14 CUSTOMER APPROVAL .................................................................................................................................................................. 38 4 PROGRAMMABLE DEVICES ...................................................................................................................................................38 4.1 LOADED DEVICE SPECIFICATION ................................................................................................................................................. 39 4.2 LOADED DEVICE SPECIFICATION FOR EEPROM FIRMWARE.................................................................................................. 39 4.3 FILES IN P/N 429- DOCUMENTS................................................................................................................................................... 39



4.3.1 Power supply field replacement unit (FRU) instruction............................................................................................... 39 4.3.1.1 FRU history ............................................................................................................................................................... 39 4.3.1.2 Programmable Device ............................................................................................................................................. 39 4.3.1.3 PIN assignments ....................................................................................................................................................... 39 4.3.1.4 Programming instruction......................................................................................................................................... 39 4.3.1.5 FRU content support document ............................................................................................................................. 40

4.3.2 Power supply commands................................................................................................................................................... 40 4.3.2.1 Device for communications.................................................................................................................................... 40 4.3.2.2 Hardware connections............................................................................................................................................. 40 4.3.2.3 Support documents for commands........................................................................................................................ 41

5 QUALITY ASSURANCE REQUIREMENTS .........................................................................................................................42 5.1 PRODUCT QA VERIFICATION........................................................................................................................................................ 42 5.2 INCOMING QUALITY CONTROL (IQC)......................................................................................................................................... 42 5.3 PROCESS INSPECTION AND AUDIT............................................................................................................................................... 42 5.4 PRODUCTION TESTING................................................................................................................................................................... 42 5.5 BURN-IN ........................................................................................................................................................................................... 43 5.6 QA AUDIT ....................................................................................................................................................................................... 43 5.7 RELIABILITY.................................................................................................................................................................................... 43 6 TEST SPECIFICATIONS ..............................................................................................................................................................43 6.1 TEST EQUIPMENT AND INSTRUMENTATION................................................................................................................................ 44 6.2 IN-CIRCUIT TEST ............................................................................................................................................................................. 44 6.3 CALIBRATION.................................................................................................................................................................................. 45

6.3.1 Initialization - Calibration Registers............................................................................................................................... 45 6.3.2 Output Voltage Calibration ............................................................................................................................................... 46 6.3.3 Ishare Calibration................................................................................................................................................................ 46 6.3.4 Vin/In/Pin/Vout/Iout/Pout Calibration Test ................................................................................................................... 49

6.4 TEST OPERATION CONDITIONS..................................................................................................................................................... 49 6.5 TEST EQUIPMENT SET-UP.............................................................................................................................................................. 50

6.5.1 Loading board or connector board setup diagram......................................................................................................... 50 6.5.2 Primary and Secondary Control Daughter Board Programming Set-up.................................................................... 50

6.5.2.1 Primary DSP.............................................................................................................................................................. 51 6.5.2.2 Secondary DSP ......................................................................................................................................................... 52

6.6 CLOSED BOX PSU TEST ................................................................................................................................................................ 52 6.6.1 Efficiency and Power Factor Test .................................................................................................................................... 52

6.6.1.1 Efficiency................................................................................................................................................................... 52 6.6.1.2 Power factor .............................................................................................................................................................. 52

6.6.2 Inrush current test (QA Audit Only)................................................................................................................................ 53 6.6.3 Line load regulation test..................................................................................................................................................... 53 6.6.4 Ishare Linearity test ............................................................................................................................................................ 53 6.6.5 Accuracy Test ...................................................................................................................................................................... 54 6.6.6 Ripple/Noise test................................................................................................................................................................. 54 6.6.7 Transient response test ....................................................................................................................................................... 55 6.6.8 Timing test............................................................................................................................................................................ 55 6.6.9 Overshoot/Undershoot test ................................................................................................................................................ 56 6.6.10 Protection test................................................................................................................................................................. 57

6.6.10.1 OCP............................................................................................................................................................................. 57 6.6.10.2 Short circuit test........................................................................................................................................................ 58 6.6.10.3 Low Input Test.......................................................................................................................................................... 59

6.6.11 PLD test (QA Audit Only) ........................................................................................................................................... 60 6.6.12 Auto Restart .................................................................................................................................................................... 60 6.6.13 Brownout test (QA Audit Only).................................................................................................................................. 61 6.6.14 Missing Cycle test (QA Audit Only).......................................................................................................................... 61 6.6.15 Signal integrity check.................................................................................................................................................... 62



6.6.15.1 PSON# ........................................................................................................................................................................ 62 6.6.15.2 Present# Pin Test...................................................................................................................................................... 62 6.6.15.3 PWOK# Loading Check.......................................................................................................................................... 62 6.6.15.4 ACOK#....................................................................................................................................................................... 63 6.6.15.5 LED response............................................................................................................................................................ 63

6.6.16 EEPROM / PROM programming ............................................................................................................................... 64 6.6.16.1 Programmable device .............................................................................................................................................. 64 6.6.16.2 EEPROM FRU Content Programming................................................................................................................. 64 6.6.16.3 EEPROM FRU test procedure ............................................................................................................................... 78 6.6.16.4 Example FRU Definition table............................................................................................................................... 79 6.6.16.5 Example power supply command library ............................................................................................................. 79 6.6.16.6 Commands for communications............................................................................................................................ 79

6.6.17 PMBus Test..................................................................................................................................................................... 80 6.7 REDUNDANT OPERATION............................................................................................................................................................... 83

6.7.1 Current Sharing - Two units in parallel.......................................................................................................................... 84 6.7.2 Regulation at Parallel Operation....................................................................................................................................... 84 6.7.3 Ripple and Noise at Parallel Operation (QA audit Only)............................................................................................. 84 6.7.4 Power Up and Power Down in Parallel Operation (QA Audit Only) ........................................................................ 85 6.7.5 PS_ON Toggling (QA Audit Only) ................................................................................................................................. 85 6.7.6 AC HOTPLUG.................................................................................................................................................................... 86 6.7.7 PSU HOTPLUG (QA Audit Only) .................................................................................................................................. 87

6.8 SAFETY TEST................................................................................................................................................................................... 87 6.8.1 Isolation test......................................................................................................................................................................... 87 6.8.2 Ground continuity test (Skip this Test) ........................................................................................................................... 88 6.8.3 Leakage current test (QA Audit Only) ............................................................................................................................ 88 6.8.4 EMI scan............................................................................................................................................................................... 88 6.8.5 Acoustic test......................................................................................................................................................................... 88 6.8.6 Burn-in testing..................................................................................................................................................................... 88 6.8.7 Audible noise test................................................................................................................................................................ 88

6.9 CUSTOMER SPECIFICATION CHECKLIST ...................................................................................................................................... 89 APPENDIX A PMBUS PROTOCOL....................................................................................................................................................90 A.1 BYTE/WORD WRITE WITH PEC........................................................................................................................................................... 90 A.2 BYTE/WORD READ WITH PEC.............................................................................................................................................................. 90 A.3 BLOCK READ WITH PEC........................................................................................................................................................................ 90 A.4 BLOCK WRITE WITH PEC...................................................................................................................................................................... 90 A.5 PACKET ERROR CHECKING (PEC)....................................................................................................................................................... 90 A.6 HPS3000-9: CRC IMPLEMENTATION.................................................................................................................................................. 91 APPENDIX B ASSEMBLY CABLE PROPER TERMINATION ................................................................................................92



LIST OF TABLES Table 1 Definitions 17 Table 2 Acronyms 17 Table 3 Output connection definition 25 Table 4 Input connection 26 Table 5 Mating Connector definition 26 Table 6Input Settings 27 Table 7 Output voltage accuracy 28 Table 8 Load Definition 28 Table 9 Output noise and ripple 28 Table 10 Capacitive load 29 Table 11 Load share output characteristics 30 Table 12 PSON# Signal characteristics 31 Table 13 PWOK# Signal characteristics 32 Table 14 ACOK# Signal characteristics 32 Table 15 LED indicators 33 Table 16 Turn On/Off timing 33 Table 17 Over Voltage Requirements 35 Table 18 Over Current Requirements 35 Table 19 Instrumentation used for testing 45 Table 20 Loading Condition 51

LIST OF FIGURES Figure 1 Output Connector PCB Component and Solder Side 22 Figure 2 Mating Connector 24 Figure 3 Timing Diagram 33 Figure 4 HPS3000-9 I2C Bus Interface Diagram 40 Figure 5 Calibration Set-up 48 Figure 6 Loading Board Set-up Diagram 45 Figure 7 JTAG Connection into the Primary and Secondary Ctrl Boards 50 Figure 8 Assembly Cable Proper Termination 89



1.2 Product Revision History

Model ID: H081 HPS3000-9 Customer Specs

P/N Primary Software

Secondary Software

Revision Release Version

Customer P/N Specs

Rev Date Issue

P/N SW Rev

P/N SW Rev

Stage

A HPS3000-9 01 12/07/07 429-66005630 A 429-66005640 A DVT

B HPS3000-9 02 09/30/08 429-66005630 A 429-66005640 A DVT

C HPS3000-9 02 09/30/08 429-66005630 B 429-66005640 B DVT

C HPS3000-9 02 09/30/08 429-66005630 D 429-66005640 C DVT2

01 HPS3000-9 02 09/30/08 429-66005630 01 429-66005640 01 PILOT

02 HPS3000-9 02 09/30/08 429-66005630 01 429-66005640 01 PILOT

Model ID: I648

HPS3000-9 Customer Specs P/N

Primary Software

Secondary Software

Revision Release Version

Customer P/N Specs

Rev Date Issue P/N

SW Rev P/N

SW Rev

Stage

01 HPS3000NF-9

03 09/30/08 429-66005630 01 429-66010720 0A PILOT

Please note that the Engineering tools (e.g. test software, calibration programs) are listed and controlled in section 1.4 and should be called in test specification.



1.3 Design Authority

This product is controlled by (AIL-Philippines/Design Team 1). 1.4 Reference Design And Manufacturing Documents

The following documents shall be used to assemble, build and test the product. Please refer to section 3.1 for design requirements documents. Please refer to BOM for the revision of the p/n. Document Description

HPS3000-9 / HPS3000NF-9 Bill of Materials 418-66006230 Circuit Diagram HPS3000-9 420-66005740 PROD SAF CHK L HPS3000-9 429-66005630 / 42966010710 SRN HPS3000-9 PRI / SRN PRI HPS3000NF-9 429-66005640 / 42966010720 SRN HPS3000-9 SEC / SRN SEC HPS3000NF-9

BOOTLOADER HPS3000-9 COMMAND SET HPS3000-9 ASTEC INDIVIDUAL PARTS AND ASSEMBLY DRAWING

HPS3000-9_Tool_Calibration_v01.04.00 (__;NORMAL;Fix CalibCodeUsage)for DVT2.xls

41766106970 MECH OUTLINE HPS3000-9 1.5 Label

Please refer to additional details and use of these documents in section 3.2.2

DESCRIPTION PRINTING FORMAT (p/n) PRINTING CONTENT (p/n) MODEL ID LABEL n/a n/a PCBA ID LABEL n/a n/a POWER RATING LABEL n/a n/a SAFETY LABEL n/a n/a SERIAL NO. LABEL n/a n/a PATENT LABEL n/a n/a WARNING LABEL n/a n/a WARRANTY START DATE LABEL

n/a n/a

LABEL 41766210180 41766210180 LABEL-BLANK n/a n/a CLEI LABEL n/a n/a FIRMWARE LABEL n/a n/a Packing label (Carton) 03900367002 03900367002



2 GENERAL DESCRIPTION AND CONTENTS

2.1 Scope

This specification covers the requirements and quality assurance provisions for HPS3000-9 and HPS3000NF-9 and offers the necessary instructions for proper testing and configuration of the model after its assembly. Any deviations from these instructions must be documented in this present file and thus approved as per procedures in place. 2.2 General Product Description

HPS3000-9 & HPS3000NF-9 (no fan version, customer must provide external airflow through the unit) are 3000-Watt switching power supplies with the following features; Power factor correction, single 48V output with a 5V stand-by aux output. This power supplies has a power density of 40-Watts / cubic inch and the efficiency shall be 89% at nominal high AC line. The form factor is 1U by 3U and may be used in single or in redundant configurations. 2.3 Definitions

2.3.1 Terminology

Within this specification, the terms ‘shall’ and ‘must’ are used to express provisions which are binding or mandatory. The terms ‘should’ or ‘may’ are used to express provisions which are desirable but not mandatory. Within this specification, all values will be interpreted as meaning true values inclusive of measurement errors and tolerance. Where a tolerance is given, then this will be interpreted as absolute. Issue: A change made to a document is reflected in a different issue. Release (Rel.): A configuration management action whereby a particular revision of hardware or software is made available for a specific purpose. Revision and release are, in this document, synonymous. However, generally, Release is the term used with legacy products or by some customer while revision is used for all new products. Revision (Rev.): A change made to a Configurable Item (model, document), that normally affects Form, Fit, and/or Function, is identified by a revision change. More generally, a new revision is required when the change is visible and/or requires tracking.



Version: A product offering a different set of functions or features. For example, two versions of a product may be a yellow version of a product as opposed to a green version; or, the same product available in yellow and green versions. These products will be characterized with a different model ID. The term version can also designate an internal software reference for a certain load module (e.g. firmware version 3.01). 2.4 Acronyms and Abbreviations

Definitions for this document are shown in Table 1. They are provided in generic terms. The application or definition may be supplemented in context in the document. The acronyms and abbreviations are shown in Table 2.

Table 1: Definition

DEFINITION IDENTIFICATION DESCRIPTION

Room temperature or 20ºC to 25ºC

Ambient When ambient is used, it shall mean “at a temperature in the 20ºC to 25ºC range” with a Relative Humidity in the vicinity of 50-70%

Vin Vdc The measured input DC voltage of the PSU Vout Vdc The measured output DC voltage of the PSU Iin A The measured input current of the PSU Iout A The measured output current of the PSU Pin W The measured input power of the PSU Pout W The measured output power of the PSU

Table 2: Acronyms

ACRONYM AND ABBREVIATIONS

DESCRIPTION

?C Degree Celsius CC Constant Current CR Constant Resistance CV Constant Voltage DC/DC Direct Current / Direct Current EMC Electromagnetic Compatibility EMI/RFI ElectroMagnetic Interference/Radio-Frequency Interference FRU Field Replaceable Unit FT1, FT2 Functional Test 1 (after assembly and in-circuit), Functional Test 2 (after BI) IEC International Electrotechnical Commission IPS Internal Product Specifications ISO International Standard Organization MTBF Mean Time Between Failure N/A Not Available or Not Applicable OCP Over current protection OVP Over voltage protection OTP Over temperature protection P/N or p/n Part Number PSU Power Supply Unit Rel. Release Rev Revision RMS Root Mean Square S/N Serial Number



ACRONYM AND ABBREVIATIONS

DESCRIPTION

TBC To Be Confirmed TBD To Be Determined UUT Unit Under Test

3 REQUIREMENTS

The following section provides a detailed list of all applicable requirements for this product. 3.1 Applicable Documents – Standards and Specifications

The following documents and standards form a part of this specification to the extent specified herein. Please refer to the requirements for applicability in whole or in part, otherwise it is for reference only. In the event of any conflict between this document and the referred document, this specification shall govern the final decision. For construction and manufacturing document, please refer to section 0. 3.1.1 External regulatory standards and requirements

3.1.1.1 Safety

Document Description

UL 60950 US and Canada Requirements EN60950 European Requirements EN60950 Deviations (CB scheme) International Requirements CCC Approval CHINA Requirements POE Internal Safety Requirement CSA 22.2 No. 60950



3.1.1.2 Electromagnetic compatibility (EMC)

Document Description

FCC Part 15, Subpart B CISPR 22/EN55022 EN61000-3-2 Harmonics EN61000-3-3 Voltage Fluctuations

IEC/EN 61000-4-2 Electromagnetic Compatibility (EMC) - Testing and measurement techniques - Electrostatic discharge immunity test. +/-15KV air, +/-8KV contact discharge, performance Criteria B

EN 61000-4-3 Radiated Susceptibility

80 – 1000Mhz, 10V/m, AM 80% (1Khz), 900Mhz, 10V/M, PM 100% (200Hz), Criteria A

IEC/EN 61000-4-4

Electromagnetic Comp atibility (EMC) - Testing and measurement techniques, Electrical Fast Transient/Burst Immunity Test. 2KV for AC power port, 1.0KV for DC ports, I/O and signal ports performance Criteria B

IEC/EN 61000-4-5

Electromagnetic Compatibility (EMC) - Testing and measerement techniques – 2KV common mode and 1KV differential mode for AC ports and 0.5kV differential mode for DC power, I/O and signal ports, performance criteria B.

IEC/EN 61000-4-11

Electromagnetic Compatibility (EMC) - Testing and measurement techniques : Voltage Dips and Interruptions: 30% reduction for 500ms-Criteria B>95% reduction for 10mS, CriteriaA, >95% reduction for 5000mS, Criteria C

EN55024:1998 Information Technology Equipment-Immunity Characteristics, Limits and Method of Measurements

EN 61000-4-3 Conducted Susceptibility 0.15 – 80Mhz, 10V/m, AM 80% (1Khz), Criteria A

3.1.2 Internal regulatory standards and requirements

Please refer to section 1.4 3.2 Mechanical Requirements

The unit shall conform to the mechanical drawings (including assembly drawings) listed in section 1.4 within the tolerances stated. Materials and finishes are defined in the individual part drawings. 3.2.1 Mechanical outline

The unit shall conform to the mechanical outline drawings listed in section 1.4 within the tolerances stated. 3.2.2 Marking and labels

Marking shall be permanent and legible. For label location, refer to assembly drawings listed in section 0.



Model number label shall be as specified on the drawing (which includes Astec name or logo, location of manufacture, model number, serial number, and date code for examples). Customer part number and revision level should also be included as necessary. Please refer to Section 1.2 for revision information. The list of labels is available in section 1.5 3.2.2.1 Safety approval marking

The unit must have the following logo: cUL, UL, Demko, CE, and CCC which must be as near as possible to the Model Number Label. For authorized use of product safety labels, refer to the latest and separate listing from product safety group. 3.2.2.2 Model label format

The list of labels is available in section 1.5 3.2.2.3 Material of model label

The list of labels and material is available in section 1.5 3.2.2.4 Model label size and format

The list of labels is available in section 1.5 3.2.2.4.1 Item required on label Item 1. Date code Item 2. Model revision Item 3. Serial number bar code Item 4. Serial number (Human Readable) Item 5. A/C code: STD Item 6. Country of origin e.g. “Made in China” for AECL, FuYong (or Bao’an) “Made in Philippines” for APHI Item 7. Country code 1) “AI” for Taiwan A/C where made in China 2) Blank for AMSB & APHI Item 8. Safety factory code

Refer to safety procedure CPSS102-06 Item 9. Date Bar Code Item10. Model Revision Bar Code



3.2.2.4.2 Label printing requirement Refer to the label drawing for further details. See section 1.5 for p/n. 3.2.2.5 Voltage range identification

The power supply will automatically detect the voltage range it is ON. 3.2.2.6 Fuse marking

F800: F25AH/250 F801: F25AH/250 3.2.2.7 Safety earth marking

Safety EARTH marking is located near AC Line and AC Neutral input connectors. Screw is used to connect PSU EARTH to Chassis. 3.3 Approach To Testing

Unless otherwise specified, all voltages and currents provided in this document are referenced to the unit's input or output connection termination points and include the input and output connection losses (of the unit). The complete assembly shall be given a thorough visual inspection for proper soldering, component and assembly prior to performing the electrical tests. 3.4 Input Settings And Default.

Unless otherwise specified, use AC source for input voltage supply. 3.5 Output Load Settings And Default.

Unless otherwise specified, all of the outputs electronic loads shall be set to constant current mode. Minimum load shall be set as 1A for 48V output and 0.5A for 5V standby. 3.6 Default Output Load Capacitance.

No minimum capacitive load specified on customer specification. 3.7 General Settings

Unless otherwise specified, when the PSON# switch is de-asserted (48V o/p is disabled).



3.8 Connections 3.8.1 Output connection

Figure 1:Output Connector PCB Component and Solder Side

CON 1.25 CON 1.26

CON 1.1 CON 1.2

Component Side Top Row Solder Side Bottom Row



Table 3: Output connection definitions

Signal Pin #

Comp Side Top Row

Signal Function

Signal Description

Signal Pin # Solder Side

Bottom Row

Signal Function

Signal Description

CON 1.25 ISHARE Load share Bus CON 1.26 A0 I2C address bit 0 CON 1.23 #ALERT CON 1.24 A1 I2C address bit 1 CON 1.21 PSON# Power enable input CON 1.22 PSKILL CON 1.19 HVCC 5 - 6V Output CON 1.20 A2 I2C address bit 2 CON 1.17 SDA I2C data signal CON 1.18 SCL I2C clock signal CON 1.15 DCOK/PWOK Pwr OK output CON 1.16 UNUSED CON 1.13 PRESENT# Power Supply Present CON 1.14 ACOK# AC input present CON 1.11 STBY_RTN_SENSE CON 1.12 UNUSED CON 1.9 V_STBY STANDBY CON 1.10 SYS_GND STANDBY GND

CON 1.7 +48V_RTN MAIN OUTPUT CON 1.8 +48V_RTN MAIN OUTPUT

CON 1.5 +48V_OUT MAIN OUTPUT RETURN

CON 1.6 +48V_OUT MAIN OUTPUT RETURN

CON 1.3 NEUTRAL AC INPUT CON 1.4 NEUTRAL AC INPUT

CON 1.1 LINE AC INPUT CON 1.2 LINE AC INPUT

3.8.2 Input connection definition

For Functional Test (NHR – initial testing), the following connection applies

Table 4: Input Connection No. Designation Identification Terminal Type T1 VINP Input Voltage Positive C20 AC input connector 20A/125Vac – 16A/250Vac T2 VINN Input Voltage Negative C20 AC input connector 20A/125Vac – 16A/250Vac T3 SGND Surge Ground C20 AC input connector 20A/125Vac – 16A/250Vac



3.8.3 Mating connectors

Use PCB edge connector CTR-CARD EDGE C-200709, Emerson P/N is 13866007130.

Figure 2: Mating Connector

Table 5: Mating Connector definitions

Bottom side (left to right) Top side (left to right) Pin 1 AC Line Pin 64 AC Line Pin 2 AC Line Pin 63 AC Line Pin 3 no pin Pin 62 no pin Pin 4 AC Neutral Pin 61 AC Neutral Pin 5 AC Neutral Pin 60 AC Neutral Pin 6 no pin Pin 59 no pin Pin 7 no pin Pin 58 no pin Pin 8 no pin Pin 57 no pin Pin 9 +48Vdc out Pin 56 +48Vdc out Pin 10 +48Vdc out Pin 55 +48Vdc out Pin 11 +48Vdc out Pin 54 +48Vdc out Pin 12 +48Vdc out Pin 53 +48Vdc out Pin 13 +48Vdc out Pin 52 +48Vdc out Pin 14 +48Vdc out Pin 51 +48Vdc out Pin 15 +48Vdc out Pin 50 +48Vdc out Pin 16 +48Vdc RTN Pin 49 +48Vdc RTN Pin 17 +48Vdc RTN Pin 48 +48Vdc RTN Pin 18 +48Vdc RTN Pin 47 +48Vdc RTN Pin 19 +48Vdc RTN Pin 46 +48Vdc RTN Pin 20 +48Vdc RTN Pin 45 +48Vdc RTN Pin 21 +48Vdc RTN Pin 44 +48Vdc RTN Pin 22 +48Vdc RTN Pin 43 +48Vdc RTN Pin 23 no pin Pin 42 no pin Pin 24 V_STBY Pin 41 SYS_GND Pin 25 STBY_RTN_SENSE Pin 40 UNUSED Pin 26 PRESENT# Pin 39 ACOK# Pin 27 DCOK/PWOK# Pin 38 UNUSED Pin 28 SDA Pin 37 SCL Pin 29 HVCC Pin 36 A2 Pin 30 PSON# Pin 35 PSKILL Pin 31 #ALERT Pin 34 A1 Pin 32 ISHARE Pin 33 A0



3.9 Electrical Requirements

The Operating Characteristics are as below, unless otherwise, specified in the operating conditions. Vin = 200V as appropriate Ta = 25 deg C Thermal stabilization – 30 minutes minimum 3.9.1 Input

Table 6: Input Settings PARAMETER MIN NOM MAX UNITS

Vin Range at 3000W 180 200 264 Vrms Vin Frequency 47 60 63 Hz

3.9.1.1 Input line current

17 Amps max input current, at either 200Vac. 3.9.1.2 Power Factor Correction

Harmonic Line Currents must meet IEC 1000-3-2 at 230Vac with 50% loading. 3.9.1.3 Inrush current

40 Amps peak maximum at Cold or Hot start for a 1/2 cycle at any rated input voltage decaying to the nominal value within 100 milliseconds. This test is performed at 264 VAC, hot start. 3.9.1.4 Leakage current

Leakage current shall not exceed 1.40mA at 240Vac input voltage 60Hz. 3.9.1.5 Input fusing

The AC input line shall be protected by internal fuse one for each AC Input line. Recommended fuse ratings are 25A/250V FB.

Model label specs should have wording “Caution: Double Pole Neutral Fusing” both in English and simplified Chinese translation. 3.9.1.6 Power line transient protection

The power supply front-end input shall be protected from high voltage transients by an MOV (Directly after the line fuse). In addition, switch or AC input plug bounce, shall not cause any of the power supply’s components to exceed their respective ratings or fail.



3.9.1.7 Holdover Storage

The AC line Dropout, Holdover Storage ride through shall be 12mS minimum. 3.9.1.8 AC under voltage tolerance

The power supply shall not be damaged and shall either operate properly or shut down (latching or non-latching: output load dependent) when the input voltage is less than the minimum operating voltage. 3.9.2 Output

The power supply shall provide a single main +48VDC output and a single auxiliary +5Vsb output. The 5Vsb output shall be always available when AC input power is applied to the power supply (with the exception of a fault condition that has opened the AC line fuse(s)). 5Vsb is used to power system components that must be available even when the system is powered down (standby mode). 3.9.2.1 Regulation

The +48V Output Voltage must be able to be externally programmable with the I2C interface +/- 10%.

NOTE: ENGINEERING TO INFORM MARKETING ASAP THE OUTPUT VOLTAGE CHANGE PER “BIT” THROUGH THE I2C INTERFACE.

The power supply must hold regulation limits under all operating conditions (AC Line, transient loading and output loading) as shown in Table 6.

Table 7: Output Voltage Accuracy OUTPUT MIN NOM MAX UNITS % REG 48VDC 46.1 48.00 56.1 Volts -4% to +17% 5.0Vsb +4.8 +5 +5.2 Volts ±4%

Note: The static load regulation only must be within +/-1% for the +48V output. 3.9.2.2 Load range

Table 8: Load Definitions Output No Load (Amps) Rated Load (Amps) Input Voltage (VAC) 48VDC 0 62.5 A max 180 - 264 VAC

5Vsb 0 3.0 max 180 - 264 VAC

NOTE: At 180-264Vac, the maximum rated output power is 3000watts, including the 5Vsb 3.9.2.3 No Load Operation

The power supply operation at no load shall meet all requirements with the exception of the transient loading requirements.



3.9.2.4 Grounding

The 5Vsb Return and the +48V Output Return can be tied together internally, but both are brought to the output connector of the power supply. All control signals are referenced to the 5Vsb Return. 3.9.2.5 Output ripple

48VDC ripple and noise is measured with 0.1 ?F of ceramic capacitance and 10 ?F of tantalum capacitance. 5Vsb ripple and noise is measured with 0.1 ?F of ceramic capacitance and 10 ?F of tantalum capacitance. The ripple and noise requirements shall be met between 10% – 100% load range and AC line voltages. The output noise requirements apply over a 0Hz to 20MHz bandwidth.

Table 9: Output noise and ripple Output 48VDC 5Vsb Maximum Ripple / Noise 480 mVp-p 100 mVp-p

3.9.2.6 Dynamic load

The power supply must operate within specified limits and meet regulation requirements over the following transient loading conditions. The transient load can occur anywhere within 10% - 100% of the load range of the power supply. This is tested with no additional load. The output voltage shall not exceed the +/-5% output voltage error band. 3.9.2.7 Capacitive load

The minimum capacitance is defined in section 4.6. The power supply should be able to power up and operate normally with and up to the following capacitance simultaneously present on the DC outputs:

Table 10: Capacitive Load OUTPUT CAPACITIVE

LOAD NUMBER OF POWER

SUPPLIES IN PARALLEL 48VDC 3,000?F 1 48VDC 6,000?F 2 48VDC 12,000?F 4 5VDC 200uF 1

3.9.2.8 Remote Sensing

Not applicable. 3.9.2.9 Hot Swap Requirements (Up to 4 power supplies in Parallel)

Hot swapping a power supply is the process of inserting and extracting a power supply from an operating power system. During this process the output voltage shall remain within the limits specified with the capacitive load. The hot swap test shall be conducted when the system is



operating under both static and dynamic conditions. The power supply can be hot swapped by the following methods: 1. Up to 4 power supplies may be on a single AC line. Extraction: The AC power will be disconnected from the power supply as the power supply is being extracted from the system. This could occur in standby mode or powered on mode. Insertion: The AC power will be connected to the power supply as the supply is inserted into the system and the supply will power on into standby mode or powered on mode. 2. Server management turning on the hot swapped power supply. Extraction: Server management turns off only one of the power supplies via the PSON# signal, then the power supply is removed from the system. Insertion: Power supply is inserted into the system, server management looks for power supply, depending upon the state of the system (on or off), the system then turns on the power supply via the PSON# signal or goes to standby mode operation. Many variations of the above are possible. Supplies need to be compatible with these different variations. In general, a failed (off by internal latch or external control) supply may be removed, then replaced with a good power supply, however, hot swap needs to work with operational as well as failed power supplies. The newly inserted power supply may get turned on by insertion (AC is at the internal face), by plugging AC into the external face, or by system management recognizing an inserted supply and explicitly turning it on.

Hot Plug Sequencing - The power supply shall be designed to allow connection into and removal from the system without removing power. During any phase of insertion, start-up, shutdown, or removal, the power supply shall not cause any other like modules in the system to exceed their specifications. Upon application of AC power, the Auxiliary supply shall turn on providing bias power internal to the supply 5Vsb output.

3.9.2.10 Output Isolation/ ORing Diode

The main output +48Vdc and the 5Vsb output must have an isolating device to isolate the power supply from the system power during a power supply failure or during a hot swap operation. This device must be located in the power supply.

3.9.3 Forced Load Sharing

The 48VDC output shall have active load sharing. The output must share within 10% at full load. All current sharing functions are implemented internal to the power supply by making use of the 48V IShare signal. The system connects the 48V IShare lines between the power supplies. The supplies must be able to load share with up to 4 power supplies in parallel and operate in a hot swap/redundant n+1 configuration where n =1, 2, 3, 4.



3.9.4 Load sharing Control

The power supplies load share by using a single wire Digitally Controlled Analog Current Sharing connected between the power supplies for the 48VDC output. If the load sharing is disabled by shorting the load share bus to ground, the power system must continue to operate within regulation limits for loads less than or equal to one power supply. The failure of a power supply should not effect the load sharing or output voltages of the other supplies still operating. 3.9.5 Load sharing Signal Characteristics

Table 11: Load share output characteristics ITEM DESCRIPTION MIN NOM MAX UNITS

Vshare; Iout= max Voltage of load share bus at specified max output current.

8 V

? Vshare/? Iout; Iout>1A Slope of load share bus voltage with changing load.

8 / Ioutmax V / A

Ishare sink; Vshare=8V Amount of current the load share bus output from each power supply sinks.

2.5 mA

I share source; Vshare=8V Amount of current the load share bus output from each power supply sources.

4.0 mA

Tshare ; Iout=max Delay from output voltages in regulation to load sharing active with maximum load of one power supply and two power supplies in parallel.

100 msec

3.9.6 Standby Load Sharing

Each 5Vsb / 3.0A output in the system will deliver current up to the current limit point. At this point the power supply will go into constant current mode and allow other power supplies in the system to deliver additional standby current. 3.9.7 Efficiency

>89%, at 3000w, nominal at 200Vac 3.9.8 Line Transient Deviation and Response

The maximum transient amplitude on all outputs shall be less than 1% of the nominal output voltage following an input line step of +/- 25% following an input line step of 50%. No variation or step of any input voltage between 200Vac shall cause the power supply to exceed its OVP threshold or cause damage to the power supply. 3.9.9 Housekeeping

3.9.9.1 5VSB Standby



5Vsb standby voltage may be used to power end-system circuits that are used during the powered-down state of the main output rail. 5Vsb is required for the implementation of PSON# and other host system circuits that must stay powered even when the main 48Vdc output is turned off. 3.9.9.2 Remote ON/OFF (PSON#)

The PSON# signal is required to remotely turn on/off the power supply. PSON# is an active low signal that turns on the +48VDC power rail. When this signal is not pulled low by the system, or left open, the +48VDC output turns off. The 5Vsb output remains on. This signal is pulled to a standby voltage by a pull-up resistor internal to the power supply. The power supply fan(s) shall operate at the lowest speed.

Table 12: PSON# Signal characteristics Signal Type

Accepts an open collector/drain input from the system. Pulled-up to the 3V3sb located inside the power supply.

PSON# = Low ON PSON# = Open OFF MIN MAX Logic level low (power supply ON) 0V 0.4V Logic level high (power supply OFF) 2.40V 3.40V Source current, Vpson = low 4mA Power up delay: Tpson_on_delay 5msec 400msec

3.9.9.3 Power Good (PWOK#)

PWOK# is a power good signal and will be pulled LOW by the power supply to indicate that both the outputs are above the regulation limits of the power supply. When any output voltage falls below regulation limits or when AC power has been removed for a time sufficiently long so that power supply operation is no longer guaranteed, PWOK will be de-asserted to a HIGH state. The start of the PWOK# delay time shall be inhibited as long as the +48VDC output is in current limit or the 5Vsb output is below the regulation limit.

Table 13: PWOK# Signal characteristics Signal Type

Open collector/drain output from power supply. Pull-up to 5Vsb external to the power supply.

PWOK = High Power Not Good PWOK = Low Power Good MIN MAX Logic level low voltage, Isink=4mA 0V 0.8V Logic level high voltage, Isource=200? A 2.0V 5.250V Sink current, PWOK = low 4mA Source current, PWOK = high 2mA PWOK delay: Tpwok_on 100ms 1000ms PWOK rise and fall time 100?sec Power down delay: T pwok_off 1ms 1000msec



3.9.9.4 Power Supply Present Indicator (PRESENT#)

The PRESENT# signal is primarily used to provide a mechanism by which the host system can sense the number of power supplies physically present (operational or not). This pin is connected to ground in the power supply. 3.9.9.5 AC Input Present Indicator (ACOK#)

The AC OK# signal is used to indicate presence of AC input to the power supply. This signal shall be connected to 5Vsb through a resistor on the host system side. A logic “Low” level on this signal shall indicate AC input to the power supply is present. A Logic “High” on this signal shall indicate a loss of AC input to the power supply.

Table 14: ACOK# Signal characteristics

Signal Type

Pull-up to 5Vsb through a resistor in the host system.

PRESENT# = Low Present PRESENT# = High Not Present MIN MAX Logic level low voltage, Isink=4mA 0V 0.8V Logic level high voltage, Isink=50? A 2.0V 5.250V Sink current, PRESENT# = low 4mA Sink current, PRESENT# = high 50?A

3.9.9.6 I2C signal Characteristics

Engineering to complete and add the I2C Characteristic Table. Electrically compatible with I2C Bus Specification, Version 2.1. Philips Semiconductors, January 2000. 3.9.9.7 LED Indicators

There will be a green POWER LED (PWR) to indicate that AC is applied to the PSU and standby voltage is available when blinking. This same LED should go solid when the +48VDC output is enabled and operational. There will be an Amber Power Supply Fail LED (FAIL) to indicate that the power supply has failed and a replacement of the unit is necessary. Faults including UVP, OVP, OTP, or Fan Fail when PSON# is asserted “Logic Low” shall cause the amber LED to turn on. The LED can be turned off by recycling the PSON# signal or by an AC power interruption of greater than 1 second. The LED shall be off when PSON# is NOT asserted “Logic Low”. Refer to table 13 for conditions of the LED’s:



Table 15: LED indicators POWER SUPPLY CONDITION Power LED

(GREEN) Fail LED (AMBER)

No AC power to PSU OFF OFF AC present / Standby Output On Blinking OFF Power supply DC output ON and OK ON OFF Power supply failure (includes over voltage, over temperature)

OFF ON

Current limit ON Blinking 3.9.9.8 Timing or sequence

Timing requirements for single power supply operation are defined for turn ON and turn OFF of the power supply. The output voltage must rise from 10% to within regulation limits (Tvout_rise) within 5 to 300 ms. Outputs must rise monotonically.

Table 16: Turn On/Off timing

ITEM DESCRIPTION MIN MAX UNITS

Tvout_rise Output voltage rise time from each main output. 5 300 msec

Tvstby_rise Standby risetime 5 msec

Tsb_on_delay Delay from AC being applied to 5Vsb being within regulation.

1500 msec

Tac_on_delay Delay from AC being applied to all output voltages being within regulation.

2000 msec

Tvout_holdup Time all output voltages, including 5Vsb, stay within regulation after loss of AC.

10 msec

Tpwok_holdup Delay from loss of AC to de-assertion of PWOK 5 msec

Tpson_on_delay Delay from PSON# active to output voltages within regulation limits.

5 400 msec

Tpson_pwok Delay from PSON# de-active to PWOK being de-asserted.

50 msec

Tacok_delay Delay from loss of AC input to de-assertion of ACOK#.

10 msec

Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at turn on.

100 1000 msec

Tpwok_off Delay from PWOK de-asserted to 48VDC or 5VSB dropping out of regulation limits.

1 1000 msec

Tpwok_low Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON# signal.

100 msec

Tsb_vout Delay from 5Vsb being in regulation to 48VDC being in regulation at AC turn on.

50 2000 msec



Figure 3:

Timing Diagram

AC Input

Vout

PWOK

5VSB

PSON

ACOK

T sb_on_delay

T AC_on_delay

T pwok_on

T vout_holdup

T pwok_holdup

T pson_on_delay

T sb_on_delay T pwok_o

n T pwok_off T pwok_of

f

T pson_pwok

T acok_delay

T pwok_off

T sb_vout

AC ON/OFF Cycle

PSON ON/OFF Cycle

NOTE: The PWOK Logic shown is the reverse logic that is desired; Low when OK, and High under Fault.

3.9.9.9 Protection

A protection circuit inside the power supply shall cause only the power supply’s main output to shutdown. The 5Vsb output shall remain powered on if the failure does not involve this output. When a protection circuit shuts down the 48VDC rail an AMBER LED on the front panel shall be activated. If the power supply latches off due to a protection circuit tripping, an AC cycle OFF for a maximum of 15sec must be able to reset the power supply. 3.9.9.10 Over voltage protection

The power supplies over voltage protection shall be locally sensed. The power supply shall shutdown in a latch off mode after an over voltage condition. This latch can be cleared by an AC power interruption. The values are measured at the output of the power supply DC connector.



Table 17: Over Voltage Requirements

OUTPUT MIN MAX % WINDOW 48VDC 52.8v 57.6v 110-120%

5vsb 5.5v 6.25v 110-125% 3.9.9.11 Over current/short circuit protection

The power supply shall have current limit to prevent the +48VDC output from exceeding the over current limit. The current limiting shall be of the constant current type for both the +48VDC and 5Vsb output.

Table 18: Over Current Requirements VOLTAGE OVER CURRENT LIMIT (IOUT LIMIT) +48VDC 120% minimum; 130% maximum

5Vsb 110% minimum; 140% maximum

Vout

( 5VSB ) 110% 140%

Iout limit

Iout (48VDC) 120% 130%

Vout nominal

3.9.9.12 Over temperature protection

The power supply shall be protected against over temperature conditions caused by a loss of fan cooling or excessive ambient temperature. In an OTP condition, the power supply shall be shutdown with the exception of the 5Vsb output. When the power supply temperature drops to within specified limits, the power supply shall restore the +48VDC output automatically. The OTP circuit must have built in Hysteresis such that the power supply will not oscillate on and off due to temperature recovering condition. 3.9.9.13 Fan Speed control

TBA 3.9.9.14 I2C Devices

TBA 3.10 Environmental

The unit shall be capable of withstanding the conditions described in the following sub-sections.



3.10.1 Operating Temperature

-10 to +40 deg C 3.10.2 Storage temperature

-40 to +85 deg C 3.10.3 Operating relative humidity

5 to 95% non-condensing 3.10.4 Storage relative humidity

5 to 95% non-condensing 3.10.5 Operating altitude

Up to 10, 000 feet above sea level 3.10.6 Storage altitude

Up to 30, 000 feet above sea level 3.10.7 Cooling

External fan(s), with Fan Fail and Fan Speed Control Required 3.10.8 RoHS compliant

TBA 3.10.9 Acoustic requirements

50dB(A) at 70% max load at 30degC. 3.10.10 Vibration/Shock

The HPS3000-9 power supply shall be subjected to a non-operational 5G-sine sweep from 5 Hz to 500 Hz, dwelling at resonant frequencies for 1 hour, each. All components within the power supply shall be appropriately secured to prevent failure resulting from this test. At the conclusion of any of the above referenced Shock/Vibration tests listed in this section of this document, the power supply shall be powered up under maximum rated load and shall perform within specification. 3.11 Safety approval



3.11.1 UL 60950

The supply must be recognized to UL60950 and so labeled. The recognition shall be without D3 deviations and shall include stalled fan tests. Deliver UL Conditions of Acceptability as early in as possible. Apply for CuL to cover the CSA requirement.

3.11.2 EN60950 Apply for Demko + CB Report

The supply must be certified and licensed to EN60950, Class 1, SELV, and so labeled. This certification must be done by an international safety approvals granting organization such as TUV.

3.11.3 EN60950 Deviations Apply for Demko + CB Report

The supply shall be designed to meet all EN60950 Nordic Deviations. CB Report required which includes all deviations. 3.11.4 CHINA CCC APPROVAL:

Administrative and performance requirements for the CQC China "Related Regulations of Detailed Rules and Procedures for Implementing the Safety License System of Import Commodities” in accordance with Standard GB9254

3.11.5 POE Internal Safety Qualification

PSU should be have internal qualification for POE requirements

3.11.6 CSA 22.2 No. 60950

The supply must be certified to CSA 22.2 No. 60950 Level 5 and so labeled. See UL.

3.11.7 Conducted EMI

The power supply shall meet the conducted EMI limits specified in FCC Docket No. 20780 Part 15 Subpart J Class B and the limits specified in EN55022, Level “A”.

3.11.8 Radiated EMI

The power supply shall meet the compliance to the radiated EMI limits specified in FCC Docket No. 20780 Part 15 Subpart J Class B and the limits specified in EN55022, Level “A” with a minimum of 6dB margin under the limits.

The unit shall not be considered approved and shall not carry Safety Agency logos until this has been authorized by Safety department.



3.12 Electromagnetic Compatibility/Input Transients

EN61000-3-2 Harmonics

EN61000-3-3 Voltage fluctuations

EN61000-4-2 ESD: +/-15KV air, +/-8kV contact discharge, performance Criteria B

EN61000-4-3 Radiated Susceptibility: 80 – 1000 MHz, 10V/m, AM 80% (1KHz), 900MHz, 10V/M, PM 100% (200Hz), Criteria A

EN61000-4-3 Conducted Susceptibility: 0.15 - 80 MHz, 10V/m, AM 80% (1KHz), Criteria A

EN61000-4-4 Fast Transient: 2KV for AC power port, 1.0 KV for DC power, I/O and signal ports, performance Criteria B.

EN61000-4-5 Surges: 2KV common mode and 1KV differential mode for AC power ports and 0.5 KV differential mode for DC power, I/O and signal ports, performance criteria B.

EN61000-4-11 Voltage Dips and Interruptions: 30% reduction for 500 mS – Criteria B, >95% reduction for 10 mS, Criteria A, >95% reduction for 5000 mS, Criteria C. EN55024:1998 – Information Technology Equipment – Immunity Characteristics, Limits and Method of Measurement. 3.13 Packing and shipping

Packing shall be adequate to provide protection against damage, breakage or loss during shipment and shall be of type not destroyed by opening. For packing details and pallet packing, refer p/n: 85566112490 PKG-PALLET HPS3000-9 & 85566112500 PKG-IND HPS3000-9 3.14 Customer Approval

Prior to the shipment of production, written approval from cognizant customer purchasing authority must be obtained, such that, all customer samples have been examined, tested and found to meet the requirement of the customer specification.

4 PROGRAMMABLE DEVICES



4.1 Loaded Device Specification

4.2 Loaded Device Specification for EEPROM Firmware

4.3 Files In P/N 429- Documents

Part Number begins with 429 defined as SOURCE DISK. For all power supply with programmable devices, it is advised to use this section of part number for controlling FRU content, MCU content, and suggested testing software in document control. A full package of source disk for a power supply with programmable device may include:

?? IMAGE FILE OF NON-FRU CONTENT – IN FILE FORMAT ?? FRU DEFINITION TABLE – IN DOCUMENT FORMAT ?? RELATED COMMAND LIBARARY – IN DOCUMENT FORMAT ?? REFERENCE SOFTWARE FROM DESIGN ENGINEERING – IN FILE FORMAT

4.3.1 Power supply field replacement unit (FRU) instruction

4.3.1.1 FRU history

DATE OF RELEASE

(MM/DD/YYYY)

ISSUE REVISION PART NUMBER

1 A 42966005660

4.3.1.2 Programmable Device

This power supply shall be equipped with a (256 x 8) bit serial EEPROM. The following customer approved manufacturer part numbers of EEPROM shall be used:

?? Microchip 24LC02BT-E/ST or equivalent 4.3.1.3 PIN assignments

Five pins are allocated for the FRU information on the Power Supply connector. One pin is the Serial Clock (SCL). The second pin is used for Serial Data (SDA). Both pins are bi-directional and are used to form a serial I2 C bus. EEPROM address lines A0, A1 and A2 are to indicate to the power supply’s EEPROM which position the power supply occupies in the power bay. 4.3.1.4 Programming instruction



Below table showed command of address byte with combination of EEPROM Address. EEPROM ADDRESSING TABLE FOR WRITING

* A2 is pulled LOW internally in the power supply

**It is the default EEPROM address when A0 and A1 are left open.

Default Address for this model is 0xB6.

4.3.1.5 FRU content support document

FRU Data Format - The FRU data format shall be compliant with the IPMI V2.1 specifications. The current versions of these specifications are available at Astec Marketing (Rich Hannon) and / or Astec Eastwood Engineering, (Nonoy Neri) or at; http://developer.intel.com/design/servers/ipmi/spec.htm. 4.3.2 Power supply commands

4.3.2.1 Device for communications

DSP (IC506, P/N 22166013930) is used for I2C management, and report status of power supply.

4.3.2.2 Hardware connections

A2* A1 A0 Address

Low Low Low 0xB0

Low High Low 0xB4

Low Low High 0xB2

Low High High 0xB6 **



4.3.2.3 Support documents for commands

A comprehensive command summary is documented in 42966005660.

SYSTEM BACKPLANE PSU Side

PSU MONITOR FUNCTION PSU MICRO CONTROLLER

5VSB

5k 5k 10k 10k

A

SC

SD

A

A

FRU DATA EEPROM

SYSTEM BACKPLANE PROCESSOR

GND

Interconnect

SD

A

A

SC

Figure 4: HPS3000-9 I2C BUS INTERFACE DIAGRAM



5 QUALITY ASSURANCE REQUIREMENTS

5.1 Product QA Verification

Detailed inspection, functional test, environmental test and reliability test are to be carried out at both design and manufacturing stages. The procedure shall be in line with QA Product Verification Procedure QP3201. The Compliance, Requirements and Traceability Matrix shall be completed as per QP3411. 5.2 Incoming Quality Control (IQC)

Samples will be drawn from every lot delivered according to the MIL-STD-105E inspection level II. Procedure followed is per the Incoming Material Inspection Procedure.. Incoming quality control will be carried out in accordance with the relevant procedures of the factory where the product is built unless specified otherwise by a specific quality plan. The inspection criteria will be in line with the Part Specification or Drawings. For mechanical parts and assemblies manufactured by an outside supplier, please use QP3408, Mech. Parts First Article Inspection Procedure. 5.3 Process Inspection And Audit

Process inspection and audit will be carried out in accordance with the relevant documents of the factory where this model will be built.. Subassemblies and final assembly must conform to the applicable specification, drawings and Workmanship standard QP4601. 5.4 Production Testing

Testing shall be carried out to assure that the design specification of the UUT not being affected by manufacturing process. Please refer to Section 6 for the test specifications or reference to it. Note: HPS3000NF-9 MUST have an external fan to direct airflow through the PSU. CFM MUST be 20.6CFM or higher.



5.5 Burn-in

For DVT Stage: Ambient Test Temperature 35°C +/-5°C AC power cycling ½ hour on and ½ hour power off Output Loading 80%-100% loading

AC input: 200-240Vac: Loading Condition: +48V / 49.75A to 62.19A, +5Vsb / 2.4A to 3A

AC Input: ALL units will have an AC input of 200-240 VAC Monitoring: Monitoring: PWOK must be monitored during burn-in test. Monitoring

must be often enough that an intermittent failure that could be reset by an AC power cycle is not missed.

Burn in Time: 24Hrs for first 1,000 units, quality can reduce burn-in over time when reliability is sufficient to do so. For Pilot and MP Stage: All units will be subjected to a burn-in process and shall be based on QP3775 Manufacturing Burn-in Procedure. 5.6 QA Audit

All units, which pass QC final test and packaging, will be randomly sampled by QA audit team. QA audit procedure referred to QP 209-03 Final Audit and Test Procedure. 5.7 Reliability

The power supply has a minimum MTBF of 300K hours using the Telcordia specification @ 25 degrees C and 40 degrees C, ambient, at full load. With the power supply installed in a system in a 25 degree C ambient environment and operating at full load, capacitor life shall be 10 years, minimum for ALL electrolytic capacitors contained within this power supply. The power supply shall demonstrate a MTBF level of > 500,000 hours.

6 TEST SPECIFICATIONS

The following section provides a detailed list of all applicable requirements for this product. These parameters are the major worst-case conditions at 25?C and have to be tested but not necessarily at final test. It is not the intention of this section to abrogate the Test Engineers’ responsibility for ensuring conformance with the rest of this specification. Audits testing and margining are techniques that may be appropriate for tests like EMI and performance over temperature range.



6.1 Test Equipment and Instrumentation

The purpose is to ensure the list if complete and that any special needs or capability is fully clear and addressed. This table represents a standard set; equivalent test equipment can be used as needed. However any special settings, capability MUST be clearly identified.

Table 19: Instrumentation used for testing

Description (Manufacturer and Model) Remarks Digital Multimeter DC (may be built in DC source and loads)

Regulated DC power Supply Digital Oscilloscope (4 channels) Digital Oscilloscope (4 channels) Thermal meter Current Probe for the Digital oscilloscope Current Amplifier Dielectric Strength Tester Power Analyzer PM100 or equivalent Kikusui PLZ 153W Electronic load or equivalent

Chroma63203 Electronic load or equivalent Waveform generator 1 PC with WINDOWS 95 or greater, and parallel/printer port and with USB connectors

1 I2C adapter 1USB adapter

For engineering tools, which usage is described below, please refer to section 1.4 for correct part numbers. 6.2 In-circuit Test

Perform in-circuit test to ensure correct components assembly. During such tests, care must be taken to test each I/O separately and not only as a group (multiple pins sued for one output: need to ensure connection of each pad, pin)



6.3 Calibration Prior to power-up, calibration shall be performed. 6.3.1 Initialization - Calibration Registers *Take note of the PSU Address on Item 4.3.1.4. Signal A1 must be connected to SYS_GND to set PSU address B2.

Initial conditions:

Item Condition Vin 200V 47Hz PS_ON# High PS KILL Low 5Vsb Load 0.5A +48V Load 29.26

Write Default Values to Calibration registers. S B2 W E0 B3 59 P S B2 W 21 00 66 P S B2 W FF 01 00 00 00 00 00 P S B2 W EC 03 00 EB 3E P S B2 W EC 03 01 1B 4F P S B2 W EC 03 02 37 00 P S B2 W EC 03 03 33 06 P S B2 W EC 03 04 15 00 P S B2 W EC 03 05 42 06 P S B2 W EC 03 06 5C 00 P S B2 W EC 03 07 BC 3F P S B2 W EC 03 08 6A C2 P S B2 W EC 03 09 97 2A P S B2 W EC 03 0A 86 F5 P S B2 W EC 03 0B 87 20 P S B2 W EC 03 0C 70 FF P S B2 W EC 03 0D C9 8D P S B2 W EC 03 0E 75 47 P S B2 W EC 03 0F ED FB P S B2 W EC 03 10 BD 1F P S B2 W EC 03 11 ED FF P S B2 W EB 55 55 P S B2 W 15 P Then perform AC recycle.



6.3.2 Output Voltage Calibration

Initial conditions: Item Condition Vin / Fin 200V 47Hz PS_ON# Low 5Vsb Load 0.5A +48V Load 29.26A

1. Set PS_ON# to Low and Wait for 20sec.

2. Measure 48V O/P.

Vm = ______

3. Turn PS_ON# to HIGH.

4. Calculate for the value of Reg E0h.

VmVn

22963*51?

LB = Vn MOD 256

HB = Vn / 256

5. Write the value of Reg E0h and 21h. Store by writing to Reg 15h (STORE_ALL command).

S B2 W E0 LB HB P S B2 W 21 00 60 P S B2 W 15 P

6. Turn-off PSU for about 10s then turn it on again. Turn PS_ON# to LOW. Then measure 48V O/P.

47.85V ? 48V O/P ? 48.15V Go / No Go

6.3.3 Ishare Calibration

Test Conditions: Vin = 200Vac / 47Hz +5Vsb @ 0.5A



1. Turn-on PSU with PSON# = LOW.

Load Actual Load*

Ishare (measured)

Ishare (expected)**

Iout (Raw)*** Iout (Computed)****

1.00A X1 Y1 62.19A X2 Y2

Notes: * - Actual load: measured on e-loads display ** - Ishare (Expected) = 8.00 * (Actual Load / 62.19A) *** - Iout (Raw): Read Reg F0h, convert HEX value to DEC. **** - Iout (Computed) = (Iout raw / Ishare measured) * Ishare expected

2. Set 48V load to 1A once all data has been gathered. 3. Using above data, use formula m = (Y2-Y1)/(X2-X1) and Y2 = m*X2 + b to find the slope (m)

and intercept (b). Example:

Load Actual Load*

Ishare (measured)

Ishare (expected)** Iout (Raw)*** Iout (Computed)****

1.00A 1.0687 1.085 0.137475478 3253 412.1730241 62.19A 62.231 7.99 8.00527416 25054 25101.89472

m = (25101.89472-412.1730241) / (25054-3253) = 1.132504091

b = Y2 – m*X2 = 25101.89472– (1.132504091*25054)

= -3271.862785 4. Get m2 and m1.

m2 = m TRUNC 0 ? m2 = 1.132504091TRUNC 0 m2 = 1 -Note: TRUNC or truncate is a process of removing the decimal or fractional part of a number. m1 = m – m2 ? m1 = 1.132504091– 1 m1 = 0. 132504091

5. Get b’, m2’ and m1’.

b’ = b converted into HEX form m2’ = m2 converted into HEX form



m1’ = (m1*32768) converted to HEX form Values DEC Form HEX Form

m2 = 1 ? ? 1 0001 ? m2’ m1 = 0. 132504091 m1* 32768 ? 4341.894053888

10F5 ? m1’

b = -3271.862785

? ? -3271.862785 F339 ? b’

6. Write above result to address FFh using format below:

S B2 W FF 01 00 F5 10 39 F3 P

7. Turn PSON# = HIGH. Send 15h Store_All command.

S B2 W 15 P

8. Turn PSU OFF. 9. Wait for 10sec, then turn PSU ON with PSON# = LOW. 10. Set load: 48V / 1.0A; 5VSB / 0.5A. Ishare should be within

0V > Ishare < 0.5V Go / No Go

11. Set load: 48V / 62.19A; 5VSB / 0.5A. Ishare should be within

7.9V > Ishare < 8.1V Go / No Go



6.3.4 Vin/In/Pin/Vout/Iout/Pout Calibration Test

Setup the unit as shown in Figure 5. The PSU I2C port must be connected to the I2C

adapter. The adapter must then be connected to I2C master. Use proper equipments for this test. DMM for voltages and Power Analyzer for current readings.

Figure 5: Calibration Setup

Please refer to the excel file HPS3000-9_Tool_Calibration_v01.04.00 (__;NORMAL;Fix CalibCodeUsage)for DVT2.xls for the procedures/details of readouts and computations. 6.4 Test Operation Conditions The operating conditions are as below, unless otherwise specified. Vin = 200Vac/47Hz as appropriate Ta = 25 deg. C Input frequency = 47Hz for Vin = 180Vac ~ 264Vac, Max O/P Power = 3000W

PSU

I2C adapter

I2C master

Equipme



6.5 Test Equipment Set-up 6.5.1 Loading board or connector board setup diagram

Figure 6: Loading Board Set-up Diagram

Note: R1 and R2 should be 1K0 0W25 resistor. Measure 48V, 5VSB and AC line regulations as close as possible to the UUT, see figure above for suggested test points. Also, measure PWOK# and ACOK# signals as close as possible to the UUT, test points shown above. Other signals can be connected elsewhere on the loading board (PSON#, A0, A1, etc) 6.5.2 Primary and Secondary Control Daughter Board Programming Set-up



Figure 7: JTAG Connection into the Primary and Secondary Ctrl Boards

6.5.2.1 Primary DSP

Connect the Jtag into the programming header as shown in Figure 3. Apply 3.3Vdc to FP402.6 (P3V3) with respect to FP402.1 (B-). Load the latest Primary Software revision. Get checksum and check if it same as checksum specified in latest Primary SW P/N. Refer to Section 1.2 Product revision History for latest revisions.

1.1 CPU Par

JTAG

HPS3000-9 Pri / Sec Ctrl Brd

GND pins: Red colored portion of Ribbon Cable

JTAG PIN CONFIGURATION



6.5.2.2 Secondary DSP Connect the Jtag into the programming header as shown in Figure 3. Apply 3.3Vdc to CN505.6 (S3V3D) with respect to CN505.1 (SYS_GND). Load the latest Secondary Software revision. Get checksum and check if it same as checksum specified in latest Primary SW P/N. Refer to Section 1.2 Product revision History for latest revisions.

6.6 Closed Box PSU Test

Table 20: Loading condition Loading +48V (A) +5VSB (A) No Load: Load 1 0 0 Min Load: Load 2 1 0.5 Load Combination B 25%: Load 9 15.6 0.75 50%: Load 10 31.17 1.5 75%: Load 11 46.7 2.25 FL: Load 12 62.19 3 Min-Max: Load 13 1 3 Max-Min: Load 14 62.5 0.5

6.6.1 Efficiency and Power Factor Test

The power supply efficiency (watts output/watts input) shall be equal to or greater than 89% at the maximum load with 200 VAC input. Measure efficiency after 10-15 minutes operation at 20CFM airflow. Make a graph showing efficiency versus load. 6.6.1.1 Efficiency

Load Combination B

Input Voltage Specs FL: Load 12

200Vac/47Hz > 89% 6.6.1.2 Power factor



Load Combination B

Input Voltage 50%: Load 10 (>=0.97)

FL: Load 12 (>=0.97)

200Vac/47Hz

6.6.2 Inrush current test (QA Audit Only)

Vin = 264Vac/ 47Hz Loading Condition: (FL: Load 12) Inrush Current < 40Apk, AC is turn on at 90° phase angle Inrush Current < 40Apk Go/No Go 6.6.3 Line load regulation test

The power supply must hold regulation limits under all operating conditions (AC line and output loading). Connect a Pull-up Resistor (about 1K? ) on PWOK# signal to the +5VSB in testing Line Regulation. Vin = 200VAC/47Hz

OUTPUT VOLTAGES (V) LIMITS (V) Loading Condition +5VSB +48V +48V +5VSB

Min Load: Load 2 45.60 – 50.40 4.80 – 5.20 50%: Load 10 45.60 – 50.40 4.80 – 5.20 FL: Load 12 45.60 – 50.40 4.80 – 5.20 Max-Min: Load 14 45.60 – 50.40 4.80 – 5.20 With PSON# high: Vin = 200VAC/47Hz

LOAD (A) OUTPUT VOLTAGES (V) LIMITS (V) +48V +5VSB +5VSB +48V +48V +5VSB

0 0 < 0.8 V 4.80 – 5.20 0 1.5 < 0.8 V 4.80 – 5.20 0 3.0 < 0.8 V 4.80 – 5.20

6.6.4 Ishare Linearity test

Measure ISHARE at different load conditions AT 200Vac/47Hz input. Measure ISHARE by DMM.

Input (Vac)/Load Condition (A) Vac 5VSB 48V

ISHARE (V) Specs Range (V)

0.5 1 0 - 0.9 200 0.5 62.19 7.8 – 8.2



6.6.5 Accuracy Test

Vin and Iin Accuracy Test Condition Vin (Reg 0x88h) Iin (Reg 0x89h)

Vin (60Hz)

Iout PMBus Rdng

Actual Val

Req %Error

PASS /FAIL

PMBus Rdng

Actual Val

Req %Error

PASS /FAIL

180 31.09 5.000% 5.000% 200 24 5.000% 5.000% 230 40 5.000% 5.000% 264 62.19 5.000% 5.000%

Vout and Iout Accuracy Test

Condition Vout (Reg 0x8Bh) Iout (Reg 0x8Ch)

Vin (60Hz)

Iout PMBus Rdng

Actual Val

Req %Error

PASS /FAIL

PMBus Rdng

Actual Val

Req %Error

PASS /FAIL

180 31.09 5.000% 5.000% 200 24 5.000% 5.000% 230 40 5.000% 5.000% 264 62.19 5.000% 5.000%

Pin and Pout Accuracy Test

Condition Pin (Reg 0x97h) Pout (Reg 0x96h)

Vin (60Hz)

Iout PMBus Rdng

Actual Val

Req %Error

PASS /FAIL

PMBus Rdng

Actual Val

Req %Error

PASS /FAIL

180 31.09 5.000% 5.000% 200 24 5.000% 5.000% 230 40 5.000% 5.000% 264 62.19 5.000% 5.000%

6.6.6 Ripple/Noise test

48VDC ripple and noise is measured with 0.1 ?F of ceramic capacitance and 10 ?F of tantalum capacitance. 5Vsb ripple and noise is measured with 0.1 ?F of ceramic capacitance and 10 ?F of tantalum capacitance. The ripple and noise requirements shall be met between10% – 100% load range and AC line voltages. The output noise requirements apply over a 0Hz to 20MHz bandwidth.

Vin = 200Vac/47Hz Loading Condition OUTPUT VOLTAGES (V)

48V 5VSB 5VSB 48V FL: Load 12

Max-Min: Load 14 6.219 3.0

Limits Max 100mVpp 480mVpp



6.6.7 Transient response test

The power supply must operate within specified limits and meet regulation requirements over the following transient loading conditions. The transient load can occur anywhere within 10% - 100% of the load range of the power supply. This is tested with no additional bulk capacitance. The output voltage shall not exceed the +/-5% output voltage error band.

RAIL Frequency / Duty SLEW RATE

(A/usec)

CAPACITIVE LOAD (uF)

Minimum (V)

Maximum (V)

5VSB 50Hz / 50% 0.5 0uF 4.74 5.25 48V 50Hz / 50% 1.0 0uF 45.6 50.4

Vin = 200VAC/47Hz Note: Output not under test will be loaded to: 48Vdc/1A; 5VSB/0.5A

Output Under Test

Load Condition (A)

Overshoot (V) Undershoot (V)

5VSB 0.3 – 1.5 5VSB 1.5 – 3.0 48V 6.22 – 31.09 48V 31.09 – 62.19

6.6.8 Timing test

Test Conditions: Vin = 200V / 47 Hz (FL: Load 12)

Turn On/Off Timing


Tvout_rise Output voltage rise time from each main output. 5 300 msec Tsb_on_delay Delay from AC being applied to 5Vsb being within

regulation. 1500 msec

Tac_on_delay Delay from AC being applied to all output voltages being within regulation.

2000 msec

Tvout_holdup Time all output voltages, including 5Vsb, stay within regulation after loss of AC.

12 msec

Tpwok_holdup Delay from loss of AC to de-assertion of PWOK 5 msec



Turn On/Off Timing


Tpson_on_delay Delay from PSON# active to output voltages within regulation limits.

5 400 msec

Tpson_pwok Delay from PSON# de-active to PWOK being de-asserted.

50 msec

Tacok_delay Delay from loss of AC input to de-assertion of ACOK#.

10 msec

Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at turn on.

100 1000 msec

Tpwok_off Delay from PWOK de-asserted to 48VDC or 5VSB dropping out of regulation limits.

1 1000 msec

Tpwok_low Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON# signal.

100 msec

Tsb_vout Delay from 5Vsb being in regulation to 48VDC being in regulation at AC turn on.

50 2000 msec

6.6.9 Overshoot/Undershoot test

Any overshoot at turn on or turn off shall be less than 5% of the nominal value and must decay to within regulation band within 50 ms.

Test Condition: 200Vac/47Hz (FL: Load 12)

FL: Load 12: +48V/62.19A, +5VSB/3.0A

Specs requirements: 1. The output voltage overshoot /undershoot during the turn-on shall be less than +/-5%

of nominal voltage setting. 2. Output should settle into the regulation within 50ms. 3. There must be a smooth and continuous ramp of each DC output voltage from 10% to

95% of its final set point within the regulation band. (Monotonic rise time). 4. Output should rise monotonically with no negative slope.

Output Rail

+48V +5VSB Turn ON

using:

Load condition

Overshoot Non

monotonic Overshoot Non

monotonic Min V V PS_ON

asserted Max V V Min V V

AC Max V V



6.6.10 Protection test

6.6.10.1 OCP

Test Condition: Test2 – Vin = 200Vac/47Hz; Load Condition: (FL: Load 12)

Note: XX corresponds to the computed CRC for the power supply address plus the data.

6.6.10.1.1 +48V Output OCP Load

a) Set PSU to initial settings as mentioned above, the PSU must not shutdown. b) Gradually increase the +48V O/P load current at a rate of 1A/sec until unit shutdown.

At Vin = 200Vac; Measured Load Current = 74.63A ? 48V OCP? 81.25A Go / No Go c) POK LED must be solid and Fault LED Amber must turn into blinking mode Go / No Go d) Read PMBus Status Registers through SCL and SDA Reg 0x79h must be HEX = 51 58 or 51 48 Go/No Go Reg 0x78h must be HEX= 51 XX Go/No Go Reg 0x7Bh must be HEX = A0 XX Go/No Go e) Set output load current to initial current set condition then recycle PSON#, output should

recover. Fault LED must turn OFF and POK LED must be solid. f) Read PMBus Status Registers through SCL and SDA Reg 0x79h must be HEX = 00 00 Go/No Go Reg 0x78h must be HEX= 00 XX Go/No Go Reg 0x7Bh must be HEX = 00 XX Go/No Go

6.6.10.1.2 +5VSB OCP a) Increase the load at a rate of 0.05A/sec until output latch.

Measured Load Current = 3.3A ? 5V OCP ? 4.3A Go/No Go b) +48V must also shutdown, Fault LED Amber must turn SOLID and Power LED Green

must turn-off. Go/No Go c) Read Pmbus Power Status Register through SCL and SDA

Reg0x 79h must be HEX = 40 18 XX Go/No Go Reg0x78h must be HEX = 40 XX Go/No Go Reg 0x80h must be HEX = 04 XX or 44 XX or 40XX Go/No Go d) Set back load to 3A, 5VSB and +48V must both recover. Fault LED must turn OFF.



POK LED must turn solid green. Go/No Go e) Clear Fault by performing the procedure below via I2C.

S B2 W 03 P f) Read Pmbus Power Status Register through SCL and SDA

Reg0x79h must be HEX = 00 00 Go/No Go Reg0x78h must be HEX = 00 XX Go/No Go Reg 0x80h must be HEX = 00 XX

6.6.10.2 Short circuit test Initial condition Test Condition: Vin = 200Vac/47Hz (Min Load: Load 2) 6.6.10.2.1 +48V output a) Short +48V output to 48V_RTN, +48V output must shutdown, 5VSB must remain ON. Go/No Go

b) Read Pmbus Status Registers through SDA and SCL. Reg 0x79h must be HEX = 40 18 Go/No Go Reg 0x78h must be HEX= 40 XX Go/No Go

Reg 0x80h must be HEX = 20 XX Go/No Go c) Fault LED Amber must be BLINKING. Power LED Green must be SOLID GREEN Go/No Go

d) Remove short, perform PSON# recycling, output must recover.

Power LED must turn-on Fault LED must turn-off Go/No Go

e) Read Pmbus Status Registers through SDA and SCL. Reg 0x79h must be HEX = 00 00 Go/No Go Reg 0x78h must be HEX= 00 XX Go/No Go Reg 0x80h must be HEX = 00 XX Go/No Go

6.6.10.2.2 +5VSB output



a) Short circuit +5VSB output to SYS_GND. +5VSB output current must fold back. +48V must turn-off Go/No Go

b) Fault LED Amber turn SOLID, Power LED Green must turn-off Go/No Go c) Read Pmbus Power Status Register through SCL and SDA

Reg0x 79h must be HEX = 40 18 Go/No Go Reg0x78h must be HEX = 40 XX Go/No Go Reg 0x80h must be HEX = 04 XX or 44 XX or 40XX Go/No Go

d) Remove 5VSB short, 5VSB and +48V output must recover. Fault LED must turn OFF. POK LED must turn solid green. Go/No Go e) Clear Fault by performing the procedure below via I2C.

S B2 W 03 P f) Read Pmbus Power Status Register through SCL and SDA

Reg0x79h must be HEX = 00 00 Go/No Go Reg0x78h must be HEX = 00 XX Go/No Go Reg 0x80h must be HEX = 00 XX

6.6.10.3 Low Input Test Initial condition Vin = 200Vac/47Hz (FL: Load 12)

1) Turn On PSU, let it stabilize for 5secs, then gradually decrease input voltage to 160Vac.Outputs should shut down. Go/No Go

2) Fault LED Amber must turn off; Power LED Green must turn off Go/No Go 3) Read PMBus Power Status Register through SCL and SDA Reg0x79h must be HEX = 48 38 Go/No Go Reg0x78h must be HEX = 48 XX Go/No Go Reg 0x7Ch must be HEX = 10 XX Go/No Go 4) Gradually increase input voltage up to 180Vac. Outputs should turn-on. Go/No Go 5) Fault LED Amber must turn off and Power LED Green must turn-on. Go/No Go 6) Read PMBus Power Status Register through SCL and SDA Reg0x79h must be HEX = 00 00 Go/No Go Reg0x78h must be HEX = 00 XX Go/No Go



Reg 0x7Ch must be HEX = 00 XX Go/No Go 6.6.11 PLD test (QA Audit Only)

The power supply must maintain “error free” operation for minimum and maximum output loading conditions when subjected to the following disturbances: 1. A line input under voltage of 25% below 240Vac input for 2 seconds, repeated ten (10) times with a 10% duty cycle. 2. A line input under voltage of 35% below 240Vac input for 500 ms, repeated ten (10) times with a 10% duty cycle. 3. A line input under voltage of 100% below 240Vac input for 10 ms, repeated ten (10) times with a 10% duty cycle.

Test2 – Vin = 240Vac; Load Condition: (FL: Load 12) Monitor the +48V O/P, +5VSB O/P and PWOK#. Perform tests at 47 and 63Hz. 1) Set the line to 240Vac and load the output up to their respective full load condition. 2) Drop the line to 180Vac for 2 seconds repeated 10 times with 10% duty cycle. 3) The outputs should remain within regulation and there should be no glitch on

PWOK#. Go/No Go

4) Set the line to 240Vac and load the output up to their respective full load condition. 5) Drop the line to 156Vac for 500 ms repeated 10 times with 10% duty cycle. 6) The outputs should remain within regulation and there should be no glitch on

PWOK#. Go/No Go

7) Set the line to 240Vac and load the output up to their respective full load condition. 8) Drop the line to 0Vac for 10 ms repeated 10 times with 10% duty cycle. 9) The outputs should remain within regulation and there should be no glitch on

PWOK#. Go/No Go

6.6.12 Auto Restart

Although the power supply may power off under these conditions, it must be capable of restarting, either automatically or under program control after the disturbance. In addition the power supply should not be in a latched state such that any of the operator buttons/switches do not operate correctly after the disturbance. At no time should the AC power cord have to be removed to clear an error condition.

Test Conditions: Test1 – Vin = 200Vac; Load Condition: (FL: Load 12)



A. Test Conditions (For Production Testing)

Input Time Duration During Input Disturbance Voltage

Input Drop 2.0s

200Vac 100% Note: = PASS = FAIL

B. Testing Conditions (For QA Audit Only)

6.6.13 Brownout test (QA Audit Only)

1) Set AC at 200VAC/47Hz and load settings at (FL: Load 12). 2) Decrease AC line voltage from the 200VAC nominal voltage to 25% of nominal at a rate 2V

per 40sec and then increase back to nominal voltage at the same rate. The power supply may turn off due to low line OCP will be triggered. PSON or AC interrupt is needed. The power supply should not generate any false PWOK signals during these conditions. Go / No Go

6.6.14 Missing Cycle test (QA Audit Only)

While operating under nominal input voltage and any permissible output loading, the power supply shall continue to operate normally when subjected to a line voltage interruption of at least 10ms from any phase angle. The term interruption means a dropout of the line to 0% followed by its re-application to 100%. Additional power supplies operating in N+N redundant mode shall continue to operate normally when subjected to a line voltage interruption of at least 20ms from any phase angle.

Test Conditions:

Test1 – Vin = 200Vac; Load Condition: (FL: Load 12)

Monitor the +5V Output, +48V Output, PWOK# and ACOK#.

-40%-50%-60%-70%-80%-90%

-100%

Note: = FAIL= PASS

200V

ac



Subject the PSU to a line voltage interruption for at least 10 times for each Line/Load conditions mentioned above. Each line interruption should have at least 10% duty cycle (ex. 90ms ON tine and 10ms OFF time).

+5VSB O/P and +48V O/P should not turn-off or latch during interruption. Go/No Go PWOK# should not go HIGH during interruption Go/No Go

6.6.15 Signal integrity check Note: All tests will be conducted under these conditions unless otherwise specified.

Test Condition:

Vin = 200Vac F = 47Hz Load Condition: (FL: Load 12) 6.6.15.1 PSON#

A) PS_ON switch to SYS_GND. B) Open PS_ON +48V must shut down, Power LED green must be blinking mode

(Amber LED must not turn-on) Go /No Go C) Read Pmbus Power Status Register through SCL and SDA

Reg0x79h must be HEX 40 08 Go/No Go Reg0x78h must be HEX 40 XX Go/No Go

D) Close PS_ON, +48V must recover, Power LED green must turn-on. Go/No Go E) Read Pmbus Power Status Register through SCL and SDA

Reg0x79h must be HEX 00 00 Go/No Go Reg0x78h must be HEX 00 XX Go/No Go

6.6.15.2 Present# Pin Test Test Condition:

PSU is OFF.

Measure resistance from – Present# pin (CON 1.13) to SYS_GND, R < 250 ohms. 6.6.15.3 PWOK# Loading Check

1) Connect a resistor = 2k2 ohms from PWOK# pin (CON 1.15) to +5VSB. 2) Turn-off the +48V by PSON# high. 3) Measure the PWOK# pin > 2.0V



4) Turn-on the +48V by PSON# low. 5) Measure the PWOK# voltage is should be <0.8V.

6.6.15.4 ACOK#

1) Connect a resistor = 2k2 ohms from ACOK# pin (CON 1.14) to +5VSB. 2) Turn On the input of PSU with PSON# low, Measure the ACOK# pin <0.8V 3) Turn-off AC Input, Measure the ACOK# pin >2.0V Test Condition: Load 1: (No Load) Load 2: (Load 12) 4) Turn On the input of PSU with PSON# low, 5) Starting from 170 VAC gradually increase line voltage (1V/sec) and record the line voltage

when the main outputs come into regulation. Increase the line voltage to 180 VAC. 6) From 180 VAC gradually reduce the line voltage (1V/sec) and record the line voltage when

the main outputs go out of regulation.

AC Input Voltage Parameter Load A Load B

Limit

ACOK# goes LOW 176 - 180Vac ACOK# goes HIGH 165 -173VAC

6.6.15.5 LED response Test Conditions: Vin= 200Vac/47Hz; Load Conditions: (FL: Load 12)

1) Power-up PSU with –PSON# “OFF”. Power LED should be BLINKING Green. Go/No Go

2) Turn-ON -PS_ON. Power LED will light “Green”.

Go/No Go 3) Load short +5Vsb out.

Fault LED must light “Solid Amber” while the Power LED must turn-off. Go/No Go

4) Remove short, output must recover Power LED must turn-on Solid Green Fault LED must turn-off

Go/No Go 5) Load +48V to Full load and then gradually increase the output load until it latches.

Fault LED should be “BLINKING” while Power Led must turn ON.



6) Set output load current to initial current set condition then recycle PS_ON, output should recover.

Power LED must turn-on solid Green. Fault LED must turn-off

Go/No Go 6.6.16 EEPROM / PROM programming

Please refer to Standard EEPROM FRU Program Specification P/N 429-66000260. Refer to

Section 1.2 Product revision history for updated revision of P/N 429-66003820 for the software used in programming the EEPROM. 6.6.16.1 Programmable device

MCU (MC56F8037VLH, P/N 22166013930 circuit code IC506) and MCU (MC56F8025, P/N 22171000310 circuit code IC434), must be programmed before undergoing production tests

6.6.16.2 EEPROM FRU Content Programming

HPS3000-9 FRU

OFFSET DEFINITION SPEC (REMARKS) VALUE COMMON HEADER, 8 bytes

000d 00h Format Version Number (Common Header) 001d 01h 001d 01h Internal Use Area Offset (In multiples of 8 Bytes) 024d 18h 002d 02h Chassis Info Area Offset (In multiples of 8 Bytes) 001d 01h 003d 03h Board Info Area Offset (Not Used) 000d 00h 004d 04h Product Info Area Offset (In multiples of 8 Bytes) 005d 05h 005d 05h Multi Record Area Offset (In multiples of 8 Bytes) 015d 0Fh 006d 06h PAD (reserved – always 00H) 000d 00h 007d 07h Zero Check Sum (256 – (Sum of bytes 000d to 006d)) 210d D2h

COMPUTER/CHASSIS INFORMATION AREA, 32 bytes 008d 08h Format Version Number (Default value is 1.) 001d 01h 009d 09h Chassis Info Area Length (Default value is 0.) 000d 00h 010d 0Ah Chassis Type (Default value is 0.) 000d 00h 011d 0Bh Chassis Part Number Type/Length 10 byte allocation

0CAH (if used) (Default value is 0.) 000d 00h

012d 0Ch Chassis Part Number 000d 00h 013d 0Dh (Default value is 0.) 000d 00h 014d 0Eh 000d 00h 015d 0Fh 000d 00h 016d 10h 000d 00h



017d 11h 000d 00h 018d 12h 000d 00h 019d 13h 000d 00h 020d 14h 000d 00h 021d 15h 000d 00h 022d 16h Chassis Serial Number Type/Length 15 byte allocation

0CFH (if used) (Default value is 0.) 000d 00h

023d 17h Chassis Serial Number 000d 00h 024d 18h (Default value is 0.) 000d 00h 025d 19h 000d 00h 026d 1Ah 000d 00h 027d 1Bh 000d 00h 028d 1Ch 000d 00h 029d 1Dh 000d 00h 030d 1Eh 000d 00h 031d 1Fh 000d 00h 032d 20h 000d 00h 033d 21h 000d 00h 034d 22h 000d 00h 035d 23h 000d 00h 036d 24h 000d 00h 037d 25h 000d 00h 038d 26h End Tag (0C1H if used) (Default value is 0.) 000d 00h 039d 27h Zero Check Sum (From 08d to 38d if used) 255d FFh COMPUTER/CHASSIS INFORMATION AREA, 32 bytes 040d 28h Format Version Number 001d 01h 041d 29h Product Info Area Length (In multiple of 8 bytes)

80 Bytes are allocated. 80-Bytes / 8 = 0AH. 010d 0Ah

042d 2Ah Language English = 19H

025d 19h

043d 2Bh Manufacturer Name Type/Length (0C5H) 7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (000101)b, 5-Byte Allocation

197d C5h

044d 045d 046d 047d 048d

2Ch 2Dh 2Eh 2Fh 30h

Manufacturer Name “E” “N” “P” “ ” “ ”

069d 078d 080d 032d 032d

45h 4Eh 50h 20h 20h

049d 31h Product Name Type/Length (0CEH) 7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (001110)b, 14-Byte Allocation

206d CEh



050d 051d 052d 053d 054d 055d 056d 057d 058d 059d 060d 061d 062d 063d

32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh

Product Name “H” “P” “S” “3” “0” “0” “0” “-” “9”

072d 080d 083d 051d 048d 048d 048d 045d 057d 000d 000d 000d 000d 000d

48h 50h 53h 33h 30h 30h 30h 2Dh 39h 00h 00h 00h 00h 00h

064d 40hH

Part/Model Number Type/Length (0CAH) 7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (001000)b, 8-Byte Allocation

200d C8h

065d 066d 067d 068d 069d 070d 071d 072d

41h 42h 43h 44h 45h 46h 47h 48h

Power Supply Spare Kit Number Power Supply Spare Kit Number NOT APPLICABLE

000d 000d 000d 000d 000d 000d 000d 000d

00h 00h 00h 00h 00h 00h 00h 00h

073d

49h

Product Version Number Type/Length (0C2H) 7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (000010)b, 2-Byte Allocation

194d

C2h Product Version Number / Auto Rev

074d 4Ah XXXd XXh 075d 4Bh *SHOULD TRACK MODEL REVISION on IPS Sec. 1.2 XXXd XXh

076d

4Ch

Product Serial Number Type/Length (0CDH) *PRODUCT SERIAL NUMBER IS BASED ON ASTEC SERIAL NUMBER FORMAT P/N: 417-00201000

7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (001101)b, 13-Byte Allocation

205d

CDh

Product Serial Number: MODEL ID 077d 4Dh “H” 072d 48h 078d 4Eh “0” 048d 30h 079d 4Fh “8” 056d 38h 080d 50h “1” 049d 31h

Product Serial Number: MANUFACTURING YEAR AND WEEK CODE *REFER TO 417-00201000 FOR DETAILS

081d 51h XXXd XXh 082d 52h XXXd XXh

Product Serial Number: UNIQUE SERIAL NUMBER



*REFER TO 417-00201000 FOR DETAILS 083d 53h XXXd XXh 084d 54h XXXd XXh 085d 55h XXXd XXh 086d 56h XXXd XXh

Product Serial Number: MODEL REVISION *SHOULD TRACK MODEL REVISION on IPS Sec. 1.2


Product Serial Number: MANUFACTURING LOCATION *REFER TO 417-00201000 FOR DETAILS

089d 59h “P” (P for Laguna Philippines) 080d 50h 090d 5Ah ASSET TAG


200d C8h

091d 092d 093d 094d 095d 096d 097d 098d

5Bh 5Ch 5Dh 5Eh

5Fh 60h 61h 62h

NO ASSET TAG 000d 000d 000d 000d 000d 000d 000d 000d

00h 00h 00h 00h 00h 00 00h 00h

099d

63h FRU File ID 7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (010001)b, 17-Byte Allocation

209d D1h

100d 101d 102d 103d 104d 105d 106d 107d 108d 109d 110d 111d 112d

113d 114d 115d 116d

64h 65h

66h 67h 68h

69h 6Ah 6Bh 6Ch 6Dh

6Eh 6Fh 70h 71h 72h 73h 74h

“Should track latest EEPROM Revision on IPS Sec. 1.2” NOT APPLICABLE

000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

117d 75h End of Fields Marker 193d C1h 118d 76h RESERVED 000d 00h 119d 77h Zero Checksum From 040d to 118d XXXd XXh

MULTI RECORD AREA : Power Supply Information 72 Bytes Power Supply Record Header



120d 78h Record Type ID (0x00 = Power Supply Information) 000d 00h 121d 79h 7: (0)b, End of List

6-4: (000)b, Reserved 3-0: (0010)b, Record Format Version

002d 02h

122d 7Ah Record Length: 24 Bytes 024d 18h 123d 7Bh Record Checksum (Zero Checksum From 125d To 148d ) 100d 64h 124d 7Ch Header Checksum (Zero Checksum From 120d To 123d) 130d 82h

Power Supply Record

125d 126d

7Dh 7Eh

Overall Capacity (Watts) 15-12: (0000)b, Reserved 11-0: (11111010000)b, 3000W Stored with LSB first then MSB.

184d 011d

B8h 0Bh

127d 128d

7Fh 80h

Peak VA (Watts) 15-12: (0000)b, Reserved 11-0: No peak VA rating Stored with LSB first then MSB.

000d 000d

00h 00h

129d

81h

Inrush Current (Amps) 40Amps

040d

28h

130d

82h

Inrush Interval (ms) 0ms

000d

00h

131d 132d

83h 84h

Low End Input Voltage Range 1 000d 000d

00h 00h

133d 134d

85h 86h

High End Input Voltage Range 1

000d 000d

00h 00h

135d 136d

87h 88h

Low End Input Voltage Range 2 180V = 18000 (x10mV) Stored with LSB first then MSB.

080d 070d

50h 46h

137d 138d

89h 8Ah

High End Input Voltage Range 2 264V = 26400 (x10mV) Stored with LSB first then MSB.

032d 103d

20h 67h

139d 8Bh Low End Input Frequency Range, 47Hz 047d 2Fh 140d 8Ch High End Input Frequency Range, 63Hz 063d 3Fh 141d 8Dh A/C Dropout Tolerance in ms, 12ms 012d 0Ch 142d 8Eh Binary Flags

7-5: (000)b, Reserved 4: (1)b, Tachometer Pulses per Rotation / Predictive Fail Polarity (2 Pulses Per Rotation = 1; 1 Pulse Per Rotation = 0) OR (Signal Asserted(1) Indicates Failure = 0, Signal Deasserted(0) Indicates Failure = 1) 3: (1)b, Hot Swap / Redundancy Support 2: (0)b, AutoSwitch Support 1: (1)b, Power Factor Correction Support 0: (0)b, Predictive Fail Support

026d 1Ah

143d 144d

8Fh 90h

Peak Wattage Capacity and Holdup Time 15-12: (0000)b, Hold Up Time in Seconds = 00H (Not Specified) 11-0: (000000000000)b, Peak Capacity in Watts = 00H (Not Specified)

000d 000d

00h

00h

145d 146d

91h 92h

Combined Wattage NOT APPLICABLE

000d 000d

00h 00h



147d 93h 000d 00h 148d 94h Predictive Fail Tachometer Lower Threshold, Not applicable 000d 00h

48V DC Output Record Header

149d 95h Record Type ID (0x01 = DC Output) 001d 01h 150d 96h End Of List/Record Format Version Number

7: (0)b, End of List 6-4: (000)b, Reserved 3-0: (0010)b, Record Format Version

002d 02h

151d 97h Record Length: 13 Bytes 013d 0Dh 152d 98h Record Checksum (Zero Checksum From 154d To 166d ) 194d C2h 153d 99h Header Checksum (Zero Checksum From 149d To 152d ) 46d 2Eh

+48V DC Output Record 154d 9Ah +48V Output Information

7: (0)b, Standby 6-4: (000)b, Reserved 3-0: (0001)b, Output Number 1

001d 01h

155d 156d

9Bh 9Ch

Nominal Voltage 48V = 4800 (x10mV) Stored with LSB first then MSB.

192d 018d

C0h 12h

157d 158d

9Dh 9Eh

Maximum Negative Voltage Deviation 43.2V = 4320 (x10mV) Stored with LSB first then MSB.

224d 016d

E0h 10h

159d 160d

9Fh A0h

Maximum Positive Voltage Deviation 52.8V = 5280x(10mV) Stored with LSB first then MSB.

160d 020d

A0h 14h

161d 162d

A1h A2h

Ripple And Noise pk-pk 10Hz To 30MHz (mV) 480mV Stored with LSB first then MSB.

224d 001d

E0h 01h

163d 164d

A3h

A4h

Minimum Current Draw (10mA) 1A = 100 (x10mA) Stored with LSB first then MSB.

100d 000d

64h 00h

165d 166d

A5h A6h

Maximum Current Draw (10mA) 62.50A = 6250 (x10mA) Stored with LSB first then MSB.

106d 024d

6Ah 18h

5VSB DC Output Record Header 167d A7h Record Type ID (0x01 = DC Output) 001d 01h

168d

A8h

End Of List/Record Format Version Number 7: (1)b, End of List 6-4: (000)b, Reserved 3-0: (0010)b, Record Format Version

130d

82h

169d A9h Record Length: 20 Bytes 020d 14h 170d AAh Record Checksum (Zero Checksum From 172d To 191d ) 219d DBh 171d Abh Header Checksum (Zero Checksum From 167d To 170d ) 142d 8Eh

5VSB DC Output Record

172d ACh 5VSB Output Information 7: (1)b, Standby (Bit = 1 to indicate standby output)

130d 82h



6-4: (000)b, Reserved 3-0: (0010)b, Output Number 2 = 010b

173d 174d

ADh AEh


244d 001d

F4h 01h

175d 176d

AFh B0h


224d 001d

E0h 01h

177d 178d

B1h B2h

Maximum Positive Voltage Deviation 5.2V = 520 (x10mV) Stored with LSB first then MSB.

008d 002d

08h 02h

179d 180d

B3h B4h

Ripple And Noise pk -pk 10Hz To 30MHz (mV) 100mV Stored with LSB first then MSB.

100d 000d

64h 00h

181d 182d

B5h

B6h

Minimum Current Draw (10mA) 0.5A = 50(x 10mA) Stored with LSB first then MSB.

050d 000d

32h 00h

183d 184d

B7h

B8h

Maximum Current Draw (10mA) 3.00A = 300(x 10mA) Stored with LSB first then MSB.

044d 001d

2Ch 01h

185d B9h Reserved 000d 00h 186d BAh Reserved 000d 00h 187d BBh Reserved 000d 00h 188d BCh Reserved 000d 00h 189d BDh Reserved 000d 00h 190d BEh Reserved 000d 00h 191d BFh Reserved 000d 00h

INTERNAL USE AREA, 64 bytes

192d 0C0h Format Version Number 7:4 -reserved, write as 0000b 3:0 -format version number = 1h for this specification.

001d 01h

193d C1h 000d 00h 194d C2h 000d 00h 195d C3h 000d 00h 196d C4h 000d 00h 197d C5h 000d 00h 198d C6h 000d 00h 199d C7h 000d 00h 200d C8h 000d 00h 201d C9h 000d 00h 202d CAh 000d 00h 203d CBh 000d 00h 204d CCh 000d 00h 205d CDh 000d 00h 206d CEh 000d 00h 207d CFh 000d 00h 208d D0h 000d 00h 209d D1h 000d 00h 210d D2h 000d 00h 211d D3h 000d 00h 212d D4h 000d 00h



213d D5h 000d 00h 214d D6h 000d 00h 215d D7h 000d 00h 216d D8h 000d 00h 217d D9h 000d 00h 218d DAh 000d 00h 219d DBh 000d 00h 220d DCh 000d 00h 221d DDh 000d 00h 222d DEh 000d 00h 223d DFh 000d 00h 224d E0h 000d 00h 225d E1h 000d 00h 226d E2h 000d 00h 227d E3h 000d 00h 228d E4h 000d 00h 229d E5h 000d 00h 230d E6h 000d 00h 231d E7h 000d 00h 232d E8h 000d 00h 233d E9h 000d 00h 234d EAh 000d 00h 235d EBh 000d 00h 236d ECh 000d 00h 237d EDh 000d 00h 238d EEh 000d 00h 239d EFh 000d 00h 240d F0h 000d 00h 241d F1h 000d 00h 242d F2h 000d 00h 243d F3h 000d 00h 244d F4h 000d 00h 245d F5h 000d 00h 246d F6h 000d 00h 247d F7h 000d 00h 248d F8h 000d 00h 249d F9h 000d 00h 250d FAh 000d 00h 251d FBh 000d 00h 252d FCh 000d 00h 253d FDh 000d 00h 254d FEh 000d 00h 255d FFh Zero Checksum From 192d to 254d if used 255d FFh

HPS3000NF-9 FRU data

OFFSET DEFINITION SPEC (REMARKS) VALUE COMMON HEADER, 8 bytes

000d 00h Format Version Number (Common Header) 001d 01h 001d 01h Internal Use Area Offset (In multiples of 8 Bytes) 024d 18h 002d 02h Chassis Info Area Offset (In multiples of 8 Bytes) 001d 01h



003d 03h Board Info Area Offset (Not Used) 000d 00h 004d 04h Product Info Area Offset (In multiples of 8 Bytes) 005d 05h 005d 05h Multi Record Area Offset (In multiples of 8 Bytes) 015d 0Fh 006d 06h PAD (reserved – always 00H) 000d 00h 007d 07h Zero Check Sum (256 – (Sum of bytes 000d to 006d)) 210d D2h

COMPUTER/CHASSIS INFORMATION AREA, 32 bytes 008d 08h Format Version Number (Default value is 1.) 001d 01h 009d 09h Chassis Info Area Length (Default value is 0.) 000d 00h 010d 0Ah Chassis Type (Default value is 0.) 000d 00h 011d 0Bh Chassis Part Number Type/Length 10 byte allocation

0CAH (if used) (Default value is 0.) 000d 00h

012d 0Ch Chassis Part Number 000d 00h 013d 0Dh (Default value is 0.) 000d 00h 014d 0Eh 000d 00h 015d 0Fh 000d 00h 016d 10h 000d 00h 017d 11h 000d 00h 018d 12h 000d 00h 019d 13h 000d 00h 020d 14h 000d 00h 021d 15h 000d 00h 022d 16h Chassis Serial Number Type/Length 15 byte allocation

0CFH (if used) (Default value is 0.) 000d 00h

023d 17h Chassis Serial Number 000d 00h 024d 18h (Default value is 0.) 000d 00h 025d 19h 000d 00h 026d 1Ah 000d 00h 027d 1Bh 000d 00h 028d 1Ch 000d 00h 029d 1Dh 000d 00h 030d 1Eh 000d 00h 031d 1Fh 000d 00h 032d 20h 000d 00h 033d 21h 000d 00h 034d 22h 000d 00h 035d 23h 000d 00h 036d 24h 000d 00h 037d 25h 000d 00h 038d 26h End Tag (0C1H if used) (Default value is 0.) 000d 00h 039d 27h Zero Check Sum (From 08d to 38d if used) 255d FFh PRODUCT INFORMATION AREA (80 bytes) 040d 28h Format Version Number 001d 01h 041d 29h Product Info Area Length (In multiple of 8 bytes)

80 Bytes are allocated. 80-Bytes / 8 = 0AH. 010d 0Ah

042d 2Ah Language English = 19H

025d 19h

043d 2Bh Manufacturer Name Type/Length (0C5H) 7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (000101)b, 5-Byte Allocation

197d C5h

Manufacturer Name



044d 045d 046d 047d 048d

2Ch 2Dh 2Eh 2Fh 30h

“E” “N” “P” “ ” “ ”

069d 078d 080d 032d 032d

45h 4Eh 50h 20h 20h

049d 31h Product Name Type/Length (0CEH) 7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (001110)b, 14-Byte Allocation

206d CEh

050d 051d 052d 053d 054d 055d 056d 057d 058d 059d 060d 061d 062d 063d

32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh

Product Name “H” “P” “S” “3” “0” “0” “0” “N” “F” “-“ “9”

072d 080d 083d 051d 048d 048d 048d 078d 070d 045d 057d 000d 000d 000d

48h 50h 53h 33h 30h 30h 30h 4Eh 46h 2Dh 39h 00h 00h 00h

064d 40hH

Part/Model Number Type/Length (0CAH) 7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (001000)b, 8-Byte Allocation

200d C8h

065d 066d 067d 068d 069d 070d 071d 072d

41h 42h 43h 44h 45h 46h 47h 48h

Power Supply Spare Kit Number Power Supply Spare Kit Number NOT APPLICABLE

000d 000d 000d 000d 000d 000d 000d 000d

00h 00h 00h 00h 00h 00h 00h 00h

073d

49h

Product Version Number Type/Length (0C2H) 7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (000010)b, 2-Byte Allocation

194d

C2h Product Version Number / Auto Rev

074d 4Ah XXXd XXh 075d 4Bh *SHOULD TRACK MODEL REVISION on IPS Sec. 1.2 XXXd XXh

076d

4Ch

Product Serial Number Type/Length (0CDH) *PRODUCT SERIAL NUMBER IS BASED ON ASTEC SERIAL NUMBER FORMAT P/N: 417-00201000


205d

CDh

Product Serial Number: MODEL ID 077d 4Dh “I” 073d 49h 078d 4Eh “6” 054d 36h



079d 4Fh “4” 052d 34h 080d 50h “8” 056d 38h

Product Serial Number: MANUFACTURING YEAR AND WEEK CODE *REFER TO 417-00201000 FOR DETAILS


Product Serial Number: UNIQUE SERIAL NUMBER *REFER TO 417-00201000 FOR DETAILS

083d 53h XXXd XXh 084d 54h XXXd XXh 085d 55h XXXd XXh 086d 56h XXXd XXh

Product Serial Number: MODEL REVISION *SHOULD TRACK MODEL REVISION on IPS Sec. 1.2


Product Serial Number: MANUFACTURING LOCATION *REFER TO 417-00201000 FOR DETAILS

089d 59h “P” (P for Laguna Philippines) 080d 50h 090d 5Ah ASSET TAG


200d C8h

091d 092d 093d 094d 095d 096d 097d 098d

5Bh 5Ch 5Dh 5Eh

5Fh 60h 61h 62h

NO ASSET TAG 000d 000d 000d 000d 000d 000d 000d 000d

00h 00h 00h 00h 00h 00 00h 00h

099d

63h FRU File ID 7-6: (11)b, 8-Bit ASCII + Latin 1, 5-0: (010001)b, 17-Byte Allocation

209d D1h

100d 101d 102d 103d 104d 105d 106d 107d 108d 109d 110d 111d 112d

113d 114d 115d

64h 65h

66h 67h 68h

69h 6Ah 6Bh 6Ch 6Dh

6Eh 6Fh 70h 71h 72h 73h

“Should track latest EEPROM Revision on IPS Sec. 1.2” NOT APPLICABLE

000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d 000d

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h



116d 74h 000d 00h 117d 75h End of Fields Marker 193d C1h 118d 76h RESERVED 000d 00h 119d 77h Zero Checksum From 040d to 118d XXXd XXh

MULTI RECORD AREA : Power Supply Information 72 Bytes Power Supply Record Header

120d 78h Record Type ID (0x00 = Power Supply Information) 000d 00h 121d 79h 7: (0)b, End of List

6-4: (000)b, Reserved 3-0: (0010)b, Record Format Version

002d 02h

122d 7Ah Record Length: 24 Bytes 024d 18h 123d 7Bh Record Checksum (Zero Checksum From 125d To 148d ) 100d 64h 124d 7Ch Header Checksum (Zero Checksum From 120d To 123d) 130d 82h

Power Supply Record

125d 126d

7Dh 7Eh

Overall Capacity (Watts) 15-12: (0000)b, Reserved 11-0: (11111010000)b, 3000W Stored with LSB first then MSB.

184d 011d

B8h 0Bh

127d 128d

7Fh 80h

Peak VA (Watts) 15-12: (0000)b, Reserved 11-0: No peak VA rating Stored with LSB first then MSB.

000d 000d

00h 00h

129d

81h

Inrush Current (Amps) 40Amps

040d

28h

130d

82h

Inrush Interval (ms) 0ms

000d

00h

131d 132d

83h 84h

Low End Input Voltage Range 1 000d 000d

00h 00h

133d 134d

85h 86h

High End Input Voltage Range 1

000d 000d

00h 00h

135d 136d

87h 88h

Low End Input Voltage Range 2 180V = 18000 (x10mV) Stored with LSB first then MSB.

080d 070d

50h 46h

137d 138d

89h 8Ah

High End Input Voltage Range 2 264V = 26400 (x10mV) Stored with LSB first then MSB.

032d 103d

20h 67h

139d 8Bh Low End Input Frequency Range, 47Hz 047d 2Fh 140d 8Ch High End Input Frequency Range, 63Hz 063d 3Fh 141d 8Dh A/C Dropout Tolerance in ms, 12ms 012d 0Ch 142d 8Eh Binary Flags

7-5: (000)b, Reserved 4: (1)b, Tachometer Pulses per Rotation / Predictive Fail Polarity (2 Pulses Per Rotation = 1; 1 Pulse Per Rotation = 0) OR (Signal Asserted(1) Indicates Failure = 0, Signal Deasserted(0) Indicates Failure = 1) 3: (1)b, Hot Swap / Redundancy Support 2: (0)b, AutoSwitch Support 1: (1)b, Power Factor Correction Support

026d 1Ah



0: (0)b, Predictive Fail Support

143d 144d

8Fh 90h

Peak Wattage Capacity and Holdup Time 15-12: (0000)b, Hold Up Time in Seconds = 00H (Not Specified) 11-0: (000000000000)b, Peak Capacity in Watts = 00H (Not Specified)

000d 000d

00h

00h

145d 146d 147d

91h 92h 93h

Combined Wattage NOT APPLICABLE

000d 000d 000d

00h 00h 00h

148d 94h Predictive Fail Tachometer Lower Threshold, Not applicable 000d 00h 48V DC Output Record Header

149d 95h Record Type ID (0x01 = DC Output) 001d 01h 150d 96h End Of List/Record Format Version Number

7: (0)b, End of List 6-4: (000)b, Reserved 3-0: (0010)b, Record Format Version

002d 02h

151d 97h Record Length: 13 Bytes 013d 0Dh 152d 98h Record Checksum (Zero Checksum From 154d To 166d ) 194d C2h 153d 99h Header Checksum (Zero Checksum From 149d To 152d ) 46d 2Eh

+48V DC Output Record 154d 9Ah +48V Output Information

7: (0)b, Standby 6-4: (000)b, Reserved 3-0: (0001)b, Output Number 1

001d 01h

155d 156d

9Bh 9Ch


192d 018d

C0h 12h

157d 158d

9Dh 9Eh


224d 016d

E0h 10h

159d 160d

9Fh A0h

Maximum Positive Voltage Deviation 52.8V = 5280x(10mV) Stored with LSB first then MSB.

160d 020d

A0h 14h

161d 162d

A1h A2h


224d 001d

E0h 01h

163d 164d

A3h

A4h

Minimum Current Draw (10mA) 1A = 100 (x10mA) Stored with LSB first then MSB.

100d 000d

64h 00h

165d 166d

A5h A6h

Maximum Current Draw (10mA) 62.50A = 6250 (x10mA) Stored with LSB first then MSB.

106d 024d

6Ah 18h

5VSB DC Output Record Header 167d A7h Record Type ID (0x01 = DC Output) 001d 01h

168d

A8h

End Of List/Record Format Version Number 7: (1)b, End of List 6-4: (000)b, Reserved 3-0: (0010)b, Record Format Version

130d

82h

169d A9h Record Length: 20 Bytes 020d 14h



170d AAh Record Checksum (Zero Checksum From 172d To 191d ) 219d DBh 171d Abh Header Checksum (Zero Checksum From 167d To 170d ) 142d 8Eh

5VSB DC Output Record

172d ACh 5VSB Output Information 7: (1)b, Standby (Bit = 1 to indicate standby output) 6-4: (000)b, Reserved 3-0: (0010)b, Output Number 2 = 010b

130d 82h

173d 174d

ADh AEh


244d 001d

F4h 01h

175d 176d

AFh B0h


224d 001d

E0h 01h

177d 178d

B1h B2h

Maximum Positive Voltage Deviation 5.2V = 520 (x10mV) Stored with LSB first then MSB.

008d 002d

08h 02h

179d 180d

B3h B4h


100d 000d

64h 00h

181d 182d

B5h

B6h

Minimum Current Draw (10mA) 0.5A = 50(x 10mA) Stored with LSB first then MSB.

050d 000d

32h 00h

183d 184d

B7h

B8h

Maximum Current Draw (10mA) 3.00A = 300(x 10mA) Stored with LSB first then MSB.

044d 001d

2Ch 01h

185d B9h Reserved 000d 00h 186d BAh Reserved 000d 00h 187d BBh Reserved 000d 00h 188d BCh Reserved 000d 00h 189d BDh Reserved 000d 00h 190d BEh Reserved 000d 00h 191d BFh Reserved 000d 00h

INTERNAL USE AREA, 64 bytes

192d 0C0h Format Version Number 7:4 -reserved, write as 0000b 3:0 -format version number = 1h for this specification.

001d 01h

193d C1h 000d 00h 194d C2h 000d 00h 195d C3h 000d 00h 196d C4h 000d 00h 197d C5h 000d 00h 198d C6h 000d 00h 199d C7h 000d 00h 200d C8h 000d 00h 201d C9h 000d 00h 202d CAh 000d 00h 203d CBh 000d 00h 204d CCh 000d 00h 205d CDh 000d 00h 206d CEh 000d 00h



207d CFh 000d 00h 208d D0h 000d 00h 209d D1h 000d 00h 210d D2h 000d 00h 211d D3h 000d 00h 212d D4h 000d 00h 213d D5h 000d 00h 214d D6h 000d 00h 215d D7h 000d 00h 216d D8h 000d 00h 217d D9h 000d 00h 218d DAh 000d 00h 219d DBh 000d 00h 220d DCh 000d 00h 221d DDh 000d 00h 222d DEh 000d 00h 223d DFh 000d 00h 224d E0h 000d 00h 225d E1h 000d 00h 226d E2h 000d 00h 227d E3h 000d 00h 228d E4h 000d 00h 229d E5h 000d 00h 230d E6h 000d 00h 231d E7h 000d 00h 232d E8h 000d 00h 233d E9h 000d 00h 234d EAh 000d 00h 235d EBh 000d 00h 236d ECh 000d 00h 237d EDh 000d 00h 238d EEh 000d 00h 239d EFh 000d 00h 240d F0h 000d 00h 241d F1h 000d 00h 242d F2h 000d 00h 243d F3h 000d 00h 244d F4h 000d 00h 245d F5h 000d 00h 246d F6h 000d 00h 247d F7h 000d 00h 248d F8h 000d 00h 249d F9h 000d 00h 250d FAh 000d 00h 251d FBh 000d 00h 252d FCh 000d 00h 253d FDh 000d 00h 254d FEh 000d 00h 255d FFh Zero Checksum From 192d to 254d if used 255d FFh

6.6.16.3 EEPROM FRU test procedure



?? Vin = 200Vac ?? Loading = (0.5A) ?? Load EEPROM Data ?? Read/ Verify EEPROM Data

6.6.16.4 Example FRU Definition table

Below contents should be a part number 429 documents for FRU definition table

1.0 REVISION AND HISTORY

2.0 TABLE OF CONTENTS 3.0 TERMS AND DEFINITIONS 3.1 OFFSET The OFFSET denotes the address (or range of addresses) in HEXADECIMAL format of a particular data byte. 3.2 DEFINITION

The contents DEFINITION refers to the description of a particular data byte. It can refer to characters in barcode, or calibration parameters, or whatever descriptive. If it is checksum value, method of calculation has to be state in definition content. 3.3 SPEC. VALUE The SPEC VALUE stated the expected value in HEXADECIMAL format, or unless in specified format, that must be written in a particular offset location. If value is not fixed, the range of values has to state in DEFINITION.

6.6.16.5 Example power supply command library

Below contents should be a part number 429 document for Power supply command summary.

MCU ADDRESSING FOR WRITING Default address is A6h. Read address = Write Address+1

6.6.16.6 Commands for communications

The power supply uses PMBUS Specifications for Communications



6.6.17 PMBus Test Test Load Condition: Vin = 200Vac/60Hz (FL: Load 12) Read the following Pmbus commands via I2C

Note: XX is the computed CRC for the power supply address plus the data.

HPS3000-9 COMMAND

CODE COMMAND NAME SPECS READ GO/NO GO

00h PAGE 00 XX 01h OPERATION 80 XX

02h ON_OFF_CONFIG 1C XX 03h CLEAR_FAULTS --

10h WRITE_PROTECT 00 XX 15h STORE_USER_ALL --

16h RESTORE_USER_ALL -- 19h CAPABILITY 90 XX

20h VOUT_MODE 17 XX 21h VOUT_COMMAND 66 00 22h VOUT_TRIM 00 00 XX

23h VOUT_CAL_OFFSET 00 00 XX 24h VOUT_MAX 70 33 XX

31h POUT_MAX 13 B9 XX 35h VIN_ON EA C0 XX

36h VIN_OFF EA 80 XX 3Ah FAN_COMMAND_CONFIG_1_2 99 XX

3Bh FAN_COMMAND_1 00 00 XX 3Ch FAN_COMMAND_2 00 00 XX

40h VOUT_OV_FAULT_LIMIT 7A 00 XX 41h VOUT_OV_FAULT_RESPONSE 80 XX

42h VOUT_OV_WARN_LIMIT 75 4C XX 43h VOUT_UV_WARN_LIMIT 59 93 XX

44h VOUT_UV_FAULT_LIMIT 52 00 XX 45h VOUT_UV_FAULT_RESPONSE 80 XX 46h IOUT_OC_FAULT_LIMIT 58 EA XX

47h IOUT_OC_FAULT_RESPONSE 80 XX 4Ah IOUT_OC_WARN_LIMIT EA 24 XX

4Fh OT_FAULT_LIMIT E3 20 XX

50h OT_FAULT_RESPONSE C0 XX 51h OT_WARN_LIMIT E2 D0 XX

55h VIN_OV_FAULT_LIMIT FA 26 XX



56h VIN_OV_FAULT_RESPONSE C0 XX 59h VIN_UV_FAULT_LIMIT EA 80 XX

5Ah VIN_UV_FAULT_RESPONSE C0 XX 5Bh IIN_OC_FAULT_LIMIT DA 80 XX

5Ch IIN_OC_FAULT_RESPONSE 80 XX 60h TON_DELAY F3 20 XX

61h TON_RISE F2 A8 XX 78h STATUS_BYTE --

79h STATUS_WORD -- 7Ah STATUS_VOUT --

7Bh STATUS_IOUT -- 7Ch STATUS_INPUT --

7Dh STATUS_TEMPERATURE -- 7Eh STATUS_CML -- 80h STATUS_MFR_SPECIFIC --

81h STATUS_FANS_1_2 -- 88h READ_VIN --

89h READ_IIN -- 8Ah READ_VCAP --

8Bh READ_VOUT -- 8Ch READ_IOUT --

8Dh READ_TEMPERATURE_1 -- 8Eh READ_TEMPERATURE_2 --

90h READ_FAN_SPEED_1 -- 91h READ_FAN_SPEED_2 --

96h READ_POUT -- 97h READ_PIN --

98h PMBUS_REVISION 11 XX 99h MFR_ID 07 45 4D 45 52 53 30 4E

XX

9Ah MFR_MODEL 09 48 50 53 33 30 30 30 2D 39 XX

9Bh MFR_REVISION 02 30 41 XX

9Ch MFR_LOCATION 04 50 68 69 6C XX A0h MFR_VIN_MIN EA D0 XX

A1h MFR_VIN_MAX FA 10 XX A2h MFR_IIN_MAX DA 60 XX

A3h MFR_PIN_MAX 13 41 XX A4h MFR_VOUT_MIN 5B CD XX

A5h MFR_VOUT_MAX 70 33 XX A6h MFR_IOUT_MAX E3 E3 XX

A7h MFR_POUT_MAX 12 EE XX



A8h MFR_TAMBIENT_MAX E2 80 XX ABh MFR_EFFICIENCY_HL 0E C8 00 00 00 00 00 00 00

00 00 EE 12 5A 00 XX

HPS3000NF-9 COMMAND

CODE COMMAND NAME SPECS READ GO/NO GO

00h PAGE 00 XX 01h OPERATION 80 XX

02h ON_OFF_CONFIG 1C XX 03h CLEAR_FAULTS --

10h WRITE_PROTECT 00 XX 15h STORE_USER_ALL --

16h RESTORE_USER_ALL -- 19h CAPABILITY 90 XX

20h VOUT_MODE 17 XX 21h VOUT_COMMAND 66 00

22h VOUT_TRIM 00 00 XX 23h VOUT_CAL_OFFSET 00 00 XX

24h VOUT_MAX 70 33 XX 31h POUT_MAX 13 B9 XX 35h VIN_ON EA C0 XX

36h VIN_OFF EA 80 XX 40h VOUT_OV_FAULT_LIMIT 7A 00 XX

41h VOUT_OV_FAULT_RESPONSE 80 XX 42h VOUT_OV_WARN_LIMIT 75 4C XX

43h VOUT_UV_WARN_LIMIT 59 93 XX 44h VOUT_UV_FAULT_LIMIT 52 00 XX

45h VOUT_UV_FAULT_RESPONSE 80 XX 46h IOUT_OC_FAULT_LIMIT 58 EA XX

47h IOUT_OC_FAULT_RESPONSE 80 XX 4Ah IOUT_OC_WARN_LIMIT EA 24 XX

4Fh OT_FAULT_LIMIT E3 20 XX

50h OT_FAULT_RESPONSE C0 XX 51h OT_WARN_LIMIT E2 D0 XX

55h VIN_OV_FAULT_LIMIT FA 26 XX 56h VIN_OV_FAULT_RESPONSE C0 XX 59h VIN_UV_FAULT_LIMIT EA 80 XX

5Ah VIN_UV_FAULT_RESPONSE C0 XX 5Bh IIN_OC_FAULT_LIMIT DA 80 XX

5Ch IIN_OC_FAULT_RESPONSE 80 XX



60h TON_DELAY F3 20 XX 61h TON_RISE F2 A8 XX

78h STATUS_BYTE -- 79h STATUS_WORD --

7Ah STATUS_VOUT -- 7Bh STATUS_IOUT --

7Ch STATUS_INPUT -- 7Dh STATUS_TEMPERATURE --

7Eh STATUS_CML -- 80h STATUS_MFR_SPECIFIC --

88h READ_VIN -- 89h READ_IIN --

8Ah READ_VCAP -- 8Bh READ_VOUT -- 8Ch READ_IOUT --

8Dh READ_TEMPERATURE_1 -- 8Eh READ_TEMPERATURE_2 --

96h READ_POUT -- 97h READ_PIN --

98h PMBUS_REVISION 11 XX 99h MFR_ID 07 45 4D 45 52 53 30 4E

XX

9Ah MFR_MODEL 0B 48 50 53 33 30 30 30 4E 46 2D 39 XX

9Bh MFR_REVISION 02 30 41 XX 9Ch MFR_LOCATION 04 50 68 69 6C XX

A0h MFR_VIN_MIN EA D0 XX A1h MFR_VIN_MAX FA 10 XX A2h MFR_IIN_MAX DA 60 XX

A3h MFR_PIN_MAX 13 41 XX A4h MFR_VOUT_MIN 5B CD XX

A5h MFR_VOUT_MAX 70 33 XX A6h MFR_IOUT_MAX E3 E3 XX

A7h MFR_POUT_MAX 12 EE XX A8h MFR_TAMBIENT_MAX E2 80 XX

ABh MFR_EFFICIENCY_HL 0E C8 00 00 00 00 00 00 00 00 00 EE 12 5A 00 XX

6.7 Redundant operation

The unit/s under test (UUT) shall be paralleled to one resident unit. The ISHARE pins of the units should be connected. Note: +5VSB load is at 3.0A



6.7.1 Current Sharing - Two units in parallel

Vin = 200VAC/47Hz

Output Load (A) +48V Load (A)

Resident UUT % Error

(%) +% Error limits (%)

31.10 10 46.64 10 62.19 10

Measure the actual +48V current of the UUT and the resident unit. Compute the percent error with the following formula:

Iuut = current given by the UUT Ires = current given by the resident unit Iave = the average of Iuut and Ires

6.7.2 Regulation at Parallel Operation

Vin = 200VAC/47Hz

OUTPUT VOLTAGES (V) Loading Condition

5VSB 48V No Load: Load 1

Max-Min: Load 14 Min-Max: Load 13

FL: Load 12 Max 4.8 50.40 Limits Min 5.2 45.60

6.7.3 Ripple and Noise at Parallel Operation (QA audit Only)

Measure at output terminal with the following capacitors for a bandwidth of 20MHz: All outputs will be measured with 0.1uF ceramic capacitor in parallel with 10µF Tantalum capacitor.

%100||

% ??

?Iave

IaveIuuterror

2IresIuut

Iave?

?



Vin = 200VAC/47Hz OUTPUT VOLTAGES (V)

Loading Condition 5VSB 48V

No Load: Load 1 Max-Min: Load 14 Min-Max: Load 13

FL: Load 12

Limits 100mVpp 480mVpp

6.7.4 Power Up and Power Down in Parallel Operation (QA Audit Only) Vin = 200VAC/47 Hz (FL: Load 12)

Initial Condition: Plug-in and power-up both Resident Unit and UUT. PSON# signals are “LOW”.

a) Alter the PSON# signal of the resident unit to high. Monitor the PWOK# signal of the UUT.

The signal should be < 0.8V. No glitch must be observed. Go / No Go

b) Alter the PSON# signal of the resident unit to low. Monitor the PWOK# signal of the UUT. The signal should be < 0.8V. No glitch must be observed. Go / No Go

c) Alter the PSON# signal of the UUT to high. Monitor the PWOK# signal of the resident unit. The signal should be < 0.8V. No glitch must be observed.

Go / No Go d) Alter the PSON# signal of the UUT to low. Monitor the PWOK# signal of the resident unit.

The signal should be < 0.8V. No glitch must be observed. Go / No Go

6.7.5 PS_ON Toggling (QA Audit Only)

Vin = 200VAC/47 Hz (FL: Load 12) a) Plug in and power up both UUT and Resident unit: Set PSON# of both unit to “LOW” b) Toggle the PSON# to “HIGH” of the UUT and measure the minimum and maximum bus

voltage of all outputs. Use the rising edge of ISHARE to trigger the waveform and capture at a 20msec-time scale. All output bus voltages should stay within the regulation limits without any glitches.

Go / No Go c) Toggle the PSON# to “LOW” of the UUT and measure the minimum and maximum bus

voltage of all outputs. Use the falling edge of ISHARE to trigger the waveform and capture at a 20-msec time scale. All output bus voltages should stay within the regulation limits without any glitches.



Go / No Go d) Toggle the PSON# to “HIGH” of the Resident unit and measure the minimum and

maximum bus voltage of all outputs. Use the rising edge of ISHARE to trigger the waveform and capture at a 20-msec time scale. All output bus voltages should stay within the regulation limits without any glitches.

Go / No Go e) Toggle the PSON# to “LOW” of the resident unit and measure the minimum and

maximum bus voltage of all outputs. Use the falling edge of ISHARE to trigger the waveform and capture at a 20-msec time scale. All output bus voltages should stay within the regulation limits without any glitches.

Go / No Go 6.7.6 AC HOTPLUG

a) In the redundancy jig, perform the conditions below with the Resident Unit.

Resident Unit conditions:

Item Condition Vin 200V 47Hz PS_ON# Low 5Vsb Load +48V Load

FL: Load 12

b) Insert the UUT in the redundancy jig with the following conditions:

?? No AC Input Voltage ?? PS_ON# is LOW ?? PS_KILL is LOW

c) Turn-on the UUT by plugging the AC (with Vin = 200V 47Hz). d) Check the following signals in the Resident Unit while Procedure (c) is being

performed. ?? PWOK# must <0.8V. No glitches must be observed. ?? 5Vsb must stay in regulation. No glitches must be observed. ?? 48Vout must stay in regulation. No glitches must be observed.

e) Unplug the power of the UUT. f) Check the following signals in the Resident Unit while Procedure (e) is being

performed.



?? PWOK# must <0.8V. No glitches must be observed. ?? 5Vsb must stay in regulation. No glitches must be observed. ?? 48Vout must stay in regulation. No glitches must be observed

g) Repeat the Procedures (c) to (f) five times.

6.7.7 PSU HOTPLUG (QA Audit Only)

a) Perform the conditions below with both the Resident Unit and UUT.

Initial conditions:

Item Condition Vin 200V 47Hz PS_ON# Low 5Vsb Load +48V Load

FL: Load 12

b) Remove the UUT. c) Check the following signals in the Resident Unit while Procedure (b) is being performed.

?? PWOK# must <0.8V. No glitches must be observed. ?? 5Vsb must stay in regulation. No glitches must be observed. ?? 48Vout must stay in regulation. No glitches must be observed.

d) Re-insert the UUT in the redundancy jig. e) Check the following signals in the Resident Unit while Procedure (d) is being

performed. ?? PWOK# must <0.8V. No glitches must be observed. ?? 5Vsb must stay in regulation. No glitches must be observed. ?? 48Vout must stay in regulation. No glitches must be observed

f) Repeat the Procedures (b) to (g) five times. 6.8 Safety Test 6.8.1 Isolation test



The test shall be applied between the PRIMARY (AC LINE and NEUTRAL) and EARTH GROUND (CHASSIS/INPUT RECEPTACLE GROUND TERMINAL) with all OUTPUT pins connected to EARTH GROUND. Test voltage : 2500 VDC Trip current : 600 uA Voltage ramp time : 500 V/sec Test time : 10 sec Breakdown arc detection : 10 usec 6.8.2 Ground continuity test (Skip this Test) The test shall be applied between the GROUNDED SHEET METAL CHASSIS and the INPUT RECEPTACLE EARTH GROUND TERMINAL. Output Current : 25A minimum Output Voltage : 2.5 Vac or Vdc minimum Trip Resistance Sensitivity : 0.1 Ohms maximum 6.8.3 Leakage current test (QA Audit Only)

Vin = 240VAC F = 60Hz +48V / 0A; +5VSB / 0A Line to PE = ______mA; Limit = 1.4mA Neutral to PE = _____mA Limit 6.8.4 EMI scan

There is no requirement to perform EMC tests as part of the production acceptance tests. 6.8.5 Acoustic test

There is no requirement to perform acoustic (sound levels) tests as part of the production acceptance tests. 6.8.6 Burn-in testing

Refer to section 5.5 for Burn-In specifications. 6.8.7 Audible noise test

There is no requirement to perform acoustic (sound levels) tests as part of the production acceptance tests



6.9 Customer Specification Checklist

There are no customer specific tests for this model. The tests described in the rest of the documents offer sufficient coverage.



Appendix A Pmbus Protocol A.1 Byte/Word Write with PEC

A.2 Byte/Word Read with PEC

A.3 Block Read with PEC

A.4 Block Write with PEC

A.5 Packet Error Checking (PEC) The power supply shall use the CRC-8 polynomial.

G(x) = X8 + X2 + X1 + 1



CRC Procedure Using Polynomial X8+X2+X1+X0 Table crc_table[256] = 0, 7, 14, 9, 28, 27, 18, 21, 56, 63, 54, 49, 36, 35, 42, 45, 112,119,126,121,108,107, 98,101, 72, 79, 70, 65, 84, 83, 90, 93, 224,231,238,233,252,251,242,245, 216,223,214,209,196,195,202,205, 144,151,158,153,140,139,130,133, 168,175,166,161,180,179,186,189, 199,192,201,206,219,220,213,210, 255,248,241,246,227,228,237,234, 183,176,185,190,171,172,165,162, 143,136,129,134,147,148,157,154, 39, 32, 41, 46, 59, 60, 53, 50, 31, 24, 17, 22, 3, 4, 13, 10, 87, 80, 89, 94, 75, 76, 69, 66, 111,104, 97,102,115,116,125,122, 137,142,135,128,149,146,155,156, 177,182,191,184,173,170,163,164, 249,254,247,240,229,226,235,236, 193,198,207,200,221,218,211,212, 105,110,103, 96,117,114,123,124, 81, 86, 95, 88, 77, 74, 67, 68, 25, 30, 23, 16, 5, 2, 11, 12, 33, 38, 47, 40, 61, 58, 51, 52, 78, 73, 64, 71, 82, 85, 92, 91, 118,113,120,127,106,109,100, 99, 62, 57, 48, 55, 34, 37, 44, 43, 6, 1, 8, 15, 26, 29, 20, 19, 174,169,160,167,178,181,188,187, 150,145,152,159,138,141,132,131, 222,217,208,215,194,197,204,203, 230,225,232,239,250,253,244,243 Generating Packet CRC

Initialize crc register to 0x00 XOR each incoming byte with the previous crc value. Use the value as index to the table, to obtain the new crc. The last byte retrieved from the table is the final crc value. Append the final crc to the data packet.

Example: Data (decimal) = 25 36 1 crc = 0 2 crc = crc XOR 25 = 25 3 crc = crc_table[crc] = 79 4 crc = crc XOR 79 = 107 5 crc = crc_table[crc] = 22 Final Data to be transmitted should be: 25 36 22

Checking or verification of Packet CRC Initialize crc register to 0x00 XOR each incoming byte with previous crc value. Use the value as index to the table, to obtain the new crc. The last byte retrieved from the table is the final crc value. If the final crc value is zero then data is correct.

Example: Received Data (decimal) = 25 36 22

1 crc = 0 2 crc = crc XOR 25 = 25 3 crc = crc_table[crc] = 79 4 crc = crc XOR 79 = 107 5 crc = crc_table[crc] = 22 6 crc = crc XOR 22 = 0 7 crc = crc_table[crc] = 0 Final crc is zero, which means packet received is correct

A.6 HPS3000-9: CRC Implementation

CRC was computed with out shifting the slave address to the left.



"For master write (slave read), the "Wr" bit is used and the CRC of the following packet is computed:"

"For master read (slave write), the "Rd" bit is used and the CRC of the following packet is

computed:" Appendix B Assembly Cable Proper Termination

Applies to wire assemblies P/N 80866011470 (ASSY WIRE PRI/SEC CTRL HPS3000) and 80866012870 (ASSY WIRE FAN-LED FLEXI HPS3K9).

On the secondary control daughter board, terminate FAN-LED cable first before PRI/SEC cable

on Sec Control daughter board. On the other end, terminate first wire FAN-LED to the FAN BRD daughter board before connecting wire PRI/SEC to the primary control daughter board. See Figure below:

Figure 7 Assembly Cable Proper Termination