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UNIVERSITY OF LONDON
IMPERIAL COLLEGE OF SCIENCE, TECHNOLOGY AND MEDICINE
DEPARTMENT OF ELECTRICAL & ELECTRONIC ENGINEERING
INFORMATION ENGINEERING SECTION
INTERMEDIATE FREQUENCY CMOS ANALOGUE CELLS
FOR WIRELESS COMMUNICATIONS
by
KONSTANTINOS MANETAKIS
September 1998
A Thesis submitted for the degree of Doctor of Philosophy
of the University of London
and for the Diploma of Membership of Imperial College
To my parents and my teachers
II
Acknowledgments
I wish to express my gratitude to my supervisor Professor Chris Toumazou for his
guidance and support throughout this research period. His patience and meticulous
supervision are greatly appreciated and I am grateful to him
I would also like to thank Nortel Ltd. for financial and technical support. Special
thanks to Dr. Peter Mole and Mr. George Swanson of Nortel Ltd., Dr. Christos
Papavassiliou and Dr. Alison Payne of hnperial College, as well as. Dr. John Hughes
of Phillips Ltd. for technical discussions and encouragement.
Many thanks to Mrs. Wiesia Hsissen, Mrs. Melanie Joyce and to all the students of the
Information Engineering Section at hnperial College for their help, kindness and
patience.
Last but not least, I would like to thank my family for their love and support all the
way through.
Ill
Abstract
In modem wireless communications applications, higher operating frequencies, lower
power dissipation and a very high degree of integration are new specifications which
ask for design approaches quite different from the traditional radio-frequency design
techniques. CMOS, technology is becoming very attractive for the implementation of
wireless transceivers, because the very high integration levels that can be achieved,
and the prospect of integrating both the analogue and the digital part on the same
piece of silicon, offer a unique combination in meeting the above requirements with
reduced cost. In this Ph.D. thesis, we address a number of issues associated with the
application of CMOS technology in the design of VLSI circuits for wireless
applications. A number of high-performance CMOS analogue cells for IF signal
processing in wireless communications receivers have been designed and fabricated in
modem sub-micron CMOS technologies.
A CMOS compound device that achieves higher transconductance in comparison to a
single MOS transistor is presented. Based on this device, a CMOS current feedback
operational amplifier has been designed. Due to its high performance, it can be
utilized as a fundamental building block in various IF signal processing functions such
as amphfiers, filetrs, oscillators, etc. IF-sampling techniques utilizing bandpass
comtinuous-time Sigma-Delta modulators, offer several advantages in modem
receiver topologies. Integrated bandpass implementations of continuous-time
modulators require integrated continuous-time resonators. The linearity of the
modulator is limited by the linearity of the resonators utilized. We investigate the
fundamental performance limits, and the tradeoffs inherent in such configurations, and
present the design of a fully integrated, high-performance CMOS resonator. We
believe the long term plan in modem receiver topologies should be to push the A/D
converter closer to the antenna, and digitize directly the RF signal. For this, we
IV
investigate the fundamental limits of subsampling techniques for downconversion. We
propose a novel subsampling quadrature mixer, that lends itself to signle path
implementation by interleaving in time the in-phase and quadrature components. The
requirement for good phase and gain matching is thus inherently relaxed. A detailed
investigation of the feasibility of using monolithic subsampling mixers is included.
Contents
Acknowledgments III
Abstract IV
Contents VI
List of Figures IX
List of Tables XV
List of Principal Symbols XVII
Introduction- Thesis Outline XIX
Chapter 1 - Receivers for Mobile Communications
1.1 Introduction 1
1.2 Receiver Performance Specifications 4
1.3 Heterodyne Architectures 8
1.4 Image-Reject Architectures 11
1.5 Direct Conversion Architectures 12
1.6 Low-Intermediate Frequency Architectures 15
1.7 Wideband-Intermediate Frequency Architectures 17
1.8 Intermediate Frequency Sampling 19
1.9 Modem Receiver Architectures- Literature Survey 21
1.10 Technology Options 25
1.11 Conclusions 26
Chapter 2 - CMOS Compound Device and its Applications
2.1 Introduction 28
VI
2.2 Compound Device- Basic Operation 29
2.3 Compound Device- Large Signal Analysis 31
2.4 Compound Device- Small Signal Analysis 35
2.5 Voltage Buffer Implementation 39
2.6 The Current Feedback Opamp 46
2.7 Current Feedback Opamp Implementation 50
2.8 CFOA Application-Non Inverting Amplifier 53
2.9 Conclusions 58
Appendix 60
Chapter 3 - Gm-C Integrated Resonators: Design Methods and Nonidealities
3.1 Introduction 63
3.2 Review of Filter Synthesis Methods 67
3.3 Synthesis Methods for Gm-C Bandpass Filters 73
3.4 Integrators Nonidealities 76
3.5 Noise-Dynamic Range 81
3.6 Tuning Methods 87
3.7 Conclusions 89
Appendix 91
Chapter 4 - High Frequency CMOS Resonator Implementation
4.1 Linear CMOS Transconductors 93
4.2 Linear CMOS Transconductor- Basic Operation 99
4.3 Transconductor- Frequency Response 103
4.4 Transconductor- Noise Analysis 105
4.5 Transconductor- Linearity Analysis 108
4.6 Integrator Implementation 113
4.7 Resonator Implementation 118
4.8 Simulation Results 122
4.9 Conclusions 126
VII
Appendix 128
Chapter 5 - IF Bandpass Sampling Techniques
5.1 Introduction 130
5.2 Sample & Hold for Downconversion 133
5.3 Noise Folding 135
5.4 Sampling Clock Jitter 137
5.5 Switch Nonidealities 141
5.6 Proposed Quadrature Subsampling Mixer- Basic Principle 144
5.7 Opamp 1/f Noise and Offset 149
5.8 Wideband Thermal Noise 155
5.9 Finite Opamp Bandwidth and Gain 158
5.10 IF- Sampling Design Example 161
5.11 RF- Sampling Design Example 166
5.12 Interfacing to the A/D 168
5.13 Image Rejection 169
5.14 Conclusions 171
Chapter 6 - Conclusions and Future Work
6.1 Conclusions and Future Work 173
Appendix-1 MOS Transistor Modeling 178
Appendix- 2 Nonlinearity Analysis 185
Appendix-3 Circuit Details 189
Appendix-4 Typical Process Parameters 191
References 192
Publications 208
VIII
List of Figures
Chapter 1 - Receivers for Mobile Communications
Fig. .2.1 Basic Wireless Receiver Configuration 5
Fig. .2.2 Performance Degradation due to Adjacent channel Interferer 8
Fig. .3.1 Heterodyne Architecture 9
Fig. .4.1 Hartley Image Rejection 11
Fig. .4.2 Weaver Image Rejection 12
Fig. .5.1 Self-image problem in Direct Frequency Translation 13
Fig. .5.2 Direct Conversion Architecture 13
Fig. .5.3 Practical Homodyne System 14
Fig. .6.1 Active Asymmetric Polyphase Filter 16
Fig. .&2 Low-IF Topology 16
Fig. .6.3 Two-stage Passive sequence Asymmetric Polyphase Filter 17
Fig. .7.1 Wideband-IF Receiver 18
Fig. .7.2 Wideband-IF Downconversion Process 18
Fig. .7.3 Complex Downconverter 19
Fig. .8.1 Typical IF-Sampling Topology 20
Fig. .&2 Lowpass-SA and Bandpass-ZA A/Ds for IF-Sampling 21
Chapter 2 - CMOS Compound Device and its Applications
Fig 2.2.1 Cornmon-Drain and Cornmon-Gate Configurations 29
Fig 2.2.2 Compound Device (p-type) 30
Fig 2.3.1 Implementation of p-Compound Device 31
Fig. 2.4.1 Small Signal Equivalent of p-Compound Device 36
IX
Fig. 2.4.2 Noise Equivalent of p-Compound Device 38
Fig. 2.4.3 PSRR Equivalent Circuit 39
Fig. 2.5.1 Voltage Follower 40
Fig. 2.5.2 Buffer Second Order Harmonic Distortion 41
Fig. 2.5.3 Measured Harmonic Distortion at lOMHz 42
Fig. 2.5.4 Buffer Step Response 43
Fig. 2.5.5 Buffer Small Signal Equivalent 44
Fig. 2.5.6 Buffer Frequency Response 45
Fig. 2.5.7 Buffer Output Impedance 45
Fig. 2.6.1 Current-Feedback Opamp Macromodel 48
Fig. 2.6.2 Non-inverting Amplifier Configuration with CFOA 48
Fig. 2.7.1 Current Feedback Opamp 51
Fig. 2.7.2 Current Feedback Opamp Layout Plot 52
Fig. 2.7.3 Open-Loop Transimpedance Gain 52
Fig. 2.7.4 Negative Supply Common-Mode Rejection Analysis 53
Fig. 2.8.1 Non-Inverting Amplifier 54
Fig. 2.8.2 Non-Inverting Amplifier Frequency Response 56
Fig. 2.8.3 Non-Inverting Amplifier Step Response 56
Fig. 2.8.4 Non-Inverting Amplifier, Distortion Spectrum 57
Fig. 2.9.1 Utilizing the proposed CFOA as a building block 58
Chapter 3 - Gm-C Integrated Resonators: Design Methods and Nonidealities
Fig. 3.1.1 IF-Sampling Receiver 65
Fig. 3.1.2 Continuous-time ZA A/D in IF-Sammpling Receiver 66
Fig. 3.2.1 Gm-C First Order Section 68
Fig. 3.2.2 Bandpass - Lowpass Biquad 68
Fig. 3.2.3 Ladder Termination and Source Resistor Simulation 69
Fig. 3.2.4 Ideal Gyrator 70
Fig. 3.2.5 Inductance Simulation 70
Fig. 3.2.6 Grounded Inductor Simulation 71
Fig. 3.2.7 Floating Inductor Simulation 71
Fig. 3.2.8 Gm-C Lossless and Lossy Integrator Implementation 72
Fig. 3.3.1 Lowpass-to-Bandpass Transformation 73
Fig. 3.3.2 Lowpass-to-Bandpass Element Transformation 74
Fig. 3.3.3 Series Resonator with Gyrator 75
Fig. 3.3.4 Lowpass-to-Bandpass Integrator Transformation 76
Fig. 3.4.1 Nonideal Integrator Model 77
Fig. 3.4.2 Gm-C Resonator 78
Fig. 3.4.3 Simplified Nonideal Resonator Model 80
Fig. 3.5.1 Passive Resonator 81
Fig. 3.5.2 Resonator Noise Model 82
Fig. 3.5.3 Voltage Driven Resonator 84
Fig. 3.6.1 Frequency Tuning with external resistor 88
Fig. 3.6.2 FLL Frequency Tuning 88
Fig. 3.6.3 ALL Quality Factor Tuning 89
Chapter 4 - High Frequency CMOS Resonator Implementation
Fig. 4.1.1 Triode Region Transconductor 94
Fig. 4.1.2 Source-Coupled Pair 95
Fig. 4.1.3 Source Degeneration Scheme 95
Fig. 4.1.4 Varying Bias Triode Devices 96
Fig. 4.1.5 Source-connected Differential Pair 97
Fig. 4.1.6 Cross-coupled, Source-connected Pairs 97
Fig. 4.1.7 Differential Pair with Floating Voltage Sources 98
Fig. 4.1.8 Offset Bias Linearization 98
Fig. 4.1.9 Inverter based Transconductor 99
Fig. 4.2.1 Proposed CMOS Transconductor 100
Fig. 4.2.2 Offset-control Circuitry 103
Fig. 4.3.1 Small Signal Equivalent of MTB 104
Fig. 4.4.1 Main Transconductance Block Noise equivalent 106
Fig. 4.4.2 Total Output Noise Calculation 107
Fig. 4.5.1 Differential half-circuit of MTB 109
XI
Fig. 4.5.2 Transconductance Model Comparison 112
Fig. 4.5.3 Intermodulation Model Comparison 113
Fig. 4.6.1 Gm-C Integrator 114
Fig. 4.6.2 Positive PSRR Equivalent 116
Fig. 4.6.3 Transconductance Element Nonlinearity 118
Fig. 4.7.1 The Proposed Resonator 119
Fig. 4.7.2 Temperature Insensitive Frequency Tuning 121
Fig. 4.7.3 Temperature Insensitive Q-Tuning 122
Fig. 4.8.1 Continuous-time ZA AYD in IF-Sampling 123
Fig. 4.8.2 Layout Plot of the Fabricated Chip 124
Fig. 4.8.3 Frequency Response 125
Fig. 4.8.4 Two Tone Test 125
Chapter 5 - IF Bandpass Sampling Techniques
Fig. 5.1.1 Digital-IF Receiver 130
Fig. 5.2.1 Sample and Hold Model 133
Fig. 5.2.2 Downconversion due to spectral superposition 134
Fig. 5.3.1 Sample and Hold for Downconversion 137
Fig. 5.4.1 Clock time-uncertainty Model 140
Fig. 5.5.1 Sample and Hold 142
Fig. 5.5.2 Charge Injection Elimination 142
Fig. 5.6.1 Typical super-heterodyne Receiver Architecture 145
Fig. 5.6.2 Quadrature Downconversion from to IF 145
Fig. 5.6.3 Switched-Capacitor Implementation of Quadrature Mixer 147
Fig. 5.6.4 I/Q Components after Downconversion 148
Fig. 5.6.5 Spectrum of the I downconverted Stream 148
Fig. 5.6.6 Spectrum of the Q downconverted Stream 148
Fig. 5.7.1 SC Downconverter with Opamp Offset Voltage 149
Fig. 5.7.2 SC CDS Subsampler 151
Fig. 5.7.3 One Capacitor CDS S/H Subsampler 151
Fig. 5.7.4 Alternative S/H Stage 152
XII
Fig- 5.7.5 Improved S/H Stage 153
Fig. 5.7.6 Improved S/H for Subsampling Applications 154
Fig. 5.7.7 Chopper Stabilization Configuration 155
Fig. 5.8.1 Basic Sample and Hold Stage 156
Fig. 5.8.2 Basic S/H Stage - Noise Analysis 156
Fig. 5.8.3 Improved S/H for Subsampling Applications 157
Fig. 5.8.4 Improved S/H stage - Noise Analysis 157
Fig. 5.9.1 Quadrature SC Downconverter 159
Fig. 5.9.2 Opamp in closed-loop configuration during holding phase 159
Fig. 5.10.1 Subsampler Design Example 162
Fig. 5.10.2 Output Voltage after Quadrature Downconversion 165
Fig. 5.10.3 Slewing and Settling Detail 165
Fig. 5.11.1 RF-Sampling Design Example 167
Fig. 5.13.1 Hartley Image Rejection Architecture 169
Fig. 5.13.2 Hartley Image Rejection with the Proposed Mixer 170
Fig. 5.14.1 Proposed S/H Quadrature Mixer in IF and RF Sampling 171
Chapter-6 Conclusions and Future Work
Fig. 6.1.1 Utilizing the proposed CFOA as building block 174
Fig. 6.1.2 Utilizing the proposed Continuous-time Resonator 175
Fig. 6.1.3 Proposed S/H Quadrature Mixer in IF and RF Sampling 177
Appendix- 1 MOS Transistor Modeling
Fig. A l . l Simplified View of a MOS Transistor 178
Fig. A1.2 Small-Signal Equivalent of MOST 181
Fig. A1.3 Simplified Layout of MOST 183
Fig. A 1.4 Noise Model for MOST 183
Appendix- 2 Nonlinearity Analysis
XIII
Fig. A2.1 Weakly Nonlinear System 186
Fig. A2.2 Third Order Intermodulation 187
XIV
List of Tables
Chapter 1 - Receivers for Mobile Communications
Table 1.1.1 Summary of Digital telephony Standards 3
Table 1.2.1 GSM Adjacent Channel Interference Specifications 6
Table 1.2.2 GSM Blocking Level Specifications 7
Table 1.2.3 GSM Intermodulation Specifications 7
Chapter 2 - CMOS Compound Device and its Applications
Table 2.5.1 Measured Second Order Harmonic Distortion 42
Table 2.5.2 Measured and Predicted Slewrate Values 43
Table 2.5.3 Voltage Buffer Performance 46
Table 2.9.1 Current Feedback Opamp measurements Summary 57
Chapter 3 - Gm-C Integrated Resonators: Design Methods and Nonidealities
Table 3.1.1 Fully Integrated Continuous-time Resonator Specifications 67
Chapter 4 - High Frequency CMOS Resonator Implementation
Table 4.8.1 Fully Integrated Continuous-time Resonator Specifications 123
Table 4.8.2 Simulation Results of the Proposed Filter 124
Table 4.8.3 Performance Comparison 126
Chapter 5 - IF Bandpass Sampling Techniques
X V
Table 5.6.1 Quadrature Downconversion with S/H 146
Table 5.10.1 Quadrature Subsampler Design Examples 166
Table 5.11.1 RF-Sampling Design Example 167
Table 5.12.1 A/D Specifications 168
XVI
List of Principal Symbols
gTM Small Signal Transconductance
gak Small Signal Drain-Source Conductance
A Channel Length Modulation Parameter
K Transconductance Parameter
C Capacitance
R Resistance
I Current
V Voltage
Vt Threshold Voltage
a Body Effect Parameter
Y Conductance
k Boltzmann's Constant
T Absolute Temperature
Power Supply Rejection Ratio
HD, Second Order Harmonic Distortion
Third Order Intermodulation
Slewrate
A Gain
(0 Radial Frequency
f , F Frequency
tr Risetime
T Time Constant
Settling Time
Z Impedance
Vs Early Voltage
XVII
W Width
L Length or Inductance
BW Bandwidth
Q Quality factor
G Conductance
^ Phase
DR Dynamic Range
SFDR Spurious Free Dynamic Range
P Power
CMRR Common Mode Rejection ratio
0 Mobihty Reduction Parameter
S { f ) Spectral Density
H { f ) Trans fer Function
T Period
Channel Bandwidth
NF Noise Figure
M Oversampling Factor
Q , Oxide Capacitance
Q,. Overlap Capacitance
S/H Sample and Hold
I/Q Inphase, Quadrature Components
CDS Correlated Double Sampling
SC Switched Capacitor
Offset Voltage
P Feedback Factor
// Mobility
XVIII
Introduction - Thesis Outline
Under the current, and by large unanticipated, explosive growth in wireless
telecommunication applications, the interest amongst industry and universities in
utilizing CMOS technology should not be taken by surprise. Higher operating
frequencies, lower power dissipation and a very high degree of integration are new
specifications which ask for design approaches quite different from the traditional
radio-frequency design techniques. Traditionally, GaAs and Silicon Bipolar and
BiCMOS have constituted the major section of the RF applications. However, CMOS
technology is becoming very attractive for the implementation of wireless
transceivers, because the very high integration levels that can be achieved, as well as,
the prospect of integrating both the analogue and the digital part on the same piece of
silicon, offer a unique combination in meeting the above requirements with reduced
cost. In this Ph.D. thesis, we aim to contribute towards this direction, by addressing a
number of issues associated with the application of CMOS technology in the design of
VLSI circuits for wireless applications.
In chapter one, after a brief introduction to the contemporary wireless mobile
communication applications, we survey traditional and modem receiver architectures.
The advantages and disadvantages of each configuration are presented. A discussion
of the currently available technology options is also included. The important issue of
performance requirements from the analogue part of a modem mobile receiver is
addressed. Much attention is paid to contemporaiy IF and RF sampling techniques,
that appear to be an important step towards the software re-configurable receiver.
One of the main disadvantages of the MOS transistor when compared to the bipolar
transistor, is the smaller transconductance it achieves for the same bias current.
Because of this limitation, several important building blocks in analogue signal
XIX
processing, suffer from deteriorated performance when implemented in CMOS. In
chapter two, we approach this problem with the introduction of a novel CMOS
compound device that achieves higher transconductance in comparison to a single
MOS transistor by the application of local feedback. Up to now, high performance
current feedback operational amplifiers have been mostly implemented in bipolar
technologies. The reason being that the output impedance achieved by conventional
CMOS voltage followers is much higher than their Bipolar counterparts. Our
technique enable us to design a CMOS voltage follower with considerable lower
output impedance. As a result, the CMOS current feedback opamp we then propose,
achieves high performance, and can be used as a general VLSI building block for the
realization of various baseband and IF signal processing functions such as amplifiers,
filters, oscillators, etc. in CMOS as shown in Figure 1.
V — o — [ y -
premier LNA
gam conirol
+ CFOA
UK CMOS CFOA a* building block
Figure 1. Utilizing the proposed CFOA as building block in a modem receiver
A different way to overcome the poor characteristics of MOS transistors for RF is by
utilizing alternative receiver architectures. Receiver architectures can be tailored to the
specific characteristics of CMOS. Early digitization offers several advantages. IF-
sampling techniques utilizing bandpass Sigma-Delta modulators, provide a first step
towards this direction. Most Delta-Sigma modulators are implemented with discrete-
time circuits, switched-capacitor (SC) implementations being by far the most
common. This is mainly due to the ease with which monolithic SC filters can be
designed, as well as, the high linearity they offer. The demand for high speed ZA
oversampling A/D converters especially for bandpass signals, makes it necessary to
look for a technique that is faster than switched-capacitor. This demand has stimulated
X X
researchers to develop a method for designing continuous-time AE A/Ds. Although
continuous-time modulators are not easy to integrate, they possess a key advantage
over their discrete-time counterparts. The sampling operation takes place inside the
modulator loop. As a result, it is possible to "noise-shape" the errors introduced by
sampling and provide a certain amount of anti-aliasing filtering at no cost. On the
other hand, they are sensitive to memory effects in the D/As and are very sensitive to
jitter. They must also process continuous-time signals with high linearity, hi
communications applications, meeting the latter requirement is complicated by the
fact that the signals are located at very high fi-equencies.
LNA Mixer
Oscillator
Dig. Sinew«ve Gen.
MUL LPF MUL LPF
4* J — ) Continuous-lime j — )
7lC resonator 7 ^
Continuous-time resonator H >
Most difficult to imokmeni block
Figure 2. Utilizing the proposed Continuous-time Resonator in Modem Receiver
Integrated bandpass implementations of continuous-time modulators require
integrated continuous-time resonators. The linearity of the modulator is limited by the
linearity of the resonators utilized. The gm-C approach offers advantages of complete
system integration and total design fi-eedom. However, the design of pure CMOS
high-Q, high-linearity resonators at the tens of MHz is very difficult. It is considered
to be the most demanding and challenging sub-block of a bandpass continuous-time
Sigma-Delta modulator. In chapter three, the fundamental performance limits, and the
tradeoffs inherent in the design of continuous-time resonator configurations are
investigated in detail. Having understood the fundamental tradeoffs, in chapter four,
we present a CMOS high performance resonator. A test chip has been designed and
XXI
fabricated. Our implementation offers a good tradeoff between integratability,
tunability and performance, and can be used in the implementation of continuous-time
ZA converters in contemporary wireless applications as shown in Figure 2.
Our investigation of the design tradeoffs inherent in high-frequency, high-selectivity
integrated resonators, reveals that receiver architectures with relaxed analogue
filtering requirements are highly desirable. Much research is currently conducted
towards IF digitization. IF sampling has the advantage of shifting the demanding
channel selection task from the analogue part to the DSP, which is an important step
towards the software re-configurable receiver. However we believe that the long term
plan should be to push the Analogue-to-Digital converter closer to the antenna, and
digitize directly the RF signal.
V LNA Mixer RF
— r > — @ — IF
S&H I/Q
A/D Filler — r > — @ — Filler f. S&H A/D
aniialiwing
Local Oscillaior \
IF-SampUng
V RF
Filler ~t> ^ S&H I/Q.
A/D S&H A/D
' . RT-Sampling .
Figure 3. Proposed S/H Quadrature Mixer in IF and RF Sampling Configurations
In chapter five of the thesis we concentrate on discrete-time, subsampling techniques
for downconversion. The fundamental performance limits when utilizing bandpass
sampling are discussed. Then, we propose a novel sampled-data quadrature mixer
based on a sample/hold stage. By strategically choosing the undersampling frequency,
the technique lends itself to single path implementation by interleaving in time the in-
phase and quadrature components. The requirement for good phase and gain matching
is thus inherently relaxed. An additional advantage is that well established switched-
capacitor circuit techniques can be readily applied. Several alternative sample/hold
implementations are presented, and the performance required by the operational
amplifier for both IF and RF sampling applications is discussed. An image rejection
topology based on the proposed quadrature mixer is subsequently presented. Our
investigation reveals that with the presented CMOS techniques, RF sampling is a
XXII
viable alternative to continuous-time mixers in non-critical receiver applications as
shown in Figure 3. However, further work is needed to boost the performance to the
levels of modem mobile telephony standards.
XXIII
Chapter 1 - Receivers for Mobile Communications
Chapter 1
Receivers for Mobile Communications
1.1 Introduction
Wireless technology came into existence in 1901 when Guglielmo Marconi succeeded
in transmitting radio signals across the Atlantic. Wireless two-way communications
however, did not become available to the public, but had been mainly utilized by
emergency workers like police officers, paramedics, and the military etc. Public
bidirectional communications remained wired, except for a small minority of
dedicated radio hobbyists. The invention of the transistor, the development of
Shannon's information theory and the conception of the cellular system paved the way
for cheap mobile communications for the public. The last few years, wireless
communications and its applications have grown rapidly. The introduction of digital
data transmission in combination with digital signal processing and digital flow
control has provided for the development of many new wireless services. While an
immediate objective of the wireless industry is to combine cordless and cellular
phones to allow seamless communication virtually everywhere, the long term plan is
to produce an omnipotent wireless terminal that can handle voice, data, video, and
provide computing power. Personal communication systems (PCS) are almost here [1-
1].
Cellular radio can be regarded as the earliest form of wireless personal
communications. It allows the subscriber to place and receive telephone calls over the
wireline telephone network wherever cellular coverage is provided. Roaming
Chapter 1 - Receivers for Mobile Communications
capabilities extend service to users traveling outside their home service areas. Cellular
system design was pioneered during the seventies by Bell Labs with the development
of the AMPS system (Advanced Mobile Phone Service). First generation cellular
systems (AMPS, TAGS etc.) use analogue frequency modulation (FM) for speech
transmission and frequency shift keying (FSK) for signaling, hidividual calls use
different frequencies (FDMA). Analogue cellular telephone systems use the frequency
spectrum inefficiently. The modulation schemes consume a large bandwidth, and
every cellular telephone transmits continuously at constant power, therefore appearing
as a potential interferer to other users at nearby frequencies. As a result, the spectrum
allocated to analogue cellular phones especially in metropolitan areas nears exhaustion
[1-7].
The development of low rate digital speech coding and the continuous increase in
device density of integrated circuits made full digital second-generation systems
viable. Digitization allows the use of time division multiple access (TDMA) and code
division multiple access (CDMA) as alternatives to FDMA, to better utilize the scarce
spectrum. With TDMA, the usage of each radio channel is partitioned into multiple
timeslots. Each user is assigned a specific frequency/timeslot combination. Thus, only
a single mobile handset in a given cell, uses a given frequency at any particular time.
With CDMA, a frequency channel is used simultaneously by multiple mobile handsets
in a given cell, and the signals are distinguished by spreading them with different
codes (direct sequence spreading). The obvious advantage of both TDMA and CDMA
over FDMA, is the support of more users per base station per spectrum unit.
Additional advantages include flexibility for mixed voice/data communications,
reduced RF transmit power, encryption capabilities, and reduced system complexity
[1-2].
Today, many new digital cellular systems are being introduced. In Europe, the GSM
system (Global System Mobile) dominates. It is used for person-to-person voice and
data communication around 900MHz. TDMA with eight timeslots per radio channel
is utilized. Each user transmits periodically in every eighth slot and receives in a
corresponding slot. Thus, each base station needs only one transceiver for eight
channels. Speech data is transmitted compressed at 22.8kb/sec including error
Chapter 1 - Receivers for Mobile Communications
correction. The system utilizes medium sized cells of approximate radii lOKm, and a
typical maximum transmission power of IW. It has now become very successful in
Asia, Africa and South America. Originally GSM was intended for the 900MHz band.
In 1989, 150MHz near 1.8GHz were assigned for Personal communication networks
(PCN) using the GSM standard. This new system DCS 1800 (Digital Cellular System)
for Europe and DCS 1900 for the USA does not yet provide country-wide coverage as
standard GSM does, but ultimately a similar success is expected as for GSM. In north
America, the NADC (North American Digital Cellular) system is also used. It utilizes
smaller cells than GSM, and CDMA for channel multiplexing. Channel rate is
9.6kb/sec. In Japan, PDC is used (Personal Digital cellular). It is based on TDMA
with signaling rate 42kb/sec.
GSM NADC DECT PHS
Down-link Freq. Band (MHz) 935-960 869-894 1880-1900 1900
Up-link Freq. Band (MHz) 890-915 824-849 1880-1900 1900
Multiple Access Method TDMA TDMA TDMA-
TDD
TDMA-
TDD
Modulation Method GMSK 7t/4 -
DQPSK
GMSK 7t/4 -
QPSK
Speech Data Rate (kb/s) 13 8 32 32
Modulation Data Rate (kb/s) 271 49 32 384
Handset Output Power (W) 3.7m-l 2.2m-6 &25 10m
Channel Spacing (KHz) 200 30 1762 300
Table 1.1.1 Summary of Digital telephony Standards
A digital wireless application intended for indoor and office use is the DECT system
(Digital European Cordless Telephone). DECT uses TDMA and time division
duplexing with 12 timeslots per carrier in each direction. As a result, a DECT base
station can support multiple handsets simultaneously with a single transceiver. In
north America and Japan, alternative digital cordless systems are the PACS (Personal
Access Communications Services) and PHS (Personal Handyphone System)
respectively. The salient characteristics of these various systems are summarized in
Chapter 1 - Receivers for Mobile Communications
Table 1.1.1 [1-7]. For data transmission, new wireless data systems are being
introduced. These systems are designed for packet-switched operation. Wide-area
messaging systems (paging) use licensed spectrum, while wireless local area networks
(LANs) are privately owned and provide high-rate data communication over a small
area, usually in the ISM bands (Industrial, Scientific and Medical) [1-2, 1-3, 1-4].
The future of wireless personal communications offers many possibihties. In Europe,
the short term is in exploiting GSM and DECT including further evolution and
internetworking these standards. Mobile handsets that can roam across Europe and
beyond are currently under development. On the long term, goal is a Universal Mobile
Telecommunications System (UMTS), which would unify cellular, cordless, wireless
LAN and paging systems. There are some situations in which providing radio
coverage with cellular-like terrestrial wireless networks is either not economically
viable (in sparsely populated areas) or physically impractical (in the sea). In these
cases, mobile satellite services (MSS) could fill the gap, allowing complete global
coverage. These systems can support both data services, as well as, interconnection to
the public switched telephone network (PSTN). Geostationary satellites, low earth
orbit, medium earth orbit or highly elliptical orbit satellites are utilized in various
existing systems (INMARSAT-M, Iridium, Odyssey and ELMSAT are some
examples). Despite the technical and economic hurdles, MSS may become an
important component in the future wireless global network [1-2, 1-4].
1.2 Receiver Performance Specifications
The bandpass form of wireless communication channels, defines the two basic
functions a receiver must accomplish. On the antenna side, a front-end part accurately
translates the desired RF spectrum to a frequency band, where the processing required
to extract the message is relatively cost effective. At the same time it needs to
condition the signal and remove adjacent channel interference while maintaining
receiver sensitivity. On the user side, a back-end or baseband part performs the actual
demodulation and information extraction. Figure 1.2.1 illustrates the basic
configuration of a wireless receiver.
Chapter 1 - Receivers for Mobile Communications
high-frequency
information in user detectable
form \
front-end \ baseband / front-end 'f\
baseband user
low-frequency
Figure 1.2.1 Basic Wireless Receiver Configuration
The receiver front-end has to be able to downconvert very small signals (typically
some microvolts) from a very-high operating frequency (typically hundreds of MHz to
some GHz), to a much lower intermediate frequency (typically tens of MHz to DC).
Low-noise and linearity specifications are extremely challenging. In most modem
digital wireless communications receivers, demodulation is performed in the digital
domain with the aid of a digital signal processor (DSP) or dedicated digital hardware.
Demodulation circuitry/algorithm depends on the kind of modulation that has already
been performed (BPSK, QPSK, MSK, FSK, OMSK etc.). As an example, most of the
baseband processing in GSM is done by DSPs. DECT baseband processing on the
other hand is usually delivered with digital hardware alone [1-7]. In any case,
demodulation circuitry requires a quadrature baseband signal. The front-end circuitry
must therefore downconvert the wanted channel in a quadrature (In-phase and
Quadrature-phase components) fashion. This however needs not necessarily be done
in an analogue way. The front-end may downconvert to an intermediate frequency,
while the final quadrature downconversion to baseband can be done by the DSP itself
In general, complexity, cost, power dissipation and the number of external
components are the primary criteria in selecting receiver architectures.
The wireless communications environment imposes severe constraints upon receiver
specifications. The most important limitation is the narrowband spectrum allocated by
regulatory organizations to wireless services. This in turn translates to limited rate of
information, and as a result, data compression and bandwidth efficient methods for
modulation and coding are indispensable. A wireless radio-frequency receiver
typically finds itself immersed in a sea of unwanted and potentially interfering signals.
From that chaos, it must be able to pick out the unique desired signal, reproduce and
Chapter 1 - Receivers for Mobile Communications
amplify it with near perfect fidelity. Nonlinearities in the front-end along with strong
off-band signals, corrupt reception resulting to various unwanted effects. Harmonic
generation, gain compression, desensitization and blocking, cross modulation as well
as intermodulation phenomena may appear. Therefore, mobile receiver systems must
achieve high 1-dB compression points, as well as, high third-order intercept points
(Appendix-2). Another important issue is the dynamic range of the receiving system.
Dynamic range is the ratio of the most strong signal the receiver can handle to the
most weak one. The upper bound is limited by linearity performance, while the lower
bound is set by noise. The minimum detectable signal is usually in the vicinity of
— WOdBm ( 0.71//F^^^ in a 50^2 system), thus demanding very low noise in the
receive path. Due to the wide range of received signal levels, automatic gain control is
often used [1-1].
The required performance for mobile receivers is specified in function of the bit error
rate (BER), frame error rate (PER) and residual frame error rate (RFER), which must
be met for different types of channels and propagation conditions. These performance
measures take into account all possible effects that can result in limiting the amount of
received useful information, and characterize the receiver as a whole (including path-
loss and multi-path fading). The analogue part of the receiver however, can only
deteriorate the performance by adding unwanted signals (noise, image,
intermodulation). To measure the performance of the analogue part, the signal-to-
unwanted-signal ratio (SUSR) specification is introduced. This index, known also as
reference sensitivity performance, can be obtained by means of the BER, FER and
RFER. For GSM, SUSR specification is required to be larger than 9dB [1-3, 1-5].
GSM co-channel and adjacent-channel Interference specifications
co-channel interferer 9dB below wanted signal
interferer at ±200KHz 9dB above wanted signal
interferer at +400KHZ 41dB above wanted signal
interferer at ±600KHZ 49dB above wanted signal
Table 1.2.1 GSM Adjacent Channel Interference Specifications
Chapter 1 - Receivers for Mobile Communications
The reference sensitivity level is the lowest possible input signal level for which the
SUSR specification can still be met when no other interfering signal is present. For
GSM, this is defined as -102dBm. As a result, total equivalent input noise level must
be lower than -11 IdBm, For GSM, the SUSR specification has to be met with a co-
channel and adjacent channel interferers as shown in Table 1.2.1.
The effects of interfering signals appearing further than ±600KHz from the wanted
channel are specified by the blocking signal characteristics. These are given in Table
1.2.2. As mentioned before, performance degradation occurs when two strong off-
band signals, generate third order intermodulation products in the band of interest. For
GSM, reference sensitivity performance must be met, when the signals shown in
Table 1.2.3 are present.
GSM Blocking Level Specifications
f '\n\ erfercr f channel < 1.6 MHz — AZdBm
1 . 6 M % < f int erferer f channel < 'iMHz — hZdBm
f'mierferer fchannel — ^ M H z - ThdBm
1 0 0 ^ z < / ; , , ^ _ < 9 1 5 M ; 6 QdBm
9 8 0 A r % < / i , . ^ _ < 1 2 . 7 5 G . / 6 OdBm
Table 1.2.2 GSM Blocking Level Specifications
GSM Intermodulation Specifications
wanted chaimel -99dBm
pseudo-random modulated signal, SOOKHz from wanted
channel frequency
-43dBm
sine-wave signal, 1.6MHz from wanted channel frequency -43dBm
Table 1.2.3 GSM Intermodulation Specifications
Figure 1.2.2 illustrates performance degradation due to single and double interferers.
On the top half of Figure 1.2.1, a single interferer is shown. On the lower half, two
Chapter 1 - Receivers for Mobile Communications
interferers create intermodulation components that fall in the band of interest. In both
cases, the in-band resulting interference components must be at least 9dB (GSM
SUSR specification) below the wanted signal. Detailed signal levels are shown in
Tables 1.2.1, 1.2.2 and 1.2.3.
wanted channel
SUSR
Inlejferers
wanted channel
SOOKHz gOOKHz
Figure 1.2.2 Performance Degradation due to Adjacent channel Interferers
In the next few sections, we review the basic options available for implementing
integrated receivers. It should be noted that there is no obvious 'right' architectural
solution, and this is reflected in the fact that different manufacturers have
implemented different approaches for existing products, and in no doubt will continue
to do so in the future.
1.3 Heterodyne Architectures
The classic and most widely used implementation for wireless receivers is the
superheterodyne architecture illustrated in Figure 1.3.1. The first RF filter at the input
serves to attenuate strong out-of-band signals, that may act as potential interferers and
deteriorate the linearity performance of the low noise amplifier (LNA). The local
oscillator frequency is chosen to mix with the received radio frequency (RF) spectrum,
thereby translating the wanted signal to the intermediate frequency (IF). Tuning is
accomplished by varying the local oscillator frequency to mix different input
frequencies into the IF passband. High-performance, low phase-noise voltage
controlled oscillators (VCO) are typically realized with discrete-component high-Q
inductors and varactor diodes [1-8]. The resulting signal is subsequently bandpass
Chapter 1 - Receivers for Mobile Communications
filtered and amplified. A second downconversion may follow. In the case of digital
modulation, the last downconversion generates both I and Q components [1-1].
Y — I R F 1—TV-
Filler I 1 / ^
rniage rejection Mixer seleciivity limiting
band LNA seleciing
image channel
Fi l e r 2 Filler I
Oscillaior
Filter 2 ' 10 Demodulator
wanted channel image rejection
filter
fLO
4 >
downconversion
1|F
Figure 1.3.1 Heterodyne Architecture
The most important feature of the heterodyne receiver is its selectivity, i.e. its
capability to process and select small signals in the presence of strong interferers.
Thus, because channel selection takes place in the last intermediate frequency, the
selectivity filters have much more relaxed requirements. Because the mixing process
generates both the sum and the difference frequency products, there is an input
frequency other than the desired one, which can also mix to produce an output at the
IF. This is known as the image, and is shown at the lower half of Figure 1.3,1. The
image response can be reduced with the use of RF anti-imaging filtering prior the
mixer input. Since the desired RF signal can be 40 to 60dB below the image signal,
the RF anti-image filters are required to provide 60 to 80dB of image rejection.
Because of the very high frequency of operation and the severe selectivity-linearity
specifications, anti-imaging filters are usually external discrete SAW filters [1-3].
The issue of image rejection leads to an interesting tradeoff among four parameters:
the amount of image noise, the exact value of the intermediate frequency IF, the loss
introduced by the image-reject SAW filter and the power dissipation [1-1, 1-7]. The
choice of high intermediate fi-equency IF, increases the separation of the image from
the wanted channel, thus allowing the image-reject filter to provide more attenuafion.
Therefore, the task of image rejection is simplified. On the other hand, it is usually
Chapter 1 - Receivers for Mobile Communications
more difficult to obtain the necessary channel selectivity and gain within the
acceptable power budget if the IF frequency becomes very high. For a given value of
the intermediate frequency, image noise is reduced by utilizing a higher-Q image
rejection filter. This is achieved, at the expense of increased passband. Because of
Noise Figure (NF) specifications, the filter loss should not exceed a few dB. For the
900MHz and 1.8GHz bands, typical values of intermediate frequencies range from
50MHz to about 200MHz [1-7].
One way to overcome the limitations of the heterodyne is to introduce a second
frequency conversion. In this case gain is divided between the first and second
intermediate frequencies, thus simplifying the overall design. For noise reduction
purposes, the gain at the first IF should be as large as possible. A tradeoff exists
between first IF gain and overall linearity. A drawback of the heterodyne architecture
is the fact that the high-Q image-rejection and the channel-selection filters cannot be
integrated and are therefore placed off-chip. This means that the low-noise amplifier
(LNA) at the input, as well as, the mixer and/or the IF amplifier must drive a 5 0 0
load. This adds another dimension to the tradeoffs among noise, linearity, gain and
power dissipation. The off-chip SAW filters are expensive and bulky. As a result, the
heterodyne architecture is less attractive for small, low-cost handsets.
The great majority of radio receivers employ the superheterodyne principle because
the fixed intermediate frequencies lead to high selectivity. That is, a first high IF is
used for image rejection, and a second low IF is used for ease of high-selective
filtering. The ability to carefully confrol the gain, noise figure, and selectivity through
the use of different stages and high-Q discrete components, has made the
superheterodyne approach the dominant choice for many decades [1-14]. As a typical
example, the first chip-set from Siemens for GSM, uses a double-heterodyne
architecture with selectable first IF anywhere between 45 to 90 MHz. A SAW image
rejection filter with passband 25MHz is utilized. For mixing, a Gilbert-cell loaded
with an of-chip LC tank is used. An on-chip buffer subsequently drives a second
external SAW filter that provides the desired 200KHz channel selectivity. Automatic
gain control (AGC) with 70dB range is utilized. Finally, the selected channel is
downconverted to baseband with a quadrature mixer to provide the I and Q
10
Chapter 1 - Receivers for Mobile Communications
components required for the GMSK demodulation done by the DSP. Input noise
Figure is 7dB with 27mA drawn from the 5V supply [1-7]. Recently, the use of a
tunable monolithic notch filter centered at the image frequency has been proposed as
an alternative solution to an external bandpass SAW filter [1-10]. The measured
image rejection is 65dB with an image range from 2.34 to 2.55 GHz. However, this
method of image rejection does not provide protection from strong of-band blocking
signals.
1.4 Image-Reject Architectures
The issues related to the off-chip image reject filter have motivated wireless designers
to seek for alternative techniques. Image-reject mixers provide a trigonometric
solution to the problem. The desired channel and its image are downconverted by a
two-path mixer, each mixer path driven by quadrature phases of the local oscillator.
The mixer outputs are then phase-shifted 90° with respect to one another. The sum of
these two signals will select the desired chaimel (above the local oscillator frequency),
while the difference will select the image charmel (below the local oscillator
frequency). This architecture was first introduced by Hartley in 1928 [1-1], and is
illustrated in Figure 1.4.1.
Figure 1.4.1 Hartley Image Rejection Mixer
An alternative solution is offered by the Weaver architecture shown in Figure 1.4.2.
The Weaver technique allows an arbitrary translation of the signal band without image
interference. In this configuration, the signal is downconverted in two steps. In the
first step, the input is mixed with the quadrature phases of the first local oscillator and
the result is lowpass filtered. In the second step, a downconversion to zero frequency
11
Chapter 1 - Receivers for Mobile Communications
is implemented, followed by signal subtraction. The result is the downconversion of
the wanted channel at DC without image noise. The charmel selection can then be
achieved with lowpass filtering. In practice, some amplification is required after the
first mixer pair in order to reduce the total noise Figure [1-1].
) LPF
Figure 1.4.2 Weaver Image Rejection Mixer
With image-rejection mixers, the extent of image suppression depends on the gain
matching of the two paths, the phase accuracy of the LO quadrature outputs, and in the
case of the Hartley architecture on the phase accuracy of the 90° phase shift between
the two paths. Phase shift circuits generally suffer from tradeoffs among linearity,
noise and power dissipation [1-1]. For these reasons, this concept has only become
practical with the advent of integrated circuits, where the two paths can be well-
matched on chip and track each other over temperature. For typical matching in IC
technologies, the image is rejected by about 30 to 40 dB [1-1, 1-7]. As an example, in
[1-8] a receiver based on the Weaver architecture needs phase matching better than 4°
and gain matching better than 5% to obtain 30dB image rejection. In practice, image
rejection mixers are used to relax the requirements on the external SAW anti-imaging
filters.
1,5 Direct Conversion Architectures
Also known as the homodyne architecture appears to be the natural topology for
downconverting a signal from radio frequencies to baseband. In this approach, the
input spectrum is mixed with a local oscillator, so that the wanted channel is
downconverted directly at DC. In this case, the image channel is the mirror of the
wanted channel itself (self-image), as shown in Figure 1.5.1.
12
Chapter 1 - Receivers for Mobile Communications
î O f-O
downconvcTsion , / A
F 1 f̂ O
Figure 1.5.1 Self-image problem in Direct Frequency Translation
The image problem is solved by utilizing a quadrature mixer. The wanted channel is
downconverted by a two-path mixer, each mixer path driven by quadrature phases of
the local oscillator. This is equivalent to mixing with a positive frequency 6 '̂̂ '-°' only.
Mixing with a single positive frequency translates only negative frequencies down.
f = 0 f i o
d o w n c o n vers ion
M)
SIN
COS
LPF
LPF
Figure 1.5.2 Direct Conversion Architecture
A typical configuration is shown in Figure 1.5.2. The precision with which the two
paths of Figure 1.5.2 can be matched determines how good the image signal is
suppressed. However, the specifications on image suppression are not as demanding
as in the case of the heterodyne receiver. This is because, the image channel is the
mirror of the wanted channel itself, while in the case of a heterodyne system the image
signal can be much stronger than the wanted signal. An image suppression of at least
20 to 40 dB is still required for acceptable reception quality. In fact, although the
13
Chapter 1 - Receivers for Mobile Communications
homodyne receiver was the first receiver topology proposed, only during the last
fifteen years has become feasible. This is because of the matching properties modem
integrated technologies offer. The advantages of the direct conversion architecture are
obvious. There is no need for high-Q image-rejection filters. However, pre-filtering is
still required to reduce of-band strong interferers and prevent mixing of the RF
spectrum with components of the local oscillator signal [1-3]. Another important
advantage is that channel selection can be done with lowpass integrated filters as
shown in Figure 1.5.2.
The elimination of external expensive and bulky high-Q components renders the
homodyne architecture as the ideal solution for efficient integrated receiver
implementations. One of the first integrated implementations for paging receivers can
be found in [1-20]. However, several issues have impeded its widespread use. One of
the most important problems associated with direct conversion is the leakage of the
local oscillator signal to either the mixer input, or the antenna itself, where radiation
may occur. The unintentionally transmitted LO signal may reflect off nearby objects
and be re-received. This results in self-mixing and consequently to a time-varying DC
offset at the output of the mixer [1-8]. It can also create interference problems to other
nearby receivers, and necessitates the use of diplexers in ft'equency division duplexing
(FDD) systems [1-4].
A/D
prefilter LNA
gain control
offset control
DSP
— ) ( ^
Figure 1.5.3 Practical Homodyne System
This Hvandering' offset can easily be of the order of tens of millivolts, and along with
the inherent circuit offset results in saturation phenomena and severely reduces the
dynamic range. For this reason, homodyne receivers require sophisticated offset-
cancellation techniques. With the introduction of DSP technology for baseband
processing, complex non-linear algorithms can be realized that determine the DC-
14
Chapter 1 - Receivers for Mobile Communications
level dynamically. DC-level information is then fed-back to the analogue part as
shown in Figure 1.5.3 (decision feedback).
Since a zero-IF system is a lowpass system, it is sensitive to even order distortion
products. If two strong interferers close to the channel of interest experience even
order distortion, they may be translated to low frequencies before the mixing
operation takes place. This can happen due to nonlinearities in the LNA, as well as,
mismatches in the quadrature mixer [1-1], For this, LNAs and mixers intended for use
in direct conversion systems need high linearity and a dynamic range of about 60dB
[1-19]. Due to the limited gain provided by the LNA and the mixer, the
downconverted signal is relatively small and quite sensitive to noise. Since flicker
noise becomes significant at very low frequencies, low-noise amplification of the
baseband signal is required [1-1]. Finally, in the absence of RF pre-filtering, a
harmonic of the local oscillator can downconvert interference at the baseband. A
typical modem implementation is presented in [1-21]. The receiver has a maximum
gain of 105dB with 80dB automatic gain control range. The measured phase error is
less than 1°. A class-AB servo amplifier is used to reduce DC offset, while
maintaining a turn-on time of 200|J.Sec. Power supply range is from 2,7 to 5V, with
50mA supply current.
1.6 Low-Intermediate Frequency Architectures
Recently, nonzero-IF, or low-IF, architectures have been proposed. By offsetting the
local oscillator from the carrier frequency by a small, but nonzero, amount, many of
the problems associated with the direct conversion approach are alleviated. FUcker
noise, Vandering' DC offset, self interference, as well as, sensitivity to even-order
distortion products are not issues any more [1-3]. The IF is chosen so that the image
frequency is strategically located to meet image rejection specifications. For example,
in a GSM receiver there are 'holes' located between two adjacent channels.
Low-IF topologies are based on the use of complex filters. Active complex filters are
obtained by applying a linear frequency transformation j c o j [ a } - 0 } , p ) , on a
15
Chapter 1 - Receivers for Mobile Communications
lowpass prototype, that does not preserve frequency symmetry [1-3]. The resulting
structure has a passband at either positive or negative frequencies as shown in Figure
1.6.1. These filters can be used to provide channel selection in a low-IF topology. The
IF is chosen sufficiently low at about twice the channel bandwidth. Using quadrature
mixing, the wanted channel is located at the positive side of the spectrum, while the
image channel at the negative side of the spectrum. In this way, the active asymmetric
polyphase filter can be implemented using integrated active-RC techniques with large
signal to noise ratio [1-11]. Figure 1.6.2 shows a typical low-IF architecture.
Lowpass Filter
Atqucncy transfbnnation
Complex Bandpass Filter •
image channel wanted channel
Figure 1.6.1. Active Asymmetric Polyphase Filter
Alternatively, passive sequence asymmetric polyphase filters can also be utilized.
These passive networks are a symmetric and repetitive version of a classical RC-CR
allpass network as shown in Figure 1.6.3. Each section of the network has a pole
frequency (In- RC). The poles are spaced equally on a log scale across the
desired frequency bandwidth. The resulting topology has a stopband at either positive
or negative frequencies [1-12].
1 \ A/D 1 J } A/D
active asymmetric
LO A polyphase filter
i I—Ha/D|
Figure 1.6.2 Low-IF Topology
By increasing the number of cascaded sections, the sensitivity to absolute component
values is reduced. A passive sequence asymmetric polyphase filter may be used in
reverse as a wideband quadrature generator [1-3]. In this case a differential input
16
Chapter 1 - Receivers for Mobile Communications
signal is applied, while the other input is grounded. By increasing the number of
stages, the phase difference of the outputs remains 90° relative to each other, while the
amplitude errors become smaller over a larger frequency range. With such a topology,
any signal, even the antenna signal can be put to quadrature.
9 0
H h H h j H h j H h eyvw- i—e-fWv-L
9 0
k I 'VVV-—t-fvvv
270
r v v v Y-rvvv^
Figure 1.6.3 Two-stage Passive sequence Asymmetric Polyphase Filter
A low-IF implementation using integrated passive sequence asymmetric polyphase as
wideband quadrature generators can be found in [1-13]. The double-quadrature
downconverter used reduces the effect of local oscillator phase errors on the image
rejection. However, gain mismatch still limits the image rejection to about 40 to 50dB.
As a conclusion, the low-IF architecture avoids the offset problems of the homodyne
approach by utilizing a non-zero low-IF frequency. At the same time, it avoids the
need for external high-Q anti-imaging filters by employing asymmetric passive or
active polyphase filtering structures along with quadrature mixing. Overall, it offers
good performance and integratability.
1.7 Wideband Intermediate Frequency Architectures
Although the heterodyne and the homodyne topologies have been separately proposed,
it is possible to combine them in a double conversion receiver where the first
frequency translation takes place to a high-frequency IF, while the second to zero IF.
An example is shown in Figure 1.7.1. The fixed first local oscillator downconverts all
the receive channels to the intermediate frequency, as shown in Figure 1.7.2, hence the
name wideband-IF. The fact that a fixed first local oscillator is used, results in
improved phase noise performance. A band-select filter is used to suppress the image
frequency.
17
Chapter 1 - Receivers for Mobile Communications
Mixer
IF filter
IF Amplifier
A/D USP
constant Local
Oscillator V V
Figure 1.7.1. Wideband-IF Receiver
Because a high intermediate frequency is used (200 to 300 MHz), the RF filter can be
quite relaxed. A bandpass filter at the first IF is used to relax linearity performance in
the IF amplifier. All the channels at IF are then frequency translated directly to
baseband (DC) using the second variable local oscillator and a quadrature mixer.
Channel tuning is done with the second local oscillator. Individual channel selection is
obtained with lowpass filters as in the case of the homodyne receiver.
RF prefilter
IF filter
wanted channel
1 St Downconversion
2nd Direct conversion
Figure 1.7.2 Wideband-IF Downconversion Process
The second frequency translation directly to zero frequency does not create
retransmission problems that plagues a direct conversion system and results in time-
varying dc offsets. Although the second local oscillator is at the same frequency of the
IF desired carrier, the offset that results at baseband from self-mixing is relatively
constant and can be canceled using one of the adaptive DC offset compensation
methods as for example in [1-9]. Since channel selection is done at baseband, the
architecture renders itself to the possibility of a programmable integrated channel
18
Chapter 1 - Receivers for Mobile Communications
filter for multistandard receiver applications. A wideband-IF receiver has been
presented in [1-8]. To further suppress the image frequency, a complex downconverter
with six mixers (Figure 1.7.3), bearing resemblance to the Weaver technique has been
utilized. However, the RF bandpass filter still needs to provide greater than 30 to
40dB image rejection. Increased hardware, increased power dissipation and path gain
mismatch are additional drawbacks.
cos
U(S) ±
Chapter 1 - Receivers for Mobile Communications
A step towards this direction is the IF-sampling receiver, which can utihze the
principle of using the inherent aliasing property of sampling, to realize the last
downconversion stage (bandpass sampling) [1-16, 1-17]. IF-sampling architectures are
usually based on the heterodyne approach, where analogue frequency translations
move the receive spectrum to a lower intermediate frequency. Digitization then takes
place at this lower frequency, and DSP techniques are subsequently used to extract the
signal. Such techniques include direct digital synthesis (DDS), digital
downconversion, digital filtering for channel selection, demodulation, as well as,
multirate techniques such as decimation and interpolation for reducing the sampling
rate down to the Nyquist rate [1-14]. In this type of architecture, the DSP chip can
control narrowband channel characteristics such as bandwidth and the rejection of
adjacent interferers by means of numerical parameters. The receiver can dynamically
adapt itself as the properties of the wireless channel change with time. Such
characteristics open the possibility of implementing software-controlled receivers that
can support multiple standards and are suitable for use in widely varying propagation
environments [1-15].
Mixer
RF
Filter
1 St Local
Mixer
Ist IF
® ~ " 2nd IF
Filter ® ~ " Filter f. A/D DSP
antialiasing
. 2nd Local , .
Oscillator \ Oscillator I
Figure 1.8.1 Typical IF-Sampling Topology
Figure 1.8.1 illustrates the principle of operation. Since A/Ds usually perform
sampling before quantization, they can operate as downconversion mixers.
Configurations may vary depending on whether a single or double conversion
heterodyne is utilized. The A/D converter is the key component in these radio
receivers. In the absence of channel select filtering to remove potential nearby
interferers, the dynamic range of A/Ds must be high. Accuracy and linearity are
primarily determined by the sample-and-hold (S&H) circuitry, while jitter in the
sampling clock can introduce noise in the desired output of the converter [1-18]. The
penalty incurred with the use of high-speed A/Ds is the increased power consumption
and the increased DSP speeds. Oversampling, noise-shaping converters of the
20
Chapter 1 - Receivers for Mobile Communications
baseband or bandpass type are commonly used to relax the requirements on the
analogue components at the expense of higher sampling rates [1-18, 1-25, 1-26, 1-27].
In the upper half of Figure 1.8.2, digitization using lowpass Sigma-Delta converters is
shown. Because of the direct conversion utilized, the system is sensitive to dc offsets,
flicker noise, and path mismatch errors.
cos
* A / D I
A / D
D S P
A / D Q
A / D
SIN
1,0,-1,0
A,/D D S P
0,1,0,-1
Figure 1.8.2. Lowpass-SA and Bandpass-ZA A/Ds for IF-Sampling
The lower half of Figure 1.8.2 shows the use of a bandpass Sigma-Delta instead, to
digitize the signal at IF. Downconversion to baseband is done in the digital domain.
DC offsets, flicker noise, as well as, path mismatch is not an issue. The disadvantages
in this case is that the bandpass Sigma-Delta modulator need to sample the input
signal at a higher frequency than the IF (usually by a factor of four). This results in
increased power dissipation. Also, any center frequency shift due to circuit
imperfections such as incomplete opamp settling and finite DC gain, can translate into
significant SNR degradation.
1.9 Modern Receiver Architectures - Literature Survey
A typical example of the IF-sampling architecture is the Marconi H2550 MF/HF
Receiver, presented in [1-22]. A bandpass sigma-delta (ZA) A/D converter is used to
sample the final IF of 2.5MHz. Sampling frequency is lOMHz. This type of converter
21
Chapter 1 - Receivers for Mobile Communications
provides two distinct advantages. First, the high Spurious Free Dynamic Range
(SFDR) ensures that conventional automatic gain control is not required. Secondly,
the converter provides a near 'analogue' 3-to-l third order nonlinearity characteristic.
This well behaved linearity characteristic helps to specify performance in
conventional RF circuit terms [1-23]. Final downconversion to baseband takes place
in the digital domain with the aid of a digital ASIC. Baseband processing is
accomplished with three Motorola 56002 Digital Signal Processors.
In [1-24], a tunable bandpass Sigma-Delta A/D converter is utilized to sub-sample the
RF signal. RF pre-filtering is used to fulfil the Nyquist criterion. In a conventional
bandpass ZA modulator, the loop filter is usually designed so that it has an all-pass
characteristic for the input, and a bandstop characteristic for the quantization noise. In
[1-24], an extra bandpass filter function for the input is implemented at the expense of
less quantization noise suppression in the signal band. This filter is tunable, and
provides channel selection. After the SA converter, a frequency estimator for FM
demodulation is used. For BER = 10^, the sum of the quantization noise and off-
band signals should be at least 6dB less than the desired signal.
In [1-28], a BiCMOS bandpass Delta-Sigma modulator for a 200KHz channel
centered at an intermediate firequency of 10.7MHz is presented. Sampling fi-equency is
42.8MHz. A second-order noise shaping is used to obtain 57 dB SNR. In [1-29], an
alternative method is proposed. The direct-conversion concept is applied to the
bandpass modulator. In this way, a bandpass modulator can be implemented using
lowpass integrators after the bandpass spectrum is shifted down to baseband. In order
to downconvert the IF spectrum to DC without image folded into the same baseband,
quadrature demodulation is utilized. The path gains, as well as, the phase differences
of the two paths need to be matched. The circuit is independent to capacitor mismatch,
but finite dc gain results in incomplete charge transfers between the storage capacitors
and the output capacitors. Sampling fi-equency is 8MHz to shape noise at 2MHz. With
3.3V supply, it exhibits an SNR of 56dB within a 30KHz bandwidth. Circuit
nonidealities, such as finite dc gain, switch mismatch etc., create an image component
56dB below the wanted signal.
22
Chapter 1 - Receivers for Mobile Communications
In [1-30], a CMOS receiver for a 200KHz signal at an intermediate frequency of
81 MHz is presented. A sixth-order bandpass Sigma-Delta modulator, sampled at
13MHz, downconverts and digitizes the signal at an IF of 3.25MHz. Subsequently, the
bitstream at the output of the converter is frequency translated to baseband digitally.
With 3V supply and 14.4mW consumed power, the receiver achieves 92dB of
dynamic range. In [1-31], a passive sigma-delta modulator without operational
amplifiers is presented for digitization of a 20KHz signal at lOMHz. A switch clocked
at lOMHz, samples the input and downconverts the signal at DC. The loop filter of the
modulator is based on a passive switched capacitor voltage amplification scheme,
with a low pass characteristic. More gain is provided by the comparator. The
modulator achieves 13bit resolution with 0.25mW from a 3.3V supply.
In [1-32], a fourth-order quadrature bandpass Sigma-Delta modulator is described.
The receiver architecture is based on the low-IF approach. The wanted channel is first
downconverted in quadrature to an IF of 3.75MHz. The traditional bandpass
modulator takes in a real , analogue input, and produces a single high-speed bitstream
output that is representative of the input within a narrow bandwidth. This can be
extended to the quadrature, or complex case, if a complex filter is placed in the
modulator loop. A quadrature modulator takes in a complex analogue input (pair of
real signals in quadrature) and produces a complex digital bitstream that is
representative of the complex input within a narrow bandwidth. The modulator
complex loop filter is sampled at lOMHz. The resulting noise transfer function obtains
more than 60dB attenuation at +3.75MHz. The signal transfer function obtains 20dB
amplification at +3.75MHz, and lOdB attenuation at -3.75MHz (image band). With
130mW power dissipation, the modulator obtains 67dB dynamic range for a 200KHz
bandwidth.
In [1-33], a two-path, switched capacitor bandpass Sigma-Delta modulator is
presented. Conventional bandpass Sigma-Delta modulators are made of resonators,
implemented using a two-integrator loop. Nonideal effects such as finite DC op amp
gain and incomplete settling in the integrators, degrade resonator performance.
Performance degradation becomes worse with increasing the sampling frequency. In
[1-33], performance degradation is attacked at the architectural level by implementing
23
Chapter 1 - Receivers for Mobile Communications
the resonators with a 2-path filter structure. Each path is sampled at only the half
frequency. Gain and phase mismatch between the signal transfer functions in the two
paths compromises the suppression of mirror images of the desired signal that appear
in the passband. With an effective sampling of 80MHz, a dynamic range of 75dB is
obtained for a 200KHz channel. Image suppression is better than 40dB.
hi [1-34], a subsampled, switched-capacitor narrowband bandpass decimator is
proposed, to simultaneously implement the functions of frequency downconversion
and narrowband filtering. An analogue front-end is assumed, that downconverts the
RF signal to an intermediate frequency of 21.4MHz followed by an antialiasing filter
that rejects unwanted bands according to antialiasing specifications. The subsequent
decimator consists of two cascaded stages. The first stage is a polyphase FIR
decimator, that downconverts the signal to 455KHz. The sampling frequency is
reduced by a factor of four, from 27.927MHz to 6.982MHz. Its frequency response
characteristic attenuates potential aliasing bands by putting notches at frequencies
77 • 6.9817M/fe±455AHz, except at the mirrors of the passband at 21.4MHz. The
resulting nearest aliasing bands at 6.527MHz and 34.454MHz need to be attenuated
by the antialiasing filter. The second stage is an IIR decimator that reduces the
sampling frequency by a factor of three, to 2.327MHz. It consists of an input
polyphase structure, and a SC filter, based on a bandpass ladder-type coupled
resonators prototype, clocked at 2.327MHz. The input polyphase structure is
responsible for creating the zeros that attenuate aliasing bands around 2.327MHz and
4.654MHz. The subsequent SC filter, provides a sixth-order, allpole characteristic,
with center frequency at 455KHz, bandwidth 25KHz, and passband ripple 0.5dB. It
serves the required channel selection. With perfect matching, the structure offers more
than 50dB attenuation of aliasing bands. However, mismatch between the different
paths of the polyphase structures, compromises the suppression of mirror images of
the desired signal that appear in the passband.
In [1-35], a four-IF superheterodyne architecture is presented. The RF signal (ISM
Band) is subsampled at 78MHz. The resulting first IF is 26MHz. In order to avoid
destructive aliasing during the subsampling process, the RF signal is bandlimited by
an external RF pre-filter. Subsequently, three 2:1 decimators downconvert the signal
24
Chapter 1 - Receivers for Mobile Communications
to the final IF at 3.25MHz. Each decimator is preceded by a SC biquad to suppress
potential alias bands. The final sampling rate is 9.8MHz. The total gain provided by
the circuit is 36dB. Noise Figure for a 30KHz bandwidth is 47dB. The input third-
order intercept point is -16dBm.
1.10 Technology Options
The choice of a viable IC technology for RF applications depends on factors such as
performance, wafer cost, level of integration, and time to market [1-38]. Traditionally,
GaAs and silicon Bipolar and BiCMOS constitute the major section of the RF
applications. GaAs processes offer higher cutoff frequencies due to improved electron
mobility and saturated drift velocity. Additionally, their semi-insulating substrate
allows the fabrication of high quality inductors and capacitors. On the other hand,
silicon Bipolar and BiCMOS technologies offer higher levels of integration. This
results in reduced routing of RF signals on- and off-chip, therefore minimizing the
overall power dissipation and cost [1-38, 1-39, ]. Silicon-germanium technologies
now evolving have the potential to provide bipolar and MOS devices with
considerable larger speed capabilities [1-41].
Modem silicon technologies have reached the level where they are comparable with
GaAs for applications in the 1-10 GHz range. At very short lengths, the saturated drift
velocity dominates the unity current-gain fi-equency, and transistors fabricated in
silicon need higher voltage levels to obtain cutoff fi-equencies comparable to GaAs.
The relatively low substrate resistivity of silicon, results in severe coupling problems
in monolithic implementations. Careful circuit design including the use of fully
balanced signal paths, guard rings, as well as, a variety of silicon-on-insulator (SOI)
and silicon-on-sapphire (SOS) technologies can alleviate the problems significantly
[1-40]. Additionally, the higher low-field mobility and the metal-gate stmcture of
GaAs have a major impact on device noise figure [1-38].
Supported by the enormous momentum of the digital market, CMOS technology has
recently become a topic of active research. Modem sub-micron processes offer tens of
GHz unity gain fi-equencies. Additionally, CMOS offers the unique possibility to
25
Chapter 1 - Receivers for Mobile Communications
integrate the RF front-end and the baseband digital circuitry on the same chip.
However, substrate coupling, parameter variation with temperature and incomplete
device characterization for RF are problems that must be addressed. Nevertheless, in
the long run, CMOS technology will acquire many of qualities desirable for RF, and
GaAs and silicon Bipolar will find themselves increasingly pressed by competition
with CMOS in the 1-3 GHz frequency range [1-38].
1.11 Conclusions
In this chapter, after a brief introduction to the contemporary wireless mobile
communication applications, the issue of performance requirements from the analogue
part of a modem mobile receiver is addressed. In order to quantify our discussion, the
challenging performance requirements of the GSM mobile telephony standard were
given. Then, the various different options available for implementing integrating
receivers were presented. Their advantages and disadvantages were discussed, while
special attention was paid to the feasibility of complete integration. Subsequently,
modem IF-sampling techniques were presented, including a brief presentation of the
most important current research directions. Finally, a discussion of the available
technologies was included.
In order to realize a modem mobile wireless communications receiver, a number of
basic blocks such as amplifiers, mixers, oscillators, and filters need to be utilized.
Moreover, in order to achieve a high degree of integration and meet the portability
requirements at reduced cost, CMOS implementations are highly desirable. These
basic blocks should also achieve high performance in order to meet the very
demanding specifications required by the modem mobile telephony standards. In the
next few chapters we concentrate on the design of pure CMOS building blocks for
such applications. In chapter two, a CMOS current-feedback operational amplifier that
can be used as a general VLSI building block for the realization of various signal
processing functions at baseband or IF (amplifiers, oscillators, filters etc.) in both
traditional and modem receiver architectures is presented, hi chapter four, a novel
high-performance continuous-time CMOS resonator that can be utilized to provide
26
Chapter 1 - Receivers for Mobile Communications
noise-shaping in continuous-time EA modulators is discussed. Continuous-time EA
modulators are used in state-of-the-art IF-sampling receiver topologies. Finally, in
chapter five, along with the discussion of bandpass sampling techniques, a novel
switched-capacitor, discrete-time quadrature mixer that can be used in IF-sampling
and direct RF-sampling applications is presented.
27
Chapter 2 - CMOS Compound Device and its Applications
Chapter 2
CMOS Compound Device and its Applications
2.1 Introduction
Over the last decade MOS technology has made possible a tremendous increase in
chip size and complexity. As a result, it is now feasible to integrate complete systems
containing both analogue and digital parts on the same chip. Currently, in
communication electronics there is considerable interest in utilising CMOS not only
for the baseband but also for the IF and RF functions. Highly integrated
implementations of transceivers in CMOS require new circuit ideas for the
fundamental building blocks (LNAs, Mixers, etc.), as well as, alternative system
architectures in order to overcome the poor characteristics of the MOS transistor at RF
[2-1].
One of the main disadvantages of the MOS transistor over the BJT, is its reduced
transconductance gm for the same bias current. The transconductance is one of the
most important parameters of a transistor, because it is a measure of the transfer
efficiency from input to output. The higher the transconductance, the higher the
current gain of the transistor. A better criterion however, is the transconductance to
bias current ratio gm / . It measures the efficiency with which the current is used
to create transconductance. For the MOS transistor, this ratio obtains its maximum
value in the weak inversion region of operation. In strong inversion it is inversely
proportional to the square root of the bias current [2-2]. Because of this limitation,
several important building blocks in analogue signal processing, suffer from
deteriorated performance when implemented in CMOS. In the following section, a
novel CMOS compound device that achieves higher transconductance in comparison
28
Chapter 2 - CMOS Compound Device and its Applications
to a single MOS transistor for the same bias current is introduced. This is achieved by
the application of local feedback [2-3]. In the next sections, the basic operation of the
compound device is discussed, and the design tradeoffs are investigated in detail.
Up to now, high performance current feedback operational amplifiers have been
mostly implemented in bipolar technologies. The reason being that the output
impedance achieved by conventional CMOS voltage followers is much higher than
their bipolar counterparts. Our technique enable us to design a CMOS voltage
follower with considerably lower output impedance. As a result, the CMOS current
feedback opamp we then propose, achieves high performance, and can be used as a
general VLSI building block for the realization of various baseband and IF signal
processing functions such as amplifiers, filters, oscillators, etc. in CMOS. Finally, a
typical non-inverting amplifier based on the proposed current feedback opamp is
included, and measured results are reported to verify the high performance obtained.
2.2 Compound Device - Basic Operation
Figure 2.2.1 shows two typical MOS transistor configurations. In both cases, current
source provides the bias current. On the left, the common-drain configuration is
presented. This configuration serves as a voltage buffer with input at the gate of Ml
and output at the source of Ml . On the right, the common gate configuration is shown.
This configuration can be used as a current buffer stage. The input is at the source of
Ml , while the output current is obtained from the drain terminal. In both cases,
performance can be optimised by maximising the transconductance of the MOS
device utilized.
Figure 2.2.1. Common-Drain and Common-Gate Configurations
29
Chapter 2 - CMOS Compound Device and its Applications
In the case of the common-drain configuration, the impedance looking into the source
of Ml is given by the inverse of parameter. Small signal analysis reveals:
y22=m + gds, (2.2.1.a)
(2.2. l.b)
(2.2. l.c) out v..
gTM
gm + gds
where gm, gds are the small signal transconductance and the drain-source
conductance of Ml respectively. Since gm = K- Ig [Appendix-1], in order to
increase the transconductance of Ml , one must increase the bias current 1^. This
results in increased power dissipation. Alternatively, the dimensions of Ml can be
increased {K = j i - - W j L). This however, results in additional parasitic
capacitances, and thus inferior frequency performance. Figure 2.2.2 shows a
configuration which can achieve higher transconductance than the source follower of
Figure 2.2.1, for the same bias current [2-3]. The current of M2 is fed back to M l by
the current mirror with current transfer a:l . This configuration can be seen as a
compound transistor, with gate that of Ml , and source the source of M2. A drain
terminal can be obtained, by duplicating the current of M2.
Figure 2.2.2. Compound Device (p-type)
Small signal analysis reveals:
30
Chapter 2 - CMOS Compound Device and its Applications
gm, • gffl,
(gTM, gTMz '
>̂21 (gm^+gds^)-&-gm^
(2.2.2.a)
(2.2.2.b)
(2.2.3.c) (gm, + gcfa,) - (gTM; + gckz)
Equations (2.2.2.a) and (2.2.2.b), show that by setting the current mirror transfer ratio
to a = (gm, + gds^ , the output impedance looking into the compound source
becomes very small. At the same time, the compound transconductance becomes very
large. A simpler technique than of Figure 2.2.2, has been used before for reducing the
X node impedance in BJT implementations of current conveyors [2-4]. There