Interleaved switching of parallel ZVS hysteresis currentcontrolled invertersCitation for published version (APA):Schellekens, J. M., Duarte, J. L., Hendrix, M. A. M., & Huisman, H. (2010). Interleaved switching of parallel ZVShysteresis current controlled inverters. In Proceedings of the 2010 International Power Electronics Conference(IPEC) (pp. 2822-2829). Piscataway: Institute of Electrical and Electronics Engineers.https://doi.org/10.1109/IPEC.2010.5543891

DOI:10.1109/IPEC.2010.5543891

Document status and date:Published: 01/01/2010

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Download date: 31. Jan. 2020

Interleaved Switching of Parallel ZVS HysteresisCurrent Controlled Inverters

J.M. Schellekens, J.L. Duarte, M.A.M Hendrix and H. HuismanDepartment of Electrical Engineering, Electromechanics and Power Electronics

Eindhoven University of Technology, Eindhoven, The Netherlands

Abstract—A robust self-interleaving mechanism for par-allel hysteresis current controlled inverters is proposed,with sustained switching under all load conditions. A fastinterleaving technique that can be applied for normal loadconditions is combined with a self-interleaving mechanism,which ensures correct switching during voltage clampingoperation. A minimum switching frequency and maximumduty cycle is guaranteed under all load conditions enablingthe use of low-cost bootstrap circuits to drive the high-side switches. The interleaving approach results in reducedvolume of the passive components and better dynamicresponse. The self-interleaving mechanism was analyzedusing the state-plane method, extended to multiple parallelmodules. Simulations were conducted to verify the combinedoperation of both methods and measurements were per-formed on a 3 kW prototype zero-voltage-switching inverterwith a discrete hysteresis current controller.

I. INTRODUCTION

With respect to the switching losses, voltage stress,and natural commutation of the switching node voltage,Zero Voltage Switching (ZVS) inverters have significantadvantages over conventional hard switched inverters.A disadvantage is the large circulating current, at leasttwo per unit current stress, that is required to achieveZVS. This high current results in a large volume of thepassive components for high power inverters. Interleavingreduces the input and output current ripple significantlyand results in better dynamic response and smaller volumeof passive components. The advantages of both techniquescan be exploited by combining ZVS and interleavingtechniques [1].

ZVS hysteresis current controlled inverters, also re-ferred to as Resonant Pole Inverters (RPI) [2], normallystop switching under voltage clamping conditions (i.e.,no voltage difference across the inductor) because thedesired current level is not reached. This precludes theuse of a low-cost bootstrap circuit to drive the high-side MOSFETs in the switching legs because of thepossibility of very long on time. To enable the use ofsimple bootstrap circuits, a minimum on time of thelow side switch and a maximum duty cycle has to beguaranteed. Parallel connected modules, with interleavedswitching and guaranteed minimum on time of the lowside switch, must maintain interleaved switching underall output conditions to make volume reduction of thepassive components possible.

This paper proposes a method to guarantee a minimumon time of the low side switch and maximum duty cycle,together with a novel self-interleaving technique that

guarantees interleaved switching under voltage clamp-ing conditions. Both are combined with an improvedinterleaving technique for normal output condition, basedon [3], [4]. The methods together guarantee interleavedZVS under all output conditions, enabling the use of alow-cost boot strap circuit to drive the high-side switchesand a reduced volume of the passive components.

In Section II the basic topology of the RPI is pre-sented. Section III introduces a mechanism to guaranteea minimum on time of the lower switch and a maximumduty cycle, based on additional turn-off criteria. In Sec-tion IV the topology is extended to operate in paralleland the advantages of interleaved switching are analyzed.Section V presents the proposed improved interleavedswitching method for hysteresis current controlled invert-ers under normal load conditions. Section VI introducesa novel self-interleaving technique with sustained inter-leaved switching during voltage clamping. Finally, theoryand simulations are compared to measurements of a 3 kWzero voltage switching resonant pole inverter prototypewith its control implemented in an FPGA.

II. BASIC TOPOLOGY

Figure 1 shows a single RPI switching leg as presentedin [5], where all voltages are referenced to ground. Zerovoltage turn-on is guaranteed by ensuring that iLf commu-tates to the anti-parallel diode before the correspondingswitch is turned on. Zero voltage turn-off is achievedby fast turn-off of the switches in combination withlimited dusn/dt of switching node voltage usn duringcommutation. The limited dusn/dt is accomplished bycharging or discharging the switching node capacitanceCr, using the energy stored in the filter inductor Lf , duringthe dead-time between switching. A minimum current inLf is required to guarantee complete commutation of theswitching node voltage [2], given by

iLfmin =2Zr

�UDC |uout|, (1)

where Zr =�

Lf/Cr. When applying hysteresis currentcontrol to the RPI topology, the rules that have to beapplied to guarantee Zero Voltage Switching (ZVS) andgeneration of the requested output current iout are thefollowing:

1) Turn-off of S1 shall only occur if iLf ≥ iLfmin .2) Turn-off of S2 shall only occur if iLf ≤ −iLfmin .

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978-1-4244-5393-1/10/$26.00 ©2010 IEEE

S1D1

Lf LlRlD2

S2

Cr/2 Cf/2

Cf/2Cr/2

ioutuoutusn

iLfUDC

Gnd

UDC

Fig. 1. Resonant pole inverter (RPI) switching leg with load.

3) Turn-on of a switch shall only occur when the bodydiode (D1 or D2) of the corresponding switch startsconducting.

4) The average filter current iLf equals the set-pointcurrent iset.

Rule 4 is accomplished by setting the turn-off levels suchthat iset = (ihi + ilo) /2, where ihi and ilo are the highand low turn-off levels of the hysteresis current controller(see Fig. 2).

Different types of hysteresis current control have beenproposed for the RPI topology [6], [7]. Most of themmake use of fixed minimum current to guarantee commu-tation of the switching node voltage over the full outputvoltage range, given by

ıLfmin = max�iLfmin (uout)

�=

2Zr

UDC. (2)

Fixed hysteresis current control [6] results in variableswitching frequency, depending on uout, with high circu-lating current, at least 2 p.u. current stress, over the fullrange of iset. Variable hysteresis current control can beused to minimize the circulating currents. Figure 2 depictsthe variable hysteresis current control strategy proposedin [6], where ith has to be set such that commutationof usn is guaranteed (≥ ıLfmin ) and that the maximumswitching frequency is limited. The maximum switchingfrequency can be approximated by

fswmax ≈ 1min (TonS1 + TsnD2 + TonS2 + TsnD1)

, (3)

where TonS1 and TonS2 are the on time of the correspond-ing switches, and TsnD1 and TsnD2 are approximationsof the time required to commutate the switching nodevoltage usn to the positive or negative supply voltage rail.The maximum switching frequency occurs when iset anduout are 0, resulting in TonS1 = TonS2 and TsnD1 = TsnD2 ,which leads to

fswmax ≈ 1

2�2LfUDC

ith + 2Crith

UDC

�

=UDCith

4 (Lf i2th + CrU2DC)

. (4)

The switching frequency is limited by the resonancefrequency of Cr and Lf , resulting in the following upperbound for guaranteed ZVS:

fswmax ≤ 12π

√LfCr

(5)

Variable hysteresis current control results in a switchingfrequency that is dependent on both iset and uout, but

⇐ ihi = 2 · iset + ith

ilo = 2 · iset− ith ⇒

⇓ihi = ith ≥ ıLfmin

⇑ilo = −ith ≤ −ıLfmin

t [s]

i[A

]

→

↑

0

iset

iLf

ihi / ilo

Fig. 2. Variable hysteresis current control.

it leads to less current stress for |iset| ≤ ıset comparedto fixed hysteresis current control, where ıset is themaximum set-point current. Also, more sophisticated hys-teresis current control schemes have been proposed [7],which include the sign of uout to reduce the current stresseven more under certain output conditions. The approachdepicted in Fig. 2 is used in this paper. Table I shows thecorresponding turn-off levels.

TABLE ITURN-OFF CURRENT LEVELS FOR VARIABLE HYSTERESIS CURRENT

CONTROL

iset ≥ 0 < 0ihi 2iset + ith ithilo −ith 2iset − ith

III. SUSTAINED SWITCHING

A minimum on time of the lower switch (S2) anda maximum duty cycle is required when a low-costbootstrap circuit is used to drive the high side switch(S1). This minimum on time is not guaranteed when usinghysteresis current control. Normally, hysteresis currentcontrolled inverters stop switching when voltage clampingoccurs, that is, when there is no voltage difference leftacross Lf to change the current (uout = ±UDC). Thishalted switching can be prevented by adding additionalturn-off criteria to the hysteresis current controller. Suchan additional turn-off criterion can be based on diLf/dtor uout.

Figure 3 shows simulated data and the correspondingstate-plane for clamping of uout to the positive supplyvoltage UDC using variable hysteresis current control onthe RPI topology (Fig. 2) combined with the followingadditional turn-off criteria:

1) If diLf/dt ≤ 0 and S1 is conducting then turn offS1.

2) If diLf/dt ≥ 0 and S2 is conducting then turn offS2.

From t0 to t1 in Fig. 3, S1 is conducting and iLfis increasing. When assuming no losses in the resonantcircuit and constant iout during the on time of S1, the state

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i[A

]

ihi = 2 · iset + ith⇑

ilo = −ith⇑

ith = ıLfmin⇓

ilo = 2 · iout − ith⇓

iLfioutiset

t [s]

u[V

]

→t0 t1 t2 t3 t4 t5

0

UDC

uoutusn

(a) Time waveforms

uout [V]

Zf·i

[V]

↑

Zf · ilo⇑

Zf · ihi⇑

Zf · ith⇓

Rmin

t0

t1

t2

t3

t4

t5

0 Udc

0

↑

Zf · ilo⇑

Zf · ihi⇑

Zf · ith⇓

Rmin

t0

t1

t2

t3

t4

t5

0 Udc

0

↑

Zf · ilo⇑

Zf · ihi⇑

Zf · ith⇓

Rmin

t0

t1

t2

t3

t4

t5

0 Udc

0

↑

Zf · ilo⇑

Zf · ihi⇑

Zf · ith⇓

Rmin

t0

t1

t2

t3

t4

t5

0 Udc

0

↑

Zf · ilo⇑

Zf · ihi⇑

Zf · ith⇓

Rmin

t0

t1

t2

t3

t4

t5

0 Udc

0

↑

Zf · ilo⇑

Zf · ihi⇑

Zf · ith⇓

Rmin

t0

t1

t2

t3

t4

t5

0 Udc

0

Zf · iLfZf · ioutZf · isetihi / ilo

(b) State-plane

Fig. 3. Sustained switching during voltage clamping.

variables in this interval can be described as follows,

uout (t) =�

uout (tn) − UDC

�cos

�ωf (t − tn)

�+ (6)

Zf

�iLf(tn) − iout

�sin

�ωf(t − tn)

�+ UDC

iLf (t) =�

iLf(tn) − iout

�cos

�ωf(t − tn)

�− (7)

Yf

�uout(tn) − UDC

�sin

�ωf(t − tn)

�+ iout,

where Zf =�

Lf/Cf , Yf = Z−1f and ωf = 1/

√Lf Cf . At

t1, diLf/dt ≤ 0 occurs and S1 is turned off. The switchingnode voltage usn commutates to the negative supply andD2 starts conducting. After that, S2 is turned on and iLfdecreases. To ensure that the minimum current requiredto commutate (ith ≥ ıLfmin) is reached at t3 and t5, theradius R of the circular path in Fig. 3(b), that occurswhen S1 is conducting, should satisfy R ≥ Rmin =Zf (ith − iout). To guarantee ZVS during, or just before,voltage clamping of uout to the positive supply, ilo has tobe adjusted to ilo = 2iout − ith if iout < iset < 0 and

0 ≥ (uout − UDC)2 + Z2

f

�i2Lf − i2th − 2iout (iLf − ith)

�.

(8)To reduce computational load or to allow implementationin an analog circuit, (8) can be simplified to a conservativebound as

0 ≥ (uout − UDC) − Zf (ith − iout) . (9)

Equation (9) triggers the clamping operation in aconservative way, resulting in a reduced slew rate duringone switching cycle.In the state-plane of Fig. 3(b) during voltage clampingoperation (6) and (7) describe a half circle with radius

R centered around (UDC, Zf iout). This cycle repeatsuntil clamping stops, which occurs when iout ≥ iset.The above derived equations are valid for clamping ofuout to the positive supply rail. Similar equations can bederived for clamping to the negative rail. Also a differentdiLf/dt can be chosen to optimize the minimum on timeof the lower switch and the maximum duty-cycle (δmax).

When using the above presented method for sustainedswitching under voltage clamping conditions, the mini-mum switching frequency of the RPI topology depictedin Fig. 1, can be approximated as

fswmin ≈ 1max (TonS1 + ToffS1)

≈ UDC

πUDC

√Lf Cf + Lf (|iout| + ith)

, (10)

when neglecting the influence of the commutation timeof usn. Also the maximum duty cycle can be determined,resulting in

δmax ≈max�

TonS1

TonS1 + ToffS1

�

≈ πUDC

√Lf Cf

πUDC

√Lf Cf + Lf (|iout| + ith)

. (11)

The maximum duty-cycle and minimum on time of thelower switch depend on Lf , Cf , ith, and iout, and are welldefined, making it easy to design a low-cost bootstrapcircuit to drive the high side switch.

IV. PARALLEL CONNECTION

Figure 4 depicts the parallel connection of modules asproposed in [3]. Every module has its own filter inductorLf but the filter capacitor Cf is shared. This shouldbe compared to simply paralleling switches to achievethe desired output current/power specification, in whichcase the output filter consists of only one inductor andcapacitor.

Parallel modules with interleaved switching presentadvantages over paralleling of switching devices. The

Cr/2/N

Cr/2/N

N·Lf

Cf/2

Cf/2

Cr/2/N

Cr/2/N

N·Lf

Fig. 4. Parallel connection of modules.

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effective switching frequency of the system is N timeshigher. As a consequence the response time to a change ofiset is on average N times faster than for single modules,resulting in a better dynamic response. Each modulesupplies only N−1 of the current to the load resultingin less stored energy per filter inductor. When assumingthe same number of switches used for both N parallelmodules and a single module, and that ith = ıLfmin foriset = ıset, the ratio between total stored energy in Nparallel inductors and a single inductor becomes

ELfN

ELfS

=N 1

2NLf

�2N−1 ıset + 2N−1ith

�212Lf (2ıset + 2ith)

2 = 1. (12)

Due to the N times smaller ripple current with N timeshigher frequency that occurs due to interleaved switching,the capacitance, and consequently the volume of Cf , canbe reduced compared to paralleling of switching devices.For equal maximum voltage ripple on uout, the ratiobetween the filter capacitance required for N parallelmodules with interleaved switching CfN and a singlemodule CfS becomes

CfN

CfS

=1

N2. (13)

The current ripple through Cf is reduced significantlycompared to a single module, leading to a significant totalvolume decrease of the passive components compared toa single module with parallel switching devices. This isat the cost of (N−1) more circuits to sense the individualfilter inductor currents.

V. INTERLEAVED SWITCHING

In [3] a master-slave interleaving scheme is presentedbased on correcting ramps that are added to the turn-offcurrent levels. The approach is improved in [4] to operatein a ring configuration. Ramps can be used to steer thetime shift between the filter inductor current ripples (iLf )of the individual modules. Figure 5 depicts the currentwaveform iLf for a single module, together with thedesired current waveform and the correcting ramps rpand rn. The correcting ramps are added to both turn-offlevels, ihi and ilo, to improve the dynamic response [4].To steer the actual current waveform to the desired currentwaveform, the control ramps are positioned such that theyintersect ihi and ilo at the time of desired turn-off of thecorresponding switch [3]. This results in a time shift and,as a consequence, convergence of the actual iLf to thedesired waveform.

The interleaving scheme, using correcting ramps, canbe analyzed from the time-shift between the actual anddesired waveform before ΔTsh[k] and after ΔTsh[k+1]each switching cycle (see Appendix). The time-shift isgiven by

ΔTsh[k+1] =

�diLfS1dt − drn

dt

��diLfS2dt − drp

dt

��diLfS1dt − drp

dt

��diLfS2dt − drn

dt

�ΔTsh[k] ,

(14)

t[s]

i Lf[A

]

⇐ rp(t)

⇐ rn(t)

iLfS1(t) ⇒

iLfS2 (t) ⇒

ΔTsh [k] ΔTsh [k + 1]

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9

ilo

0

ihi

Desired waveform Actual waveform Control ramps

Fig. 5. Adjusting phase shift using control ramps.

where diLfS1/dt is the slope of iLf when S1 is conducting,diLfS2/dt the slope of iLf when S2 is conducting, anddrp/dt and drn/dt are the slopes of the ramps thatare added to ihi and ilo. Equation (14) results in stableconvergence to the desired waveform if

������

�diLfS1dt − drn

dt

��diLfS2dt − drp

dt

��diLfS1dt − drp

dt

��diLfS2dt − drn

dt

�������< 1, (15)

and in dead-beat control if the numerator of the polyno-mial equals 0. If the denominator becomes zero, switchingis halted. This cannot occur if (15) is satisfied.

By substituting drp/dt with κ diLfS2/dt and drn/dtwith κ diLfS1/dt the speed of convergence can be set bychoosing κ between 0 and 1, resulting in

ΔTsh[k+1] =

�diLfS1dt −κ

diLfS1dt

��diLfS2dt −κ

diLfS2dt

��diLfS1dt −κ

diLfS2dt

��diLfS2dt −κ

diLfS1dt

�ΔTsh[k] .

(16)The slope of the ramps can be calculated from themeasurement of uout for a given UDC and Lf , leading to asimple adaptive interleaving control scheme compared tothe scheme proposed in [3], where the slope of the rampsis fixed.

The time-shift between the inductor currents of Nindividual parallel modules can be controlled by addingramps to the turn-off levels of the N−1 slave modules. Thesteady-state time shifts Tsh between the inductor currentsand consequently the positive and negative ramps can bedetermined from the steady-state switching time of themaster module (Tsw = Tsw[k] = Tsw[k−1]) as

Tshx=

TswN

x, (17)

where x is the number of the corresponding slave module[1, 2, .., N−1].

The time shifts in (17) are used for the positioning ofthe correcting ramps rpx

and rnx, which are added to

ihi and ilo of the slave modules. This can be seen fromFig. 6, where Tsh1 = t7−t6, Tsh2 = t8−t6, Tsw = t9−t6,N = 3, and i�hi is the positive turn-off level after a stepon iset is applied. In [3] the time-shifts of the positiveramps rpx

are determined from the previous switchingperiod of the high-side switch of the master module

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i Lf

[A]

Master

ilo0

ihi

i�hii L

f[A

]

Slave 1

ilo0

ihi

i�hi

i Lf

[A]

Slave 2

ilo0

ihi

i�hi

t [s]

i Cf

[A]

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

0

Δiset

proposed

original

Fig. 6. Simulated step response with Δiset = 5 A and κ = 0.5.

i Lf

[A]

Master

ilo0

ihi

i�hi

i Lf

[A]

Slave 1

ilo0

ihi

i�hi

i Lf

[A]

Slave 2

ilo0

ihi

i�hi

t [s]

i Cf

[A]

t0 t1 t2 t3 t4 t5 t6

0

Δiset

proposed

original

Fig. 7. Simulated step response with 5% variation of Lf .

TswS1 [k−1], eg. (t2−t0) for the ramps rpxpositioned in

the interval (t2..t4), when using this method with positiveand negative ramps. The time shifts of rnx

would bedetermined from the previous switching period of thelow-side switch (TswS2 [k−1]), eg. (t3−t1) for the rampsrnx

positioned in the interval (t3..t5). However, fasterdynamic response can be obtained by using the newestavailable switching time of both the high-side and thelow-side switch of the master module to position bothrnx

and rpx. This can be seen from the bottom graph of

Fig. 6 (iCf ), where both the original (based on [3]) andthe proposed methods are applied for Δiset = 5 A andκ = 0.5. For clarity, the individual inductor currents areonly plotted for the proposed method.

Component variation of Lf results in different steady-state switching times of the individual parallel modules.As a consequence sub-optimal time shifts and smallsteady-state current differences between the individualparallel modules will occur. Also a ripple componentwith frequency equal to 1/Tsw will appear. Componentvariation between the filter inductors of the individualmodules should be kept low. The disturbance can be seenin Fig. 7 where the simulated step response is depictedunder the same conditions as in Fig. 6 but with 5%variation of the individual filter inductors (Lf ). Simula-tions were conducted with the parameters and componentvalues shown in Table II.

VI. INTERLEAVED SWITCHING UNDER VOLTAGE

CLAMPING CONDITIONS

During voltage clamping operation of parallel mod-ules (uout = ±UDC in Fig. 1), (16) is not valid andthe interleaving approach using correcting ramps is noteffective. The ramps, used for interleaving during normaloperation, have to be disabled during voltage clampingoperation. Under voltage clamping conditions, no voltageis left across Lf to change the current. Because thefilter capacitor Cf is shared, this occurs for all parallelconnected modules simultaneously, and synchronization,not interleaving, of iLf will occur if one of the additionalturn-off criteria is satisfied. To prevent this the additionalcriteria are extended to the following,

1) If diLf/dt ≤ 0 and S1 is conducting, then only turnoff S1 of the module carrying maximum iLf .

2) If diLf/dt ≥ 0 and S2 is conducting, then only turnoff S2 of the module carrying minimum iLf .

To analyze the behavior during voltage clamping, thestate-plane of Fig. 3(b) was extended to multiple parallelmodules. Figure 9 depicts the time waveform and thecorresponding state-plane of the filter inductor currentfor N =3 parallel modules, when applying the extendedadditional turn-off criteria, and for voltage clamping tothe positive supply rail. During time intervals (t4..t5),(t6..t7), and (t8..t9), S1 of all modules is closed untildiLf/dt ≤ 0 occurs. This can be modeled as in Fig.8(a), when assuming iout constant over one switchingcycle. For this condition the state-plane for the sum ofthe filter inductor currents (

�iLf ) can be defined using

impedance Zf , depicted in the right graph of Fig. 9(b).The resonance that occurs during conduction of S1 of allparallel modules describes a half circle with radius R�,centered round (UDC, Zf iout) in the state-plane. This canbe translated to a state-plane representation for individualfilter inductor currents using impedance ZN = N Zf ,which is depicted in the left graph of Fig. 9(b). At timest5, t7, and t9, turn-off occurs of S1 of the module carryingmaximum iLf due to diLf/dt ≤ 0. As a consequencecommutation of the corresponding switching node voltageusn occurs, after which S2 is turned on. The filter inductorcurrent iLf of the commutating module decreases until ilois hit in intervals (t3..t4), (t5..t6), (t7..t8), and (t9..t10).This can be modeled as in Fig. 8(b). During the currentcommutation uout remains approximately constant due tothe relatively short time of the resonance that is completedduring commutation. The current in the filter inductorsthat are not commutating will therefore be approximatelyconstant during current commutation. This can be seenfrom the left graph of Fig. 9(b). After current commuta-tion, S2 is turned off again and transition of usn occurs.The cycle repeats until clamping of uout stops. From Fig.9 it can be seen that self-interleaving occurs when usingthe suggested additional turn-off criteria.

For clamping of uout to the positive supply UDC, whenassuming iLf constant for the modules that are not com-mutating, the filter inductor currents of the N−1 modules

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that are not commutating at t4, t6, t8, and t10 can bedetermined from ilo together with the current increase ineach cycle, which equals 2R�/ZN = 2/N |� iLf − iout|.A discrete-time description for the transient behavior ofthe inductor currents is given by

iLf [tk+2] = GiLf [tk] + Hu [tk] (18)

where iLf is a vector containing the N−1 inductor currentsof the modules that are not commutating, sorted from highto low, and u is a vector containing the output current ioutand the negative turn-off level ilo, that is,

iLf [tk] =

⎡⎢⎣

iLf1...

iLfN−1

⎤⎥⎦ , u [tk] =

�ioutilo

�.

G is of size (N−1)×(N−1) and H of size (N−1)×2and are found to be

G =�

0 I0 0

�− 2

NJ, H =

2N

⎡⎢⎣

1 −1...

...1 −1 + N

2

⎤⎥⎦ ,

where I is an identity matrix of size (N−2) × (N−2)and J a unit matrix of size (N−1) × (N−1). A con-sequence of (18) is that an addition of 2R�/ZN to thecorresponding N−2 inductor currents occurs, where thelowest current is defined by ilo+2R�/ZN. Stability of theself-interleaving mechanism can now be determined byexamining the eigenvalues of G. The approach results instable interleaved switching if all eigenvalues are withinthe unit circle. Interleaved switching occurs only when Nis odd, for an even number of parallel modules, G hasone eigenvalue on the unit circle at −1, see Fig. 11. Noconvergence to interleaved switching for N is even occurswhen using diLf/dt = 0 as additional turn-off criterion,shown in Fig. 10. The eigenvalues will be closer to theunit circle for increasing N , resulting in decrease of speedof convergence for an increasing, odd, number of parallelmodules (see Fig. 11).

For parallel connected modules also other measures arerequired to ensure that commutation of usn is possible. Toguarantee ZVS during, and just before, voltage clampingto the positive supply, ilo has to be adjusted to ilo =2iout/N − ith if iout < iset < 0 and

0 ≥ (uout − UDC)2 + Z2

f

��iLf − iout

�2

− 14N2Z2

f

�ith − max (iLf)

�2, (19)

where max (iLf) represents the highest of the N filterinductor currents. To reduce computational load or toallow implementation in an analog circuit, (19) can besimplified to a conservative bound as

0 ≥ (uout − UDC) − 12NZf

�ith − max (iLf)

�. (20)

The above derived equations are valid for clampingof uout to the positive supply rail. Similar equationscan be derived for clamping to the negative supply rail.

N·Lf

N·Lf

N·LfCfUDC

iout

(a) S1 of all modules conducting

N·Lf

N·Lf

N·LfCfUDC UDC

iout

(b) S2 of one module conducting

Fig. 8. Equivalent schematics for voltage clamping to UDC.

i Lf

[A]

Master

i�lo

ilo0

ihi

i Lf

[A]

Slave 1

i�lo

ilo0

ihi

i Lf

[A]

Slave 2

i�lo

ilo0

ihi

i[A

]

iout0

iset

iCf

iset

iout

t [s]uout

[V]

t0 t1 t2 t3t4 t5t6 t7t8t9 t10 t11−UDC

0

UDC

(a) Time waveforms

uout [V]

Zn

i[V

]

t3

t9

t4

t5

t7

t6

t2

t8

UDC

Zn i�lo

Zniout/N

0

Zn ihi Zn · iLf , t > t3Zn · iLfZn · iout/N

uout [V]

Zf

�i L

f[V

]

UDC

Zf iout

0R�

(b) State-plane

Fig. 9. Interleaved switching during voltage clamping, N =3.

Also a different diLf/dt can be chosen as an additionalturn-off criterion. When choosing diLf/dt � 0 forclamping to the positive supply rail UDC and diLf/dt�0for clamping to the negative rail −UDC, this results insteady-state interleaved switching for any number ofparallel connected modules. This is not treated in thispaper and will be discussed elsewhere.

VII. EXPERIMENTAL RESULTS

The proposed interleaving method was implemented inthe FPGA of a digitally controlled 2.8 kW RPI prototype,based on an existing 12 kW 3 phase hysteresis currentcontrolled ZVS inverter. The related parameters, supplyvoltage and component values are presented in Table II.

The threshold current ith was chosen at 5 A to limit themaximum switching frequency to approximately 30 kHz,although 1.2 A is sufficient to guarantee commutation ofusn over the full output voltage range of the converter.Fig 12 shows the measured step response of the proposed

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i Lf

[A]

Master

i�lo

ilo0

ihi

i Lf

[A]

Slave 1

i�lo

ilo0

ihi

i Lf

[A]

Slave 2

i�lo

ilo0

ihi

i Lf

[A]

Slave 3

i�loilo0

ihi

i[A

]

iout0

iset

iCf

iset

iout

t [s]

uout

[V]

t0 t1 t2 t3t4 t5t6t7t8 t9t10 t11 t12−UDC

0

UDC

(a) Time waveforms

uout [V]

Zn

i[V

]

t2

t3

t4t5

t6t7

t8t9

t10

t11

UDC

Zn i�lo

Zniout/N

0

Zn ihiZn · iLf , t > t2Zn · iLfZn · iout/N

uout [V]

Zf

�i L

f[V

]

UDC

Zf iout

0

(b) State-plane

Fig. 10. Interleaved switching during voltage clamping, N =4.

real

imag

inar

y

−1 −0.5 0 0.5 1−1

−0.5

0

0.5

1N=2N=3N=4N=5N=6

Fig. 11. Eigenvalues of G, for N = {2, 3, 4, 5, 6}.

interleaving method, which is in good agreement withthe simulation results presented in Fig. 7, and confirmsthe fast dynamic response of the approach.

Measurements with sinusoidal excitation were madeto verify the achieved ripple cancellation, the results aredepicted in Fig. 13. A ripple current amplitude of 2.5A is achieved for iset = 5 + 5 sin (2π50t) A. This isin good agreement with the factor N reduction of theripple current that can be expected from odd interleavedtriangular current waveforms.

TABLE IICOMPONENT VALUES PROTOTYPE AND SIMULATION

item ValueUDC 70 Vith 5 AN 3Cr 9 nFLf 120 μHCf 100 μFLl 4.5 mHRl 1.4 Ω

i Lf

[A]

Master

−50

8.311.7

i Lf

[A]

Slave 1

−50

8.311.7

i Lf

[A]

Slave 2

−50

8.311.7

t [s]i C

f[A

]

−5 0 5 10 15

0

5

·10−5

Fig. 12. Measured step response, 5 A step.

Figure 14 shows the step response with voltage clamp-ing, demonstrating fast convergence to interleaved switch-ing when moving back and forth between voltage clamp-ing and normal operation.

VIII. CONCLUSION

An all-digital interleaving method is suggested in thispaper, aiming to improve the system dynamic response.The effectiveness of the method is analytically demon-strated. Simulations done on models with componentvariation confirm the effectiveness of the approach. Thesuggested interleaving method shows significant improve-ments on ripple current cancellation, dynamic response,and total volume of the passive components, compared toa single module. A self-interleaving mechanism for oddnumber of modules is proposed and is demonstrated ana-lytically and with simulations. This results in a maximumon time of the high side switches during voltage clampingoperation, enabling the use of low-cost bootstrap circuitsfor ZVS hysteresis current controlled converters. A 3 kW

i Lf

[A]

Master

−505

1015

i Lf

[A]

Slave 1

−505

1015

i Lf

[A]

Slave 2

−505

1015

t [s]

i Cf

[A]

−0.025 −0.02 −0.015 −0.01 −0.005 0 0.005 0.01 0.015 0.02 0.025−10−5

05

10

Fig. 13. Measured sinusoidal excitation, iset = 5 + 5 sin (2π50t) A.

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i Lf

[A]

Master

−100

1020

i Lf

[A]

Slave 1

−100

1020

i Lf

[A]

Slave 2

−100

1020

i[A

]

015

iCf

iset

iout

t [s]

uout

[V]

−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5−70

0

70

·10−3

Fig. 14. Measured step response with voltage clamping.

prototype consisting of 3 parallel modules was built, withthe suggested interleaving method implemented by meansof an FPGA. Measurements verify the simulation resultsand demonstrate the effectiveness of both approaches.

APPENDIX

Figure 15(a) depicts the positive correcting ramp withthe corresponding current waveforms. ΔT

�sh[k] represents

the time difference between the actual and desired induc-tor current after turn-off of S1. The time shift of iLf thatoccurs due to rp can be expressed as follows,

ΔT�sh[k] = ΔTsh[k] − ΔT

��sh[k], (21)

where

ΔT��sh[k] = δip

diLfS2dt − diLfS1

dtdiLfS1dt · diLfS2

dt

, (22)

and

δip = −drpdt

diLfS1dt

diLfS1dt − drp

dt

ΔTsh[k] . (23)

Combining (21) to (23) results in

ΔT�sh[k] =

diLfS1dt

diLfS2dt

�diLfS2dt − drp

dt

��diLfS1dt − drp

dt

�ΔTsh[k]. (24)

Figure 15(b) depicts the negative correcting ramp withthe corresponding current waveforms. ΔTsh[k+1] repre-sents the time difference between the actual and desiredinductor current after turn-off of S2. The time shift of iLfthat occurs due to rn can be expressed as follows,

ΔTsh[k+1] = ΔT�sh[k] − ΔT

���sh [k], (25)

where

ΔT���sh [k] = δin

diLfS1dt − diLfS2

dtdiLfS1dt · diLfS2

dt

, (26)

and

δip = −drndt

diLfS2dt

drndt − diLfS2

dt

ΔTsh[k] . (27)

Desired waveform Actual waveform Control ramps

t[s]

i Lf[A

]

⇐ rp(t)iLfS1 (t) ⇒⇐ iLfS2 (t)

δip

ΔTsh [k]

ΔT�sh [k]

ΔT��sh [k]

t�1 t2 t�2 t3

ihi

(a) Positive ramps

t[s]

i Lf[A

]

⇐ iLfS1 (t)iLfS2 (t) ⇒

δin

ΔTsh [k + 1]

ΔT�sh [k]

ΔT���sh [k]

t�3 t4 t�4 t5

ilo

(b) Negative ramps

Fig. 15. Control ramps with actual and desired current waveforms.

Combining (25) to (27) results in

ΔTsh[k+1] =diLfS2dt

diLfS1dt

�diLfS1dt − drn

dt

��diLfS2dt − drn

dt

�ΔT�sh[k]. (28)

Equation (24) and (28) can be combined to

ΔTsh[k+1] =

�diLfS1dt − drn

dt

��diLfS2dt − drp

dt

��diLfS1dt − drp

dt

��diLfS2dt − drn

dt

�ΔTsh[k] ,

(29)which is the result of (14).

ACKNOWLEDGMENT

The authors would like to thank Jan Coenders forthe valuable discussions on non-interleaved zero-voltage-switching hysteresis current controlled inverters and sus-tained zero-voltage switching under all load conditions.Special thanks go to Han Severt for his help writing anddebugging the amplifier’s firmware.

REFERENCES

[1] Y.-C. Hsieh, T.-C. Hsueh, and H.-C. Yen, “An interleaved boostconverter with zero-voltage transition,” Power Electronics, IEEETransactions on, vol. 24, no. 4, pp. 973 –978, april 2009.

[2] D. Divan and G. Skibinski, “Zero-switching-loss inverters for high-power applications,” Industry Applications, IEEE Transactions on,vol. 25, no. 4, pp. 634 –643, jul/aug 1989.

[3] J. Batchvarov, J. Duarte, and M. Hendrix, “Interleaved convertersbased on hysteresis current control,” in Power Electronics Special-ists Conference, 2000. PESC ’00., 2000 IEEE 31st Annual, jun2000, pp. 655 –661 vol.2.

[4] M. Hendrix, R. van der Wal, J. Leijssen, and J. van Erp, “Switchedmode power supply,” Patent WO 2005/006 526 A1, january, 2005.

[5] R. De Doncker and J. Lyons, “The auxiliary resonant commutatedpole converter,” in Industry Applications Society Annual Meeting,1990., Conference Record of the 1990 IEEE, oct 1990, pp. 1228–1235 vol.2.

[6] J. Cho, D. Hu, and G. Cho, “Three phase sine wave voltagesource inverter using the soft switched resonant poles,” in IndustrialElectronics Society, 1989. IECON ’89., 15th Annual Conference ofIEEE, nov 1989, pp. 48 –53 vol.1.

[7] D. Perreault, J. Kassakian, and H. Martin, “A soft-switched parallelinverter architecture with minimal output magnetics,” in PowerElectronics Specialists Conference, PESC ’94 Record., 25th AnnualIEEE, jun 1994, pp. 970 –977 vol.2.

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