Interfacing Micron OmneoTM

P5Q PCM memory to Xilinx Spartan-6 FPGA SP601 Evaluation Kit

Avnet Japan Co., LtdProduct Sales and Technology Div.Technical Marketing Dept.Sept. 11th, 2010

MotivationCreate demo platform to demonstrate the benefit of Micron OmneoTM

P5Q PCM memory against conventional Flash technology.2 Major benefit to focus on

Bit-alterable: no separate erase stepShorten re-writing time

Endurance: 10x of Conventional NOR FlashGood for the application which require multiple of rewriting

Target Consideration…

FPGA Configuration ROMTypically, FPGA is configured via PROMSeveral configuration schemes are supported, some FPGA family is supporting SPI interface.Small foot print is desirable since it is only used during device power up.Faster rewriting time is desirable during development stage; multiple of configuration data is uploaded for design test purpose.Longer device endurance is preferred also.

Demo Image…

.mcsfile

.mcsfile

1. Prepare FPGA configuration file

2. Upload configuration datavia USB to Nike Board

3. Configuration Data is transferred to SP601 eval. Kit via SPI interface.Data will be stored in PCM memory

4. FPGA is configured via PCM memory, and audience can realize the speed of configuration time.

SP601 J12 SPI external Connector and P5Q PCM Memory Daughter Card (Prototype)

P5Q PCM Memory Daughter Card (Prototype)

SP601 J12 external SPI interface

P5Q PCM Memory Daughter Card Schematic

P5Q is Connected to SP601 Eval Kit

PCM Configure Spartan-6 FPGA!!!

Youtube Video: http://www.youtube.com/watch?v=6Ufq3oeYmQc

Reference

ReferenceMicron OmneoTM P5Q PCM

http://numonyx.com/Documents/Datasheets/210052_P5Q_DS.pdf

Winbond 64M-bit Serial Flash Memory with uniform 4KB sectors and Dual/Quad SPIhttp://www.winbond.com.tw/NR/rdonlyres/A88DEF07-8303-4617-BAE6- B8A365057DC8/0/W25Q64CV.pdf

UG518: SP601 Hardware User Guidehttp://japan.xilinx.com/support/documentation/boards_and_kits/ug518.pdf

UG380: Spartan-6 FPGA Configuration User Guidehttp://www.xilinx.com/support/documentation/user_guides/ug380.pdf

SP601 Xilinx Spartan-6 Evaluation Kit Schematicshttp://japan.xilinx.com/support/documentation/boards_and_kits/xtp051_sp601_schematics.pdf

Getting Started with the Xilinx Spartan-6 FPGA SP601 Evaluation Kithttp://japan.xilinx.com/support/documentation/boards_and_kits/ug523.pdf

SP601 Xilinx Spartan-6 Evaluation Kit Documentation page (Xilinx Web Link) http://japan.xilinx.com/products/boards/sp601/reference_designs.htm

Target Example: Xilinx Spartan-6 FPGA SP601 Evaluation Kit

The evaluation Kit include Winbond W25Q64CV SPI Flash as configuration memoryIt also include external SPI interfaceSP601 is utilized for Spartan-6, latest FPGA family of Xilinx targetting low-cost, Mid-to-High Volume Market.Utilize J12 Connector for SPI base external FPGA configuration

SP601 Evaluation Kit: SPI interface Close Lookup

UG518.pdf: SPI Header Description

UG380.pdf: SPI Configuration Interface1. The connection shown in Figure 2-13

uses the Winbond W25Q SPI series flash PROM. To enable the Quad output operation, the user must set the QE bit of the PROM’s status_reg[9] to 1 before the device can transmit in quad output mode, which is done at programming time in iMPACT software.

2. CCLK can be provided by the FPGA or an external clock source.

3. There are default pull-ups on the PROGRAM_B, INIT_B, and M0 pin.

4. Software support for x4 requires the x4 capability enabled in BitGen

5. The SPI device needs to be programmed with a specific register setting, which can bedone in iMPACT software, to enable x4 output.

For Winbond’s W25Q64CV, status register bit, status_reg[9], need to be enabled for QOFR operation. By default, P5Q supports QOFR!

UG380.pdf: Read Data Byte Command

UG380.pdf: Master SPI Vendor Auto- Detection and Error Handling

The SPI read command is automatically selected, using a read-command looping mechanism for the initial device configuration. This looping algorithm is outlined in Figure 2-14. SPI x2 and x4 applications use this sequence for an initial data load. After the first set of commands are issued to the FPGA, the read command changes in the Mode_Reg and configuration changes to x2 or x4 mode using the IPROG command. To enable these modes, the BitGen spi_buswidth option needs to have the SPI x2 or x4 command set.MultiBoot applications require a manual setting of the read command to be used along with other MultiBoot settings contained in the Mode_Reg, General 2, and General 4 registers.

UG380.pdf: Quad Read Bit Command

UG380.pdf: Power-On Sequence Precautions

P5Q vs. W25Q64CV Instruction Set Comparison: W25Q64CV Instruction Set

: Common instruction : P5Q Only : W25Q64CV Only

P5Q vs. W25Q64CV Instruction Set Comparison: W25Q64CV Instruction Set (Cont.)

: Common instruction : P5Q Only : W25Q64CV Only

P5Q vs. W25Q64CV Instruction Set Comparison: P5Q Instruction Set

: Common instruction : P5Q Only : W25Q64CV Only

UG380.pdf: Configuration Register List

UG380.pdf: Configuration Register: MODE_REG format

UG380.pdf: Configuration Packets

To set SPI memory in QFOR, MODE_REG(6’h18) need to be set with Type 1 Configuration packet.

Type1: 001 10 01100 00001 = 0x3301, Data: 000 10 001 0000 0000 = 0x1100

[15:13]Type1 Header

[12:11]Write Op

[10:5]MODE_REG Addr: 6’h18

[4:0]Word Cnt: 1 word

[12:11]: SPI bus width setting00: x1, 01: x2, 10: x4

Bitgen dump file

QFOR is enabled(Quad SPI read)

Design file with QFOR off. Design file with QFOR on.

QFOR is disabled.(Normal SPI read)

Technical Consideration

FPGA of SP601 Evaluation Kit can be configured via external SPI interface.SP601 Evaluation Kit configures its FPGA with Quad Output Fast Read (QOFR) instruction.Micron OmneoTM P5Q PCM memory supports QOFR instruction.As long as P5Q data format is readable from FPGA, P5Q should be able to utilized for FPGA configuration purpose

Backup

Xilinx Spartan-6 FPGA SP601 Evaluation Kit

P5Q Daughter Card

Demo: Real-time Image Filtering via Ethernet Port