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Mike Mayberry, Senior VPIntel CTO & GM Technology Development
Copyright © 2019 Intel Corporation
inter
FUTURE COMPU[ING MODELS . . • '. ~ ' : 0 . ,;,~ "':',, ··>
TECHNOLOGY IN THE 2030-2040 HORIZON ,
2
Legal Notices
This presentation contains information provided by Intel Corporation (“Intel”), and may refer to Intel’s plans and expectations for the future, which are provided for discussion purposes only and are subject to change without notice. Forward-looking statements involve a number of risks and uncertainties: Refer to Intel’s SEC filings for authoritative discussion of Intel’s results and plans.
This presentation imposes no obligation upon Intel to make any purchase, and Intel accepts no duty to update this presentation based on more current information. Intel is not liable for any damages, direct or indirect, consequential or otherwise, that may arise, directly or indirectly, from the use or misuse of the information in this presentation.
Copyright © 2019 Intel Corporation.Intel and the Intel logo, are trademarks of Intel Corporation in the U.S. and/or other countries. Other names and brands may be claimed as the property of others.
… motivates new optimizationsData at the edge, more unstructured
Distributed compute, more M2M
Unintended programming inefficiencies
The Shifting Nature of Data…
160 ZB2 ZB
Broadcast Media
OTT/Streaming
Broadcasting
Digital TV
PB
M2M
Productivity data
Relational databases,
BI suites
Web data
Social
Search
Mobility
~60%
~45%
~20%
CAGR(17-25)
~20%
~15%
Digita
l Dat
a Gen
erat
ed
15 ZB
Structured UnstructuredBest processed near source
Source: Analyst and Intel Data , Oct 2018
3
PRODUCTIVITY DA TA
C++ Java JS
Deep learning▪ Known answers▪ Generate procedures
with training
Conventional▪ Known
procedures▪ Generate answers
Neuromorphic▪ Many procedures▪ Adapt the answer
with reinforcement
Quantum▪ Answers
superimposed▪ Select and measure
the answer
Graph Analytics▪ Graph edges and
vertices represent relationships
▪ Big, sparse data structures
Compute Architecture progression
4
Co-evolution of Software & Hardware Solutions
2015-2025
2020-2030
2025-2035
sw defined hw AI generated sw
IA++/XPU ISA
DSL + Runtime
(execution model)
Application
SW defined flow
XPUCPU
Domain Accelerator Processing Unit
Central Processing Unit
Domain Specific Arch.
SDH Augments GP Processors
5
AI Driven SW Development
App
Domain Specific Language
Domain Specific Architecture
H/W Product
Design
Intelligent Assist
Code Generation
Manage
Test
Maintain
• Identify patterns• Discover dependencies• Suggest reuse
• Automate code gen• Proactive command gen• Improve productivity
• Automate deployment• Decrease defects• Optimize traffic routing
• Analyze code• Automate test generation• ID bugs/focus testing• Predict outcomes
Program Development
Cycle
i=i== □□ ooo §:§:§:oo:S:S:S §§§00888
Graph Analytics
opportunitiesStatus ChallengesMultiple query languages and processing engines
DARPA Graph Challenge
Real-time decision making
Fraud detection
Social network analysis
Anomaly detection
Sparse and irregular memory accesses
Small data accesses with frequent synchronization
Scaling to very large datasets
6
neuromorphic computing
opportunitiesStatus ChallengesComplex neural network
topologies
~1 billion neurons demonstrated
Constraint Satisfaction
Real-time Learning
Adaptive Control
Complex Systems Modeling
Neuroscience model development
Algorithm development
S/W & Simulation tools
7
Quantum computing
opportunitiesStatus Challenges~100 organizations investing
8 qubit types
~100ms coherence time for SC
Hybrid classic-quantum algo’s in dev’t
Molecular structure
Materials science
Pharmacology
Cryptography
Decoherence & error-correction
Low-latency qubit control
Qubit scale-up
Algorithms/Compilers
Workloads for testing
8
power/thermals drives beyond cmosP
ow
er
De
nsi
ty
R. Schmidt et. al., IBM J R&D (2002)
2030 2050
?Beyond CMOS
9
14
12
10
8
6 Junction Transistor
Integrated Circuit
Bipolar
• • . . . • . . . . . . . . . . • . . . .
CMOS • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
4
2 Vocuum ~
.4,!;_....:,:'u,iib@.,-,~ ---l.--....;;• ;...--=!!!!=::::._ ______ ....,:•_,:•~--.J f - - - - - - -+
Beyond CMOS
10
Source: C. Pan; A. Naeemi. “An Expanded Benchmarking of Beyond-CMOS Devices Based on Boolean and Neuromorphic Representative Circuits” IEEE Jan 2018 10.1109/JXCDC.2018.2793536
Desired state
Improved switching efficiency
Enabled by academic-industry-government
Novel devices improving Example: meso
Better understanding of logic circuits
Magneto-Electric Spin-Orbit
100mV operation
10X-30X better power/perf than CMOS
MESO
10'
CMOS
10 5 • TFET1
0 FefTOIIIKlric
• .,._ 0 --· 10
4
-, ,S 10 3
f w
10 2
10 1
G - 0 Gpn.1-Vo3 Vol
• • CMOS HP MITTET
• 't>FEFET CoMET
r MEMTJ
Ho<JTFET • NCFET • ITFET e_; MEMT-"
'"-'TFET f GeHTFET • YlfNFeT-8P SWO
• TMOTFET ~ (:) MT ........
* CMOSLV
BioFET
Summary
New architectures and new technologies needed to manage massive workloads
The new data era will shift compute toward data and S/W-centric H/W
Power & Thermal drive the need to move beyond CMOS
11
"Any opinions, findings, conclusions or recommendations
expressed in this material are those of the author(s) and do not
necessarily reflect the views of the Networking and Information
Technology Research and Development Program."
The Networking and Information Technology Research and Development
(NITRD) Program
Mailing Address: NCO/NITRD, 2415 Eisenhower Avenue, Alexandria, VA 22314
Physical Address: 490 L'Enfant Plaza SW, Suite 8001, Washington, DC 20024, USA Tel: 202-459-9674,
Fax: 202-459-9673, Email: [email protected], Website: https://www.nitrd.gov