Document Number: 316972-004

Intel I/O Controller Hub 9 (ICH9) FamilyDatasheet

For the Intel 82801IB ICH9, 82801IR ICH9R, 82801IH ICH9DH, 82801IO ICH9DO, 82801IBM ICH9M and 82801IEM ICH9M-E,and ICH9M-SFF ICH9-I/O Controller Hubs

August 2008

2 Intel I/O Controller Hub 9 (ICH9) Family Datasheet

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Intel I/O Controller Hub 9 (ICH9) Family Datasheet 3

Contents

1 Introduction ............................................................................................................ 431.1 About This Document......................................................................................... 431.2 Overview ......................................................................................................... 47

1.2.1 Capability Overview................................................................................ 491.3 Intel ICH9 Family High-Level Component Differences ........................................... 54

2 Signal Description ................................................................................................... 552.1 Direct Media Interface (DMI) to Host Controller ..................................................... 582.2 PCI Express* .................................................................................................... 592.3 LAN Connect Interface ....................................................................................... 592.4 Gigabit LAN Connect Interface ............................................................................ 602.5 Firmware Hub Interface...................................................................................... 612.6 PCI Interface .................................................................................................... 622.7 Serial ATA Interface........................................................................................... 642.8 LPC Interface.................................................................................................... 672.9 Interrupt Interface ............................................................................................ 682.10 USB Interface ................................................................................................... 692.11 Power Management Interface.............................................................................. 712.12 Processor Interface............................................................................................ 742.13 SMBus Interface................................................................................................ 752.14 System Management Interface............................................................................ 762.15 Real Time Clock Interface................................................................................... 782.16 Other Clocks..................................................................................................... 782.17 Miscellaneous Signals ........................................................................................ 782.18 Intel High Definition Audio Link ......................................................................... 802.19 Serial Peripheral Interface (SPI) .......................................................................... 812.20 Controller Link .................................................................................................. 822.21 Intel Quiet System Technology (Desktop Only) ................................................... 832.22 General Purpose I/O Signals ............................................................................... 832.23 Power and Ground Signals .................................................................................. 862.24 Pin Straps ........................................................................................................ 88

2.24.1 Functional Straps ................................................................................... 882.24.2 External RTC Circuitry............................................................................. 90

3 Intel ICH9 Pin States............................................................................................. 913.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 913.2 Output and I/O Signals Planes and States............................................................. 923.3 Power Planes for Input Signals .......................................................................... 101

4 Intel ICH9 and System Clock Domains................................................................. 107

5 Functional Description ........................................................................................... 1095.1 DMI-to-PCI Bridge (D30:F0) ............................................................................. 109

5.1.1 PCI Bus Interface ................................................................................. 1095.1.2 PCI Bridge As an Initiator ...................................................................... 109

5.1.2.1 Memory Reads and Writes........................................................ 1105.1.2.2 I/O Reads and Writes .............................................................. 1105.1.2.3 Configuration Reads and Writes ................................................ 1105.1.2.4 Locked Cycles ........................................................................ 1105.1.2.5 Target / Master Aborts............................................................. 1105.1.2.6 Secondary Master Latency Timer............................................... 1105.1.2.7 Dual Address Cycle (DAC) ........................................................ 1105.1.2.8 Memory and I/O Decode to PCI................................................. 111

4 Intel I/O Controller Hub 9 (ICH9) Family Datasheet

5.1.3 Parity Error Detection and Generation......................................................1115.1.4 PCIRST# .............................................................................................1125.1.5 Peer Cycles ..........................................................................................1125.1.6 PCI-to-PCI Bridge Model ........................................................................1125.1.7 IDSEL to Device Number Mapping ...........................................................1135.1.8 Standard PCI Bus Configuration Mechanism..............................................113

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) ................................................1135.2.1 Interru