In December 19731ntel shipped the first 8bit, N-channel microprocessor,the 8080. Since then it has become the most widely usea microprocessor inthe industry. Applications of the 8080 span from large, intelligent systemsterminals to decompression computers for deep sea divers.

This BOBO Microcomputer Systems User's Manual presents all of the8080 system components. Over twenty-five devices are described in detail.These new devices further enhance the 8080 system:

8080A - 8-Bit Central Processor UnitFunetlonally and Electrically Compatible with the 8080.TTL Drive Capability.Enhanced Timing.

8224 - Clock Generator for B080A.Single 16 Pin (DIP) Package.AlJKiliary Timing FlJnction~Power-On Re!iet.

BnB - System Controller for 8080A.Single 28 Pin (DIP) P~ckage.Single lnterrlJpt Vector (RST 71.MultiBvte InterrlJpt Instruction Capability le.g. CALLI.Direct Dat~ and Control BlJS Connect to all BOBO SY5tem I/O

~nd Memory Components.

B251 - Programmable Communication Interface.ASYNC or SYNC (including IBM ij-SYNCI.Single 2B Pin PacKage.Single +5 Volt Power Supply.

8255 - Programmable Peripheral Interface.ThrEtll 8--Bit Poru.Bit Set/Reset Capabiiity.Interrupt Generation.Single 40 Pin Package.Single +5 Volt Power Supply.

In addition, new memory components include: 870B, 8K Erasable PROM;8316A, High Density Mask ROM; and 5101, Low Power CMOS RAM.

inter Microcomputers. First from the beginning.

CONTENTS

INTRODUCTIONGeneral .AdYantagl!S of Designing with MicrocomputerSMicrocomputer Design Aids .Application Example .Application Table. . . . . . . . .

CHAPTER 1 -THE FUNCTIONS OF A COMPUTER

A Typical Computer System .The Architecture of a CPU .Computer Operations. . .

CHAPTER 2-THE 8080 CENTRAL PROCESSING UNIT

General _ ..Architecture of the 8080 CPUThe Processor Cycle.Intern.Jpt Sequences.Hold Sequences.Halt SequencesStan-up of the 8080 CPU

CHAPTER 3-INTERFACING THE 8080

GeneralBasic System Operation .CPU Module Design .Interiacirlg the 8080 to Memory and110 Devices

iiiiiiii;,

,-,"'-3

",-,'-3

211212213213

3-'3-'3-'

3-6

CHAPTER 4-INSTRUCTION SET

General . . . 4-1Data Transfer GrouP 4-4Arithmetic Group .. 4-5Branch Group ... _ . _ . . . . . ... __ . . .. 4-11Stack, tiD and Machine Controi Group 4-13Summary Table.. .. ... .. 4-15

CHAPTER 5-8080 MICROCOMPUTER SYSTEM COMPONENTSCPU Group

8224 Clock. GeneratorFunctional Description andSystem Applications 5- 1Data Sheet. 5-4

8228 System ControilerFunctional Description andSystem Applications. :-7Data Sheet _ 5- 11

8OBOA Central ProcessorData Sheet . . . . . . . . . . . . . . . . . . . . 5-13

OOOOA-l Central Proceuor (l.3j.(slData Sheet . . . . . . . . . . . . . . . . . . . . . . .. 5-20

0080A-2 Central Processor (l.5/.lslData Sheet . . . . . . . . . . 5-24

M8080A Central Processor (-55 to +125Q

ClData Sheet . . . . . . . . . . . . . . . . . . . . . . 5-29

5-11351165-127

5-'30

5-147, . 5149

5-151

.. 6-'

5-1695-171

' .. 5-173

... 5-1535-1555-157

. .. 5-160

5-1355-139

... 5-1435-144

8255 Programmable Perioheral 1nterfaceBasic Functional DescriptionDetailed Operational DescriptionSystem Applications of the 8255Data Sheet.

8251 Programmable Communication InterfaceBasic Functional DescriptionDetailed Operational DescriptionSystem Applications of the 8251Data Sheet.

Coming Soon8253 Programmable IntelVal Timer ..8257 Programmable DMA Controller8259 Programmable Interrupt Controller.

CHAPTER 6-PACKAGING INFORMATION ..

P1Iripheral58205 One of 8 Decoder

Functional DeSCrllltion .System Applications of the 8205Data Sheet.

8214 Priority Interrupt Control UnitInterrupts in Microcomputer SystemsFunctional Description.System Applications of 1I1e 8214Data Sheet.

8216/8226 48it BiDirectional Bus DriverFunctional Description. . .. 5-163System Applications of the 8216/8226 5-165Data Sheet. . 5-1665-91

5-99

5-95

5-71

5-79

5-61

>5'

5-59

5-45

5-1015-1035-109

''08212 8-8it I/O Port

Functional Desc(lpflOn _System ApplicatIons ot the 8212Data Sheet _

ROM~

8702A Erasable PROM 1256 x 81Data Sheet.

8708/8704 Erasable PROM (lK" 81Data Sheet,

8302 Mask ROM {256" 8iData Sheet.

8308 Mask ROM {lK x 81Data Sheet.

8316A Mask ROM (2K x 81Data Sheet _

RAMs8101-2 Static RAM (256 x 41

Data Sheet.81112 Static RAM (256 x 41

Data Sheet.8102-2 Static RAM 11 K x 11

Data Sheet.8102A-4 Static RAM (1 K x 11

Data Sheet.81078-4 Dynamic RAM (4K xl)

Data Sheet,5101 Static CMOS RAM (256 x 4)

Data Sheet _8210 Dynamic RAM Driver

Data Sheet _8222 Dynamic RAM Refresh Controller

New Product Announcement.

Since their inception, digital computers have continuously become more efficient, expanding into new appli-cations with each major technological improvement. Theadvent of minicomputers enabled the inclusion of digitalcomputers as a permanent part of various process controlsystems. Unfortunately, the size and cost of minicomputersin "dedicated" applications has limited their use. Anotherapproach has been the use of custom built systems made upof "random logic" (i.e., logic gates, flipflops, counters, etc.l.However, the huge expense and development time involvedin the design and debugging of these systems has restrictedtheir use to large volume applications where the development costs couid be spread over a large number of machines.

Today, Intel offers the systems designer a new alternative ... the microcomputer. Utilizing the technologies andexperience gained in becoming the worid's largest supplierof LSl memory components, Intel has made the power ofthe digital computar avaiiable at the integrated circuit level.Using the nchannel silicon gate MOS process. Intei engineers have implemented the fast j2 IlS. cyclel and powerful(72 basic instructions) 8080 microprocessor on a single LSIchip. When this processor Is combined with memory and110 circuits, the computer is complete. Intel offers a varietyof random-access memory (RAM), readonly memory (ROMland shift register circui.ts, that combine with the 8080 pro-cessor to form the MCS-80 microcomputer system, a systemthat can directly address arid retrieve es many as 65,536bytes stored in the memory devices.

The 8080 processor is packaged in a 40pin dual inlinepackege (OIPI that ailows for remarkabiy easy interfacing.The 8080 has a 16-bit address bus, a 8-bit bidirectional databus and fully decoded, TTL-compatible coMlol outputs. Inadditiorl to supporting up to 64K bytes of mixed RAM lindROM memory, the 8080 can address up to 256 input portsand 256 output ports; thus allowing for virtuaily uniimitedsystem expansion. The 8080 instruction set includes conditional branching, decimal as well as binary arithmetic,

logical, registertoregister,stack control and memory refer-ence instructions. In facl, the 8080 instruction set is power-ful enough to rival the performance of many of the muchhigher priced minicomputers, yet the 8080 is upward software compatible with Intel's earlier 8008 microprocessor(i.e., programs written for the 8008 can be assembled andexecuted on the 8080).

In addition to an extensive irlstruction set oriented toproblem solving, the 8080 has another significant feature-SPEED. lr1 contrast to random logic designs which tend towork in parallel, the microcomputer works by sequentiallyexecuting its program. As a result of this sequential exO(:ution, the number of !asks a microcomputer can undertakein a given period of time is directly proportional to theexecution speed of the microcomputer. The speed of execution is the limiting factor of the realm of applications ofthe microcomputer. The 8080, with instruction times asshort as 2 Ilsec., is an order of magnitude faster man earliergenerations of microcomputers, and therefore has an expanded field of potential applications.

The architecture of the 8080 also shows a significantimprovement over earlier microcomputer designs. The 8080contains a 16bit stack pointer that controls the addressingof an external stack located in memory. The pointer can beinitialized via the proper instructions such that any portionof external memory can be used as a last in/first out stack;tI1usenabling almost unlimited subroutine nesting. The stackpointer allows the contents of the program counter, the accumulator, the condition flags or any of the data registers tobe stored in or retrieved from the external stacK. In addition, multi-level interrupt processing is possible using the8080's stack controi instruction$. The status of the processor can be "pushed" onto the stack when an interrupt isaccepted, then "popped" off the stack after the irlterrupt hasbeen serviced, This ability to save the contents of the pro-cessor's regi5te11 is possible even if an interrupt serviceroutine, itself, is interrupted.

PrOduct definitionSystem and logIc design

Debug

PC Cilrd layoutDocumentation

Cooling and packaging

Power distributionEngJoeering changes

CONVENTIONAL SYSTEM

Done with logic diagrams

Done with conventlonai

Lab Instrumentation

Done with yellow wire

PROGRAMMED lOGIC

Simplified because of ease 01 incorporatH'g features

Can be programmed with design aids(compIlers, assemblers, eUllOrsj

Sollware and hardware aids reduce time

Fewer cards to layout

Less hardware to documentRetiuced system size and power consumption

eases job

Less power to distributeChange program

Table 0' The Ad~antage~ of U~ing Microproce5~ors

ADVANTAGES OF DESIGNINGWITH MICROCOMPUTERS

Microcomputers ~implify almo~t every phase of pro

duCt development. The first step, as in any product devel

opment iTogram, 'IS to ident'rfy the various funct'IOOS {hat

the end IyStem 15 expected to perform, Instead of realizingthese funclions wilh networks of gates ~nd flip flops, the

functions are implemented by encoding sU'luble sequencesof instructions (programsl in the memory elements. Data

and certain types of programs are stored in RAM, while the

basic program C~n be stored in ROM. The microprocessorperforms all of the system's funCllons by fetching the in

structlon~ in memory, execuling them and communicating

the resuliS via Ihe microcompUler'S 1/0 ports. An 8080microprocessor, executing the programmed logic stored in asingle 2048byte ROM element, can perform Ihe same logical

functions that might have previously required up to 1000logic gales,

The benefits of designing a microcomputer into your

'ystem go far beyond the advantages of merely simplifyingproduct development. You will also appreciale the profit

making advantages of using a microcomputer in place ofcustom-designed random logic. The mo,t apparent advantage

is the signIficant S

APPLICATIONS EXAMPLE

The 8080 can be used as the basis for a wide nr;etvof calculation and control systems. The system configura-tions for particular applications will differ in the nature ofthe peripheral devices used and in the amount and the typeof memory required. The applications and solutions described in this section are presented primarily to show howmicrocomputers can be used to solve design problems. The8080 shOuld not be considered limited either in scope orperformance to those applications listed here.

Consider an 8080 microcomputer used within an automatic computing scale for a supermerket. The basic machinehas two input devices: me weighing unit and a keyboard.u:oed for function selection and to enter the price per unitof weight. The only output device is a display showing thetotal price, although a ticket printer might be added as anoptional output device.

The control unit must accept weight information fromme weighing unit, function and data inputs from the key.board, and generate the display. The only arithmetic function to be performed is a simPle multiplication of weighttimes rate,

The control unit could probably be realized withstandard TTL logic. State diagrams for the various portionscould be drawn and a multiplier unit designed. The whaledasign could then be tied together, and eventually reducedto a selection of packages and a printed cirCuit board layout.In effect, when delligning with a logic family such as TIL.the designs are "customized"' by the chOIce of packages andthe wiring of me logic.

If, however, an 8080 microcomputer is used to realize

the control unit (asshown in Figure 0-11. the only "custom"logic will be that of the interface circuits. These circuits areusually quite simple. providing electrical buffering for theinput and outPUt signals.

Instead of drawing state diagrams leading to logic, thelIystem designer now prepares a flow chart, indicating whichinput signals must be read, what processing and compute.tions are needed, and what output signals must be produced.A program is written from the flow cl1art. The program isthen aSllemb!ed into bit panerns which are loaded into theprogram memory. Thus, this lIystem is customized primarilyby the contents of program memory.

For this automatic scale, the program would probablyreside in read,only memory (ROM), since the microcom-puter would always execute the same program, the onewhich implements the scale functions. The processor wouldconstantly monitor the keyboard and weighing unit. and up.date the display whenever necessary. The unit would requirevery little data memory; it would only be needed for ratestorage, intermediate results, and for storing a copy of thedisplay.

When the control portion of a product is implementedwith a microcomputer chip set, functions can be changedand features added merely by altering the program in memoory. With a TIL based system, however, alterations may re-quire extensive rewiring, alteration of PC boards, etc.

The number of applications for microcomputers islimited only by the depth of the designer's imagination. Wehave listed a few potential applications in Table 0-2, alongwith the types of peripheral devices usually associated witheach product.

~Ev80ARO PR1NTER

000 00

000 00OISPLAY LJWE'CHING 000 00 'jli3lblP 1;'1 ....L'~" 00000 00 UII'-'UII

1 1 IIr------IN'uT IN'Ur OUTPUT

I OPnONALI OVWUTINTER"ACE ~ , INTER"ACE ~, INTERFACE "' INTER'ACE "'I

iii !II~--TT--

,.. il ,,1 1'"" ~'""

cONTRO"

"i Ii[uN'TpROGRAM DATAMEMORy M~MORY"ROM' IRAM]

Figura 0-1. Microcomputer Application - Automatic Scale

iii

APPLICATION

Intelligent Terminals

Gaming Machines

Cash Registers

Accounting and Billing Machines

Telephone Switching Control

Numerically Controlled Machines

Process Control

Table 02. Microprocessor AppliClltionl

PERIPHERAL DEViCES ENCOUNTERED

Cathode Ray Tube DisplayPrinting UnitsSynchronous and Asynchronous data linesCassette Tape UnitKeyboards

Keyboards. pushbuttons and switdwsVarious display devicesCoin acceptorsCoin dispensers

Keyboard or Input Switch ArrayChange D;spenserDigital DisplayTicket PrinterMagnetic Card readerCommunication interface

KeyboardPrinter UnitCassette or other magnetic tape unit"Floppy" disks

Telephone Line ScannerAnalog Switching NetworkDial RegistersClass of Service Parcel

Magnetic or Paper Tape ReaderStepper MotorsOptical Shaft Encoders

Analog-toDigital ConvertersDigltai-to-Analog ConvenersControl SwitchesDisplays

This chapter rr'ltroduces certain basic computer concepts. It provides background information and definitionswhim will be usefui in later chapters of this manual. Thosealready familiar with computers may skip this materlai, attheir option.

A TYPICAL COMPUTER SYSTEM

A typical digital computer consists of:

al A centrai processor unit (CPU)bj A memoryc) Input/output 11/0) ports

The memory serves as a place to store Instructions,the coded pieces of information that direct the activities ofthe CPU, and Data, tne COded pieces of information that areprocessed by the CPU, A group of logically related instruc-tions stored in memory is referred to as a Program. The CPU"reads" each instruction from memory in a logically determined sequence, and uses it to initiate processing actions.If the program sequence is coherent and logical, processingthe program will produce intelligible and useful results.

The memory i'i also used to store the data to be manipulated, a'i well as the instructions that direct that manipulation. The program must be organized 'iuch that the CPUdoes not read a noninstruction word when it expects to'iee an instruction. The CPU can rapidly access any datastored in memory; but often the memory is not large enoughto store the entire data bank required for a particular application, The problem can be resolved by providing the com-puter with one or more Input Ports. The CPU can addressthese ports and input the data contained there. The additionof input ports enables the computer to receive informationfrom external equipment ('iuch as a paper tape reader orfloppy diskl at high rates of speed and In large volumes.

A computer also requires one or more Output Portsthat permit the CPU to communicate the result of its pro-cessing to the outside world, The output may go to a dis-play, for use by a human operator, to a peripheral devicethat produces "hardcopy," such as a line-printer, to a

"

peripheral storage device, such as a floppy disk unit, or theoutput may constitute process control signals that direct theoperations of another wstem, such as an automated assemblyline. Like input ports, output poru are addressable. Theinput and output ports together permit the processor tocommunicate with the outside world.

The CPU unifies the system. It controls the functionsperformed by the other components. The CPU must be ableto fetch instructions from memory, decode their binarycontents and execute them. It must alsO be able to referencememory and 110 poru as necessary in the execution of Instructions. In addition, the CPU should be able to recognizeand respond to certain external control 'iignals, such asINTERRUPT and WAIT requests. The functional unitswithin a CPU that enable it to perform these functions aredescribed below.

THE ARCHITECTURE OF A CPU

A typical central processor unit (CPU) consists of thefollowing interconnected functional units:

Registers Arithmetic/Logic Unit (ALUI Control Circuitry

Registers are temporary storage units within the CPU,Some registers, such as the program counter and instructionregister, have dedicated uses. Other registers, such as the ac-cumulator, are for more general purpose use.

Accumulator:

Tha accumulator usually stores one of the operandsto be manipulated by the ALU. A typical instruction mightdirect the ALU to add the contents of some other register tome contents of the accumulator and store the result in theaccumulator iuel/. In general, the accumulator is both asource (operandi and a destination (resultl register.

Often a CPU will include a number of additionalgeneral purpose registers that can be used to store operandsor intermediate data. The availability of general purpose

registers eliminates the need to "shuffle" intermed,ate reosultl back and forth between memory and the accumulator,thu, imoroving processing Ipeed and efficiency.

Program Counter (Jumps, Subroutinesand the Stack):

The instructions that make up" program are storedIn the system's memory, The centr~1 processor reference,the contents of memory, in order to determine what action" appropriate. This means that the proce>sor must knowwh',m locaflon comaln5the next ',nstruct"'on.

Each of the locations in memory IS numbered, to dis-tinguish it from all other locatIOns in memory, The numberwhich identifies a memory location is called its Addross.

The processor maintains a counter whIch contains theaddress of the next program instruction. This regi,ter iscalled the Program CountOr. The processor updates the pro-gram counter by adding "1" to the counter e~ch time ;tfetches an instruction, \0 that the program counter is alway,current Ipointing to the next instruction I.

The programmer therefore stores his instructions innumerically adjacent addresses, so that the lower addressescontain the first instruction, to be executed and the higheraddresses contain later instructions. The only time the pro-grammer may violate this sequential rule is when an instruc-tion i" one section of memory is a Jump i"structio" toanother section of memory.

A jump instruction contains the address of the instruc,tion which is to follow it. The next instruction may bestored in any memory location, as long as the programmedjump specifies the correct address. During the execution ofa jump instruction, the processor replaces the co"tents of itsprogr~m counter with the address embodied in the Jump.Thus, the logical continuity of the program is malntai"ed

A special kind of program jump occurs when the storedprogram "Calls" a subroutine. In this kind of jump, the procel'or is required to "remember" the contents of the pro-gram counter at the time that the jump occurs. This enable,the processor to resume execution of the main programwhe" it ,s finished with the last instruction of the subroutine.

A Subroutine is a program within a program. Usuallyit is a geperal-purpose set of instructions that must be exe-cuted repeatedly ;n the course of a main program, Routineswhich calculate the square, the sine, or the logarithm of aprogr~m variable arE good examples of functio"s ofte"written as ,ubroutines, Other examples m',ght be progr~msdesigned for inputting or outputting data to a particularperjpheral devjce.

The processor has a special way of ha"dling sub-routines, in order to insure an orderly return to the main

program. When the processor receives a Call instruction, iti"crements the Program Counter and stores the counter'sco"tents In a reserved memory area know" ~s the Stack.The Stack thus saves the address of the instruction to beexecuted after the subroutine is completed. Then the pro-

"

cessor loads the address specified in the Call into its Pro-

gram Counter, The nen instructio" fetched will thereforebe the first step of the subroLltine.

The last instruction in any ,ubroutine is a Return. Suchan instruction need wecify no addreSI. When the processor

fetches a Return inltruction, it simply replaces the currentcontents of the Program Counter with the address 0" thetop of the Itack, This caLlses the prOCe'SOr to relume executio" of the calling program at the point immedIately following the original Call I"struction.

SubroLltines are ofte" Neded; that is, one subroutinewill sometimes call a Illcond lubrouti"e. The second maycall a third, and so on. This is perfectly ~ccept~ble,as lo"gas the processor has enough capacity to store the necessaryreturn addressel, and the logical plovision for doing so. inother words, the maximum derJth of nesting is determinedby the depth of the stack jtself. If the stack has space for,taring three return addresses, then three levels of subroutines may be accommodated.

Processors have different ways of maintaining stacks,Some have facilities for the storage of return addresses builtinto the processor itself. Other processor5 Ulll a re,ervedarea of external memory as the stack and simply maintain aPointer register which cont~in~ the address of the mostrecent stack entry. The external ltack allows virtually un-limited subroutine "esting. In additio", if the processor pro-vides instructions that cause the contents of the accumulatorand other general purpose registers to be "pushed" o"to thestack or "popped" off the stack via the address stored i" thest~ck pointer, multi-level interrupt processing Idl'scribedlater in thi, chapter) is p055ible. The Itatus of the processor(i,e., the contents of all the registersl can be saved in thestack when an interrupt is accepted and then renored afterthe interrupt has bee" serviced. Thil ability to save the pro-cessor's status at any g',ven (,me 'II possible even if an 'inter-rupt service routine, itself, is interrLlpted.

Instruction Register and Decoder:

Every computer has a Word length that is characteris_tic of that machine. A computer's word length is u5LIallydetermjned by the lize of its internal storage elements andinterco""ecting paths Ireferred to as BussuJ. for example,a computer whose regilters and busses can store and trans-fer 8 bits of informatIon has a characteristic word length of8-bits and is referred to as an abit parallel processor. Anelght-b',t parallel processor gener~lly finds 11 most efficient

to deal with eight-bit binary fields, and the memory ~~sociated with such a processor il therefore organjzed to Itoreeight bjts in each addressable memory location. Data andinstructions are stored in memory as eight-bit binary "umbers, Or as numbers that are Integral multiple, of eight bits:

16 bits, 24 bits, and so on. This characteristic eightbit fieldis often referred to as a Byte.

Each operation that the processor can perform isidentified by a unique byte of data known ~s an Instruction

Code or Operation Code, An elghtbit word used as an ,n,struction code can distinguish between 256 alternativeactions, more than adequate for IYlOSt proceswrs.

The processor fetches an instruction in 1'....0 distinctoperations. First, the processor nansmits the aodress in itsProgram Counter to the memory. Then the memory returnsthe addressed byte to the processor. The CPU stores thisinstruction byte in a register known as the InstructionRe-girter, and uses ;t to direct activities during the remainderof the instruction execution.

The mechanism by which the processor translates aninstruction code into specific processing actions requiresmore elaboration than we can here afford. The concept,however, ~hould be intuitively clear to any logic designer.The eight bits

with a cleanydefined activi,y IS called a State. And the inter-val between pulses oi the liming nscillator is referred to as aClock Period, As general rule, One or more clock periodsare necessary for the complet,on of a 'late, and there arelever.1 st.tes In a cycle.

Instruction Fetch:

The first statel,) of .ny instruction cycle will bededicated to fetching the next instruction. The CPU issues aread signal .nd the conterl1S of ,he program counter are senlto memory, which responds by returning the next instruc.tion worp, The first pyte of the instruction i, placed in theinstructLon register, If the instruction cOnsiSt5 of more thanon~ byte, .Oditionai 5tates are required to fetch each byt~of the instructIon. When the entire instruction is present inthe CPU, the program Counter is incremented (in prepara-tion for lhe next inSlruction fetch) and the in5truction isdecoded. The operation specified in the instruction will beexecuted in the remaining states of the instruction cycle.

The instruction may call for a memory read or write, aninput or output and/or an internal CPU operation, such asa registertoregister transfer or an addregi$ters operation,

Memory Read:

An instruction fetch is merely a special memory readoperation that brings the instruction to the CPU's instruc.tion reg'51er. The instruction fetched may then call for data

to be read from memory into the CPU. The CPU again i5suesa read signal and sends the plOper memory address; memoryresponds bv returning the requested word The data re-ceived is alaced in the accumulator or one of the other gen-eral purpose registers Inot the instruction register).

Memory Write:

A memory write OPeration is similar to a read exceptfor the direction of data flow. The CPU iS5ues a writesignal, senos the proper memory address, then sends the dataword to be written ,nto the addressed memory location.

Wait (memory synchronization):

As previously 5tated, the activities of the processorare timed by a maSter clock oscillator, The clock perioddetermines the timing of all processing activity.

The soeed of the processing cycle, however, is limitedby the memory's Acce,~ Time, Once the processor has sent aread address to memory, it cannot proceed until the memoryhas had t,me to respond. Most memories are capable ofrespondIng much faster than the proce"ing cycle requires.A few, however, cannot supply the addre"ed byte withinme minimum time establiShed by the processor's clock.

Therefore a processor shOuld contain a synchroniza-lion prov'Slon, whidl permits the memory to request a Wait

state, When the memory receives a read or write enable sig.nal, it places a request SIgnal on the processor's READY line,causing the CPU to idle temporarily. After the memory has

h.d time to respond, it frees the processor's READY line,and the instruction cycle proceeds

Input/Output:

Input and Output operations are simil~r to memoryread and write operations with the exception that a peri-pherall/O device is addressed in5tead of a memory location,The CPU issues the appropriate input or output controlsignal, sends the proper device address and either receivesthe data being input or sends the d~ta to be output.

Dat~ can be input/output in either parallel or serialform, All data within ~ digital computer is represented inbinary coded form, A bin~ry data word consists of a groupof bits; each bit is either a one or a zero. Parallal 110 con.sists of transle",ng all bits in the word at the same time,one bit per line, Serial 1/0 consists of transferring one bitat a time on a lingle line. Naturally serial 110 i~ muchslower, but it require$ considerably less hardware than doesparallel I/O,

Interrupts;

InterTl/pt provisions are included on many centralprocessors, 'lS e means of improving the proce~sor's effi-ciency. Consider the case of a computer that is processing alarge volume 01 dat~, portions of which are to be outpulto a printer, The CPU can outPUt ~ byte of data within asingle machine cycle but ii may take the printer the equiva.lent of many machine cycles to actually print the char~eterspecified by the deta byte. The CPU could then remain idlewaiting until the printer can aCCept the next d~ta byte, If~n interrupt capability is implemented On the computer, theCPU c~n output a data byte then return to d~ta processing.Whenthe printer is ready to aCCept the next data byte, itcan request an interrupt. When the CPU acknowledges their"lterrupt, it smpends main program execution and auto-matically branches to a routine that will output the nextdata byte. After the byte is OUtput, the CPU continueswith main program exeCution. Nota that this is, in principle,quite $imilar to a subroutine call, except that the jump rsinitiated externally rather than by the program.

More complex interrupt structures are possible, inwhich several interrupting devices share the same processorbut have different priority levels. Interruptive processing isan import.nt feature that enables maximum untilization ofa processor's capacity for high system throughput.

Hold:

Another important feature that improves the through.put of a processor is the Hold, The hold provision enablesDirect Memory Access (DMAI operations.

In ordin~ry input and output operations, the processoritself supervises the entire data transfer. Information to beplaced in memory is transferred from the input device to theprocessor, and then from the processor to the de~ignatedmemory location. In similar fashion, information that goes

from memory to OUtput devices \!Oes by way of theprocessor.

Some peripheral devices, however, are capable oftransferring in/ormation to and from memory much fasterthan the processor itself can accomplish the transfer. If anyappreciable quantity of data must be transferred to or fromsuch a device, then syrtem throughput will be increased by

having the device accomplish the transfer direetly. The pro-cessor mu51 temporarily suspend its operation during such atransfer, to prevent conflicts that would arise if processorand peripheral device attempted to access memory simul-taneously. It is for this reason that a hold provision is in-cluded on some processors.

The 8080 is a complete 8bit parallet central processorunit (CPU) for use in general purpose digital computer sys-tams, It is fabricated on a singla LSI chip (see Figure ,3.1 Lusing Intel's nchannel silicon gate MaS process. The 8080transfers data and internal state information via an 8-bit,bidirectional 3-state Data Bus (DOD7l. Memory and peripheral device addresses are transmitted over a separate 1&-

bit 3-state Addrass Bus (ArrA1S). Six timing and controloutputs (SYNC, D81N, WAIT,WR, HLDA and INTEl amanate from the 8080, while four control inputs (READY,HOLD. INT and RESET), lour power inputs l+12v, +5v,-5v, and GND) and two clock inpuTS 11 and 2) are accepted by the 8080.

Figul'll 21. 8080 Photo,micrograph With Pin Designations

-" ., -"'"' , , -"" , " -"" " -"" , " -"" " -," , " -," INTEt' " -," ' " -," ' " 8080 " ,-" " " -,RESET " , -,~" " " ,,~," .. " "" " " -,'NTE 0 .. " ,oB,N 0 " " WAnw. .. " READvSYNC " " ""0 " " ~LDA

ARCHITECTURE OF THE 8080 CPUThe 8080 CPU consins of the following functional

units:

Register array and address logic Arithmetic and logic unit (ALUI Instruction register and COntrOl section 8i-directional, 3-state data bus buffer

Figure 22 illustrates the functional blocks withinthe 8080 CPU,

matically during every instruction fetch, The stack pointermaintains the address of the next available stack location inmemory, The stack pointer can be initialized to use anyportion of read-write memory as a stack. The stack pointeris decremented when data is "pushed" Onto the stack andincremented when data '" "popped" off the stack (i.e., thastack grows "downward").

The six generel purpose registers can be used either assingle registers (8bit) or B$ register pairs (16bitl. Thetemporary register pair, W,Z, is not program addressableand is only used for the Internal execution of instructions.

Registers:The register section consists of a static RAM array

organiZed into six 16bit regrsters:

Program counter (PC I Stack pointer (SP) Six Sbit general purpose registen arranged in pairs,

referred to as 8,C; D,E: and H,L A temporary register pair called W,Z

The program counter maintains the memory addrassof the current program instruction and is incremented auto

Eightbit data bytes can be transferred between theinternal bus and the register array via the register-selectmultiplexer. Sixteenbit transfers can proceed between theregister array and the address latch or the incrementerldecrementer circuit. The address latch receives data fromany of the three register pairs and drives the 16 addressoutput buffers (AO-A15l. as well as the incrementerldecrementer cirCUit. The incrementer/decrementer circuitreceives data from the address latch and sends it tothe register array. The 16bit data can be incremented ordecremented or simply transferred between registers,

"".......AOO"ISS8US

BIOIReCTION~l0, 0,

08'0. INTE INT ff()LQHOCOW NC 02 R'SACK ReAOY

itOATA BUS

I, oATA eu\.J-,BUFFER/lATCH" BIT] it f881TimTERNAl OATA BUS INTERNAL OATA nus

11 11 1rACCUMULAW:I TEM' "'G'."I I'N:Eci~~~r~N.. , MUlTIPLEXIR I

l I: r 'LAG ''''1- W "'I' , '"TEMPREG, T,M'ReC,~CCU~A~~"i.T~:l i

'cl~f ops

'" , '"g ,REG. REG,I A"""MHIC INSTRUCTION , , ," '"f- COCIC o,oooe" REC, ReG.'" I- "UN" l== .,ACHINE ~ " '. , '" f-(AlUI CVCl. "EG. REG,'"I-- ENCOOINC "" STACK POINTER

TT "-PROGRAM COUNTERrOCIMU----"'- I- INC~e.,eNHRIOECRe.,'NteRADJUST AOOReSS LATCH ""TIMING..,

CONTRo~

POWER!_ "IV I.. OATARUS INtERRUPT HOLO WAIT I ~OORSS8UFH~ "'1UPPLIES _ .,vw"'T< CONTROC CO/'lT~Ol CONTRO~ CONTRol SVNC ClD

Arithmetic and Logic Unit (ALU):

The ALU COnta,ns the following registers:

An S-bit accumulator

An S-bit temporary accumulator ~ACTI

A Sbit flag register: 2, are furnished

by external circuitry. It is the 1 clock pulse which divideseach machine cycle into states. Timing logic wilhin the

8080 uses the clock inputs to produce a SYNC pulse,wkich ,dentlfies the beginning of every machine cycle. The

SYNC pulse is triggered by the lowto_high transition of 2,

"shown in Figure 2-3.

FIRST STAT~ OF 1'EV~RY MACHIN~ I

CI'CLE

\SI'NC DO~S NOT OCCUR IN THE SECOND AND THIRD MACHIN~CYCLES OF A PAP INSTRUCTION SINC~ THESE MACHIN~ CI'CL~SAR~ USE a FOR AN INTERNAL REGISTER-PAIR ADD

Figure 2-3.0"W2 And SYNC Timing

There are three exceptions 10 the defined duration of

a state. They are the WAIT state, the hold (HLDA) state

and the halt ~HLTAI state, described later in this chapter.Because the WAIT, the HLDA, and the HLTA states depend

upon external events, they are by their nature of indeter-

minate length. Even these exceptional states, however, must

be synchronized with the pulses of the driving clock. Thus,the duration of all states are 'Integral multiples of the clackperiod.

To summarize then, each clock period marks a state;three to five states constitute a machine cycle; and one tofive macbine cycles comprise an instruction cycle. A fullinstruction cycle requires anywhere from four to eight-teen states for its completion, depending on the kind of instruction involved.

Machine Cycle Identification:

With the exception of the DAD instruction, there isjust one consideration that 'determines how many machinecycles are required in any given instruction cycle: the number of times that the processor must reference a memoryaddress or an addressable peripheral device, in order tofetch and execute the instruction. Like many processors,the 8080 is so constructed that it can transmit only oneoddress per machine cycle. Thus, if the fetch and executionof an instruction requires two memory references, then the'Instruction cycle associated with that instruction consi5ts oftwo machine cycles, If five such references are called for,then the instruction cycle contains five machine cycles.

Every instruction cycle has at least one reference tomemory, during which the instruction is fetched. An instruction cycle must always have a fetch, even if the execution of the instruction requires no further references tomemory. The first machine cycle in every inmuction cycleis therefore" FETCH. Beyond that, there are no fast rule5.It depend5 on the kind of instruction that is fetched.

Consider some examples. The addregister (ADD rJinstruction is an instruction that requires only a singlemachine cycle (FETCHI for its completion. In this onebyte'Instruct'lon, the contents of one of the CPU's six generalpurpose registers is added to the existing contents of theoccumulator. Since all the information necessary to executetha command is contained in the eight bits of the instructioncode, only one memory reference is necessary. Three statesare used to extract the instruction from memory, and oneadditional state is used to accomplish the desired addition.The entire instruction cycle thus requires only one machinecycle that cons"sts of four states, or four periods of the ex-ternal clock.

Suppose now, however, that we wish to add the contents of a specific memory location to the existing contentsof the accumulator (ADD MI, Although this is quite similarin principle to the example just cited, several odd'itionalsteps will be used. An extra machine cycle will be med, inorder to address the desired memory location.

The actual sequence is as follows, First the processorextracts from memory the onebyte instruction word addressed by its program counter. This takes three states.The eight-bit instruction word obtained during the FETCHmachine cycle is deposited in the CPU's instruction registerand used to direct activit'les during the remainder of theinstruction cycle. Next, the processor sends out, as an address,

the contents of its Hand l registers, The eightbit dataword returned during this MEMORY READ machine cycleis placed in i temporary register inside the 8080 CPU, 8ynow three more clack periods (states! have elapsed. In theseventh and final state, the contents of the temporary register are added to those of the accumulator. Two machinecycles, consisting of seven states in all, complete the"ADD M" Instruction cycle,

At the opposite extreme is the save Hand l registers(SHLD) instruction, whidl require~ five maChine cycles.During an "SHlD" instruction cycle, the contents of theprocessor's Hand l registers are deposited in two sequentially adjacent memOry locations: the destination is indiocated by two address bytes which are stored in the twomemory locations immediately follow'mg the operation codebyte. The following sequence of events occurs:

(1) A FETCH machine cycle, consisting 01 fourstates. During the first three states of thismadline cycle, the processor letches the instruction indicated by its program counter. The program counter is then incremented. The fourthstate is used lor internal instruction d6i:oding.

(2! A MEMORY READ machine cycle, consistingof three states, During this machine cycle, thebyte indicated by the program counter is readfrom memory and placed in the processor'sZ register. The program counter is incrementedagam.

(3) Another MEMORY READ maChine cycle, consisting of three states, in whidl the byte indica

ted by the processor's program counter is readfrom memory and placed in the W register, Theprogram counter 'IS incremented, in anticipationof the next instruction fetch.

(41 A MEMORY WRITE machine cycle, of threestates, in which the contents of the l registerare transferred to the memory location pointedto by the present contents of the Wand Z registers. The state following the transfer is used toincrement the W,Z register P8ir so that it indi-cates the next memory location to receive data,

15) A MEMORY WRITE machine cycle, of threestates, in Which the contents of the H registerare transferred to the new memory locationpointed to by the W,Z register pair,

In summary, the "SHLD" instruction cycle containsfive machine cycles and takes 16 states to execute.

Most instructions fall somewhere between the extremes typified by the "ADD r" and the "SHlD" instruc-tions. The input (INP) and the output lOUT! ;nstruction~,for example, reqUire three machine cycles: a FETCH, toObtain the instruction: a MEMORY READ, to Obtain theaddress of the object peripheral: and an INPUT Or an OUTPUT machine cycle, to complete the transler.

While no OM instruction cycle wiil con~ist of morethen five machine cycle~. the foliowing ten different typesof machine cycles may OCCur within an ,n~truction cycle:

111 FETCH (M1:

121 MEMORY READ

131 MEMORY WRITE

141 STACK READ

151 STACK WRITE

161 INPUT

171 OUTPUT

181 INTERRUPT

191 HALT

(10l HALT. INTERRUPT

The machine cycle, that actually do occur in a partlcular imtruction cycle depend upon the kind of instruc-tion, With the overriding stipulation that the first machinecycle in any imtruction cycle is always" FETCH.

The processor identifies the maci1ine cycle in prog-ress by trensmitting an eight-bit ~tatus word during the fi"tstate of every machine CYcle. Updated status information ispresented on the 80BO's data lines 100-071. during theSYNC interval. This data should be saved in latches, andused to develop control signals for external circuitry. Table21 shows how the posltivetrue status information is distributed on tha processor's data bus.

Status signals are prov,ded princioally for the controlof external circuitry. S,mplicity of interf"ce, rather thanmachine cycle identification, dictates the logical definitionof individual status bili. You will therefore observe thatcertain processor machine cycles are uniquely identified bya single status bit, bUI that others are not. The M1 statusbit 1061, for example, unambiguously identifies a FETCHmaroine cycle. A STACK READ, on' trle other hand, isindicated by the coinciDence of STACK and MEMR sig-nals. Machine cycle identification data is also valuable inthe test and de.bugging phases of sv>lem development.Table 2-1 lists the ,tatus bit outputS lor each type 01machine cycle.

State Transition Sequence:

Every machine cycle within an inmuction cycle con-sists of three to five active states (referred to a~ Tl, T2, T3,T4, TS or TW). The actu,,1 number of states depends uponthe instruction being executed, and on the particular maoroine cycle within the greater instruction cycle. The statetransition diagram in Figure 2-4 shows how the 8080 proceeds from state to slate in the course oi a machine cycle.The diagram also shows how the READY, HOLD, andINTERRUPT lines are sampled during the machine cycle,and how the conditions on these lines may modify the

"

basic transition sequence. In the present discussion, we areconcerned only with the basic sequence and with theREADY function. The HOLD and INTERRUPT functionswill be di~cussed later.

The 8080 CPU does not directly indicate its internalstate by trammitting a "state control" output duringeach ,tate: instead, the BOBO supplies direct control output(INTE, HLDA, DBIN, WR and WAITI for use by externalcircuitry.

Recall that the BOBO passes through at least threestates in every machine cycie, with each state defined bysuccessive lowto_high transitions of the 'Ill clock, Figure2-5 shows the timing relationships in a typical FETCHmachine cvcle. Events that occur in each ~tate are referencedto transitions of the

Symboh

tNTA

STACK 0,

HlTA 0,0", 0.

M, 0,

INP' 0.

MEMR" 0,

Instructions for the 8080 require from one to five machinecycles for complete executton, The 8080 ..nds out 8 bit ofstatu. information on the data bUS at the beginning of eachmachine cycle (during SYNC time), The following table definesthe

Y' _AESET'"READV+HLTA

'"

READY. HL TA

SET I~"RN""HO'O F/'

~OlD

,,,'",I HOLD

I MOD'

"'NnANAL~OLO''''

Sf' '

RESETHLTA

SET INnR~ALHOLD f:'

"

PiL:J

RESET ,"URNALHOLD' ,

HOLD

Figure 2-4.

SET 1NHRNAl

INT '"

CPU State Transition 0'I~gram

Pi~

A'SIiT INTERNALHOLD FIF

""NTE f/' tS"'lNTER R"H IF INTO""'~SH NRL INT ,.oF'S RESP L ,KT'IF '$ SO'PAGE '.13 - I' ,,,. 'IF" "'"

The events that take place during the T3 state aredetermined by the kind 01 machine cycle in progress. In aFETCH machine cycle, the processor Interprets the data onits data bus as an instruction. During a MEMORY READ ora STACK READ. data on this bus is interpreted as a dataword, The proce"or outputs data on this bus during aMEMORY WRITE machine cycle. During I/O operations.the processor may either transmit or receive data, de-pending on whether an OUTPUT or an INPUT operationis involved.

Figure 2-6 illustrates the timing that is characteristicof a data input operation, As shown, the low-to-high transi-tion of"'2 during T2 clears status information from the processor's data line" preparing these li"es ior the receipt oii"coming data. The data prese"ted to the processor musthave stabilized prior to both the "01-data set-up" interval(tOS1), that precedes the lalli"g edge of the 01 pulse defin-ing state T3, and the "02-data set up" interval (t0521.that precede, the rising edge of 2 in state T3' This same

data mU$t remain stable during the "data hold" interval(tOHI that occurs following the rising edge of the 2 pulse.Data placed on these lines by memory or by other externaldevices will be sampled during T3.

During the input of data to the processor, the 8080generates a DBIN signal which ,hould be used externally toenable the transfer. Machine cycles in which DBIN is avail_able include: FETCH, MEMORY READ, STACK READ,and INTERRUPT. DBIN is initiated by the rising edge of 412during state T2 and terminated by the corresponding edge of02 during T3. Any TW phase, intervening between T2andT3 will therefore extend DB IN bv one or more clockperiods.

Figure 2-7 shows the timing of a machine cycle inwhich the processor outputs deta. Output data may be des-tined either for memory or for peripherals. The rising edgeof 2 within state T2 clears status information from theCPU's data lines, and loads in the data which is to be outputto external devices. This substitution takes place within the

"A"

" " '. ", '. , '.

!( n h h

I , ~I L

i , II

i i Il,INXNOWfl :

: : -ji L..-"A,n"'Oo, --------@ A flOATING-- -i (r~t:

FWATING,

I

OATA '---- A,AoMOO'

STA'"

! \ I !; :~ if :

I! I

i i I !DATA, , I! I ! ,STAW, ,; 'N'O."'ATlO, !, OATA,

IIA'~1"'OA' AM.'", """"" .,AO' OPHONAl , "TC" OATA Of'TIONAL"ow ANO"Ol T , "- o., o. , "ACT '"STAl,,:r,o" ,"STA''''''ON'10 o'v,a NU..... o. o. ,X'OOlT'ON0" ",EMO "A,T< OATA " .'OUI.'OSTAW' 'N'O...."o" ACCESS T1"" :,"'A o", AOJUS;

i~"A .0

IME". -,'" STOCK

i

Figure 2-5. Ba.ic 8080 Innruction Cycle

"

------flOATING

"

INPuT DATA TOACCUMULATOR

BVTETWO

,-

.,',

"

UNKNOWN

""

- ,BYTE

""

"

"A".

a,.

SV"C

081"

READY

IWAIT0,

'" l )STATuS 0),NFORMATIONNOTE: Refo' '0 Statu, WO'd Chart on Page 2-6.

Figure 2-6. Input lnnruction Cycle

"" : M,---- ._._----"~-",."

T, ----!"

i BYTE0,. ----l,-:---,,'c-.-'_"'_,,} -FLOATIN~ 7" - -r-t--T,"+-_,~,_,ocJ - - -r--..,-"."",O'"~O"""'O'"~"'..

SVOlC

STUUSIN~ORMATIO"

NOTE :::tel., 10 SI.N' Wo'd Chart on Page 26

FiguI'll2-7. Output Instruction Cycle

"data output delay" interval (tOO) following the

INTERRUPT SEQUENCES

The 8080 has the builtin capacity to h~ndle external,nterrupt requests. A peripheral device can initiate an inter.rupt simply by driving the processor's interrupt liNT) linehigh.

The interrupt liNT) input is asynchronous. and arequen may therefore originate at any time during anyinstruction cycle. Internal logic re-clocks the external re-quest, so that a proper correspondence with the drivingclock is established. As Figure 28 shows, an interruptrequest IINTI arriving during the time that the interruptenable line (INTE) is high, acts ,n coincidence with the 02clock to set the internal interrupt latch, This event takesplace during the last state of the mstrue-tion cycle in whichthe request occurs, thus ensurong that any mstruction ,nprogress is completed before the ",terrupt can be processed.

The INTERRUPT machine cycle which follows theerr ivai of an enabled interrupt request resembles an ordin~ryFETCH machine cycle in most respects. The M1 status bitis transmitted as usual during the SYNC interval. It isaccompanied. however. by ~n INTA status bit IDOl whichacknowledges the external requeu. The contents of theprogram counter are latched onto the CPU's add,ess linesduring T 1, but the counter itself is not incremented duringthe INTERRUPT machine cycle, as it otherwise would be_

T] -------;::--

In this way, the preinterrupt status of the program counteris preserved, so that data in the counter may be restored bythe interrupted program after the Interrupt request has beenprocessed.

The interrupt cycle is otherwise indistingw$hable from~n ordinary FETCH machine cycle. The processor itselftakes nO further special action. It is the responsibility of theperipheral logic to see that an eightbit interrupt instructionis "jammed'" onto the processor's data bus during state T3.In a typical system. this means that the datain bus frommemory must be temporarily disconnected from the processor's main data bus, so that the interrupting device cancommand the main bus WIthout interference.

The 8080's instruction set provides a special one-bytecall which facilitates the processing of interrupts (the ordinary program Call takes three bytesl. This is the RESTARTinstruction (RST). A variable threebit field embedded inthe eightbit field of the RST enables the interrupting deviceto direct a Call to one of eight fixed memory locations. Thedecimal addresses of these dedicated locations are: 0, 8. 16,24, 32, 40, 48. and 56. Any of these addresses may be usedto store the first instruction Is) of a routine designed toservice the requirements of an interrupting device. Sincethe (RSTI is a call, completion of the instruction ~Isostores the old program counter contents on the STACK.

''''9=~t:8e'hoSYNC

~TuA""" ~t==~~==~~;;~~!===~~i==i========j==~======~~~"m""

INH

,"

,NT'," :t==~~~~~:~~~~~;~~~~t;;~;;;;;~~~~;;~;;;i~~;;~""'"""INH'BIT STO~E Ofpc., i1Nn~NAL)STUUS'''FORMATION 0 0

NOTE Ref., to Statu, WO'd Cnarl on Page 2-6,

Figure 2-8. Interrupt Timing

HOLDREOUEST

HOLD

REAOV

HOLD ~!FINTERNA~

HCOA

...J il lll

iI

" ;T. ,>

I

T, T,

[" SEE ATTACHED ELECTRICAL CHARACTERISTICS

Figure 2-9. HOLD OplH"ltion (Reed Model

>T. AND T. OPERATION CAN liEDONE INTERNALLY.

HOLDR~OUEST

HOLD

REAOV

HaLO .... ,'NTERNAL

HCOA

1-- i; ., M ,.1 M 0+2 ,T ~ -'. , " '. " ,.I ,n h h h

~~~~---- ---n,i~r-':'_-! i ----- ---- --y-____ -J

i, ,

, i, , ,i . ! ,, ,

II , ,, , . I

,

i I,

WR'TE DATA

Figure 210. HOLD Oparltion (Write Model

HOLD SEQUENCESThe 0080A CPU contains provisiom for Direct Mem-

ory Access (DMAI operations. By applying a HOLD to theappropriate control pin on the processor, an external devicecan cause the CPU to ~spend its normal operations and re-linquish control of the address and data busses. The proces-sor responds to a request of this kind by floating its addressto other devices sharing the busses. At the same time, theprocessor acknowledges the HO LD by placing a high on itsHLDA outpin pin, During an acknowledged HOLD, theaddress and data busses are under control of the peripheralwhich originated the request, enabling it to conduct mem-ory tramfers without processor intervention.

Like the interrupt, the HOLD input is synchronizedinternally_A HOLD signal must be stable prior to the "Holdset-up" interval ItHSJ. thet precedes the rising edge of z.

Figures 29 and 210 illustrate the timing involved inHOLD operations, Note the delay between the asynchronousHOLD REOUEST and the re_c1ocked HOLD. As shown inthe diagram. a coincidence of the READY. the HOLD, andthe rP2 clocks sets the internal hold latch. Selling the latchenables the subsequent rising edge of the 1 clock pulse totrigger the HLOA output.

AcknOWledgement of the HOLD REQUEST precedesslightly the actual floating of the processor's address anddata lines. The processor acknowledges a HOLD at the begin-ning of T3. if a read or an input machine cycle is in progressIsee Figure 29!- Otherwise, acknowledgement is deferreduntil the beginning of the state following T3 (see Figure210). In both cases, however, the HLDA goes high withina specified delay (toe I of the rising edge of the selected 1clock pulse. Address and data lines are floated within abrief delay after the rising edge of the next

To all ourward appearances, the processor has suspended its operations once the address and data busses are floated.Internally, however, certain functions may continue. If aHOLD REQUEST is acknowledged at T3, and if the pro-cessor is in the middle of a machine cycle which requiresfour or more states to complete, the CPU proceeds throughT4 and TS before coming to a rest. Not until the end of themachine cycle is reaetled will processing activit ie, cease.Internal processing i, thus permitted to overlap the externalOMA transfer, improving both the efficiency and the speedof the entire system,

The processor exits Ihe holding state through asequence similar to that by which it entered, A HOLDREQUEST is terminated asynchronously when the externaldevice has oompleted its data transfer. The HLDA output

returns to a low level following the leading edge of the next1> 1 clock pulse. Normal processing resumes with the maochine cycle following the last cycle that was executed.

HALT SEQUENCES

When a helt instruction IHLT) i' executed, the CPUenters the hillt state ITWH) after state T2 of the next ma-chine cycle, as ,hown in Figure 2-11. There are only threewan in which the 8080 can exit the halt state',

A high on the RESET line will alwavs reset the8080 to state Tl' RESET alsO clears the programcounter,

A HOLD input will cause the 8080 to enter thehold ~tate, as previously described. When theHOLD line goes low, the 8080 re-enters the haltstate on the rising edge of the next 01 clockpulse.

An interrupt (i,e .. INT goes high while INTE isenabledl will cause the 8080 to exit the Halt stateand enter ,tate T 1 on the rising edge of the next01 clock pul se. NOTE: The Interrupt enable (INTE)flag must be ,et whan the halt stata is entered;otherwise, the 8080 will only be able to exit via aRESET signal.

Figure 2-12 illustrates halt sequencing in flow chartform.

START-UP OF THE 8080 CPU

When power is applied initially to the 8080, the pmcessor begins operating immediately. The contents of itsprogram counter, stack pointer, and the other working regis-ters are naturilliv sub'lect to random factors and cannot bespecified, For this reason, it will be necessary to begin thepower-up sequence with RESET.

An external RESET signal of three clock period dura-tion (minimum I restores the processor's internal programcounter to 'ero. Program execution thus begins with mem-orv locatIon zero, following a RESET. Systems which re-quire the processor to wait for an explicit startup signalwill store a halt instruction (EI, HLT) in the fim tw:l loca-tions. A manual or an automatic INTERRUPT will be usedfor starting. In other systems, the processor may begin ex-ecuting its stored program immediately. Note, however, thatthe RESET has no effect on status flegs, or on any of theprocessor's working registers (accumulator, registers, or,tack pointer) The contents of these registers remain inde-terminate, until initialized explicitly by the program.

Z13

,-r---1-'----r---I

"[X-I '-----~I

1

"

\I\

"

("

D"'N

,.,--..,---+---,-'-A", ---lPC0" .l-..J'----

SyNc --l

iSTATUS j 0)INFORMATlO", _----~-

NOn G """ 1050"", ,,,,,OC,,,, ,. P... ,-,

Figure 2-11. HALT Timing

TO'T~H ,"

" "ES"

n,

,,"I

HOLDn,

TST~TET,

Figure 2-12. HALT Sequence Flow Chart.

2-14

" i'" I----

r-+------------~~~~;-----~---~'"~.,o---

-'*f- - - - - - -'... ~,,~"!"_x

......

"..n:=.~.~.==jt============:==~~~=============j.....0 ..""nSYNC ~, r--'OOIN ~,--------- J

(')

''''''

orATUS

''''0"''.''0'' (')

Figure 214. Relation between HOLD and INT in the HALT State.

215

~""ON'C 0' cooe ~,;ll.,

, 0,.0.0&0. 1,0,0,00 n n l2J I " " " n n i2i ",MOvn." 0 , 0 0 0 , , , 'COUT , eo ~ PC '1 INST_T"P.'IR I 'SSSl_TM. (TM"_OOO I I ,STATuSMO. ',M 0 , 0 0 0 , , 0 ! ,Ill ~COUT , :"TA_ODO, sr~Tu,iGI ,MOVM., 0 , , , 0 ISSSI_TMP HL OUT T~"--+O,Od, 0 I 0 0 0 I 0

"LOuT5TATUSl7i

PCOuTnATUslOI

.,TOI"

PC_!'C' ,

IT"'I

"'

OATIl. BUS

" "

,., fACTI.11loI ......~

,. IACTI+ITMPI'CY_A" (AcYl'IT"'I,cY_A, '",-'., IACTl-ITlol']_A ',-,. IACT!_lr_'_A

" IACTJ_ITMPI-eV_A" IACT}_lrMPI-eV_A

H~OuT ", OATA"U'STATuS!'!

HCOlJT ", O"'T"SUSAT 171

2-17

M~"'ONIC I O'COO' M,llI "', 0,0.0.0. 0,0,0,0. n "I~ n I " " n ,,121

,n

ANI"" , , , , , , , , , 'COIJT 'C - 'C -, IN:>f_n'.II~ IAI_ACT fATUSi"i"~A , , 0 , 0 , , , , !Af-."CT , , (ACTl.(T"'I_A, (S$SI_n,,' IX~A '"

, 0 , 0 , , , , I IAI_ACT " HeOuT DATA ,.,I STATU.[a] ,," .." , , , 0 , , , 0 I , IAJ..CT 'COUT I _C - 'C -, " '.':>fATU,:'-ORA' , , , , , , IAI_A "T .. rAcTItTMPI-AI",,"_TM"ORA M , , , , , , , 'M_ACT ~C our 'ATA ,.,

STATw,l' ,ORI .." , , , , , , , iM_ACT PC OUT 'C PC" " _~r""STATUS'~ ,"",P,

, ' , , , , , , , , 'A) _ACT ,,, 'ACTI-ITMPI FLAO' II",.,_TM'CM'M , , , , , , , 0 IAJ_ACT HeOUT DATA ,.'

STATU':!

cPr ....I, , , , , , 0 , IA>_Acr / PC OUT I 'C' PC" "' m,I STATlJ',"'

RCC , , , , 0 , , , IAI_ALU ,..!

AeCf-oA, CY

"AOTAH

'I

,", , , , , , , , , IAh'"U 1+ ."AelF+A, cy

ROTAH ,

," 0 0 0 , 0 , , , , IA1. CY_ACU " AClF+A. CYAO'A".., , , 0 , , , , , 'AI, CY_ACU '"' ALlF+A. CY t{,, ~OTA"'.0 0 , , , , , , , (",l-A

" L,\w, , 0 , , , , , , , ! CY_C" \.( ,,'0' 0 , , , 0 , , , I ,~," ....x" ! '

, 0 0 0 0 , , , PC OlJT PC'PC+' ",

STAW':'; ,

J fA'US~, 0 0 0 o ! 0 , 0 0 PC OVT .C - PC + 'I 'NS~_TMPIlR ,

ST.WS ,

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NOTES:

1. The fim memory cycle (Ml) is always an instructionfetch: the first lor onlyl byte, containing the op code, isfetched during this cycle.

2. If the READY input from memory is not high duringT2 of each memory cycle, the processor will enter a waitstate (TWI until READY is sampled as high.

3. States T4 and T5 are present, as required, for opera-tions which are completely interl'\ill to the CPU. The contents of the internal bus during T4 and T5are available atthe data bus: this is designed for tening purposes only. An"X" denotes that the state is present, but is only used forsuch internal operations as instruction decoding.

4. Only register pairs rp ~ B (registers B and C) or rp= 0(registers D and E) may be specified.

5. These states are skipped.

6. Memory read SUb-cycles; an instruction or data wordwill be read.

7. Memory write SUb-cycle.

8. The READY signal is not required during the secondand third subcycles 1M2 and M31. The HOLD signal isaccepted during M2 and M3. The SYNC signal is not gene-rated during M2 and M3. During the execution of DAD,M2 and M3 are required for an internal registerpair add;memory is not referenced.

9. The resulU of these arithmetic, logical or rotate in-structions are not moved 'mto the accumulator (A) untilstate T2 of the next instruction cycle. That is, A is loadedwhile the next instruction is being fetched; this overlappingof operations allows for faster processing.

10. If the value of the least significant 4-bits of the accumu-lator is greater than 9 ~ if the auxiliary carry bit is set, 6is added to the accumulator. If the value of the most signifi-cant 4-bits of the accumulator is now greater than g. or ifthe carry bit is set, 6 is added to the most significant -4bits of the accumulator.

11. This represents the first sub-cycle ~the instructionfetch) of the next instruction cycle.

12. If the condition was met, the contents of the registerpair WZ are output On the address lines (AO-I5 ) instead ofthe contents of the program counter (PCI.

13, If the condition wa. not met, sub-cycles M4 and M5are skipped: the processor instead proceeds immediately tothe instruction fetch IM1) of the next instruction cycle.

14. If the condition was not met, subcycles M2 and M3are skipped; the processor instead proceeds immediately tothe instruction fetch (M 1) of the next instruction cycle.

15. Stack read sub-cycle.

16. Stack write Subcycle.

17. CONDITION CCC

NZ not zero (Z ~ 0) 000Z zero (2 = 1) 001

NC nocarry~CY=O) 010C carry (CY ~ 1) 01 t

PO parity odd ~pmO) 100PE parity even (p: 11 101

P plus (S=O) 110M minus~S~l) 111

18. I/O sub-cycle: the 1/0 port's 8-bit select code is duplicated on addrll5s lines 0-7 (Ao-7) and 8-15 ~A8.15).

19. Output SUb-cycle.

20. The processor will remain idle in the halt nate untilan interrupt, a reset or a hold is accepted. When a hold reoquest is accepted, the CPU enters the hold mode; after thehold mode is terminated, the processor returns to the haltstate. After a reset is accepted, the processor b!1Qins execution at memory locatiorl zero. After an irrterrupt is accepted,the processor executes the irlstructiorl forced onto the databus (usually a restart irlstrlJetion).

SSS or DOD Value " ValueA 111 B 00B 000 0 01C 001 H 10D 010 SP 11E 011H 100L 101

2-20

CPU Module- Contains the Central Processing Unit, systemtiming and interface circuitry to Memoryand I/O devices.

'''Module'' refers to a functional block, it does not reference a printed circuit board manufactured by INTEL.

t"Bus" refers to a set of signals grouped together becauseof the similarity of their functions.

I

Basic System Operation

Figure 3--1, Typical Computer SY10tem Block Diagram

1. The CPU Module issue5 an acti~ity command on theControl Bus,

2, The CPU Module issues a binary code on the AddressBus to identify which particular Memory location orI/O device will be involved in the current processactivity.

3. The CPU MOdule receive5 or transmits data with theselected Memory location or I/O device.

4. The CPU Module returns to CD and issues the nextactivity command.

It is easy to see at this point that the CPU module isthe central element in any computer SY5tem,

Control BU1 A unidirectional set of s;gnal5 that indicatethe type of activity in current proceS5.

Type of acti~ities: 1 Memory Read2. Memory Write3. I/O Read4. I/O Write5, Interrupt Acknowledge

Contains Read Only Memory IROMI andReadlWrite Memory IRAMI for program anddata storage,

Con'tain5 circuitry that aliows the computersystem to communicate with device5 orstructures exi5ting outside of the CPU orMemoryarray.

for example: Keyboard5. Floppy Disks,Paper Tape, etc.

I/O

Memory

There are three busses that ',nterconnect these blocks:

Data Bus'~ A bi-directional path on which data can flowbetween the CPU and Memory or I/O.

Addren Bus A unidirectional group of lines that identifya particular Memory location or I/O device.

Thi5 chapter will illu5trate, in detail, how to interfacethe B080 CPU with Memory and I/O. It will al50 5how thebenefit5 and tradeoffs encountered when using a variety ofsY5tem architectures to achieve higher throughput, decreased component count or minimi~ationof memory \i~e.

8080 Microcomputer sYstem design lends itself to asimple. modular approach, Such an approach will yield thedesigner a reliable. high performance system that contain5 aminimum component count and is easy to manufacture andmaintain.

The overall sy5tem can be thought of as a 5impleblock diagram. The three (31 blocks in the diagram reoresent the function5 common to any computer system.

"

The following page~ will cover the detailed design ofthe CPU Module with the 80BO. The three Busse~ (Data,Addre~s and Control) will be developed and the intercon-nection to Memory and I/O will be ~hown.

De~ign philo~ophie~ and system architectures pre~ented in this manual are consinent with product development programs underway at INTEL for the MCS~80. Thus,the designer who u~es thi, manual as a guide for his totalsystem engmeering is assured that all new developmenu incomponent! and software for MCS80 from INTEL will becompatible with his design approach.

the design and to achieve operational chariICteristics thatare as close as possible to those of the 8224 and 8228,Many auxiliary timing functions and features of the 8224and 8228 are too complex to practically implement in~tandard component~, so only the basic functions of the8224 and 8228 are generated. Since significant benefits insystem timing and component count reduction can berealized by using the 8224 and 8228, this is the preferredmethod of implementation.

1. 8080 CPU

CPU Module Design

2. A Clock Generator and High Level Driver

3. A bi-directional Data Bus Driver and System ControlLogic

The following will discuss the design of the threemajor areas contained in the CPU Module. Thi~ design Ispresented a~ on alternative to the Intel@ 8224 Clock Generator and Intel 8228 System Controller. By studying thealternative approach, the designer can more clearly see theconsideratiom involved in the specification and engineeringof the 8224 and 8228. Standard TTL components and Intelgeneral purpo~e peripheral devices are used to implement

1.

The CPU Module contains three major areas:

The 8080 Central Proce~~ing Unit 2.

The operation of the 8080 CPU was covered in previou~ chapters of this manual, so linle reference willbe made to it in the design of the Module.

Cloc:k Generator and High level Driver

The 8080 is a dynamic device, meaning that its ifllernal storage elements and logic circuitry require atiming reference (Clock), supplied by external circuitry. to refresh and provide timing control signals.

The 8080 requires two (21 such Clocks. Their waveforms must be nonoverlapping, and comply with thetiming and levels specified in the 8080 A.C. and D.C.Characteristics, page 515.

Clock Generetor Design

The Clock Generator consists of a crystal controlled,

uND ., " .,'0.

ro ".. .." "o. ro " ".11 v "

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n 00 '",., " '"" ",,_oe. " ~.." " a'o,A,c- '",mT "EO ",",RATOR " ~'AOY 0- TION" '"O~IVE" 'us O~'VfA",""E~" _ " RESET .. '"0' '"" m ",'YAC

~J".'U' "AOEE "'''A"""" o__ ~""" OO",RO, au'CONTROL __ "0"~,-::o;;;

Figura 3-2. 8080 CPU Interfece

"

::JSCILLATOR

sv"c14HOO

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AUKiliary Timing Signah and Functions

The Clock Generator can aim be used to provideother signals that the designer can use to simplifylarge system timing Or the interface to dynamicmemories.

Functions such as power-on reset, synchronization ofellternal requests (HOLD, READY, etc.1 and singlestep. could easily be added to the Clock Generator tofurther enhance in capabilities.

For instance, the 20 MHZ signal from the oscillatorcan be buffered so that it could provide the basis forcommunication baud rate generation.

The Clock Generator diagram also shows how to generate an advanced timing signal (lAI that is handyto use in clocking "D" type flipflops to synchronizeellternal requests. It can also be used to generate astrobe (STSTB) that is the latching signal for the status information which is available on the Data Bus atthe beginning of each machine cycle. A simpie gatingof the SYNC signal from the 8080 and the advanced(lAI will do the job. See Figure 3-3.

3. BiDirectional 8us Driver end System Control Logic

The system Memory and I/O devices communicatewith the CPU over the bi-directional Date Bus. Thesystem Control Bus is used to gete data on end offthe Data 8us within the proper timing sequences asdictated by the operetion of the 8080 CPU. The detalines of the 8080 CPU, Memory and 110 devices ere3-state in nature. that is, their output drivers havethe ability to be forced into a highimpedence modeand ere, effectively, remOlled from the circuit. This 3-state bus technique allows the designer to construct asystem around a single, eight 181 bit parallel. bidirec-tional Data Bus and simply gate the information onor off this bus by selecting or deselecting (3-st.ting)Memory and I/O devices with signals from the Con-trol8us.

BiDirectionel Date Bus Driver Design

The 8080 Data Bus (07-DO) has two (21 major afeasof concern for the designer;

1. Input Voltage level (V1HJ 3.3 volts minimum.

2. Output Drive Capability (I OLll.? mA maKimum,

10 R

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0'12,1. "O,.N 0;

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,0 ~8212" '5 OuT

If--L""

,

" ~" 18 ,,,.n 21 MeMR'j---'J ~,STST. V"

"'-~

Figura 3-5. 8080 System Control

The input le~el lDecification implies that any semi-conductor memory Of I/O device connected to the8080 Data Bus must be able to provide a mirtimum of3.3 ~olt~ in ill high ltata, Most semiconductor memories and standard TTL I/O de, ices have art outputcapability of beTween 2.0 and 2.8 ~olts, ob~iously adirecT connectiort OrtTO the 80BO Data Bus would require pullup resistors. whose value should not affectthe bUI lpeed or nress the drive capability of thememory or I/O componertts.

The B080A output drive capability IIOLI 1,9mA max.is sufficiertt for lmall systems wMre Memory size arld1(0 requiremenU are minimal and the erttire system iscOrltairled on a sirtgle printed circuit board. Most systems howe~er, taKe ad~antage of the high-perfor-mance computing power of the BOBO CPU and thus amore typical syStem would require some form of buffering on the BOBO Data Bus 10 IUPPOrt a larger arrayof Memory and I/O de~ices which are likely to be onseparate boards.

A de~ice specifically designed to do this bufferingfunction is the INTE~ 8216, a 14) four bit bidire

INTERFACING THE 8080 CPU TO MEMORYAND I/O DEVICES

The 8080 'Interfaces with standard semiconductorMemory components and I/O devices, In the previous textthe proper control signals and buffering were developedwhich will produce a simple bus System similar to the basicsystem example shown at the oog'mn'mg of th'ls chapter.

In Figure 36 a simple, but exact 8080 typical systemis shown that can be u,ed as a guide for any 8080 system.regardless of size or complexity, It is a "three bus" architecture, us'mg the s'lgnalsdeveloped 'In the CPU module.

Note that Memory and I/O devices interface in thesame manner and that their isOlation is only a function ofthe definition of the Read-Write signals on the Control Bus,ThiS allow, the 8080 sy,tem to be configured so that Mem-ory and I/O are treated a, a single array Imemory mapped1/01 for small ,ystems that require high thruput and haveless than 32K memory size. This approach will be broughtout later in the chapter,

This feature eliminates the need for extra equipment liketape readers and disks to load programs initially. an important aspect 'In small system design.

Interfacing standard ROMs, such as the devices shownin the diagram is simple and direct, The output Data linesare connected to the bi-directional Data Bus. the Address",puts tie to the Address bus with possible detared a method to load

I--P~'O"'TYINTE~~UP;ij21'

81'1

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I"0> a080A cpu

"" OO,DJ a.,N HLOA AD A15in I I I T;,~,4";;,,,c,

, I , ,

I"OlA a,al 8'0' 1 B'O;>",.YB

RAM memory mu~t be provided, such as: Floppy Disk,P~per T~pe, etc,

The CPU treats RAM in exactly the same manner asROM for addressing data to be read. Writing data is verys,milar. the RAM is issued an address during the first portion of the Memory Write cycle lTl & T2) in T3 when thedata that is to be written is output by the CPU and is stableon the bus an MEMW command is generated. The MEMWsignal is connected to the R!W input of the RAM andstrobes the data into the addressed location.

In Figure 37 a typical Memory system is illustratedto show how standard semiconductor components interfaceto the 8080 bus. The memory array shown has 8K bytes(8 bits/byte) of ROM storage, using four Intelt '8216Asand 512 bytes of RAM storage, using IMel 8111 staticRAMs. The basic interface to the bUi structure detailedhere is common to almost any size memory. The only addition that might have to be made for larger systems ismore buffers (8216/8212l and decoders (8205) for generating "chip selects."

The memories chosen for this example h~v. ~n acc.s~tim. of 850 nS lmaxl to illustrat. that slower, economicaldevices can be easily interfaced to the aoElo Wilh little effeet on performance. When the 8080 is operated from aclock generator with a tCY of 500 nS the required memoryaccess time is Approx, 450550 nS_ See detailed timingspecification Pg. 516. Using memory devices of this speedsuch as Inte11l'8308, 8102A, 8107A, etc. the READY inputto the 8080 CPU can remain "high" becau$e nO .......ait ..states are required. Note that the bus interface 10 memorysho..... n in Figure 3-7 remain~ the same. Ho.....ever, it slo.....ermemories are to be used. such a$ the devices i',lustrated(8316A, 8111) that have acceS$ times slower than the minimum requirement a simple logic control of the READYinput to the 8080 CPU will insert an extra "wait state" thatis equal to one or more clock periods as an access time"~diustment" delay to compensate. The effect of the extra"wait" $tate is naturally a slower execution time for theinstruction. A $ingle "wait" changes the basic imtructioncycle to 2.5 microSecond~.

8K+512 o

MEMORY MAP

"OM

Alt_

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JC]

8316A

01-08'"1101-4 AO-A]8111

RIW DOAO-A7

811t

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DATA BUS fBI

:=D 0 D 0CONTROL BUS 161

II IlADDRESS BUS (161

Figul'll 3-7. Typical Memory jnterface

I/O INTERFACE

o ,.

c:J

"OlATED' G-~~--~--------~------,

TO M"mRYD,v,ces

p- ,7Oll -IJTO ,IOOEvICES

llnput Port to any Register)10utput any R9ister to Port!10utput immediate data to Port)Iinput to ACC)10utput from ACC to Port!116 8it Input)116 Bit Output!IAdd Port to ACCII"AND" Port with ACq

f-----"""'. l

SySteMCONT~Ol

18"81

Examples:

MOVr, MMOV M,MVIMLDASTALHLDSHLDADD MANAM

It Is easy to see that from the list of possible "new'instructions that this type of 110 architechJre could have adrastic effect on increased .ystem throughput. It is concep,tually more difficult to understand than Isolated I/O and itdoes limit memory address space. but Memory Mapped 110can mean a significant increase in overall speed and at the-same time reducing required program memory area.

By assigning an area of memory address space as t/O apowerful architechJre can be developed that can manipulate110 using the same instructions that are used to manipulatememory locations. Thus, a "new" instruction set is createdthat is devoted to 110 handling.

As shown in Fi9Ufe 310, new control signals are generated by gating the MEMR and MEMW si!J1al.with A15. themost significant address bit. The new 110 control signals con-nect in exactly the same manner as Isoleted I/O, thus thesystem bus characteristics are unchanged.

By assigning A15 as the I/O "flag". a simple method of110 discipline is maintained:

If A15 is a "zero" then Memory is active.If A15 Is a "one" then I/O is active.

Other address bits can also be used for this function. A15 waschosen because it is the most significant address bit so it iseasier to controi with software and because It ~till allowsmemory addressing of 32K_

I/O devices are still considered addressed "ports" butInstead of the Accumulator as the only transfer medium anyof the internal r9i~ters can be used. All instructions thatcould be used to operate on memOry locations can be usedin 110.

Figure 39. Isolated 1/0.

Memory Mapped I/O

o ~,---____''''

I 0'00"' I,,,,,,,, 'r--------------------~~

i 1 0'00"' ')'0 T,I ','~ORV MA"ED' 0~---~-----------------j

In Figure 3-9 the system control signals. previously detailed in this chapter, are shown. This type of I/O architectureseparates the memory address space from the 110 addressspace and uses a conceptually simple transfer to or from Accumulator technique. Such an architecture is easy to understand because 110 communicates only with the Accumulatorusing the IN or OUT instructions. Also because of the isolation of memory and 110. the full address ~pace (65K) is uneffected by I/O addressing.

As in any comput~r bas~d syst~m. the 8080 CPU mu~tbe able to communicate with device~ or structure~ that existout~ide its normai memory array. Devices like keyboard~.paper tape. floppy disks. printers. displays and other controlstructures are used to input information into the B080 CPUand display or ~tore the results of the computational activity.

Probably the most imponant and strongest feature ofthe 8080 Microcomputer System is the flexibility and powerof its I/O structure and the components that ~upport it. Thereare many ways to structure the liD array so that it will "fit"the total system environment to maximize efficiency andminimize component count.

The basic operation of the I/O structure can best beviewed a~ an array of single byte memory locations that canbe Read from or Written into. The 8080 CPU has special innruction~ devoted to managing Such transfer~ (IN, OUT).These instructions generaily isolate memory and 110 arraysso that memory addres~ space is not effected by the 110structure and the general concept is that of a ~imple transferto or from the Accumulatorwith an addressed "PORT". An-other method of I/O architecture is to treat the I/O structureas part of the Memory array. This is generally referred to as"Memory Mapped 110" and provides the designer with apowerful new "inuruction set" d~voted to 110 manipulation.

Isolated I/O

Figure 3-8. Memory/liD Mapping.

General Theory

,.

1 "L MEMOR'!, DEVICES

S'ISTIM"ONTRa,

1'"''

FigutI3-10. Memory Mapped I/O.

The second example uses Memory Mapped 110 andlinear select to show how thirteen devices 18255) can be addressed without the use of extra decoders. The format showncould be the second and third bytes of the LDA or STA in-structions or any other instructions used to manipulate 110using the Memory Mapped technique.

It is easy to see that such a flexible 110 structure, thatcan be "tailored" to the overall system environment, providesthe designer with a powerful tool to optimize efficiency andminimize component count.

EXAMPLE #2

"I I I I L:=} "",,,um~}".,,,..u,,.

I/O Addressing

With both systems of I/O structure the addressing ofeach device carl be configured to optimize efficiency and re-

duce component count, One method, the most common, is

to decode the address bus into exclusive "chip selects" thatenable the addressed 110 device, similar to generating chip-selects in memory arrays.

Another method is called "linear select". In this method,irlstead of decoding the Address Bus, a singular bit from thebus is assigned as the exclusive en~ble for a specific 110 de-vice. This method, of course, limits the number of 110 de-vices that can be addressed but eliminates the need for extradecoders, an important consideration in small system design.

A simple example illustrates the power of such a flexi-ble I/O stn.Jcture. The first example illustrates the format ofthe second byte of the IN or OUT instruction using the Isolated 110 technique. The devices used are Intel"'8255 Pro-grammable Peripheral Interface units and are linear selected,Each device has three ports and from the format it can beseen that six devices can be addressed without additional de-coders.

'- 1I0HAG

ADDRfSSES _'1 _.81557,.83.91.95'99

5-1015-1135-135

5-147

"535-163

5-1695-1715-173

------ .------._..-

82248228

8080A

CPU Group

8080A-18080A-2

M8080-A

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SCHOTTKY BIPOLAR 8224

FUNCTIONAL DESCRIPTION

General

The 8224 i~ a single chip Clock GeneratorlDriver for the8080A CPU. It contains a crystal-controlled oscillator, a"divide by nine" counter, !VIIO high-level drivers and severalauxiliary logic functiom.

Oscillator

The oscillator circuit derives its basic operating frequency

from an external, series resonant, fundamental mode crystal.

Two inputs are provided for the crystal connections IXTAL 1,XTAL21.

The selection of the external crystal frequency depends

mainly on the speed at Which the 8080A is to be run at.Basically, the oscillator operates at 9 times the desired pro-cessor speed.

A simple formula to guide the crystal selection is'

,Crystal Frequency ~ - times 9

'"Example 1: {500ns tCY)

2m Hz times 9 = lBmHz'

Example 2: (BOOns tcyl1.25mHz times 9 = 11 ,25m Hz

Another input to the oscillator is TANK. This input allowsthe use overtone mode crystals. This type of crystal generally has much lower "gain" than the fundamental type soan external LC netvliork is necessary to provide the additional"gain" for proper oscillator operatlon_ The external LC net-work is connected to the TANK input and is AC coupled toground. See Figure 4.

The formula for the LC network is'

F._'__2lrYLC

The waveforms generated by the de

I!> sv~c om IDID "'" ~~,

'~PuT MRTII>

ID AOV'~ ....llVl:!>

The output of the oscillator is buffered and brought outon ElSC Ipin 12) so that other system timing signals can bederived from this stable, crystalcontrolled source.

'When using crystal, abo.e 10mH, a ,mall amoun, of frequency"trimming" may be necessary '0 produce tho exact de,ir.d Ire-qu.~oy. Thddition of , 'mall ,.Ioct.d ClIp.citanc. 13pF - 10pFli~ ""ri., with the crystal will .ccompl,

SCHOTTKY 81 POLAR 8224

STSTB (Status StrobelAt the beginning of Bach machine cycle the 8080A CPU is-;Ue5 status information on its data bus. This informationtells what type of action will take place during that machinecycle. By bringing in the SYNC signal from the CPU, andgating it with an internal timing signall~lAl. an active lowstrobe can be derived that occurs at the start of each ma-clline cycle at the earliest possible moment that status datais $lable Orl the blJs. The STSTS signal connects directly tothe 8228 System Controller.

The poweron Reset alro generates STST8. but of COUI1l!.for a longer period of time. This feature allows the 8228 tobe automatically reset without additional pins devoted forthis function.

Power-On Reset and Ready Flip-Flops

A common function in 8080A Microcomputer systems is thegeneration of an automatic system reset and startup uponinitial power-on. The 8224 has a built in feature to accomp-lish this feature.

An external RC network is connected to the RESIN input.The slow transition of the power supply rise is sensed by anInternal Schmitt Trigger. Thiscircuit converts the slow transItion into a clean, fast edge when its input leve! reaches apredetermined value_ The output of the Schmitt Trigger isconnected to a "0" type flip flop that is clocked with 20(an internal timing signal!. The flip-flop is synchronouslyreset and an octive high level that complies with the 8080Ainput SPllC 'IS generated. For manual switch type system Re-set circuits, an active low switch closing can be connectedto the RESIN input in addition to the power-on RC net-network.

The READY input to the 8080A CPU has certain timingspecifications such as "set-up and hold" thus, an externalsynchronizing flip-flop is required. The 8224 has this featurebuilt-in. The RDYIN input presents the asynchronous "waitrequest" to the "0" type flip-flop. By clocking the flip-flopwith 2D, a synchronized READY signal at the correct in-put level, can be connected directly to the 8080A.

The reason for requiring an external flip-flop to synchro-nize the "wait request" rather than Internally in the 8080CPU is that due to the relatively long delays of MOS logicsuch an implementation would "rob" the designer of about200ns during the time his logic is derermining if a "wait"is necessary. An external bipolar circuit built into the clockgenerator eliminates most of this delay and has no effect oncomponent count.

~------...,, ,, ,, ,, ,, ', ', '

~ :,,'---------',. "-

'.,.olC

U"OO~lV

Fa. OVERTONECRvSTALS

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SCHOTTKY BIPOLAR 8224

D.C. Characteristics

TA ~ OC to 70'C; Vee ~ +5.0V 5%: Voo - +12V :!5%.

L.imitsSymbol P