Integration of Power-Supply Capacitors with Ultrahigh ...pwrsocevents.com/wp-content/uploads/2012-presentations/session-4/4... · on Silicon Using Particulate Electrodes POWERSOC

Integration of Power-Supply Capacitors with Ultrahigh Density on Silicon Using Particulate Electrodes

POWERSOC 2012

P M Raj, Himani Sharma, Kanika Sethi, Prof. Rao Tummala

3D Systems Packaging Research Center

Georgia Institute of Technology, Atlanta, GA 30332-0560

2nd GIT Workshop, November 14-16, 2012

Slide 1

Outline –  Component integration using 3D IPAC Concept –  3D IPAC goals –  Applications

o VRM and decoupling §  Thinfilm decoupling capacitors

o Power convertor §  High-density capacitors


Slide 2

Passives Trend

Silicon and Glass IPDs

400-500 microns 500 microns (0402)

Discretes

Thick Devices 500-800 microns

Array of Discretes

500 microns (0402)

Thick Devices 500-800 microns 200-800 microns

Courtesy: Kemet, Fraunhofer IZM

3D IPAC

40 microns

40-100 microns


Slide 3

Passives Passives

What is 3D IPAC Concept and Why? Active IC Active IC

40 µm

10 µm

1.  Ultra-thin Glass Core ~ 30 µm

2.  Low Loss

3.  Fine-pitch and coarse-pitch through-package vias

4.  Passive components on both sides of glass. •  RF capacitors, inductors •  Power supply capacitors and inductors •  Decoupling Capacitors •  Precision components

5.  Active components for power, digital, RF and Analog

6.  Interconnections

3D IPAC is a functional module

30 µm


Slide 4

3D IPAC on Interposer

Passives Passives

Active IC Active IC

40 µm

10 µm

30 µm

3D IC

Si/Glass Core

3D IPAC

Thin 3D IPAC Capacitor

IC

10 µm

30 µm

3D IPAC

IC


Slide 5

3D IPAC in the 3D POP

Passives Passives

Active IC Active IC

40 µm

10 µm

30 µm


Slide 6

3D IPAC on PWB

Passives

Active IC Active IC

40 µm

10 µm

30 µm

PWB


Slide 7

Goals of 3D IPAC §  Miniaturization:

–  5X reduction in thickness

§  Cost: –  2—5X reduction in cost

§  Performance: –  Higher bandwidth at lower power compared to today’s systems

§  Functionality: –  Double-side component integration for heterogeneous functions in an

ultrathin module


Slide 8

3D IPAC – Applications

RF MODULE Power Convertor Module

PDN Module

Glass

Active MOSFET Switches

High-density Capacitors

High-density Inductors

•  RF ICs •  High Q and Precision

Components: •  Capacitors •  Resistors •  Inductors

•  Voltage regulator module

•  VRM output capacitors •  Decoupling capacitors

•  Power switches •  High-density capacitor •  High-density inductor

High-density Output Capacitors

Glass

High Frequency Decoupling

POWER IC

80 µm Glass

10 µm

Precision RF Capacitors

Precision Resistors

RF Inductors

By-pass capacitors

RF IC


Slide 9

3D IPAC – PDN Module

POWER

GROUND FR4

Case 3

3D IPAC VRM

Glass core

Logic IC

30 µm

•  Improved power integrity for 3D ICs and packages with thinner packages

•  VRM and decoupling functions in the interposer, close to the package

•  Reduces the number of decoupling capacitors

•  Thin power ICs (ex. MOSFET switches)

•  High-density inductors

•  High-density capacitors

Glass

High Frequency Decoupling

POWER IC


Slide 10

§  Thinfilms (100-300 nm): –  Thinner films (Barium Strontium Titanate); –  Faster crystallization; –  Higher capacitance density of 14 nF/mm2

Key Result BST on Si/SiN/Ta/Ni

BST sputtering Ar/O2 (60% O2); 100 W; 2.5 hrs

Annealing conditions

750 C, 30 min in N2

Capacitance density 9 – 11 nF/mm2

Higher yield with large area electrodes 220 nF achieved on 0.28 cm2

Leakage current of the order µA/cm2 achieved up to 3 V (4 nF/mm2)

Yield 85% (30/35 devices yielded)

Sputtered BST Thinfilm Capacitors


Slide 11

Solgel PZT –Thinfilm Capacitors

1.2 x 2.5mm2: 100-110 nF,

loss 0.1-0.3

Yield 51% (56/110)

yield 14% (8/57)

225 nF,

2.9 x 2.5mm2: loss 0.4-1.2

2.5 µF/cm2 (1 V) 1 µF/cm2 (10 V)

1.0E-‐8

1.0E-‐7

1.0E-‐6

1.0E-‐5

1.0E-‐4

1.0E-‐3

1.0E-‐2

1.0E-‐1

1.0E+0

0 5 10 15

Leakage Cu

rren

t (A/cm

2)

Volts (V)

PZT/LNO/Pt/Ta/Si

PZT/LNO/Si

PZT/LNO/ZrO2/Si


Slide 12

3D IPAC-Based PDN •  Three decoupling capacitor

integration scenarios were modeled

•  SMD on board shows highest parasitics and lowest performance;

•  Requires excessive on-chip decoupling

•  ThinFilm integration in today’s packages can achieve higher frequency stability, but has limited manufacturability

•  IPAC micro-assembled close to IC shows best performance because of thin interposer and short bump parasitics;

0.01$

0.1$

1$

10$

100$

1000$

0.00E+00$ 5.00E+08$ 1.00E+09$ 1.50E+09$ 2.00E+09$

Impedance))

(Ω))

Frequency)(Hz))

SMD

Integrated

Thin IPAC capacitor

5X improvement in frequency performance with the proposed 3D IPAC strategy


Slide 13

3D IPAC – Power Converter Module Power Module:

•  Switching regulator or charge-pump based •  Thin power ICs •  High-density inductors •  High-density capacitors

Glass

Active MOSFET Switches

High-density Capacitors

High-density Inductors


Slide 14

High-Density Capacitors


Slide 15

Area enhancement for 100 µm film

Pla

nar c

apac

itanc

e µ

F/cm

2

1.4

0.2

0.6

1.0

1.8

2.2

5 20 50 200 500

MLCC

2 µF/cm2

10 µF/cm2

40 µF/cm2

100 µF/cm2

Tantalum

PRC Focus


Slide 16

Adhesion layer

Silicon Carrier

Rou3ng Layer

Bo7om Electrode

Dielectric

Top Electrode

Process flow for High-Density Capacitors


Slide 17

Silicon Trench vs. Copper Par3culate Electrode

Silicon Compatible 100 X enhancement in area Expensive silicon micromachining tools

Silicon Compatible Potential for >2000 X enhancement in surface area from BET measurements ( 100 µm) Low-cost paste processing

Porous Electrode with Highest Surface Area Efficiency


Slide 18

0

5

10

15

20

25

30

35

5 10 15 20 25 30 0

100

200

300

400

500

600

700

800

900 0.2 0.5 1 3 5 10

500 - 700 !!

ASPECT RATIO (TENCH)

PARTICLE SIZE (NANOELECTRODE)

AR

EA

EN

HA

NC

EM

EN

T

25 - 30

0

5

10

15

20

25

30

35

5 10 15 20 25 30 0

100

200

300

400

500

600

700

800

900 0.2 0.5 1 3 5 10

500 - 700

ASPECT RATIO (TENCH)

PARTICLE SIZE (NANOELECTRODE) A

RE

A E

NH

AN

CE

ME

NT (

TRE

NC

H)

AR

EA

EN

HA

NC

EM

EN

T (

NA

NO

ELE

CTR

OD

E)

25 - 30

Area Enhancement: Nanoelectrodes Vs Trenches


Slide 19

PRC’s Background High-Density Capacitor Research

High surface area electrodes on silicon trench;

High surface area electrodes on organic substrate with etched foil

High surface area electrodes on organic substrate with sintered particles Adhe

sion layer

Adhesion layer

US 8,084,841 B2

US 8,174,017


Slide 20

Silicon Bottom Cu

Sintered particles

Nanoelectrodes on Si

Step 1: §  Copper powder §  Dispersant (Phosphate ester) §  Binder: Propylene carbonate Step 2: §  Printing on Silicon Step 3 §  Sintering – 400o C – 600o C

§  Copper particle size : 1-2 µm §  High surface area enhancement

due to open pores §  30-40X surface area enhancement

for 25 µm film


Slide 21

Porous electrode with Sacrificial Polymers • Using a sacrificial polymer (polypropylene carbonate) that would decompose easily at

sintering temperatures in reducing atmosphere

Porosity in place of polymer

HEAT

Polymer granules

Copper particles

Polypropylene carbonate Vola3le by-‐product


Slide 22

ALD Conformality Studies

§  Increase diffusion time of the ALD vapor

§  For aspect ratio of 1000 –  1 torr: 100 seconds –  0.2 torr: 500 seconds –  Larger than ALD pumpdown

time; –  ALD time can start becoming

larger;

§  For aspect ratio of 10: –  Micro to milli seconds; –  Very small fraction of ALD

pumpdown time; –  no affect on ALD process time;

1

100

10000 10 100 1000

10

0.001

0.1

0.01

0.0001

Aspect Ratio

Torr

X

s

econ

ds

Based on modeling by: Gordon, Haussman and Kim (Harvard); Shephard (IBM)


Slide 23

Conformality Studies using EDS EDS Scan at the bo7om of 200 um thick electrode

0 20 40 60 80 1006

7

8

9

10

11

12

Ato

mic

Wei

ght %

Electrode Thickness (depth) (µm)

Al O

ALD conformality as a function of electrode depth


Slide 24

Cross-section of sintered bottom electrode showing ALD alumina layer

105 nm

§  700 cycles of ALD alumina (~ 100 nm)

§  FESEM showed 105 nm thick Alumina film on copper particle necks

Conformal Dielectric on Porous Electrodes


Slide 25

Key Challenge: To access the high surface area by using a conformal top electrode Approach : Use of a liquid conducting polymer– polyethylene dioxythiophene (PEDT) Polymerization: EDT+ oxidizer+ inhibitor – 1:25 (in-situ)

§  Conductivity ~ 100 S/cm §  Fluid nature with low viscosity for

easy infiltration of particulate electrode

§  Low temperature processability ( 50o C)

§  Self-healing characteristics

Conformal Top Electrode


Slide 26

Demonstration of Nanoelectrode Capacitors

Device Thickness Area

Enhancement

Capacitance

Density

Planar (0.6mm x 0.6mm) -- 0.12µF/cm2

<5 µm 10X 1.1 µF/cm2

10 µm 25 X 3.9 µF/cm2

25 µm 150-200X 30 µF/cm2

>75 µm 400-500X 55-60 µF/cm2


Slide 27

Particulate electrodes using PEDT show very high leakage as compared to planar capacitors. Two possible reasons identified: (I) PEDT/ Al2O3 interaction (II)  Inherent Defects in Al2O3 film

Nanoelectrode Capacitors : Leakage Current

1.00E-‐09

1.00E-‐08

1.00E-‐07

1.00E-‐06

1.00E-‐05

1.00E-‐04

1.00E-‐03

1.00E-‐02

1.00E-‐01

1.00E+00

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Leakage Cu

rren

t (A/

uF)

Voltage (V)

I-‐V plot of planar and par9culate electrode capacitor

Par3culate Capacitor with PEDT

Planar Capacitor with PEDT

Planar Capacitor with Au


Slide 28

GT PRC: HDCAP Vs State-of-the-Art

28

Permittivity X Electrode Area Enhancement

Capacitance Volum

etric D

ensity µF/cm

2

1

100

100 1,000

Si Trench

PRC’s Si and Glass IPD

10

10,000

Thin Film Capacitors

Conformal dielectric on a nanoporous electrode


Slide 29

Conclusions

Slide 29

•  3D IPAC shown as a compelling new technology for active and passive component integration in ultrathin functional modules

•  Better miniaturization •  Lower cost •  Higher performance

•  Novel silicon or glass-compatible high-density capacitor technologies investigated to meet 3D IPAC goals

Documents

Integration of Power-Supply Capacitors with Ultrahigh ...pwrsocevents.com/wp-content/uploads/2012-presentations/session-4/4... · on Silicon Using Particulate Electrodes POWERSOC