Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory

Clocks

Data

FEDv1 Final Firmware Subtasks

SerialComms

VMELINK

VMEBus

VMESystemSystemACEACE

SystemACE

Clocks

EPROMEPROM

EPROM

TTCrxQDR Write

QDRs

QDR Read

SerialComms

Headers

TTCchanA

VME LinkRegs

S-LINKS-LINK S-LINK

Clocks

Data

SerialComms

ScopeMode

HeaderMode

FIFOs

Input

Regs

SerialComms

ScopeMode

HeaderMode

Output

Input

Regs

Opto Rx DACOpto Rx DAC

DELAY FPGA x 3 x 8

FE FPGA x 8

BE FPGA

VME FPGA

ADCADC

Under Simulation

Under Test on FED

FEDv2FEDv2 Controls

Data Readout

Control

Throttle TCSInput

ClusterClusterModeMode

EdEd

SaeedSaeed

IvanIvan

EdEd

Ed, JohnEd, John

Saeed, IvanSaeed, Ivan

Chan BChan B

I2C

Temp

“Working” on FED

External Devices

TempTemp

15th May 2003

To be Implemented

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory

Clocks

Data

FEDv1 Final Firmware Subtasks

SerialComms

VMELINK

VMEBus

VMESystemSystemACEACE

SystemACE

Clocks

EPROMEPROM

EPROM

TTCrxQDR Write

QDRs

QDR Read

SerialComms

Headers

TTCchanA

VME LinkRegs

S-LINKS-LINK S-LINK

Clocks

Data

SerialComms

ScopeMode

HeaderMode

FIFOs

Input

Regs

SerialComms

ScopeMode

HeaderMode

Output

Input

Regs

Opto Rx DACOpto Rx DAC

DELAY FPGA x 3 x 8

FE FPGA x 8

BE FPGA

VME FPGA

ADCADC

Under Simulation

Under Test on FED

FEDv2FEDv2 Controls

Data Readout

Control

Throttle TCSInput

ClusterClusterModeMode

EdEd

SaeedSaeed

IvanIvan

EdEd

Ed, JohnEd, John

Saeed, IvanSaeed, Ivan

Chan BChan B

I2C

Temp

“Working” on FED

External Devices

TempTemp

11th June 2003

To be Implemented

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory

Clocks

Data

FEDv1 Final Firmware Subtasks

SerialComms

VMELINK

VMEBus

VMESystemSystemACEACE

SystemACE

Clocks

EPROMEPROM

EPROM

TTCrxQDR Write

QDRs

QDR Read

SerialComms

Headers

TTCchanA

VME LinkRegs

S-LINKS-LINK S-LINK

Clocks

Data

SerialComms

ScopeMode

HeaderMode

FIFOs

Input

Regs

SerialComms

ScopeMode

HeaderMode

Output

Input

Regs

Opto Rx DACOpto Rx DAC

DELAY FPGA x 3 x 8

FE FPGA x 8

BE FPGA

VME FPGA

ADCADC

Under Simulation

Under Test on FED

FEDv2FEDv2 Controls

Data Readout

Control

Throttle TCSInput

ClusterClusterModeMode

EdEd

SaeedSaeed

IvanIvan

EdEd

Ed, JohnEd, John

Saeed, IvanSaeed, Ivan

Chan BChan B

I2C

Temp

“Working” on FED

External Devices

TempTemp

26th June 2003

To be Implemented

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory

Clocks

Data

FEDv1 Final Firmware Subtasks

SerialComms

VMELINK

VMEBus

VMESystemSystemACEACE

SystemACE

Clocks

EPROMEPROM

EPROM

TTCrxQDR Write

QDRs

QDR Read

SerialComms

Headers

TTCchanA

VME LinkRegs

S-LINKS-LINK S-LINK

Clocks

Data

SerialComms

ScopeMode

HeaderMode

FIFOs

Input

Regs

SerialComms

ScopeMode

HeaderMode

Output

Input

Regs

Opto Rx DACOpto Rx DAC

DELAY FPGA x 3 x 8

FE FPGA x 8

BE FPGA

VME FPGA

ADCADC

Under Simulation

Under Test on FED

FEDv2FEDv2 Controls

Data Readout

Control

Throttle TCSInput

ClusterClusterModeMode

EdEd

SaeedSaeed

IvanIvan

EdEd

Ed, JohnEd, John

Saeed, IvanSaeed, Ivan

Chan BChan B

I2C

Temp

“Working” on FED

External Devices

TempTemp

23rd July 2003

To be Implemented

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory

Clocks

Data

FEDv1 Final Firmware Subtasks

SerialComms

VMELINK

VMEBus

VMESystemSystemACEACE

SystemACE

Clocks

EPROMEPROM

EPROM

TTCrxQDR Write

QDRs

QDR Read

SerialComms

Headers

TTCchanA

VME LinkRegs

S-LINKS-LINK S-LINK

Clocks

Data

SerialComms

ScopeMode

HeaderMode

FIFOs

Input

Regs

SerialComms

ScopeMode

HeaderMode

Output

Input

Regs

Opto Rx DACOpto Rx DAC

DELAY FPGA x 3 x 8

FE FPGA x 8

BE FPGA

VME FPGA

ADCADC

Under Simulation

Under Test on FED

FEDv2FEDv2 Controls

Data Readout

Control

Throttle TCSInput

ClusterClusterModeMode

EdEd

SaeedSaeed

IvanIvan

EdEd

Ed, JohnEd, John

Saeed, IvanSaeed, Ivan

Chan BChan B

I2C

Temp

“Working” on FED

External Devices

TempTemp

22nd August 2003

To be Implemented

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory

Clocks

Data

FEDv1 Final Firmware Subtasks

SerialComms

VMELINK

VMEBus

VMESystemACE

SystemACE

EPROM

EPROM

TTCrxQDR Write

QDRs

QDR Read

SerialComms

Headers

TTCchanA

VME LinkRegs

S-LINK S-LINK

Clocks

DataSerialComms

ScopeMode

HeaderMode

FIFOs

Input

Regs

SerialComms

ScopeMode

HeaderMode

Output

Input

Regs

Opto Rx DACOpto Rx DAC

DELAY FPGA x 3 x 8

FE FPGA x 8

BE FPGA

VME FPGA

ADCADC

Under Simulation

Under Test on FED

Controls

Data Readout

Control

Throttle TCSInput

ClusterMode

Ed->SaeedEd->Saeed

SaeedSaeed

SaeedSaeed

Ed->SaeedEd->Saeed

Ed, JohnEd, John

Saeed, IvanSaeed, Ivan

Chan B

I2C

“Working” on FED

External Devices

TempTemp

4th November 2003

To be Implemented

Spy

Clocks

FEDv2