Instruction Sets Characteristics

7/24/2019 Instruction Sets Characteristics

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William Stallings

Computer Organization

and Architecture

8thEdition

Chapter 10

Instruction Sets:

Characteristics and Functions


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What is an Instruction Set?

The complete collection of instructionsthat are understood by a CPU

Machine Code

Binary

Usually represented by assembly codes


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Elements o an Instruction

Operation code (Op code)

Do this

ource Operand reference

To this

!esult Operand referencePut the ans"er here

#e$t %nstruction !eference

&hen you ha'e done that do this


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Where ha!e all the Operands "one?

*on+ time passin+,

(%f you don-t understand you-re tooyoun+.)

Main memory (or 'irtual memory or

cache) CPU re+ister

%/O de'ice


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Instruction C#cle State $iagram


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Instruction %epresentation

%n machine code each instruction has auni0ue bit pattern

1or human consumption ("ellpro+rammers any"ay) a symbolic

representation is usede+ 2DD UB *O2D

Operands can also be represented in this"ay

2DD 2B


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Simple Instruction Format


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Instruction pes

Data processin+

Data stora+e (main memory)

Data mo'ement (%/O)

Pro+ram flo" control


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'um(er o Addresses )a*

3 addresses

Operand 4 Operand 5 !esult

a 6 b 7 c8

May be a forth 9 ne$t instruction (usually

implicit)#ot common

#eeds 'ery lon+ "ords to hold e'erythin+


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'um(er o Addresses )(*

5 addresses

One address doubles as operand and result

a 6 a 7 b

!educes len+th of instruction

!e0uires some e$tra "or:; Temporary stora+e to hold some results


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'um(er o Addresses )c*

4 address

%mplicit second address

Usually a re+ister (accumulator)

Common on early machines


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'um(er o Addresses )d*

< (=ero) addresses

2ll addresses implicit

Uses a stac:

e+ push a

push b add

pop c

c 6 a 7 b


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+o, -an# Addresses

More addresses

More comple$ (po"erful>) instructions

More re+isters

; %nter9re+ister operations are 0uic:er

1e"er instructions per pro+ram 1e"er addresses

*ess comple$ (po"erful>) instructions

More instructions per pro+ram

1aster fetch/e$ecution of instructions


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$esign $ecisions )1*

Operation repertoire

?o" many ops>

&hat can they do>

?o" comple$ are they>

Data types %nstruction formats

*en+th of op code field

#umber of addresses


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$esign $ecisions ).*

!e+isters

#umber of CPU re+isters a'ailable

&hich operations can be performed on "hichre+isters>

2ddressin+ modes (later,)

!%C ' C%C


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pes o Operand

2ddresses

#umbers

%nte+er/floatin+ point

Characters

2C%% etc

*o+ical Data

Bits or fla+s

(2side@ %s there any difference bet"een numbers andcharacters> 2s: a C pro+rammer.)


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/8 $ata pes

A bit Byte

4 bit "ord

35 bit double "ord

bit 0uad "ord

45A bit double 0uad"ord 2ddressin+ is by A bit unit

&ords do not need to ali+n at e'en9numbered address

Data accessed across 35 bit bus in units ofdouble "ord read at addresses di'isible by

*ittle endian


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S-I$ $ata pes

%nte+er types

%nterpreted as bit field or inte+er

Pac:ed byte and pac:ed byte inte+er Bytes pac:ed into 9bit 0uad"ord or 45A9bit double

0uad"ord

Pac:ed "ord and pac:ed "ord inte+er

49bit "ords pac:ed into 9bit 0uad"ord or 45A9bit double0uad"ord

Pac:ed double"ord and pac:ed double"ord inte+er 359bit double"ords pac:ed into 9bit 0uad"ord or 45A9bit

double 0uad"ord

Pac:ed 0uad"ord and pac:ed 0aud"ord inte+er

T"o 9bit 0uad"ords pac:ed into 45A9bit double 0uad"ord

Pac:ed sin+le9precision floatin+9point and pac:ed double9precision floatin+9point 1our 359bit floatin+9point or t"o 9bit floatin+9point 'alues

pac:ed into a 45A9bit double 0uad"ord


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/8 'umeric $ata Formats


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A%- $ata pes

A (byte) 4 (half"ord) 35 ("ord) bits

?alf"ord and "ord accesses should be "ord ali+ned #onali+ned access alternati'es Default

; Treated as truncated; Bits4@


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A%- Endian Support

G9bit in system control re+ister

Under pro+ram control


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pes o Operation

Data Transfer

2rithmetic

*o+ical

Con'ersion

%/O

ystem Control

Transfer of Control


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$ata &ranser

pecify

ource

Destination

2mount of data

May be different instructions for differentmo'ements

e+ %BM 3H


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3#te Order 'ames

The problem is called Gndian

The system on the left has the leastsi+nificant byte in the lo"est address

This is called bi+9endian

The system on the ri+ht has the leastsi+nificant byte in the hi+hest address

This is called little9endian


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E/ample o C $ata Structure


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Alternati!e ie, o -emor# -ap


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Standard9What Standard?

Pentium ($A) J2K are little9endian

%BM 3H

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Instruction Sets Characteristics