INSTRUCTION PROGRAMMING & INTERRUPTS

8085INSTRUCTION

PROGRAMMING& INTERRUPTS

FOR UGC NET, GATE & PHD ENTRANCE

I am Priyanka Chatterjee.

Website: unifystudy.com

Email: [email protected]

TELEGRAM channel name :

Unifystudy-NET JRF Paper1

Unifystudy- Computer Science

UGC NET Qualified with 99.46 Percentile. (Dec 2019)

5 years Industry Experience.

MCA (2008 – 2011 )

BSc. Honors in Computer Science (2004 - 2007)

mailto:[email protected]

8085 Architecture

Microprocessor - 8085 Architecture

It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology.

It has the following configuration −

•8-bit data bus

•16-bit address bus, which can address upto 64KB

•A 16-bit program counter

•A 16-bit stack pointer

•Six 8-bit registers arranged in pairs: BC, DE, HL

•Requires +5V supply to operate at 3.2 MHZ single phase clock

It is used in washing machines, microwave ovens, mobile phones, etc.

8085 Microprocessor – Functional Units

8085 consists of the following functional units −

Accumulator

It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE

operations. It is connected to internal data bus & ALU.

Arithmetic and logic unit

As the name suggests, it performs arithmetic and logical operations like Addition,

Subtraction, AND, OR, etc. on 8-bit data.

General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each

register can hold 8-bit data.

These registers can work in pair to hold 16-bit data and their pairing combination is

like B-C, D-E & H-L.

Program counter

It is a 16-bit register used to store the memory address location of the next

instruction to be executed. Microprocessor increments the program whenever an

instruction is being executed, so that the program counter points to the memory

address of the next instruction that is going to be executed.

Stack pointer

It is also a 16-bit register works like stack, which is always incremented/decremented

by 2 during push & pop operations.

Temporary register

It is an 8-bit register, which holds the temporary data of arithmetic and logical

operations.

Flag register

It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending

upon the result stored in the accumulator.

These are the set of 5 flip-flops −

•Sign (S)

•Zero (Z)

•Auxiliary Carry (AC)

•Parity (P)

•Carry (C)

Its bit position is shown in the following table −

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in

the Instruction register. Instruction decoder decodes the information present in the

Instruction register.

Timing and control unit

It provides timing and control signal to the microprocessor to perform operations.

Following are the timing and control signals, which control external and internal

circuits −

•Control Signals: READY, RD’, WR’, ALE

•Status Signals: S0, S1, IO/M’

•DMA Signals: HOLD, HLDA

•RESET Signals: RESET IN, RESET OUT

Interrupt control

As the name suggests it controls the interrupts during a process. When a

microprocessor is executing a main program and whenever an interrupt occurs, the

microprocessor shifts the control from the main program to process the incoming

request. After the request is completed, the control goes back to the main program.

There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,

TRAP.

Serial Input/output control

It controls the serial data communication by using these two instructions: SID (Serial

input data) and SOD (Serial output data).

Address buffer and address-data buffer

The content stored in the stack pointer and program counter is loaded into the

address buffer and address-data buffer to communicate with the CPU. The memory

and I/O chips are connected to these buses; the CPU can exchange the desired data

with the memory and I/O chips.

Address bus and data bus

Data bus carries the data to be stored. It is bidirectional, whereas address bus

carries the location to where it should be stored and it is unidirectional. It is used to

transfer the data & Address I/O devices.

8085 Instruction sets are instruction codes to perform some task. It is classified into 5

categories.

S.No. Instruction & Description

1Control Instructions Following is the table showing the list of Control instructions with

their meanings.

2Logical Instructions Following is the table showing the list of Logical instructions with

their meanings.

3Branching Instructions Following is the table showing the list of Branching instructions

with their meanings.

4Arithmetic Instructions Following is the table showing the list of Arithmetic instructions

with their meanings.

5Data Transfer Instructions Following is the table showing the list of Data-transfer

instructions with their meanings.

8085 Arithmetic Instructions

Opcode Operand Meaning Explanation

ADDR

M

Add register or

memory, to the

accumulator

The contents of the register or memory are added

to the contents of the accumulator and the result is

stored in the accumulator.

Example −ADD K.

ADCR

M

Add register to the

accumulator with

carry

The contents of the register or memory & M the

Carry flag are added to the contents of the

accumulator and the result is stored in the

accumulator.

Example −ADC K

ADI 8-bit dataAdd the immediate to

the accumulator

The 8-bit data is added to the contents of the

accumulator and the result is stored in the

accumulator.

Example −ADI 55K

ACI 8-bit data

Add the immediate to

the accumulator with

carry

The 8-bit data and the Carry flag are added to the

contents of the accumulator and the result is stored

in the accumulator.

Example −ACI 55K

LXIReg. pair,

16bit data

Load the register pair

immediate

The instruction stores 16-bit data into the

register pair designated in the operand.

Example − LXI K, 3025M

DAD Reg. pairAdd the register pair to H

and L registers

The 16-bit data of the specified register pair

are added to the contents of the HL register.

Example − DAD K

SUBR

M

Subtract the register or the

memory from the

accumulator

The contents of the register or the memory

are subtracted from the contents of the

accumulator, and the result is stored in the

accumulator.

Example − SUB K

SBBR

M

Subtract the source and

borrow from the

accumulator

The contents of the register or the memory &

M the Borrow flag are subtracted from the

contents of the accumulator and the result is

placed in the accumulator.

Example − SBB K

SUI 8-bit dataSubtract the immediate

from the accumulator

The 8-bit data is subtracted from the contents of

the accumulator & the result is stored in the

accumulator.

Example − SUI 55K

SBI 8-bit data

Subtract the immediate

from the accumulator with

borrow

The contents of register H are exchanged with the

contents of register D, and the contents of register

L are exchanged with the contents of register E.

Example − XCHG

INRR

M

Increment the register or

the memory by 1

The contents of the designated register or the

memory are incremented by 1 and their result is

stored at the same place.

Example − INR K

INX RIncrement register pair by

1

The contents of the designated register pair are

incremented by 1 and their result is stored at the

same place.

Example − INX K

DCRR

M

Decrement the

register or the

memory by 1

The contents of the designated register or memory are

decremented by 1 and their result is stored at the same

place.

Example − DCR K

DCX RDecrement the

register pair by 1

The contents of the designated register pair are

decremented by 1 and their result is stored at the same

place.

Example − DCX K

DAA NoneDecimal adjust

accumulator

The contents of the accumulator are changed from a

binary value to two 4-bit BCD digits.

If the value of the low-order 4-bits in the accumulator is

greater than 9 or if AC flag is set, the instruction adds 6

to the low-order four bits.

If the value of the high-order 4-bits in the accumulator is

greater than 9 or if the Carry flag is set, the instruction

adds 6 to the high-order four bits.

Example − DAA

8085 Data-transfer Instructions

list of Data-transfer instructions with their meanings.


MOV

Rd, Sc

M, Sc

Dt, M

Copy from the source

(Sc) to the

destination(Dt)

This instruction copies the contents of the

source register into the destination register

without any alteration.

Example − MOV K, L

MVIRd, data

M, dataMove immediate 8-bit

The 8-bit data is stored in the destination

register or memory.

Example − MVI K, 55L

LDA 16-bit address Load the accumulator

The contents of a memory location,

specified by a 16-bit address in the operand,

are copied to the accumulator.

Example − LDA 2034K

LDAX B/D Reg. pairLoad the accumulator

indirect

The contents of the designated register pair point

to a memory location. This instruction copies the

contents of that memory location into the

accumulator.

Example − LDAX K

LXIReg. pair, 16-

bit data

Load the register pair

immediate

The instruction loads 16-bit data in the register pair

designated in the register or the memory.

Example − LXI K, 3225L

LHLD16-bit

address

Load H and L registers

direct

The instruction copies the contents of the memory

location pointed out by the address into register L

and copies the contents of the next memory

location into register H.

Example − LHLD 3225K

STA16-bit

address16-bit address

The contents of the accumulator are copied into the

memory location specified by the operand.

This is a 3-byte instruction, the second byte specifies

the low-order address and the third byte specifies the

high-order address.

Example − STA 325K

STAX16-bit

address

Store the

accumulator

indirect


memory location specified by the contents of the

operand.

Example − STAX K

SHLD16-bit

addressStore H and L

registers direct

The contents of register L are stored in the memory

location specified by the 16-bit address in the operand

and the contents of H register are stored into the

next memory location by incrementing the operand.

This is a 3-byte instruction, the second byte specifies

the low-order address and the third byte specifies the

high-order address.

Example − SHLD 3225K

XCHG NoneExchange H and L with

D and E

The contents of register H are exchanged with

the contents of register D, and the contents of

register L are exchanged with the contents of

register E.

Example − XCHG

SPHL NoneCopy H and L registers

to the stack pointer

The instruction loads the contents of the H and L

registers into the stack pointer register. The

contents of the H register provide the high-order

address and the contents of the L register

provide the low-order address.

Example − SPHL

XTHL NoneExchange H and L with

top of stack

The contents of the L register are exchanged

with the stack location pointed out by the

contents of the stack pointer register.

The contents of the H register are exchanged

with the next stack location (SP+1).

Example − XTHL

PUSH Reg. pair

Push the

register pair

onto the

stack

The contents of the register pair designated in the operand are

copied onto the stack in the following sequence.

The stack pointer register is decremented and the contents of the

high order register (B, D, H, A) are copied into that location.

The stack pointer register is decremented again and the contents

of the low-order register (C, E, L, flags) are copied to that

location.

Example − PUSH K

POP Reg. pair

Pop off stack

to the

register pair

The contents of the memory location pointed out by the stack

pointer register are copied to the low-order register (C, E, L,

status flags) of the operand.

The stack pointer is incremented by 1 and the contents of that

memory location are copied to the high-order register (B, D, H, A)

of the operand.

The stack pointer register is again incremented by 1.

Example − POPK

OUT8-bit port

address

Output the data from

the accumulator to a

port with 8bit address


I/O port specified by the operand.

Example − OUT K9L

IN8-bit port

address

Input data to

accumulator from a port

with 8-bit address

The contents of the input port designated in the

operand are read and loaded into the accumulator.

Example − IN5KL

Logical instructions with their meanings


CMPR

M

Compare the register or

memory with the

accumulator

The contents of the operand (register or

memory) are M compared with the contents of

the accumulator.

CPI 8-bit dataCompare immediate with

the accumulator

The second byte data is compared with the

contents of the accumulator.

ANAR

M

Logical AND register or

memory with the

accumulator

The contents of the accumulator are logically

AND with M the contents of the register or

memory, and the result is placed in the

accumulator.

ANI 8-bit dataLogical AND immediate

with the accumulator

The contents of the accumulator are logically

AND with the 8-bit data and the result is


XRAR

M

Exclusive OR register or

memory with the

accumulator

The contents of the accumulator are Exclusive

OR with M the contents of the register or

memory, and the result is placed in the

accumulator.

XRI 8-bit data

Exclusive OR

immediate with the

accumulator

The contents of the accumulator are Exclusive OR

with the 8-bit data and the result is placed in the

accumulator.

ORAR

M

Logical OR register

or memory with

the accumulator

The contents of the accumulator are logically OR with

M the contents of the register or memory, and result is


ORI 8-bit data

Logical OR

immediate with the

accumulator

The contents of the accumulator are logically OR with

the 8-bit data and the result is placed in the

accumulator.

RLC NoneRotate the

accumulator left

Each binary bit of the accumulator is rotated left by

one position. Bit D7 is placed in the position of D0 as

well as in the Carry flag. CY is modified according to

bit D7.

RRC NoneRotate the

accumulator right

Each binary bit of the accumulator is rotated right by

one position. Bit D0 is placed in the position of D7 as

well as in the Carry flag. CY is modified according to

bit D0.

RAL None

Rotate the

accumulator left

through carry

Each binary bit of the accumulator is rotated left by one

position through the Carry flag. Bit D7 is placed in the

Carry flag, and the Carry flag is placed in the least

significant position D0. CY is modified according to bit

D7.

RAR None

Rotate the

accumulator

right through

carry

Each binary bit of the accumulator is rotated right by

one position through the Carry flag. Bit D0 is placed in

the Carry flag, and the Carry flag is placed in the most

significant position D7. CY is modified according to bit

D0.

CMA NoneComplement

accumulator

The contents of the accumulator are complemented. No

flags are affected.

CMC NoneComplement

carry

The Carry flag is complemented. No other flags are

affected.

STC None Set Carry Set Carry

list of Control instructions


NOP None No operationNo operation is performed, i.e., the instruction

is fetched and decoded.

HLT NoneHalt and enter wait

state

The CPU finishes executing the current

instruction and stops further execution. An

interrupt or reset is necessary to exit from the

halt state.

DI None Disable interruptsThe interrupt enable flip-flop is reset and all the

interrupts are disabled except TRAP.

EI None Enable interruptsThe interrupt enable flip-flop is set and all the

interrupts are enabled.

RIM None Read interrupt mask

This instruction is used to read the status of

interrupts 7.5, 6.5, 5.5 and read serial data input

bit.

SIM None Set interrupt maskThis instruction is used to implement the

interrupts 7.5, 6.5, 5.5, and serial data output.

8085PROGRAMMINGUGC NET PYQS

FOR UGC NET, GATE & PHD ENTRANCE

I am Priyanka Chatterjee.

Website: unifystudy.com

Email: [email protected]

TELEGRAM channel name :

Unifystudy-NET JRF Paper1

Unifystudy- Computer Science

UGC NET Qualified with 99.46 Percentile. (Dec 2019)

5 years Industry Experience.

MCA (2008 – 2011 )

BSc. Honors in Computer Science (2004 - 2007)

mailto:[email protected]

What will be the output at PORT1 if the following program is executed?

1.MVI B, 82H

2.MOV A, B

3.MOV C, A

4.MVI D, 37H

5.OUT PORT1

6.HLT

A. 37H

B. 82H

C. B9H

D. 00H

UGC NET Dec 2015

•MVI B, 82H // Copy value 82H to register B

•MOV A, B // Copy value of B (82H) to accumulator A

•MOV C, A // Copy value of A (82H) to register C

•MVI D, 37H // Copy value 37H to register D

•OUT PORT1 //Copy value of A(82H) to PORT 1

So output will be 82 H

Answer B

A. 37H

B. 82H

C. B9H

D. 00H

UGC NET Dec 2015

8085 microprocessor, what is the output of following program ?

LDA 8000H

MVI B, 30H

ADD B

STA 8001H

(1) Read a number from input port and store it in memory

(2) Read a number from input device with address 8000H and store it in memory at location

8001H

(3) Read a number from memory at location 8000H and store it in memory location 8001H

(4) Load A with data from input device with address 8000H and display it on the output

device with address 8001H

NET June 2018

8085 microprocessor, what is the output of following program ?

LDA 8000H

MVI B, 30H

ADD B

STA 8001H

(1) Read a number from input port and store it in memory

(2) Read a number from input device with address 8000H and store it in memory at location

8001H

(3) Read a number from memory at location 8000H and store it in memory location 8001H

(4) Load A with data from input device with address 8000H and display it on the output

device with address 8001H

NET June 2018

Sign Flag (S) –After any operation if the MSB (B(7)) of the result is 1, it indicates

the number is negative and the sign flag becomes set, i.e. 1. If the MSB is 0, it

indicates the number is positive and the sign flag becomes reset i.e. 0.

from 00H to 7F -> (0-127), sign flag is 0

from 80H to FF ->(128 - 255), sign flag is 1 1- MSB is 1 (negative)

0- MSB is 0 (positive)

Example:

MVI A 30 (load 30H in register A)

MVI B 40 (load 40H in register B)

SUB B (A = A – B)

These set of instructions will set the sign flag to 1 as 30 – 40 is a negative number.



SUB B (A = A – B)

These set of instructions will reset the sign flag to 0 as 40 – 30 is a positive

number.

Zero Flag (Z) –After any arithmetical or logical operation if the result is 0 (00)H,

the zero flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.

00H zero flag is 1.

from 01H to FFH zero flag is 0 1- zero result

0- non-zero result

Example:


SUB A (A = A – A)

These set of instructions will set the zero flag

to 1 as 10H – 10H is 00H

Auxiliary Carry Flag (AC) –This flag is used in BCD number system(0-9). If

after any arithmetic or logical operation D(3) generates any carry and passes on

to B(4) this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0. This is the

only flag register which is not accessible by the programmer 1-carry out from bit

3 on addition or borrow into bit 3 on subtraction

0-otherwise

Example:

MOV A 2B (load 2BH in register A)

MOV B 39 (load 39H in register B)

ADD B (A = A + B)

These set of instructions will set the auxiliary carry flag to 1, as on adding 2B and

39, addition of lower order nibbles B and 9 will generate a carry.

•Parity Flag (P) – If after any arithmetic or logical operation the result has even

parity, an even number of 1 bits, the parity register becomes set i.e. 1, otherwise it

becomes reset i.e. 0.

1-accumulator has even number of 1 bits

0-accumulator has odd parity

Example:


This instruction will set the parity flag to 1 as the BCD code of 05H is 00000101,

which contains even number of ones i.e. 2.

•Carry Flag (CY) – Carry is generated when performing n bit operations and the result is more than

n bits, then this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.

During subtraction (A-B), if A>B it becomes reset and if (A<B) it becomes set.

Carry flag is also called borrow flag.

1-carry out from MSB bit on addition or borrow into MSB bit on subtraction

0-no carry out or borrow into MSB bit

Example:



SUB B (A = A – B)

These set of instructions will set the carry flag to 1 as 30 – 40 generates a carry/borrow.



SUB B (A = A – B)

These set of instructions will reset the sign flag to 0 as 40 – 30 does not generate any carry/borrow.

Carry flag (Cy): after performing the addition of any two 8-bit numbers, the carry generated can be either 0

or 1. That is only 1-bit. Thus to store the carry information 1-bit storage is enough. The Cy flag is stored in the

LS bit position in the flags register. Instructions that use the Cy flag are widely used in the user programs.

Auxiliary carry flag (Ac): Now let us consider the addition of any two 8-bit (2-hex digit) numbers, a carry

may be generated when we add the LS hex digits of the two numbers. Such a carry is called intermediate

carry also known as half carry, or auxiliary carry (AC). Intel prefers to call it AC.

Sign flag (S): The S flag is set to 1, when the result thus produced against any logical or arithmetic operations

is negative, indicated by MS bit of 8-bit result being 1. It is reset to 0 otherwise if the result is positive, indicated

by MS bit of 8-bit result being 0.

Parity flag (P): The P flag is set to 1, if the 8-bit result thus produced against any logical and arithmetic

operation has an even number of 1's in it. If there are odd number of 1's in the 8-bit result, the P flag is reset to

0.

Zero flag (Z): The Z flag is set to 1, if after arithmetic and logical operations, the 8-bit result thus produced, is

00H. If the 8-bit result is not equal to 00H, the Z flag is reset to 0. Thus the Z flag is hoisted to indicate that the

result is 0.

DAA instruction in 8085 Microprocessor

Let us consider we want to add two decimal numbers 38 and 45. They will be represented in BCD as 0011 1000

and 0100 0101. The addition results in 0111 1101. But the answer will be incorrect if we want to interpret this

result as a BCD number. The result will be not only incorrect but also illegal as 1101, which we obtained as the

last nibble in the answer is not a valid BCD number. Here, in such situations, we can use DAA to have the BCD

sum as outcome. All that is required to be done is to add the BCD numbers and store the result in A, and then

execute the DAA instruction.

38 ---> 0011 1000

+ 45 ---> 0100 0101

---- ---------

83 0111 1101

---- ----

7 D

The working of DAA instruction depends on the contents of the AL register, Cy, and AC flags. In effect, it adds

00H, 06H, 60H, or 66H to Accumulator so as to get the correct BCD answer in the Accumulator. So here is

the illustration of the remedial actions against the previous example −

38 ---> 0011 1000

+ 45 ---> 0100 0101

---- --------- 1(carry)

83 0111 1101 0111 1101

-- -- ---- + 0110 (06H)

7 D ---------

1000 0011 ---> 83 (Decimal sum)

•If the LS hex digit in A is <= 9 and AC flag is 0, the LS hex digit value will not be altered.

•If the LS hex digit is >9, or if AC flag is set to 1, it adds 6 to the LS hex digit of A. If carry results, then it

increments the MS hex digit if this addition resulted in a carry to the MS digit position. In this process,

the Cy flag will be set to 1 if the MS hex digit was incremented from F to 0.

•If the MS hex digit is <= 9 and Cy flag is 0, the MS hex digit will not be altered, and Cy flag is reset to

0.

•If the MS hex digit is > 9, or if Cy flag is set to 1, it adds 6 to the MS hex digit of A and sets Cy flag to

1.

Note that for decimal subtraction DAA instruction cannot be used. Due to unavailability of decimal

subtraction in Intel 8085 instruction set, a series of instructions are to be executed to perform decimal

subtraction.

MVI A, 38H

MVI B, 45H

ADD B

DAA

A ← 38H

B ← 45H

A ←A + B; A <- 38H + 45H; A ← 7DH

A ← 83H (Decimal Sum), S = 1,Z = 0,Ac = 1,P = 0,Cy = 0 06H

got added with the Accumulator content. As Cy=0, so

interpreted result is 83 in decimal

Match the following:

List - I List - II

(a)XCHG (i)only carry flag is affected.

(b)SUB (ii) no flags are affected.

(c)STC (iii) all flags other than carry flag are affected.

(d)DCR (iv)all flags are affected.

(a) (b) (c) (d)

(1) (iv) (i) (iii) (ii)

(B) (iii) (ii) (i) (iv)

(C) (ii) (iii) (i) (iv)

(D) (ii) (iv) (i) (iii)

codes:

UGC NET June 2014

XCHG, which stands for eXCHanGe. This is an instruction to exchange contents of HL register pair with

DE register pair. This instruction uses implied addressing mode. As it is1-Byte instruction, so It occupies only

1-Byte in the memory. After execution of this instruction, the content between H and D registers and L and E

registers will get swapped respectively.

SUB is a mnemonic that stands for ‘SUBtract contents of R from Accumulator. Here R stands for any of the

following registers, or memory location M pointed by HL pair.

Here all flags are affteced depending on result . Cy=1 indicates that result is negative.

STC stands for “SeT the Carry flag”. It sets the cy flag to the 1 state, immaterial of its earlier value. It

performs set operation on the cy flag, and the result is stored back in the cy flag.

DCR is a mnemonic, which stands for ‘DeCRement’ and ‘R’ stands for any of the following registers, or

memory location M pointed by HL pair.

This instruction is used to decrease the content of register R. Also we can say it will subtract 1 from the

register R content. And the decremented value will be stored on to the register R itself. As it is an

arithmetic instruction, so all flags, except Cy flag, are affected depending on the result

Match the following:

List - I List - II

(a)XCHG (i)only carry flag is affected.

(b)SUB (ii) no flags are affected.

(c)STC (iii) all flags other than carry flag are affected.

(d)DCR (iv)all flags are affected.

(a) (b) (c) (d)

(1) (iv) (i) (iii) (ii)

(B) (iii) (ii) (i) (iv)

(C) (ii) (iii) (i) (iv)

(D) (ii) (iv) (i) (iii)

codes:

UGC NET June 2014

Specify the contents of the accumulator and the status of the S, Z and

CY flags when 8085 microprocessor performs addition of 87 H and

79 H.

A. 11, 1, 1, 1

B. 10, 0, 1, 0

C. 1, 1, 0, 0

D. 00, 0, 1, 1

UGC NET CS Dec 2014

Addition of 87H and 79H.

87 H -> 135 -> 1 0 0 0 0 1 1 1

79 H ->121 -> 0 1 1 1 1 0 0 1

1 0 0 0 0 0 0 0 0

S - sign flag - Since MSB of result is 0, hence sign bit should be 0.

Z - Zero flag - Since result is zero, hence zero bit should be 1.

CY - Carry flag - Since there is a carry from MSB (8th to 9th bit),

hence CY = 1

Specify the contents of the accumulator and the status of the S, Z and

CY flags when 8085 microprocessor performs addition of 87 H and

79 H.

A. 11, 1, 1, 1

B. 10, 0, 1, 0

C. 1, 1, 0, 0

D. 00, 0, 1, 1

UGC NET CS Dec 2014

The contents of Register (BL) and Register (AL) of 8085

microprocessor are 49H and 3AH respectively. The contents of AL, the

status of carry flag (CF) and sign flag (SF) after executing 'SUB AL, BL'

assembly language instruction, are

A. AL=0FH; CF=1; SF=1

B. AL=F0H; CF=0; SF=0

C. AL=F1H; CF=1; SF=1

D. AL=1FH; CF=1; SF=1

UGC NET Dec 2016

(A) => 3AH => 0011 1010

(B) => 49H => 0100 1001

------------------

1111 0001

(A) => F1H

(CY) => 1

(S) => 1

The carry flag is set since the first operand is less than the second operand.

Since the result produces the negative result sign flag is set

Conditional and Unconditional JUMP instructions in 8085

Microprocessor

In 8085 Instruction set, there are a set of jump instructions, which can transfer program control to a

certain memory location. These jump instructions can be divided into two categories–

•Unconditional jump instructions and

•Conditional jump instructions

Under unconditional jump instructions there is only one mnemonic i.e. JUMP.

But under conditional Jump instructions we are having 8 different mnemonics.

We know that there are 5 flag bits in 8085 Flag register. They are S, Z,P, Cy, AC.

Out of them only on AC flag bit, there is no jump instruction.

But for rest 4 flag bits, we are having 8 conditional jump instructions depending upon their 1 or 0 i.e.

TRUE and FALSE values respectively.

Here is the list of all branching instructions in the following


JMP 16-bit address Jump

unconditionall

y

The program sequence is

transferred to the memory

address given in the

operand.

Opcode Description Flag Status

JC Jump on Carry CY=1

JNC Jump on no

Carry

CY=0

JP Jump on

positive

S=0

JM Jump on minus S=1

JZ Jump on zero Z=1

JNZ Jump on no

zero

Z=0

JPE Jump on parity

even

P=1

JPO Jump on parity

odd

P=0 16-bit address Jump

conditionally

The program sequence is

transferred to the memory

address given in the

operand based on the

specified flag of the PSW.

The content of the accumulator after the execution of the following 8085 assembly language program, is:

1.82 H

2.78 H

3.76 H

4.47 H

UGC NET 2016

A is taking accumulator...

A= 4 * 16 + 2 = 66 in decimal

B= 5 in decimal

Loop runs from B=5 to 1

So 66 + 5 +4 +3+2+1

That is 81 + 25H = 81 + 37 =118

In binary ..

01110110 = 76H

The content of the accumulator after the execution of the following 8085 assembly language program, is:

1.82 H

2.78 H

3.76 H

4.47 H

UGC NET 2016

How many times will the following loop be executed ?

LXI B, 0007 H

LOP : DCX B

MOV A, B

ORA C

JNZ LOP

A 05

B 07

C 09

D 00

UGC NET 2014

How many times will the following loop be executed ?

LXI B, 0007 H // Load immediate register pair BC with 0007 H

B= 00 , C =07

LOP : DCX B //decrement BC pair B=00 , C=06

MOV A, B //A (Acc) is 8 bit but B in BC pair 16 bit so only 00 will move to A

ORA C //A OR C =>00 OR 06 =>A=06

JNZ LOP // Jump if Not Zero =>required 7 iteration to get 00 in A

A 05

B 07

C 09

D 00

UGC NET 2014

UGC NET Dec 2019

A. A1B4

B. 81B4

C. A184

D. 8184

The set of instructions incorporated in16 bit IR register are:

1.Arithmetic, logical and shift instructions (and, add, complement, circulate left, right,

etc)

2.To move information to and from memory (store the accumulator, load the

accumulator)

3.Program control instructions with status conditions (branch, skip)

4.Input output instructions (input character, output character)

Symbol Hexadecimal Code Description

AND 0xxx 8xxxAnd memory word

to AC

ADD 1xxx 9xxxAdd memory word

to AC

LDA 2xxx AxxxLoad memory word

to AC

STA 3xxx BxxxStore AC content in

memory

BUN 4xxx CxxxBranch

Unconditionally

BSA 5xxx DxxxBranch and Save

Return Address

ISZ 6xxx ExxxIncrement and skip if

0

CLA 7800 Clear AC

CLE 7400 Clear E(overflow bit)

CMA 7200 Complement AC

CME 7100 Complement E

CIR 7080 Circulate right AC and E

CIL 7040 Circulate left AC and E

INC 7020 Increment AC

SPA 7010 Skip next instruction if AC > 0

SNA 7008 Skip next instruction if AC < 0

SZA 7004 Skip next instruction if AC = 0

SZE 7002 Skip next instruction if E = 0

HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC

SKI F200 Skip on input flag

SKO F100 Skip on output flag

ION F080 Interrupt On

IOF F040 Interrupt Off

UGC NET Dec 2019

CLA //Clear AC

BUN //Branch Unconditionally

C1A5 = 1100 0001 1010 0101

93C6 = 1001 0011 1100 0110

----------------------------------------

AND 1000 0001 1000 0100

8 1 8 4

A. A1B4

B. 81B4

C. A184

D. 8184

Interrupts in 8085 microprocessor

When microprocessor receives any interrupt signal from peripheral(s) which are

requesting its services, it stops its current execution and program control is

transferred to a sub-routine by generating CALL signal and after executing sub-

routine by generating RET signal again program control is transferred to main

program from where it had stopped.

When microprocessor receives interrupt signals, it sends an acknowledgement

(INTA) to the peripheral which is requesting for its service.

Interrupts can be classified into various categories based on different parameters:

1. Hardware and Software Interrupts –

When microprocessors receive interrupt signals through pins (hardware) of

microprocessor, they are known as Hardware Interrupts.

There are 5 Hardware Interrupts in 8085 microprocessor.

They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP

Software Interrupts are those which are inserted in between the program which

means these are mnemonics of microprocessor. There are 8 software interrupts in

8085 microprocessor.

They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.1

Vectored and Non-Vectored Interrupts –

Vectored Interrupts are those which have fixed vector address (starting address of

sub-routine) and after executing these, program control is transferred to that

address.

Vector Addresses are calculated by the formula 8 * TYPE

INTERRUPT VECTOR ADDRESS

TRAP (RST 4.5) 24 H

RST 5.5 2C H

RST 6.5 34 H

RST 7.5 3C H

For Software interrupts vector addresses are given by:


RST 0 00 H

RST 1 08 H

RST 2 10 H

RST 3 18 H

RST 4 20 H

RST 5 28 H

RST 6 30 H

RST 7 38 H

Non-Vectored Interrupts are those in which vector address is not predefined.

The interrupting device gives the address of sub-routine for these interrupts.

INTR is the only non-vectored interrupt in 8085 microprocessor.

•Maskable and Non-Maskable Interrupts –

•

Maskable Interrupts are those which can be disabled or ignored by the

microprocessor. These interrupts are either edge-triggered or level-triggered, so

they can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in

8085 microprocessor.

Non-Maskable Interrupts are those which cannot be disabled or ignored by

microprocessor. TRAP is a non-maskable interrupt. It consists of both level as well

as edge triggering and is used in critical power failure conditions.

Priority of Interrupts –

When microprocessor receives multiple interrupt requests simultaneously, it will

execute the interrupt service request (ISR) according to the priority of the

interrupts.

TRAP

RST 7.5

RST 6.5

RST 5.5

INTR

Highest to lowest

Instruction for Interrupts –

1.Enable Interrupt (EI) –The interrupt enable flip-flop is set and all interrupts are enabled

following the execution of next instruction followed by EI. No flags are affected. After a system reset,

the interrupt enable flip-flop is reset, thus disabling the interrupts. This instruction is necessary to

enable the interrupts again (except TRAP).

2.Disable Interrupt (DI) –This instruction is used to reset the value of enable flip-flop hence

disabling all the interrupts. No flags are affected by this instruction.

3.Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts (RST 7.5, RST 6.5,

RST 5.5) by setting various bits to form masks or generate output data via the Serial Output Data

(SOD) line. First the required value is loaded in accumulator then SIM will take the bit pattern from it.

4.Read Interrupt Mask (RIM) –This instruction is used to read the status of the hardware interrupts (RST

7.5, RST 6.5, RST 5.5) by loading into the A register a byte which defines the condition of the mask bits for the

interrupts. It also reads the condition of SID (Serial Input Data) bit on the microprocessor.

8085 microprocessor has _____ hardware interrupts.

A. 2

B. 3

C. 4

D. 5

UGC NET June 2016

8085 microprocessor has _____ hardware interrupts.

A. 2

B. 3

C. 4

D.5

UGC NET June 2016

The RST 7 instruction in 8085 microprocessor is equivalent to:

CALL 0010 H

CALL 0034 H

CALL 0038 H

CALL 003C H

NET June 2015

For Software interrupts vector addresses are given by:


RST 0 00 H

RST 1 08 H

RST 2 10 H

RST 3 18 H

RST 4 20 H

RST 5 28 H

RST 6 30 H

RST 7 38 H

The RST 7 instruction in 8085 microprocessor is equivalent to:

CALL 0010 H

CALL 0034 H

CALL 0038 H

CALL 003C H

NET June 2015

Which of the following is an interrupt according to temporal

relationship with system clock ?

(A) Maskable interrupt

(B) Periodic interrupt

(C) Division by zero

(D) Synchronous interrupt

Types of Interrupts:

Although interrupts have highest priority than other signals, there are many type of

interrupts but basic type of interrupts are

1.Hardware Interrupts: If the signal for the processor is from external device or

hardware is called hardware interrupts. Example: from keyboard we will press the key

to do some action this pressing of key in keyboard will generate a signal which is given

to the processor to do action, such interrupts are called hardware interrupts.

Hardware interrupts can be classified into two types they are

1.Maskable Interrupt: The hardware interrupts which can be delayed when a

much highest priority interrupt has occurred to the processor.

2.Non Maskable Interrupt: The hardware which cannot be delayed and should

process by the processor immediately.

2.Software Interrupts: Software interrupt can also divided in to two types. They

are

1.Normal Interrupts: the interrupts which are caused by the software

instructions are called software instructions.

1.Exception: unplanned interrupts while executing a program is called

Exception. For example: while executing a program if we got a value which

should be divided by zero is called a exception.

Classification of Interrupts According to Periodicity of Occurrence:

1.Periodic Interrupt: If the interrupts occurred at fixed interval in timeline then

that interrupts are called periodic interrupts

1.Aperiodic Interrupt: If the occurrence of interrupt cannot be predicted then

that interrupt is called aperiodic interrupt.

Classification of Interrupts According to the Temporal Relationship with

System Clock:

1.Synchronous Interrupt: The source of interrupt is in phase to the system clock

is called synchronous interrupt. In other words interrupts which are dependent on

the system clock. Example: timer service that uses the system clock.

1.Asynchronous Interrupts: If the interrupts are independent or not in phase to

the system clock is called asynchronous interrupt.

Which of the following is an interrupt according to temporal

relationship with system clock ?

(A) Maskable interrupt

(B) Periodic interrupt

(C) Division by zero

(D) Synchronous interrupt

Documents

INSTRUCTION PROGRAMMING & INTERRUPTS