inspiron 5421 14r 1220-4-1 dne40-cr-mb 5j8y4 OAK14_CR_SCHEMATIC_A00_MB_0905-2.pdf

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Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

OAK14 Chief River DIS A00Cover Page

A3

1 105Wednesday, September 05, 2012

M14 DIS

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M14 DIS

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M14 DIS

2012-09-05REV : A00

Essentials Oak 14 Schematic

DY : None InstalledUMA: UMA only installedOPS: DISCRTE OPTIMUS installed

Chief River

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OAK14 Chief River DIS A00

Block Diagram


M14 DIS

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Block Diagram


M14 DIS

C

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Block Diagram


M14 DIS

C

14.0" LCD (16:9)

PCIe x 8128Mx16bx4(1GB)256Mx16bx4(2GB)128Mx16bx8(2GB)

VRAM(DDR3) *8

SODIMM B

Intel PCHHDMI

LVDS (2channel)

HDMI V1.4a

Camera USB2.0 x 1

RJ45Conn.

PCIE x 1

USB3.0 Port x 2USB3.0 x 2

USB2.0 x 2

Left side

Touch PAD

8MBFlash ROM

LPC debug port

KBC

Int. KB

SPI

LPC BUS

NUVOTON NCT3940S-A

NPCE885PNUVOTON

Fan Control

SMBUSThermal

FAN

SATA(Gen3) x 1

SATA(Gen1) x 1

NUVOTONNCT7718W

HDD

ODD

Combo Jack

HDACODEC

HDA

802.11 b/g/n BT V4.0 combo

PCIE x 1 Mini-Card

USB2.0 x 1

RealtekRTS5170

CardReader SD/SDHC/MS/MS ProSlotUSB2.0 x 1

HP_R/L

MIC_IN/GND

SMBUS

2CH SPEAKER(2CH 2W/4ohm)

Switchable Graphic only

Ivy Bridge

BGA1023

BGA989

DDR3 1333/1600MHz Channel B

DMIx4FDIx4x2

HM76

17W (DC)

DDR31333/1600Intel CPUSODIMM A

Oak14 Block Diagram

DDR3 1333/1600MHz Channel A

High Definition Audio

12 USB 2.0/1.1 ports

ACPI 4.0a

6 SATA ports

LPC I/F

4 USB 3.0 ports

Panther Point

8 PCIE ports

DDR31333/1600

PS2

10/100 NIC

N13P - GS - OPN13M- GSR

Nvidia

25W83,84,85,86,87

DDR3

51

49

49

RealtekALC3221 2958

58

71

27

28

28

28

88,89,90,91

4,5,6,7,8,9,10

69

69

6056

56

3274

61,62,63

17,18,19,20,21,22,23,24,25

65

3159

14

15

RealtekRTL8105E-VD

USB2.0 Port x 1USB2.0 x 1

Right side

USB Board

33

1D05V_S0

TPS51216

CPU VCCP_CPU

DCBATOUT

DCBATOUT

Intel PCH 1D8V_S0

OUTPUTSINPUTS

SYW231

1D8V_S0

1D5V_S3

3D3V_AUX_S5

5V_AUX_S5

5V_S5

3D3V_S5

TPS51216

OUTPUTS

DCBATOUT

SYSTEM DC/DC

INPUTSTPS51225

CPU Core/NB Power

OUTPUTS

VCC_CORE

VCC_GFXCORE

INPUTSISL95833

OUTPUTS

OUTPUTS

INPUTS

BQ24727CHARGER

BT+

INPUTS

DCBATOUTAD+

DDR3 SUS

INPUTS OUTPUTS

OUTPUTS

DDR3 VTT

INPUTS0D75V_S0

INPUTSADP3211MNR2G

OUTPUTS

Nvidia VGA_CORE

VGA_CORE

DCBATOUT

5V_S5

DCBATOUT

TPS51219

3D3V_S5

26

INPUTSTPS51463

OUTPUTS

Intel CPU_VCCSA

0D85V_S0

DCBATOUT

48

47

45

46

46

42~44

41

40

92

PCB LAYERL1:TopL2:VCCL3:Signal

L4:SignalL5:GNDL6:Bottom

INPUTS OUTPUTS

1D5V_S3 1D5V_S0

Switches 36 93

1D05V_VGA_S0VCCP_CPU

3D3V_S03D3V_S5

5V_S5 5V_S0

1D5V_S3 1D5V_VGA_S0

3D3V_S0 3D3V_VGA_S0

Project code: 91.4WT01.001 91.4XP01.001PCB P/N : 12204Revision: A00

Profile/Image sensor

Digital MIC

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

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OAK14 Chief River DIS A00Table of Content

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A2


M14 DIS

PCIE Routing

LANE2

LANE3

x

Mini Card1(WLAN)LANE4

CFG[0] Connect a series 1 kOhms resistor on the critical CFG[0] trace in a manner which does not introduce any stubs to CFG[0] trace. Route as needed from the opposite side of this series isolation resistor to the debug port. ITP will drive the net to GND.

CFG[2] PCIe Static x16 Lane Numbering Reversal.

1: Normal Operation; Lane # definition matches socket pin map definition0:Lane Reversed

SATA Table

PairSATA

Device

0

5

432

1

HDD1

ODD1

X

X

X

X

SPKR

Name Schematics Notes

HDA_DOCK_EN#/GPIO33

High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an active-low-signal. When deasserted the external docking switch is in isolate mode. When asserted the external docking switch electrically connects the IntelR HD Audio dock signals to the corresponding Panther Point signals. This signal can instead be used as GPIO33.

HDA_SDO

INIT3_3V#This signal has a weak internal pull-up.Note: The internal pull-up is disabled after PLTRST# deasserts.NOTE: This signal should not be pulled low. Leave as "No Connect".

GNT3#/GPIO55GNT2#/GPIO53GNT1#/GPIO51

DF_TVS

This signal is a strap for selecting DMI and FDI termination voltage. For Ivy Bridge processor only implementation:DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms 5% resistor.For future processor compatibility:It needs to be connected to PROC_SELECT through a 1.0 kOhms 5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms 5% pull-up resistorto PCH VccDFTERM.

GNT[3:0]# functionality is not available on Mobile.Used as GPIO only. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail.

INTVRMEN

The signal has a weak internal pull-down.Note: the internal pull-down is disabled after PLTRST# deasserts. If the signal is sampled high, this indicates that the system is strapped to the No Reboot mode (Panther Point will disable the TCO Timer system rebootfeature).

Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when highNOTE: This signal should always be pulled highExternal 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low.NOTE: This signal should be pulled down to GND through 330 kOhms resistor

PCH Strapping

CFG[6:5]

1:Disabled - No Physical Display Port attached to Embedded DisplayPort No connect for disable0:Enabled - An external Display Port device is connected to the Embedded Display Port Pull-down to GND through a 1K 5% resistor to enable port

CFG[4]

Pin Name Strap DescriptionConfiguration (Default value for each bit is 1 unless specified otherwise)

Chief River Schematic Checklist Revision 1.5DefaultValue

PCIE Port Bifurcation Straps

00 = 1 x 8, 2 x 4 PCI Express01 = reserved10 = 2 x 8 PCI Express11 = 1 x 16 PCI Express

1

Processor Strapping

DDR3 VREFDDR3 VREF M1 and M3 Guidelines are required.Note: The M3 traces are routed to the Sandy Bridge Processor reserved pins.

PROC_SELECT# & DF_TVS

Pin Name Configuration Schematic Notes

Sandy Bridge + Ivy Bridge

Ivy Bridge

Connect DF_TVS signal of the PCH to PROC_SELECT# of theprocessor through a 1K5% series resistor. PROC_SELECT#also needs a 2.2K5% pull up resistor to PCH VccDFTERMrail.

Sandy Bridge + Ivy Bridge Compatibility Requirements

No change.


Ivy Bridge No change.





LANE1 X

LANE5

LANE6

LANE7

LANE8 X

X

Power Plane

Display Port Presence strap 1

1

CFG[17:7]Reserved configuration lands. A test point may be placed on the board for these lands.

Chief River Schematic Checklist Revision 1.5

The POR for Ivy Bridge mobile parts is now 1.05 V. There is nolonger a requirement for a separate VCCIO VR for Sandy Bridge+ Ivy Bridge compatibility.VCCIO VR

Implementation

VCCSA_SELECT[0:1] which should be connected to VID[1:0] of the System Agent (SA) VR controller.

The total motherboard length for a pair of consecutive PCIExpress Tx lanes be length matched within 100 mils (2.54 mm)

VCCSA_SEL connection to VCCSA_VID[1:0] lines



Depending on the PDDG specifications, some IVB GT2 SKUs may require a new VR controller and 2 phase VCC GT core VR.

Layout Requirement on PCI Express Gen3



GT Core VR Implementation

To support Gen 3 PCI Express Graphic, the value of the AC coupling capacitor should be 180 - 265 nF.

No change.Ivy Bridge

Sandy Bridge + Ivy Bridge (PCIe Gen3):

Processor PCI Express Graphics Guidelines

Chief River Schematic Checklist Revision 1.5

SATA1GP/GPIO19

Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved1 0 PCI1 1 SPI0 0 LPCNOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Panther Point require SPI flash connected directly to the Panther Point's SPI bus with a valid descriptor in order to boot.NOTE: Booting to PCI is intended for debut/testing only. Boot BIOSDestination Select to LPC/PCI by functional strap or via Boot BIOSDestination Bit will not affect SPI accesses initiated by ManagementEngine or Integrated GbE LAN.NOTE: PCI Boot BIOS destination is not supported on mobile.

Reserved.This signal has a weak internal pull-down.NOTE: The internal pull-down is disabled after PLTRST# deasserts.NOTE: This signal should not be pulled high when strap is sampled.

SATA2GP/GPIO36

ReservedThis signal has a weak internal pull-down.NOTE: The internal pull-down is disabled after PLTRST# deasserts.NOTE: This signal should not be pulled high when strap is sampled.

SATA3GP/GPIO37

Signal has a weak internal pull-down.If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect (default).If sampled high, the Flash Descriptor Security will be overridden.This strap should only be asserted high via external pull-up in manufacturing/debug environments ONLY.Note: The weak internal pull-down is disabled after PLTRST# deasserts.Asserting the HDA_SDO high on the rising edge of PWROK will also halt Intel Management Engine after chipset bring up and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manufacturing/ debug.This signal has a 20k internal pull down resistor.

HDA_SYNC

This signal has a weak internal pull-down.On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled low.Needs to be pulled High for Chief River platform.Note: HDA_SYNC signal also serves as a strap for selecting VRM voltage to the PCH. The strap is sampled on the rising edge of RSMRST# signal. Due to potential leakage on the codec (path to GND), the strap may not be able to achieve the Vihmin at PCH input.Therefore, platform may need to isolate this signal from the codec during the strap phase. Refer to the example circuits provided in the latest Chief River platform design guide.

GPIO15TLS ConfidentialityLow (0) Intel ME Crypto Transport Layer Security (TLS) cipher suite with noconfidentialityHigh (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentialityThis signal has a weak internal pull-down.

NOTE:The weak internal pull-down is disabled after RSMRST# deasserts. NOTE: A strong pull-up may be needed for GPIO functionality

L_DDC_DATA

LVDS Detected.When '1'- LVDS is detected; When '0'- LVDS is not detected.This signal has a weak internal pull-down.

NOTE:The internal pull-down is disabled after PLTRST# deasserts.

SDVO_CTRLDATA

Port B DetectedWhen '1'- Port B is detected; When '0'- Port B is not detectedThis signal has a weak internal pull-down.


DDPC_CTRLDATA

Port C Detected. When '1'- Port C is detected; When '0'- Port C is not detectedThis signal has a weak internal pull-down.


DDPD_CTRLDATA

Port D Detected.When '1'- Port D is detected; When '0'- Port D is not detectedThis signal has a weak internal pull-down.


GPIO28

The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled.If not used, 8.2-k to 10-k pull-up to +V3.3A power-rail.GPIO28 signal also needs to be pulled up to 3.3V_SUS with 4.7K resistor to ensure proper strap setting when use as the chipset test interface.Refer to the latest platform debug design guide and platform design guide for more details.NOTE:This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# deasserts.

GPIO29/ SLP_LAN#

GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, SLP_LAN# must be used to control the power to the PHY LAN (no other implementation is supported). If integrated Intel LAN is not supported on the platform, GPIO29 can be used as a normal GPIO. A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default, the soft strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable GPIO functionality, then SLP_LAN# functionality is no longer available, and the signal can be used as a normal GPIO (default to GPI).

X

X

USB Table

1312

HM76 NC

Mini Card (WLAN)

X

HM76 NC

X

10

0

11

Onboard LAN

Pair

4

5

2

3

1

Device

67

89

CARD READER

Touch Panel

CAMERA

X

Voltage RailsVOLTAGE DESCRIPTION

ACTIVE INPOWER PLANE

CPU Core RailGraphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

3D3V_AUX_KBC

3.3V

DSW, Sx ON for supporting Deep Sleep states

S0

S3

All S states

WOL_EN

G3, Sx

5V_S03D3V_S01D8V_S01D5V_S01D05V_VTT0D85V_S00D75V_S0VCC_COREVCC_GFXCORE1D8V_VGA_S03D3V_VGA_S01V_VGA_S0

5V3.3V1.8V1.5V1.05V0.95 - 0.85V0.75V0.35V to 1.5V0.4 to 1.25V1.8V3.3V1V

5V1.5V0.75V

5V_USBX_S31D5V_S3DDR_VREF_S3

BT+DCBATOUT5V_S55V_AUX_S53D3V_S53D3V_AUX_S5

6V-14.1V6V-14.1V5V5V3.3V3.3V

3.3V3D3V_LAN_S5

3.3V

3D3V_AUX_S5

USB3.0 port1USB3.0 port2, with Debug Port

X

X

USB2.0 port3

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DMI_CPU_RXN_PCH_TXN0

DMI_CPU_RXP_PCH_TXP0

DMI_CPU_TXP_PCH_RXP0

DMI_CPU_TXN_PCH_RXN0

FDI_FSYNC0FDI_FSYNC1

FDI_INT

FDI_LSYNC0FDI_LSYNC1

FDI_CPU_TXN_PCH_RXN0

FDI_CPU_TXP_PCH_RXP0

PEG_IRCOMP_R

DP_COMP

CPU_RXP_C_dGPU_TXP1CPU_RXP_C_dGPU_TXP0

CPU_RXP_C_dGPU_TXP7CPU_RXP_C_dGPU_TXP6

CPU_RXN_C_dGPU_TXN7CPU_RXN_C_dGPU_TXN6

dGPU_RXP_C_CPU_TXP13

CPU_TXN_dGPU_RXN3

CPU_TXN_dGPU_RXN5

CPU_TXN_dGPU_RXN0

CPU_TXN_dGPU_RXN7

CPU_TXN_dGPU_RXN2

CPU_TXN_dGPU_RXN4

CPU_TXN_dGPU_RXN6

CPU_TXN_dGPU_RXN1

dGPU_RXN_C_CPU_TXN10



dGPU_RXN_C_CPU_TXN9



dGPU_RXP_C_CPU_TXP8



dGPU_RXN_C_CPU_TXN8



dGPU_RXP_C_CPU_TXP9

CPU_TXP_dGPU_RXP3

CPU_TXP_dGPU_RXP5

CPU_TXP_dGPU_RXP0

CPU_TXP_dGPU_RXP7

CPU_TXP_dGPU_RXP2

CPU_TXP_dGPU_RXP4

CPU_TXP_dGPU_RXP6

CPU_TXP_dGPU_RXP1



CPU_RXN_C_dGPU_TXN5CPU_RXN_C_dGPU_TXN4CPU_RXN_C_dGPU_TXN3CPU_RXN_C_dGPU_TXN2CPU_RXN_C_dGPU_TXN1

CPU_RXP_C_dGPU_TXP5

CPU_RXN_C_dGPU_TXN0

CPU_RXP_C_dGPU_TXP4CPU_RXP_C_dGPU_TXP3CPU_RXP_C_dGPU_TXP2

DMI_CPU_RXN_PCH_TXN1DMI_CPU_RXN_PCH_TXN2DMI_CPU_RXN_PCH_TXN3

DMI_CPU_RXP_PCH_TXP1DMI_CPU_RXP_PCH_TXP2DMI_CPU_RXP_PCH_TXP3

DMI_CPU_TXN_PCH_RXN1DMI_CPU_TXN_PCH_RXN2DMI_CPU_TXN_PCH_RXN3

DMI_CPU_TXP_PCH_RXP1DMI_CPU_TXP_PCH_RXP2DMI_CPU_TXP_PCH_RXP3

FDI_CPU_TXN_PCH_RXN1FDI_CPU_TXN_PCH_RXN2FDI_CPU_TXN_PCH_RXN3FDI_CPU_TXN_PCH_RXN4FDI_CPU_TXN_PCH_RXN5FDI_CPU_TXN_PCH_RXN6FDI_CPU_TXN_PCH_RXN7

FDI_CPU_TXP_PCH_RXP1FDI_CPU_TXP_PCH_RXP2FDI_CPU_TXP_PCH_RXP3FDI_CPU_TXP_PCH_RXP4FDI_CPU_TXP_PCH_RXP5FDI_CPU_TXP_PCH_RXP6FDI_CPU_TXP_PCH_RXP7

VCCP_CPU

VCCP_CPU

DMI_CPU_TXP_PCH_RXP[3:0]19

DMI_CPU_TXN_PCH_RXN[3:0]19

DMI_CPU_RXN_PCH_TXN[3:0]19

DMI_CPU_RXP_PCH_TXP[3:0]19

FDI_CPU_TXN_PCH_RXN[7:0]19

FDI_CPU_TXP_PCH_RXP[7:0]19

FDI_FSYNC019FDI_FSYNC119

FDI_INT19

FDI_LSYNC019FDI_LSYNC119

dGPU_RXP_C_CPU_TXP[8..15] 83

dGPU_RXN_C_CPU_TXN[8..15] 83

CPU_RXP_C_dGPU_TXP[7..0] 83

CPU_RXN_C_dGPU_TXN[7..0] 83

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CPU(PCIE/DMI/FDI)


M14 DIS

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CPU(PCIE/DMI/FDI)


M14 DIS

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CPU(PCIE/DMI/FDI)


M14 DIS

A3

SSID = CPU

Signal Routing Guideline:EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

Layout Note:FDI trace length 2000~6500mil

Layout Note:

DMI trace length 2000~8000milLayout Note:

Signal Routing Guideline:PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

Layout Note:

Note:PEG with reversal type.

1 2 C416 SCD22U10V2KX-1GPOPS C416 SCD22U10V2KX-1GPOPS




1 2R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2R401 24D9R2F-L-GPR401 24D9R2F-L-GP




1 2 C407 SCD22U10V2KX-1GPOPS C407 SCD22U10V2KX-1GPOPS1 2 C408 SCD22U10V2KX-1GPOPS C408 SCD22U10V2KX-1GPOPS



1 2 C411 SCD22U10V2KX-1GPOPS C411 SCD22U10V2KX-1GPOPS1 2 C412 SCD22U10V2KX-1GPOPS C412 SCD22U10V2KX-1GPOPS1 2 C413 SCD22U10V2KX-1GPOPS C413 SCD22U10V2KX-1GPOPS



DMI_RX#0M2DMI_RX#1P6DMI_RX#2P1DMI_RX#3P10

DMI_RX0N3DMI_RX1P7DMI_RX2P3DMI_RX3P11

DMI_TX#0K1DMI_TX#1M8DMI_TX#2N4DMI_TX#3R2

DMI_TX0K3DMI_TX1M7

DMI_TX3T3DMI_TX2P4

FDI0_TX#0U7FDI0_TX#1W11FDI0_TX#2W1FDI0_TX#3AA6FDI1_TX#0W6FDI1_TX#1V4FDI1_TX#2Y2FDI1_TX#3AC9

FDI0_TX0U6FDI0_TX1W10FDI0_TX2W3FDI0_TX3AA7FDI1_TX0W7FDI1_TX1T4FDI1_TX2AA3FDI1_TX3AC8

FDI0_FSYNCAA11FDI1_FSYNCAC12

FDI_INTU11

FDI0_LSYNCAA10FDI1_LSYNCAG8

PEG_ICOMPI G3PEG_ICOMPO G1

PEG_RCOMPO G4

PEG_RX#0 H22PEG_RX#1 J21PEG_RX#2 B22PEG_RX#3 D21PEG_RX#4 A19PEG_RX#5 D17PEG_RX#6 B14PEG_RX#7 D13PEG_RX#8 A11PEG_RX#9 B10

PEG_RX#10 G8PEG_RX#11 A8PEG_RX#12 B6PEG_RX#13 H8PEG_RX#14 E5PEG_RX#15 K7

PEG_RX0 K22PEG_RX1 K19PEG_RX2 C21PEG_RX3 D19PEG_RX4 C19PEG_RX5 D16PEG_RX6 C13PEG_RX7 D12PEG_RX8 C11PEG_RX9 C9

PEG_RX10 F8PEG_RX11 C8PEG_RX12 C5PEG_RX13 H6PEG_RX14 F6PEG_RX15 K6

PEG_TX#0 G22PEG_TX#1 C23PEG_TX#2 D23PEG_TX#3 F21PEG_TX#4 H19PEG_TX#5 C17PEG_TX#6 K15PEG_TX#7 F17PEG_TX#8 F14PEG_TX#9 A15

PEG_TX#10 J14PEG_TX#11 H13PEG_TX#12 M10PEG_TX#13 F10PEG_TX#14 D9PEG_TX#15 J4

PEG_TX0 F22PEG_TX1 A23PEG_TX2 D24PEG_TX3 E21PEG_TX4 G19PEG_TX5 B18PEG_TX6 K17PEG_TX7 G17PEG_TX8 E14PEG_TX9 C15

PEG_TX10 K13PEG_TX11 G13PEG_TX12 K10PEG_TX13 G10PEG_TX14 D8PEG_TX15 K4

EDP_AUXAF4EDP_AUX#AG4

EDP_TX0AC1EDP_TX1AA4EDP_TX2AE10EDP_TX3AE6

EDP_COMPIOAF3

EDP_HPD#AG11EDP_ICOMPOAD2

EDP_TX#0AC3EDP_TX#1AC4EDP_TX#2AE11EDP_TX#3AE7

P

C

I

E

X

P

R

E

S

S

-

-

G

R

A

P

H

I

C

S

DMI

Intel(

R) FDI

eDP

1 OF 9CPU1A

IVY-BRIDGE-GP-NF71.00IVY.A0U

P

C

I

E

X

P

R

E

S

S

-

-

G

R

A

P

H

I

C

S

DMI

Intel(

R) FDI

eDP

1 OF 9CPU1A


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_SNB_IVB#

SKTOCC#_R

H_CATERR#

H_PECI

H_PROCHOT#_R

H_PROCHOT#

H_PM_SYNC

VDDPWRGOOD

H_CPUPWRGD_R

BUF_CPU_RST#

CLK_EXP_PCLK_EXP_N

CLK_DP_P_RCLK_DP_N_R

SM_RCOMP_0SM_RCOMP_1SM_RCOMP_2

SM_DRAMRST#

H_THERMTRIP#

XDP_TDO

XDP_TMS

XDP_TRST#XDP_TCLK

XDP_PREQ#XDP_PRDY#

XDP_TDI

XDP_DBRESET#

XDP_TCLK

XDP_TDO

XDP_BPM1XDP_BPM2XDP_BPM3

XDP_BPM0

XDP_BPM4XDP_BPM5XDP_BPM6XDP_BPM7

XDP_TRST#

XDP_TDIXDP_TMS

H_CPUPWRGD PLT_RST# XDP_DBRESET#

VCCP_CPU

VCCP_CPU

VCCP_CPU

H_SNB_IVB#22

H_PECI22,27

H_PROCHOT#27,38,40,42

H_THERMTRIP#22

H_PM_SYNC19

H_CPUPWRGD22

VDDPWRGOOD37

PLT_RST#18,27,31,65,71,83

CLK_EXP_P 20CLK_EXP_N 20

SM_DRAMRST# 37

XDP_DBRESET# 19

XDP_BPM0 71XDP_BPM1 71

XDP_PREQ# 71

XDP_BPM2 71XDP_BPM3 71XDP_BPM4 71XDP_BPM5 71XDP_BPM6 71XDP_BPM7 71

XDP_PRDY# 71

Title


Date: Sheet of



CPU(THERMAL/CLOCK/PM)


M14 DIS

A3

Title


Date: Sheet of





M14 DIS

A3

Title


Date: Sheet of





M14 DIS

A3

SSID = CPU

C501 place near to CPU

Layout Note:R501, R513 place near to CPU

Layout Note:

Checking the connector pin's LAYOUTLayout Note:

Signal Routing Guideline:SM_RCOMP keep routing length less than 500 mils.Trace width = 15mil

Layout Note:

reserve for EMI Request

1 2R508 25D5R2F-GPR508 25D5R2F-GPSM_RCOMP1 BE43SM_RCOMP2 BG43

SM_DRAMRST# AT30

SM_RCOMP0 BF44

BCLK# H2BCLK J3

DPLL_REF_CLK# AG1DPLL_REF_CLK AG3

CATERR#C49

PECIA48

PROCHOT#C45

THERMTRIP#D45

SM_DRAMPWROKBE45

RESET#D44

PRDY# N53PREQ# N55

TCK L56TMS L55

TRST# J58

TDI M60TDO L59

DBR# K58

BPM#0 G58BPM#1 E55BPM#2 E59BPM#3 G55BPM#4 G59BPM#5 H60BPM#6 J59BPM#7 J61

PM_SYNCC48

PROC_DETECT#C57

PROC_SELECT#F49

UNCOREPWRGOODB46

C

L

O

C

K

S

MISC

THERMAL

PWR MANAG

EMENT

D

D

R

3

M

I

S

C

J

T

A

G

&

B

P

M

2 OF 9CPU1B


C

L

O

C

K

S

MISC

THERMAL

PWR MANAG

EMENT

D

D

R

3

M

I

S

C

J

T

A

G

&

B

P

M

2 OF 9CPU1B


1 2R511 200R2F-L-GPR511 200R2F-L-GP

1

2

EC501SCD1U10V2KX-5GP

DY


DY

12 3

4RN502

SRN51J-GPXDP

RN502

SRN51J-GPXDP

1 2R513

56R2J-4-GP

R513

56R2J-4-GP

1TP501TPAD14-OP-GP TP501TPAD14-OP-GP

1 2R501

62R2J-GP

R501

62R2J-GP

1TP502TPAD14-OP-GP TP502TPAD14-OP-GP

12 3

4RN503

SRN1KJ-7-GP

RN503

SRN1KJ-7-GP

1

2

R509698R2F-GP

R509698R2F-GP

1234 5

678

RN501

SRN51J-1-GP

XDP

RN501

SRN51J-1-GP

XDP

1 2R506 140R2F-GPR506 140R2F-GP

1 2R50310KR2J-3-GP

R50310KR2J-3-GP

1

2


DY


DY

1 2

R5040R0402-PAD

R5040R0402-PAD

1 2

R5101K5R2F-2-GP

R5101K5R2F-2-GP

1 2

R5074K99R2F-L-GP

R5074K99R2F-L-GP

1

2


DY


DY

1

2

C501SC220P50V2KX-3GPDYC501SC220P50V2KX-3GPDY

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_DQ44

M_A_DQ36

M_A_DQ47

M_A_DQ40M_A_DQ39

M_A_DQ37

M_A_DQ35M_A_DQ34

M_A_DQ59

M_A_DQ54M_A_DQ53

M_A_DQ63

M_A_DQ60M_A_DQ61

M_A_DQ58

M_A_DQ51

M_A_DQ48

M_A_DQ57

M_A_DQ55

M_A_DQ49M_A_DQ50

M_A_DQ62

M_A_DQ52

M_A_DQ56

M_A_DQ[63:0]M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3

M_A_DQ7

M_A_DQ5M_A_DQ4

M_A_DQ6

M_A_DQ12

M_A_DQ10

M_A_DQ13

M_A_DQ9M_A_DQ8

M_A_DQ11

M_A_DQ15M_A_DQ14

M_A_DQ27

M_A_DQ25

M_A_DQ20M_A_DQ19

M_A_DQ30

M_A_DQ18

M_A_DQ16

M_A_DQ28

M_A_DQ17

M_A_DQ26

M_A_DQ31

M_A_DQ29

M_A_DQ22M_A_DQ23M_A_DQ24

M_A_DQ21

M_A_DQ46

M_A_DQ42

M_A_DQ38

M_A_DQ32

M_A_DQ45

M_A_DQ33

M_A_DQ43

M_A_DQ41

M_A_DQS#4M_A_DQS#5M_A_DQS#6M_A_DQS#7

M_A_DQS#3M_A_DQS#2M_A_DQS#1M_A_DQS#0

M_A_DQS4M_A_DQS3

M_A_DQS5M_A_DQS6M_A_DQS7

M_A_DQS2M_A_DQS1M_A_DQS0

M_A_A7

M_A_A12

M_A_A14M_A_A13

M_A_A9

M_A_A15

M_A_A10

M_A_A0

M_A_A6

M_A_A8

M_A_A1M_A_A2M_A_A3M_A_A4M_A_A5

M_A_A11

M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11

M_B_DQ15

M_B_DQ13M_B_DQ12

M_B_DQ14

M_B_DQ16M_B_DQ17M_B_DQ18M_B_DQ19

M_B_DQ23

M_B_DQ21M_B_DQ20

M_B_DQ22

M_B_DQ28

M_B_DQ26

M_B_DQ29

M_B_DQ25

M_B_DQ31

M_B_DQ24

M_B_DQ27

M_B_DQ30


M_B_DQ39

M_B_DQ37M_B_DQ36

M_B_DQ38

M_B_DQ44

M_B_DQ42

M_B_DQ45

M_B_DQ41

M_B_DQ47

M_B_DQ40

M_B_DQ43

M_B_DQ46


M_B_DQ55

M_B_DQ53M_B_DQ52

M_B_DQ54

M_B_DQ60

M_B_DQ58

M_B_DQ61

M_B_DQ57

M_B_DQ63

M_B_DQ56

M_B_DQ59

M_B_DQ62

M_B_DQ[63:0]

M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7

M_B_DQS#3M_B_DQS#2M_B_DQS#1M_B_DQS#0

M_B_DQS#7M_B_DQS#6M_B_DQS#5M_B_DQS#4

M_B_A5M_B_A6M_B_A7M_B_A8M_B_A9M_B_A10M_B_A11M_B_A12M_B_A13M_B_A14M_B_A15

M_B_A4M_B_A3M_B_A2M_B_A1M_B_A0

M_A_DQ[63:0]14

M_A_BS014M_A_BS114M_A_BS214

M_A_CAS#14M_A_RAS#14M_A_WE#14

M_A_DIMA_CKE0 14

M_A_DIMA_CKE1 14

M_A_DIMA_CLK_DDR0 14M_A_DIMA_CLK_DDR#0 14

M_A_DIMA_CLK_DDR#1 14M_A_DIMA_CLK_DDR1 14

M_A_DIMA_CS#0 14M_A_DIMA_CS#1 14

M_A_DIMA_ODT0 14M_A_DIMA_ODT1 14

M_A_DQS#[7:0] 14

M_A_DQS[7:0] 14

M_A_A[15:0] 14

M_B_DQ[63:0]15

M_B_BS015M_B_BS115M_B_BS215

M_B_CAS#15M_B_RAS#15M_B_WE#15

M_B_DIMB_CKE0 15

M_B_DIMB_CKE1 15

M_B_DIMB_CLK_DDR0 15M_B_DIMB_CLK_DDR#0 15


M_B_DIMB_CS#0 15M_B_DIMB_CS#1 15

M_B_DIMB_ODT0 15M_B_DIMB_ODT1 15

M_B_A[15:0] 15

M_B_DQS[7:0] 15

M_B_DQS#[7:0] 15

Title


Date: Sheet of


OAK14 Chief River DIS A00CPU (DDR)

A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

SSID = CPU

SB_CK0 BA34

SB_CK1 BA36

SB_CK#0 AY34

SB_CK#1 BB36

SB_CKE0 AR22

SB_CKE1 BF27

SB_ODT0 AT43SB_ODT1 BG47

SB_DQS4 BE51

SB_DQS#4 BG51

SB_DQS5 BA61

SB_DQS#5 BA59

SB_DQS6 AR59

SB_DQS#6 AT60

SB_DQS7 AK61

SB_DQS#7 AK59

SB_DQS0 AM2

SB_DQS#0 AL3

SB_DQS1 AV1

SB_DQS#1 AV3

SB_DQS2 BE11

SB_DQS#2 BG11

SB_DQS3 BD18

SB_DQS#3 BD17

SB_MA0 BF32SB_MA1 BE33SB_MA2 BD33SB_MA3 AU30SB_MA4 BD30SB_MA5 AV30SB_MA6 BG30SB_MA7 BD29SB_MA8 BE30SB_MA9 BE28

SB_MA10 BD43SB_MA11 AT28SB_MA12 AV28SB_MA13 BD46SB_MA14 AT26SB_MA15 AU22

SB_DQ0AL4SB_DQ1AL1SB_DQ2AN3SB_DQ3AR4SB_DQ4AK4SB_DQ5AK3SB_DQ6AN4SB_DQ7AR1SB_DQ8AU4SB_DQ9AT2SB_DQ10AV4SB_DQ11BA4SB_DQ12AU3SB_DQ13AR3SB_DQ14AY2SB_DQ15BA3SB_DQ16BE9SB_DQ17BD9SB_DQ18BD13SB_DQ19BF12SB_DQ20BF8SB_DQ21BD10SB_DQ22BD14SB_DQ23BE13SB_DQ24BF16SB_DQ25BE17SB_DQ26BE18SB_DQ27BE21SB_DQ28BE14SB_DQ29BG14SB_DQ30BG18SB_DQ31BF19SB_DQ32BD50SB_DQ33BF48SB_DQ34BD53SB_DQ35BF52SB_DQ36BD49SB_DQ37BE49SB_DQ38BD54SB_DQ39BE53SB_DQ40BF56SB_DQ41BE57SB_DQ42BC59SB_DQ43AY60SB_DQ44BE54SB_DQ45BG54SB_DQ46BA58SB_DQ47AW59SB_DQ48AW58SB_DQ49AU58SB_DQ50AN61SB_DQ51AN59SB_DQ52AU59SB_DQ53AU61SB_DQ54AN58SB_DQ55AR58SB_DQ56AK58SB_DQ57AL58SB_DQ58AG58SB_DQ59AG59SB_DQ60AM60SB_DQ61AL59SB_DQ62AF61SB_DQ63AH60

SB_CS#0 BE41SB_CS#1 BE47

SB_CAS#AV43SB_RAS#BF40SB_WE#BD45

SB_BS0BG39SB_BS1BD42SB_BS2AT22

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

B

4 OF 9CPU1D


D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

B

4 OF 9CPU1D


SA_CK0 AU36

SA_CK1 AT40

SA_CK#0 AV36

SA_CK#1 AU40

SA_CKE0 AY26

SA_CKE1 BB26

SA_CS#0 BB40SA_CS#1 BC41

SA_ODT0 AY40SA_ODT1 BA41

SA_DQS0 AJ11

SA_DQS#0 AL11

SA_DQS1 AR10

SA_DQS#1 AR8

SA_DQS2 AY11

SA_DQS#2 AV11

SA_DQS3 AU17SA_DQS4 AW45

SA_DQS#4 AV45

SA_DQS5 AV51

SA_DQS#5 AY51

SA_DQS6 AT56

SA_DQS#6 AT55

SA_DQS7 AK54

SA_DQS#7 AK55

SA_MA0 BG35SA_MA1 BB34SA_MA2 BE35SA_MA3 BD35SA_MA4 AT34SA_MA5 AU34SA_MA6 BB32SA_MA7 AT32SA_MA8 AY32SA_MA9 AV32

SA_MA10 BE37SA_MA11 BA30SA_MA12 BC30SA_MA13 AW41SA_MA14 AY28SA_MA15 AU26

SA_DQ0AG6SA_DQ1AJ6SA_DQ2AP11SA_DQ3AL6SA_DQ4AJ10SA_DQ5AJ8SA_DQ6AL8SA_DQ7AL7SA_DQ8AR11SA_DQ9AP6SA_DQ10AU6SA_DQ11AV9SA_DQ12AR6SA_DQ13AP8SA_DQ14AT13SA_DQ15AU13SA_DQ16BC7SA_DQ17BB7SA_DQ18BA13SA_DQ19BB11SA_DQ20BA7SA_DQ21BA9SA_DQ22BB9SA_DQ23AY13SA_DQ24AV14SA_DQ25AR14SA_DQ26AY17SA_DQ27AR19SA_DQ28BA14SA_DQ29AU14SA_DQ30BB14SA_DQ31BB17SA_DQ32BA45SA_DQ33AR43SA_DQ34AW48SA_DQ35BC48SA_DQ36BC45SA_DQ37AR45SA_DQ38AT48SA_DQ39AY48SA_DQ40BA49SA_DQ41AV49SA_DQ42BB51SA_DQ43AY53SA_DQ44BB49SA_DQ45AU49SA_DQ46BA53SA_DQ47BB55SA_DQ48BA55SA_DQ49AV56SA_DQ50AP50SA_DQ51AP53SA_DQ52AV54SA_DQ53AT54SA_DQ54AP56SA_DQ55AP52SA_DQ56AN57SA_DQ57AN53SA_DQ58AG56SA_DQ59AG53SA_DQ60AN55SA_DQ61AN52SA_DQ62AG55SA_DQ63AK56

SA_CAS#BE39SA_RAS#BD39SA_WE#AT41

SA_BS0BD37SA_BS1BF36SA_BS2BA28

SA_DQS#3 AT17D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

A

3 OF 9CPU1C


D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

A

3 OF 9CPU1C


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DC_TEST_C4_D3

TP_DC_TEST_A59_C59

TP_DC_TEST_A61_C61

TP_DC_TEST_BE59_BE61

DC_TEST_BG59_BG61

DC_TEST_BE3_BG3

DC_TEST_BE1_BG1

CFG6

CFG0CFG1

CFG4

CFG2

CFG5

CFG3

VCC_DIE_SENSE

BCLK_ITPBCLK_ITP#

CFG2

CFG6

CFG5

CFG071

Title


Date: Sheet of


OAK14 Chief River DIS A00CPU (RESERVED)

A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

SSID = CPU

0:Lane Reversed

PEG Static Lane Reversal

1: Normal Operation; Lane # definition matches socket pin map definitionCFG[2]

CFG[6:5]

PCIE Port Bifurcation Straps

0: Enabled; An external Display Port device is connected to the Embedded Display Port

Display Port Presence Strap

1: Disabled; No Physical Display Port attached to Embedded Display PortCFG[4]

1x16 PCI Express

Reserved

2 x8 - PCI Express

1x8, 2x4 PCI Express

11:

10:

01:

00:

1

2

R7011KR2J-1-GP

DY

R7011KR2J-1-GP

DY

1TP702TP702

1

2

R7041KR2J-1-GP

OPS

R7041KR2J-1-GP

OPS

1 TP722TP722

1TP719TP719

1

2

R7021KR2J-1-GP

OPS

R7021KR2J-1-GP

OPSCFG0B50CFG1C51CFG2B54CFG3D53CFG4A51CFG5C53CFG6C55CFG7H49CFG8A55CFG9H51CFG10K49CFG11K53CFG12F53CFG13G53CFG14L51CFG15F51CFG16D52CFG17L53

DC_TEST_A4 A4

DC_TEST_A58 A58DC_TEST_A59 A59

DC_TEST_A61 A61

DC_TEST_BD1 BD1

DC_TEST_BD61 BD61

DC_TEST_BE1 BE1DC_TEST_BE3 BE3

DC_TEST_BE59 BE59DC_TEST_BE61 BE61

DC_TEST_BG1 BG1DC_TEST_BG3 BG3DC_TEST_BG4 BG4

DC_TEST_BG58 BG58DC_TEST_BG59 BG59DC_TEST_BG61 BG61

DC_TEST_C4 C4

DC_TEST_C59 C59

DC_TEST_C61 C61

DC_TEST_D1 D1DC_TEST_D3 D3

DC_TEST_D61 D61

VCC_VAL_SENSEH43VSS_VAL_SENSEK43

VAXG_VAL_SENSEH45VSSAXG_VAL_SENSEK45

VCC_DIE_SENSEF48

RSVD41 AH2RSVD42 AG13RSVD43 AM14RSVD44 AM15

RSVD8BA19RSVD9AV19RSVD10AT21RSVD11BB21RSVD12BB19RSVD13AY21RSVD14BA22RSVD15AY22RSVD16AU19RSVD17AU21RSVD18BD21RSVD19BD22RSVD20BD25RSVD21BD26RSVD22BG22RSVD23BE22RSVD24BG26RSVD25BE26RSVD26BF23RSVD27BE24

RSVD45 N50

RSVD30 N42RSVD31 L42RSVD32 L45RSVD33 L47

RSVD34 M13RSVD35 M14RSVD36 U14RSVD37 W14RSVD38 P13

RSVD39 AT49RSVD40 K24

RSVD6H48RSVD7K48

RSVD47G48

BCLK_ITP N59BCLK_ITP# N58

R

E

S

E

R

V

E

D

5 OF 9CPU1E


R

E

S

E

R

V

E

D

5 OF 9CPU1E


1 TP721TP721

1TP703TP703

1TP701TP701

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_CPU_SVIDCLKH_CPU_SVIDALRT#

H_CPU_SVIDDAT

VCCSENSEVSSSENSE

H_SNB_IVB#_PWRCTRL

VCC_CORE

VCCP_CPUVCCP_CPU

VCC_CORE

VCCP_CPU

+V1.05S_VCCPQE_R

VCC_CORE

VCCP_CPU

VCCP_CPU

VR_SVID_ALERT# 42

H_CPU_SVIDDAT 42H_CPU_SVIDCLK 42

VCCSENSE 43VSSSENSE 43

VSSIO_SENSE 45VCCIO_SENSE 45

Title


Date: Sheet of


OAK14 Chief River DIS A00CPU (VCC_CORE)

A2


M14 DIS

Title


Date: Sheet of



A2


M14 DIS

Title


Date: Sheet of



A2


M14 DIS

SSID = CPU

Need place Pull Hiat IMVP page

R803, R804, R805 need close to CPUAlert# signal must be routed between the Clock and Datalines to reduce the cross talk between them

1. PH/PL resisors place close CPU2. SENSE signal recommend differential routing


ULV 33A

Layout Note:

Layout Note:

Layout Note:

5

4

8.5

1.2

0.3~1.52

0~1.52

Voltage RailVCC_CORE

VAXG

VCCIO

VCCSA

VDDQ 1.5

Voltage(V)

1.8

1.05

Iccmax(A)33

29 (GT2)

0.675~0.9

Refer to CPU EDS V.1.7.5

VCCPLL

VCCPQ Output Decoupling CAP Recommendation:1 x 1 uF (0402)

8.5A

1

2

C842SC1U6D3V2KX

-GP

DY

C842SC1U6D3V2KX

-GP

DY

1 2

R80343R2J-GPR80343R2J-GP

1

2

C822SC2D2U6D3V2M

X-G

PC822

SC2D2U6D3V2MX

-GP

1

2

C887SC1U6D3V2KX

-GP

DY

C887SC1U6D3V2KX

-GP

DY

1

2

C838SC1U6D3V2KX

-GP

C838SC1U6D3V2KX

-GP

1

2

C846SC1U6D3V2KX

-GP

C846SC1U6D3V2KX

-GP

1

2

C885SC10U6D3V3M

X-G

PC885

SC10U6D3V3MX

-GP

1

2

C823SC2D2U6D3V2M

X-G

P

DY

C823SC2D2U6D3V2M

X-G

P

DY

1

2

C843SC1U6D3V2KX

-GP

DY

C843SC1U6D3V2KX

-GP

DY

1

2

R80710R2F-L-GPR80710R2F-L-GP

1

2

C831SC1U6D3V2KX

-GP

C831SC1U6D3V2KX

-GP

1

2

C805SC22U6D3V5M

X-2G

PC805

SC22U6D3V5MX

-2GP

1

2

C833SC1U6D3V2KX

-GP

C833SC1U6D3V2KX

-GP

1

2

C817SC2D2U6D3V2M

X-G

PC817

SC2D2U6D3V2MX

-GP

1

2

C811SC10U6D3V3M

X-G

PC811

SC10U6D3V3MX

-GP

1

2

C889SC10U6D3V3M

X-G

P

DY

C889SC10U6D3V3M

X-G

P

DY

1

2

C814SC2D2U6D3V2M

X-G

PC814

SC2D2U6D3V2MX

-GP

1

2

C890SC1U6D3V2KX

-GP

C890SC1U6D3V2KX

-GP

1

2

C847SC1U6D3V2KX

-GP

DY

C847SC1U6D3V2KX

-GP

DY

1

2

C893SC10U6D3V3M

X-G

P

DY

C893SC10U6D3V3M

X-G

P

DY

1

2

C844SC1U6D3V2KX

-GP

C844SC1U6D3V2KX

-GP

1

2

C892SC10U6D3V3M

X-G

PC892

SC10U6D3V3MX

-GP

1

2

R80575R2F-2-GP

R80575R2F-2-GP

1

2

C896SC10U6D3V3M

X-G

P

DY

C896SC10U6D3V3M

X-G

P

DY

1

2

C834SC1U6D3V2KX

-GP

C834SC1U6D3V2KX

-GP

1

2

C801SC22U6D3V5M

X-2G

PC801

SC22U6D3V5MX

-2GP

1

2

C895SC10U6D3V3M

X-G

PC895

SC10U6D3V3MX

-GP

1

2

C891SC1U6D3V2KX

-GP

DY

C891SC1U6D3V2KX

-GP

DY

1

2

C848SC1U6D3V2KX

-GP

DY

C848SC1U6D3V2KX

-GP

DY

1

2

C845SC1U6D3V2KX

-GP

C845SC1U6D3V2KX

-GP

1

2

C824SC2D2U6D3V2M

X-G

PC824

SC2D2U6D3V2MX

-GP

1

2

C818SC2D2U6D3V2M

X-G

P

DY

C818SC2D2U6D3V2M

X-G

P

DY

1

2

C835SC1U6D3V2KX

-GP

DY

C835SC1U6D3V2KX

-GP

DY

1

2

C837SC1U6D3V2KX

-GP

DY

C837SC1U6D3V2KX

-GP

DY

1

2

R802100R2F-L1-GP-UR802100R2F-L1-GP-U

1

2

R80610R2F-L-GPR80610R2F-L-GP

1

2

C803SC22U6D3V5M

X-2G

PC803

SC22U6D3V5MX

-2GP

1

2

C806SC22U6D3V5M

X-2G

PC806

SC22U6D3V5MX

-2GP

1

2

C897SC10U6D3V3M

X-G

P

DY

C897SC10U6D3V3M

X-G

P

DY

VCC_SENSE F43VSS_SENSE G43

VIDALERT# A44VIDSCLK B43VIDSOUT C44

VSS_SENSE_VCCIO AN17

VCC1A26VCC2A29VCC3A31VCC4A34VCC5A35VCC6A38VCC7A39VCC8A42VCC9C26VCC10C27VCC11C32VCC12C34VCC13C37VCC14C39VCC15C42VCC16D27VCC17D32VCC18D34VCC19D37VCC20D39VCC21D42VCC22E26VCC23E28VCC24E32VCC25E34VCC26E37VCC27E38VCC28F25VCC29F26VCC30F28VCC31F32VCC32F34VCC33F37VCC34F38VCC35F42VCC36G42VCC37H25VCC38H26VCC39H28VCC40H29VCC41H32VCC42H34VCC43H35VCC44H37VCC45H38VCC46H40VCC47J25VCC48J26VCC49J28VCC50J29VCC51J32VCC52J34VCC53J35VCC54J37VCC55J38VCC56J40VCC57J42VCC58K26VCC59K27VCC60K29VCC61K32VCC62K34VCC63K35VCC64K37VCC66K39VCC67K42VCC68L25VCC69L28VCC70L33VCC71L36VCC72L40VCC73N26VCC74N30VCC75N34VCC76N38

VCCIO1 AF46VCCIO3 AG48VCCIO4 AG50VCCIO5 AG51VCCIO6 AJ17VCCIO7 AJ21VCCIO8 AJ25VCCIO9 AJ43

VCCIO10 AJ47VCCIO11 AK50VCCIO12 AK51VCCIO13 AL14VCCIO14 AL15VCCIO15 AL16VCCIO16 AL20VCCIO17 AL22VCCIO18 AL26VCCIO19 AL45VCCIO20 AL48VCCIO21 AM16VCCIO22 AM17VCCIO23 AM21VCCIO24 AM43VCCIO25 AM47VCCIO26 AN20VCCIO27 AN42VCCIO28 AN45VCCIO29 AN48

VCCIO30 AA14VCCIO31 AA15VCCIO32 AB17VCCIO33 AB20VCCIO34 AC13VCCIO35 AD16VCCIO36 AD18VCCIO37 AD21VCCIO38 AE14VCCIO39 AE15VCCIO40 AF16VCCIO41 AF18VCCIO42 AF20VCCIO43 AG15VCCIO44 AG16VCCIO45 AG17VCCIO46 AG20VCCIO47 AG21VCCIO48 AJ14VCCIO49 AJ15

VCCIO50 W16VCCIO51 W17

VCCPQE1 AM25VCCPQE2 AN22

VCCIO_SENSE AN16

VCCIO_SEL BC22

POWER

C

O

R

E

S

U

P

P

L

Y

P

E

G

I

O

A

N

D

D

D

R

I

O

S

E

N

S

E

L

I

N

E

S

S

V

I

D

Q

U

I

E

T

R

A

I

L

S

6 OF 9CPU1F


POWER

C

O

R

E

S

U

P

P

L

Y

P

E

G

I

O

A

N

D

D

D

R

I

O

S

E

N

S

E

L

I

N

E

S

S

V

I

D

Q

U

I

E

T

R

A

I

L

S

6 OF 9CPU1F


1

2

C819SC2D2U6D3V2M

X-G

PC819

SC2D2U6D3V2MX

-GP

1

2

C809SC10U6D3V3M

X-G

PC809

SC10U6D3V3MX

-GP

1

2

C825SC2D2U6D3V2M

X-G

P

DY

C825SC2D2U6D3V2M

X-G

P

DY

1 TP801TP801

1

2

C881SC1U6D3V2KX

-GP

C881SC1U6D3V2KX

-GP

1

2

C826SC2D2U6D3V2M

X-G

PC826

SC2D2U6D3V2MX

-GP

1

2

C888SC10U6D3V3M

X-G

PC888

SC10U6D3V3MX

-GP

1

2

C883SC1U6D3V2KX

-GP

C883SC1U6D3V2KX

-GP

1

2

C839SC1U6D3V2KX

-GP

C839SC1U6D3V2KX

-GP

1

2

C808SC10U6D3V3M

X-G

PC808

SC10U6D3V3MX

-GP

1

2

C820SC2D2U6D3V2M

X-G

PC820

SC2D2U6D3V2MX

-GP

1

2

C812SC10U6D3V3M

X-G

PC812

SC10U6D3V3MX

-GP

1

2

C816SC2D2U6D3V2M

X-G

PC816

SC2D2U6D3V2MX

-GP

1

2

C830SC1U6D3V2KX

-GP

C830SC1U6D3V2KX

-GP

12

R8120R0402-PADR8120R0402-PAD

1

2

C827SC2D2U6D3V2M

X-G

P

DY

C827SC2D2U6D3V2M

X-G

P

DY

1

2

C813SC10U6D3V3M

X-G

PC813

SC10U6D3V3MX

-GP

1

2

C886SC1U6D3V2KX

-GP

C886SC1U6D3V2KX

-GP

1

2

C821SC2D2U6D3V2M

X-G

PC821

SC2D2U6D3V2MX

-GP

1

2

C840SC1U6D3V2KX

-GP

DY

C840SC1U6D3V2KX

-GP

DY

1

2

C894SC4D

7U6D3V3KX-G

PC894

SC4D7U6D3V3KX

-GP

1

2

C828SC2D2U6D3V2M

X-G

PC828

SC2D2U6D3V2MX

-GP

1

2

C836SC1U6D3V2KX

-GP

C836SC1U6D3V2KX

-GP

1

2

R801100R2F-L1-GP-UR801100R2F-L1-GP-U

1

2

C804SC22U6D3V5M

X-2G

PC804

SC22U6D3V5MX

-2GP

1

2

C807SC22U6D3V5M

X-2G

PC807

SC22U6D3V5MX

-2GP

1

2

C841SC1U6D3V2KX

-GP

C841SC1U6D3V2KX

-GP

1

2

C810SC10U6D3V3M

X-G

PC810

SC10U6D3V3MX

-GP

1

2

C802SC1U6D3V2KX-GPC802SC1U6D3V2KX-GP

1

2

C829SC2D2U6D3V2M

X-G

P

DY

C829SC2D2U6D3V2M

X-G

P

DY

1

2

C884SC4D

7U6D3V3KX-G

PC884

SC4D7U6D3V3KX

-GP

1

2

C815SC2D2U6D3V2M

X-G

PC815

SC2D2U6D3V2MX

-GP

1

2

R804130R2F-1-GPR804130R2F-1-GP

1

2

C832SC1U6D3V2KX

-GP

C832SC1U6D3V2KX

-GP

1

2

C882SC1U6D3V2KX

-GP

C882SC1U6D3V2KX

-GP

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC_AXG_SENSEVSS_AXG_SENSE

DDR_WR_VREFBDDR_WR_VREFA

TP_VDDQ_SENSETP_VDDQ_VSS

VCCSA_SEL0VCCSA_SEL1

VCCSA_SENSE

VCC_GFXCORE

0D85V_S0

+V_SM_VREF_CNT

1D5V_S0

1D5V_S0+V1.5S_VCCD_Q

VCC_GFXCORE

1D8V_S0

VCC_AXG_SENSE44VSS_AXG_SENSE44

VCCSA_SEL1 48

VCCSA_SENSE 48

VCCSA_SEL0 48

Title


Date: Sheet of


OAK14 Chief River DIS A00CPU (VCC_GFXCORE)

A2


M14 DIS

Title


Date: Sheet of



A2


M14 DIS

Title


Date: Sheet of



A2


M14 DIS

SSID = CPU


+V_SM_VREF_CNT should have 10 mil trace width

0.9

VCCSA Power Select

0

VID[0] VID[1]

0

0.85

0.775

0.75

Voltage(ULV)

0 1

01

11

5A

Layout Note:

Layout Note:

ULV 4A

5

3

8.5

1.2

0.3~1.52

0~1.52

Voltage RailVCC_CORE

VAXG

VCCIO

VCCSA

VDDQ 1.5

Voltage(V)

1.8

1.05

Iccmax(A)33

29 (GT2)

0.675~0.9

Refer to CPU EDS V2.0

VCCPLL

ULV GT2 33A

1.2A

1

2

C911SC10U6D3V3M

X-G

P

DY

C911SC10U6D3V3M

X-G

P

DY

1

2

C948SC1U6D3V2KX

-GP

DY

C948SC1U6D3V2KX

-GP

DY

1

2

C915SC1U6D3V2KX

-GP

C915SC1U6D3V2KX

-GP

1

2

C925SC4D

7U6D3V3KX-G

PC925SC4D

7U6D3V3KX-G

P

1

2

C944SC1U6D3V2KX

-GP

DY

C944SC1U6D3V2KX

-GP

DY

1

2

C907SC1U6D3V2KX

-GP

C907SC1U6D3V2KX

-GP

1

2

C951SC1U6D3V2KX

-GP

DY

C951SC1U6D3V2KX

-GP

DY

1

2

C946SC1U6D3V2KX

-GP

C946SC1U6D3V2KX

-GP

1

2

C926SC10U6D3V3M

X-G

PC926SC10U6D3V3M

X-G

P

1

2

C936SC1U6D3V2KX

-GP

C936SC1U6D3V2KX

-GP

1

2

C922SC10U6D3V3M

X-G

PC922SC10U6D3V3M

X-G

P

1

2

C912SC10U6D3V3M

X-G

P

DY

C912SC10U6D3V3M

X-G

P

DY

1

2

C927SC1U6D3V2KX

-GP

C927SC1U6D3V2KX

-GP

1

2

C902SC10U6D3V5KX

-1GP

C902SC10U6D3V5KX

-1GP

12

R9030R0402-PADR9030R0402-PAD

1

2

C952SC1U6D3V2KX

-GP

C952SC1U6D3V2KX

-GP

1

2

C929SC1U6D3V2KX

-GP

C929SC1U6D3V2KX

-GP

1

2

C932SC1U6D3V2KX

-GP

C932SC1U6D3V2KX

-GP

1

2

C919SC10U6D3V3M

X-G

PC919SC10U6D3V3M

X-G

P

1

2

C934SC1U6D3V2KX

-GP

C934SC1U6D3V2KX

-GP

1

2

C953SC1U6D3V2KX

-GP

C953SC1U6D3V2KX

-GP

1

2

C923SC10U6D3V3M

X-G

PC923SC10U6D3V3M

X-G

P

1

2

C901SC22U6D3V5M

X-2G

PC901SC22U6D3V5M

X-2G

P

1

2

C955SC10U6D3V5KX

-1GP

DY

C955SC10U6D3V5KX

-1GP

DY

1

2

C942SC10U6D3V3M

X-G

PC942SC10U6D3V3M

X-G

P1

2

C921SC10U6D3V3M

X-G

P

DY

C921SC10U6D3V3M

X-G

P

DY

1 TP902 TPAD14-OP-GPTP902 TPAD14-OP-GP

1

2

C916SC1U6D3V2KX

-GP

C916SC1U6D3V2KX

-GP

1

2

C914SC1U6D3V2KX

-GP

C914SC1U6D3V2KX

-GP

1

2

C954SC1U6D3V2KX

-GP

C954SC1U6D3V2KX

-GP

1

2

C917SC1U6D3V2KX

-GP

DY

C917SC1U6D3V2KX

-GP

DY

1

2

C931SC1U6D3V2KX

-GP

DY

C931SC1U6D3V2KX

-GP

DY

1

2

C906SC22U6D3V5M

X-2G

PC906SC22U6D3V5M

X-2G

P

1

2

C949SC1U6D3V2KX

-GP

C949SC1U6D3V2KX

-GP

1

2

C910SC10U6D3V3M

X-G

PC910SC10U6D3V3M

X-G

P

1

2

C924SC10U6D3V3M

X-G

PC924SC10U6D3V3M

X-G

P

1

2

C928SC1U6D3V2KX

-GP

C928SC1U6D3V2KX

-GP

1

2

C941SC10U6D3V3M

X-G

PC941SC10U6D3V3M

X-G

P

1

2

C947SC1U6D3V2KX

-GP

C947SC1U6D3V2KX

-GP

1

2

C933SC1U6D3V2KX

-GP

C933SC1U6D3V2KX

-GP

1

2

C937SC1U6D3V2KX

-GP

C937SC1U6D3V2KX

-GP

1

2

C939SC10U6D3V3M

X-G

PC939SC10U6D3V3M

X-G

P

1

2

C913SC10U6D3V3M

X-G

PC913SC10U6D3V3M

X-G

P

1

2

C904SC10U6D3V5KX

-1GP

C904SC10U6D3V5KX

-1GP

123

4

RN902

SRN1KJ-7-GP

DY

RN902

SRN1KJ-7-GP

DY

1

2

C905SC22U6D3V5M

X-2G

PC905SC22U6D3V5M

X-2G

P

1

2

C920SC10U6D3V3M

X-G

PC920SC10U6D3V3M

X-G

P

1

2

C930SC1U6D3V2KX

-GP

C930SC1U6D3V2KX

-GP

1

2

C935SC1U6D3V2KX

-GP

DY

C935SC1U6D3V2KX

-GP

DY

1

2

C945SC1U6D3V2KX

-GP

C945SC1U6D3V2KX

-GP

SM_VREF AY43VAXG1AA46VAXG2AB47VAXG3AB50VAXG4AB51VAXG5AB52VAXG6AB53VAXG7AB55VAXG8AB56VAXG9AB58VAXG10AB59VAXG11AC61VAXG12AD47VAXG13AD48VAXG14AD50VAXG15AD51VAXG16AD52VAXG17AD53VAXG18AD55VAXG19AD56VAXG20AD58VAXG21AD59VAXG22AE46VAXG23N45VAXG24P47VAXG25P48VAXG26P50VAXG27P51VAXG28P52VAXG29P53VAXG30P55VAXG31P56VAXG32P61VAXG33T48VAXG34T58VAXG35T59VAXG36T61VAXG37U46VAXG38V47VAXG39V48VAXG40V50VAXG41V51VAXG42V52VAXG43V53VAXG44V55VAXG45V56VAXG46V58VAXG47V59VAXG48W50VAXG49W51VAXG50W52VAXG51W53VAXG52W55VAXG53W56VAXG54W61

VDDQ11 AM40VDDQ12 AN30VDDQ13 AN34VDDQ14 AN38VDDQ15 AR26

VDDQ1 AJ28VDDQ2 AJ33VDDQ3 AJ36VDDQ4 AJ40VDDQ5 AL30VDDQ6 AL34VDDQ7 AL38VDDQ8 AL42VDDQ9 AM33

VDDQ10 AM36

VCCPLL1BB3VCCPLL2BC1

VCCSA_SENSE U10

VCCSA_VID1 D49

VAXG55Y48VAXG56Y61

VCCPLL3BC4

VAXG_SENSEF45VSSAXG_SENSEG45

VCCSA1L17

VCCSA10R21

VCCSA12V16VCCSA13V17VCCSA14V18

VCCSA4N20VCCSA5N22VCCSA6P17

VCCSA9R18

VDDQ16 AR28VDDQ17 AR30VDDQ18 AR32VDDQ19 AR34VDDQ20 AR36VDDQ21 AR40VDDQ22 AV41VDDQ23 AW26VDDQ24 BA40VDDQ25 BB28VDDQ26 BG33

VCCSA11U15

VCCSA15V21VCCSA16W20

VCCSA2L21VCCSA3N16

VCCDQ1 AM28VCCDQ2 AN26

VCCSA7P20VCCSA8R16

VDDQ_SENSE BC43VSS_SENSE_VDDQ BA43

VCCSA_VID0 D48

SA_DIMM_VREFDQ BE7SB_DIMM_VREFDQ BG7

POWER

G

R

A

P

H

I

C

S

D

D

R

3

-

1

.

5

V

R

A

I

L

S

1

.

8

V

R

A

I

L

S

E

N

S

E

L

I

N

E

S

S

A

R

A

I

L

S

E

N

S

E

L

I

N

E

S

Q

U

I

E

T

R

A

I

L

S

V

R

E

F

V

C

C

S

A

V

I

D

l

i

n

e

s

7 OF 9CPU1G


POWER

G

R

A

P

H

I

C

S

D

D

R

3

-

1

.

5

V

R

A

I

L

S

1

.

8

V

R

A

I

L

S

E

N

S

E

L

I

N

E

S

S

A

R

A

I

L

S

E

N

S

E

L

I

N

E

S

Q

U

I

E

T

R

A

I

L

S

V

R

E

F

V

C

C

S

A

V

I

D

l

i

n

e

s

7 OF 9CPU1G


1

2

C918SC1U6D3V2KX

-GP

DY

C918SC1U6D3V2KX

-GP

DY

1

2

C903SC22U6D3V5M

X-2G

PC903SC22U6D3V5M

X-2G

P

1

2

R902100R2F-L1-GP-U

R902100R2F-L1-GP-U

1

2

C950SC1U6D3V2KX

-GP

DY

C950SC1U6D3V2KX

-GP

DY

1

2

C940SC10U6D3V3M

X-G

P

DY

C940SC10U6D3V3M

X-G

P

DY

1

2

R901100R2F-L1-GP-U

R901100R2F-L1-GP-U

1

2

C909SC10U6D3V3M

X-G

PC909SC10U6D3V3M

X-G

P

1 TP901 TPAD14-OP-GPTP901 TPAD14-OP-GP

1

2

C938SC10U6D3V3M

X-G

PC938SC10U6D3V3M

X-G

P

12

3 4

RN901SRN1KJ-7-GPRN901SRN1KJ-7-GP

1

2

C908SC1U6D3V2KX

-GP

C908SC1U6D3V2KX

-GP

1

2

C943SC10U6D3V3M

X-G

PC943SC10U6D3V3M

X-G

P

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


OAK14 Chief River DIS A00CPU (VSS)

A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

SSID = CPU

VSS1A13VSS2A17VSS3A21VSS4A25VSS5A28VSS6A33VSS7A37VSS8A40VSS9A45VSS10A49VSS11A53VSS12A9VSS13AA1VSS14AA13VSS15AA50VSS16AA51VSS17AA52VSS18AA53VSS19AA55VSS20AA56VSS21AA8VSS22AB16VSS23AB18VSS24AB21VSS25AB48VSS26AB61VSS27AC10VSS28AC14VSS29AC46VSS30AC6VSS31AD17VSS32AD20VSS33AD4VSS34AD61VSS35AE13VSS36AE8VSS37AF1VSS38AF17VSS39AF21VSS40AF47VSS41AF48VSS42AF50VSS43AF51VSS44AF52VSS45AF53VSS46AF55VSS47AF56VSS48AF58VSS49AF59VSS50AG10VSS51AG14VSS52AG18VSS53AG47VSS54AG52VSS55AG61VSS56AG7VSS57AH4VSS58AH58VSS59AJ13VSS60AJ16VSS61AJ20VSS62AJ22VSS63AJ26VSS64AJ30VSS65AJ34VSS66AJ38VSS67AJ42VSS68AJ45VSS69AJ48VSS70AJ7VSS71AK1VSS72AK52VSS73AL10VSS74AL13VSS75AL17VSS76AL21VSS77AL25VSS78AL28VSS79AL33VSS80AL36VSS81AL40VSS82AL43VSS83AL47VSS84AL61VSS85AM13VSS86AM20VSS87AM22VSS88AM26VSS89AM30VSS90AM34

VSS91 AM38VSS92 AM4VSS93 AM42VSS94 AM45VSS95 AM48VSS96 AM58VSS97 AN1VSS98 AN21VSS99 AN25

VSS100 AN28VSS101 AN33VSS102 AN36VSS103 AN40VSS104 AN43VSS105 AN47VSS106 AN50VSS107 AN54VSS108 AP10VSS109 AP51VSS110 AP55VSS111 AP7VSS112 AR13VSS113 AR17VSS114 AR21VSS115 AR41VSS116 AR48VSS117 AR61VSS118 AR7VSS119 AT14VSS120 AT19VSS121 AT36VSS122 AT4VSS123 AT45VSS124 AT52VSS125 AT58VSS126 AU1VSS127 AU11VSS128 AU28VSS129 AU32VSS130 AU51VSS131 AU7VSS132 AV17VSS133 AV21VSS134 AV22VSS135 AV34VSS136 AV40VSS137 AV48VSS138 AV55VSS139 AW13VSS140 AW43VSS141 AW61VSS142 AW7VSS143 AY14VSS144 AY19VSS145 AY30VSS146 AY36VSS147 AY4VSS148 AY41VSS149 AY45VSS150 AY49VSS151 AY55VSS152 AY58VSS153 AY9VSS154 BA1VSS155 BA11VSS156 BA17VSS157 BA21VSS158 BA26VSS159 BA32VSS160 BA48VSS161 BA51VSS162 BB53VSS163 BC13VSS164 BC5VSS165 BC57VSS166 BD12VSS167 BD16VSS168 BD19VSS169 BD23VSS170 BD27VSS171 BD32VSS172 BD36VSS173 BD40VSS174 BD44VSS175 BD48VSS176 BD52VSS177 BD56VSS178 BD8VSS179 BE5VSS180 BG13

VSS

8 OF 9CPU1H


VSS

8 OF 9CPU1H


VSS181BG17VSS182BG21VSS183BG24VSS184BG28VSS185BG37VSS186BG41VSS187BG45VSS188BG49VSS189BG53VSS190BG9VSS191C29VSS192C35VSS193C40VSS194D10VSS195D14VSS196D18VSS197D22VSS198D26VSS199D29VSS200D35VSS201D4VSS202D40VSS203D43VSS204D46VSS205D50VSS206D54VSS207D58VSS208D6VSS209E25VSS210E29VSS211E3VSS212E35VSS213E40VSS214F13VSS215F15VSS216F19VSS217F29VSS218F35VSS219F40VSS220F55VSS221G51VSS222G6VSS223G61VSS224H10VSS225H14VSS226H17VSS227H21VSS228H4VSS229H53VSS230H58VSS231J1VSS232J49VSS233J55VSS234K11VSS235K21VSS236K51VSS237K8VSS238L16VSS239L20VSS240L22VSS241L26VSS242L30VSS243L34VSS244L38VSS245L43VSS246L48

VSS268 P14VSS269 P16VSS270 P18VSS271 P21VSS272 P58VSS273 P59VSS274 P9VSS275 R17VSS276 R20VSS277 R4VSS278 R46VSS279 T1VSS280 T47VSS281 T50VSS282 T51VSS283 T52VSS284 T53VSS285 T55VSS286 T56VSS287 U13VSS288 U8VSS289 V20VSS290 V61

VSS_NCTF_1#A5 A5VSS_NCTF_2#A57 A57

VSS_NCTF_3#BC61 BC61VSS_NCTF_8#BG5 BG5

VSS_NCTF_9#BG57 BG57VSS_NCTF_10#C3 C3VSS_NCTF_13#E1 E1

VSS_NCTF_14#E61 E61

VSS250 M4VSS251 M58VSS252 M6VSS253 N1VSS254 N17VSS255 N21VSS256 N25VSS257 N28VSS258 N33VSS259 N36VSS260 N40VSS261 N43VSS262 N47VSS263 N48VSS264 N51VSS265 N52VSS266 N56VSS267 N61

VSS247L61VSS248M11

VSS291 W13VSS292 W15VSS293 W18VSS294 W21VSS295 W46VSS296 W8VSS297 Y4VSS298 Y47VSS299 Y58VSS300 Y59

VSS249M15VSS_NCTF_4 BD3VSS_NCTF_5 BD59VSS_NCTF_6 BE4VSS_NCTF_7 BE58

VSS_NCTF_11 C58VSS_NCTF_12 D59

VSS

9 OF 9

N

C

T

F

N

C

T

F

T

E

S

T

P

I

N

A

5

,

A

5

7

,

B

C

6

1

,

B

G

5

B

G

5

7

,

C

3

,

E

1

,

E

6

1

CPU1I


VSS

9 OF 9

N

C

T

F

N

C

T

F

T

E

S

T

P

I

N

A

5

,

A

5

7

,

B

C

6

1

,

B

G

5

B

G

5

7

,

C

3

,

E

1

,

E

6

1

CPU1I


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


OAK14 Chief River DIS A00XDP

A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

(Blanking)

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


OAK14 Chief River DIS A00Reserved

A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

(Blanking)

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


OAK14 Chief River DIS A00(Reserved)

A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

Title


Date: Sheet of



A3


M14 DIS

(Blanking)

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_DQS#0

M_A_DQS3

M_A_DQS#5

M_A_DQS4

M_A_DQS#6

M_A_DQS5

M_A_DQS#7

M_A_DQS#1

M_A_DQS6

M_A_DQS0

M_A_DQS#2

M_A_DQS7

M_A_DQS1

M_A_DQS#3

M_A_DQS2

M_A_DQS#4



M_A_A6

M_A_A13M_A_A14M_A_A15

M_A_A12

M_A_A0

M_A_DQ40M_A_DQ41M_A_DQ42M_A_DQ43


M_A_DQ0





M_A_DQ1


M_A_DQ24

M_A_DQ2



M_A_DQ28

M_A_DQ3



M_A_DQ32



M_A_DQ7



SA0_DIMASA1_DIMA

SA0_DIMASA1_DIMA

3D3V_S0

0D75V_S0

M_VREF_DQ_DIMMAM_VREF_CA_DIMMA

1D5V_S3

0D75V_S0

1D5V_S31D5V_S0

DDR_VREF_S3

M_VREF_CA_DIMMA

M_VREF_DQ_DIMMA

DDR_VREF_S3

1D5V_S3

M_A_A[15:0]6

M_A_BS26

M_A_BS06M_A_BS16

M_A_DQ[63:0]6

DDR3_DRAMRST#15,37

M_A_DIMA_ODT06M_A_DIMA_ODT16

M_A_DQS#[7:0]6

M_A_DQS[7:0]6

PCH_SMBCLK 15,20,69PCH_SMBDATA 15,20,69

M_A_WE# 6

M_A_DIMA_CS#0 6

M_A_CAS# 6

M_A_DIMA_CKE0 6M_A_DIMA_CKE1 6

M_A_DIMA_CS#1 6



M_A_RAS# 6

Title


Date: Sheet of


DNE40 14 CR DIS A00DDR3-SODIMM1

A2


M14 DIS

Title


Date: Sheet of



A2


M14 DIS

Title


Date: Sheet of



A2


M14 DIS

Layout Note:Place these capsclose to VREF_DQ

Note:SA0 DIM0 = 0, SA1_DIM0 = 0SO-DIMMA SPD Address is 0xA0SO-DIMMA TS Address is 0x30

Layout Note:

Layout Note:For S3 reduction circuit's 1D5V return pass.

SSID = MEMORY

Layout Note:Place these capsclose to VREF_CA

All VREF traces shouldhave width=20mil; spacing=20 mil

Layout Note:Place these Caps near SO-DIMMA.

Layout Note:Place these capsclose to VTT1 andVTT2.

Close to DIMM1.199

1

2

C

1

4

0

8

S

C

1

0

U

1

0

V

5

Z

Y

-

1

G

P

DY

C

1

4

0

8

S

C

1

0

U

1

0

V

5

Z

Y

-

1

G

P

DY

1

2

C

1

4

1

4

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

4

1

4

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

R14020R0402-PADR14020R0402-PAD

1

2

C

1

4

2

7

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

4

2

7

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

C

1

4

1

5

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

4

1

5

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1 2EC1401SCD1U10V2KX-5GPDY

EC1401SCD1U10V2KX-5GPDY

1

2

C

1

4

0

5

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

DY

C

1

4

0

5

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

DY

1

2

C

1

4

0

7

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

DY

C

1

4

0

7

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

DY

1

2

R14010R0402-PAD

R14010R0402-PAD

1

2

C

1

4

1

7

S

C

1

U

6

D

3

V

2

K

X

-

G

P

C

1

4

1

7

S

C

1

U

6

D

3

V

2

K

X

-

G

P

A098A197A296A395A492A591A690A786A889A985A10/AP107A1184A1283A13119A1480A1578A16/BA279

BA0109BA1108

DQ05DQ17DQ215DQ317DQ44DQ56DQ616DQ718DQ821DQ923DQ1033DQ1135DQ1222DQ1324DQ1434DQ1536DQ1639DQ1741DQ1851DQ1953DQ2040DQ2142DQ2250DQ2352DQ2457DQ2559DQ2667DQ2769DQ2856DQ2958DQ3068DQ3170DQ32129DQ33131DQ34141DQ35143DQ36130DQ37132DQ38140DQ39142DQ40147DQ41149DQ42157DQ43159DQ44146DQ45148DQ46158DQ47160DQ48163DQ49165DQ50175DQ51177DQ52164DQ53166DQ54174DQ55176DQ56181DQ57183DQ58191DQ59193DQ60180DQ61182DQ62192DQ63194

DQS0#10DQS1#27DQS2#45DQS3#62DQS4#135DQS5#152DQS6#169DQS7#186

DQS012DQS129DQS247DQS364DQS4137DQS5154DQS6171DQS7188

ODT0116ODT1120

VREF_DQ1

VSS 2

NP1 NP1NP2 NP2

RAS# 110WE# 113

CAS# 115

CS0# 114CS1# 121

CKE0 73CKE1 74

CK0 101CK0# 103

CK1 102CK1# 104

DM0 11DM1 28DM2 46DM3 63DM4 136DM5 153DM6 170DM7 187

SDA 200SCL 202

VDDSPD 199

SA0 197SA1 201

VREF_CA126

VDD18 124

NC#1 77NC#2 122

NC#/TEST 125

VDD3 81VDD4 82VDD5 87VDD6 88VDD7 93VDD8 94VDD9 99

VDD10 100

VDD13 111VDD14 112VDD15 117VDD16 118

VSS 3VSS 8VSS 9VSS 13VSS 14VSS 19VSS 20VSS 25VSS 26VSS 31VSS 32VSS 37VSS 38VSS 43VSS 44VSS 48VSS 49VSS 54VSS 55VSS 60VSS 61

VDD1 75

VSS 65VSS 66VSS 71VSS 72

VDD2 76

VDD11 105VDD12 106

VDD17 123

VSS 127VSS 128

VSS 134VSS 133


VSS 151VSS 150

VSS 155VSS 156VSS 161VSS 162VSS 167VSS 168

VSS 173VSS 172

VSS 179VSS 178

VSS 185VSS 184


RESET#30

EVENT# 198

VSS 205VSS 206

VTT1203VTT2204

DM1

DDR3-204P-119-GP-U62.10017.Z81

DM1

DDR3-204P-119-GP-U62.10017.Z81

1 2

C1424SCD1U10V2KX-5GP

DYC1424

SCD1U10V2KX-5GP

DY1

2



1

2

C

1

4

0

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

4

0

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

1

4

2

6

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

4

2

6

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1 2


DYC1421

SCD1U10V2KX-5GP

DY

1

2

C

1

4

1

8

S

C

1

U

6

D

3

V

2

K

X

-

G

P

C

1

4

1

8

S

C

1

U

6

D

3

V

2

K

X

-

G

P

1

2

C

1

4

1

1

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

4

1

1

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

C

1

4

1

9

S

C

1

U

6

D

3

V

2

K

X

-

G

P

C

1

4

1

9

S

C

1

U

6

D

3

V

2

K

X

-

G

P

1

2

C

1

4

0

4

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

4

0

4

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

1

4

0

3

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

DY

C

1

4

0

3

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

DY

1

2

C

1

4

2

9

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

4

2

9

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

R14040R0402-PADR14040R0402-PAD

1

2

C

1

4

2

8

S

C

2

D

2

U

1

0

V

3

K

X

-

1

G

PDY

C

1

4

2

8

S

C

2

D

2

U

1

0

V

3

K

X

-

1

G

PDY

1

2

C

1

4

1

6

S

C

1

U

6

D

3

V

2

K

X

-

G

P

C

1

4

1

6

S

C

1

U

6

D

3

V

2

K

X

-

G

P

1

2

C

1

4

2

3

S

C

2

D

2

U

1

0

V

3

K

X

-

1

G

PDY

C

1

4

2

3

S

C

2

D

2

U

1

0

V

3

K

X

-

1

G

PDY

1

2

C

1

4

2

0

S

C

1

U

6

D

3

V

2

K

X

-

G

P

DY

C

1

4

2

0

S

C

1

U

6

D

3

V

2

K

X

-

G

P

DY

1

2

R14050R0402-PADR14050R0402-PAD

1

2

T

C

1

4

0

1

S

T

3

3

0

U

2

V

D

M

-

4

-

G

P

DY TC

1

4

0

1

S

T

3

3

0

U

2

V

D

M

-

4

-

G

P

DY

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SA1_DIMB

SA0_DIMB

M_B_DQ42M_B_DQ41M_B_DQ40

M_B_DQ43


M_B_DQ15

M_B_DQ0


M_B_DQ47




M_B_DQ1

M_B_DQ53M_B_DQ52

M_B_DQ24

M_B_DQ55M_B_DQ54


M_B_DQ2

M_B_DQ57M_B_DQ56

M_B_DQ59M_B_DQ58


M_B_DQ3


M_B_DQ33M_B_DQ32

M_B_DQ35M_B_DQ34

M_B_DQ5M_B_DQ4

M_B_DQ7M_B_DQ6


M_B_DQ8


M_B_DQS#0

M_B_DQS3

M_B_DQS#5

M_B_DQS4

M_B_DQS#6

M_B_DQS5

M_B_DQS#7

M_B_DQS#1

M_B_DQS6

M_B_DQS0

M_B_DQS#2

M_B_DQS7

M_B_DQS1

M_B_DQS#3

M_B_DQS2

M_B_DQS#4

M_B_A1M_B_A2M_B_A3M_B_A4M_B_A5

M_B_A7M_B_A6

M_B_A11M_B_A10M_B_A9M_B_A8

M_B_A12

M_B_A15M_B_A14M_B_A13

M_B_A0

SA0_DIMBSA1_DIMB

3D3V_S0

M_VREF_CA_DIMMBM_VREF_DQ_DIMMB

0D75V_S0

1D5V_S3

1D5V_S3

0D75V_S0

DDR_VREF_S3

M_VREF_CA_DIMMB

M_VREF_DQ_DIMMB

DDR_VREF_S3

3D3V_S0

M_B_A[15:0]6

M_B_BS06

M_B_BS26

M_B_BS16M_B_DQ[63:0]6

M_B_DQS[7:0]6

M_B_DQS#[7:0]6

M_B_DIMB_ODT06M_B_DIMB_ODT16

DDR3_DRAMRST#14,37

PCH_SMBCLK 14,20,69PCH_SMBDATA 14,20,69

M_B_WE# 6

M_B_DIMB_CS#0 6

M_B_CAS# 6

M_B_DIMB_CKE0 6M_B_DIMB_CKE1 6

M_B_DIMB_CS#1 6



M_B_RAS# 6

Title


Date: Sheet of


OAK14 Chief River DIS A00DDR3-SODIMM2

A2


M14 DIS

Title


Date: Sheet of



A2


M14 DIS

Title


Date: Sheet of



A2


M14 DIS

Layout Note:

Layout Note:Place these capsclose to VREF_DQ

Layout Note:Place these capsclose to VTT1 andVTT2.

Layout Note:

SSID = MEMORY

All VREF traces shouldhave width=20mil; spacing=20 mil

Place these capsclose to VREF_CA

Note:SO-DIMMB SPD Address is 0xA4SO-DIMMB TS Address is 0x34

Layout Note:Place these Caps near SO-DIMMA.

Close to DIMM1.199

1

2



1

2

C

1

5

1

0

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

5

1

0

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

1

5

1

7

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

5

1

7

S

C

D

1

U

1

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Documents

inspiron 5421 14r 1220-4-1 dne40-cr-mb 5j8y4 OAK14_CR_SCHEMATIC_A00_MB_0905-2.pdf