ISCS 2008

InGaAs MOSFET with self-aligned Source/Drain

by MBE regrowth

Uttam Singisetti*, Mark A. Wistey, Greg J. Burek, Erdem Arkun, Ashish K. Baraskar, Brian J. Thibeault, C. J. Palmstrøm, A.C. Gossard, and

M.J.W. Rodwell

ECE and Materials DepartmentsUniversity of California, Santa Barbara, CA, USA

Yanning Sun, Edward W. Kiewra, and D.K. SadanaIBM T J Watson Research Center, Yorktown Heights, NY, USA

2008 International Symposium on Compound SemiconductorsRust, Germany

*uttam@ece.ucsb.edu

ISCS 2008

Outline

• Motivation: III-V MOSFETs

• Approach: Self-aligned source/drain by MBE regrowth

• FET and Contacts Results

• Conclusion

ISCS 2008

Why III-V MOSFETs

Alternative III-V channel materials

Id / Wg = qnsveff Id / Qtransit = veff / Lg

III-V materials→ lower m*→ higher velocities (veff)

scmvvmmAsGaIn theff /105.3~ ,041.0 : 7*47.053.0

Silicon MOSFETs:

• Scaling limit beyond sub-22 nm Lg

• Non-feasibility of sub-0.5 nm equivalent oxide thickness (EOT)

ISCS 2008

22 nm InGaAs MOSFET

InP substrate

InAlAs barrier

metal gate

gL

InGaAs channel

gatedielectric

N+ source N+ drain

source contact drain contact

S/DL

1 Rodwell. IPRM 2008 2 Fischetti. IEDM 2007

-6

-4

-2

0

2

4

0 50 100 150 200 250

En

eg

y(e

V)

Y (Ang.)

InGaAsInAlAs

Al2O3

InP

• 1 nm EOT gate dielectric

• 5 nm channel with back barrier

• 15 m source resistance

• 5×1019 cm-3 source active doping2

Key Challenges

Predicted drive current: ~5 mA/m1,2

ISCS 2008

InGaAs MOSFET with Source/Drain regrowth

substrate

barrier

sidewallmetal gate

InGaAs quantum well

gate dielectric

N+ source N+ drain

source contact drain contact

substrate

barrier

metal gate

InGaAs quantum well

substrate

barrier

metal gate

InGaAs quantum well

substrate

barrier

sidewallmetal gate

InGaAs quantum wellN+ source N+ drain

Process scalable to 22 nm

Source/Drain defined by

MBE regrowth

Regrowth InGaAs, in situ Mo

contact Resistance:

0.5 m2 (2.5 m)*

* Wistey, EMC 2008

ISCS 2008

Gate definition

Ti/Wgate

(starting material)

blanketmetal

oxideInGaAs channel

barrier

SI substrate

blanket gatedeposition

etch gate,etch dielectricetch upper channel

sidewall formationS/D regrowthS/D contacts

side-wall

mesa isolate S/D

InP subchannel

r

well

r

well

r

well

r

Process flow

Sidewall, Source/Drain

ISCS 2008

Gate Definition: Challenges

• Must scale to 22 nm

• Dielectric cap surrounding the gate for source/drain regrowth

• Metal & Dielectric etch must stop in 5 nm channel

• Dry etch must not damage thin channel

r

well

barrierInP well

r

r

iondamage

Process must leave surfaces ready for S/D regrowth

ISCS 2008

Gate Stack: Multiple Layers & Selective Etches

Key: stop etch before reaching dielectric, then gentle low-power etch to stop on dielectric

SiO2

W

Cr

FIB Cross-section

Damage free channel

barrier

InGaAs well

InP well

SI substrate

Cr etch stop

W gate metal

SiO2

Cr etch mask

resist Cl2 / O2etch 15 W

SF6 / Aretch 50 W

Cl2 / O2etch 15 W

SF6 / Aretch 15 W dielectric

KOH wet etchAl2O3 (

r)

Dry etch scheme

Process scalable to sub-100 nm gate lengths

ISCS 2008

Dielectric etch and sidewall formation

barrier

InGaAs well

r

InP well

r

well

barrierInP well

r

r

barrier

InGaAs well

r

InP well

r

dil KOH

40 nm SiNsidewall

Dielectric etch Sidewall definition InGaAs etch

ISCS 2008

Surface cleaning before regrowth

• Clean organics by 30 min UV Ozone

• Ex-situ HCl:H2O clean

• In-situ 30 min H clean

• c(4×2) reconstruction before regrowth

• Defect free regrowth

Interface

HAADF-STEM*

2 nm

InGaAs

InGaAsregrowth

* Wistey, EMC 2008

Epi-ready surface before regrowth, defect free regrowth on processed wafer

ISCS 2008

Height selective Etching*

* Burek, J.Cryst.Growth, submitted for publication

r

r

well well

barrierInP well

barrierInP well

r

r

r

well

barrierInP well

rPlanarize

ICP O2 ash SF6/Ar Mo etch

InGaAs wet etch

r

well

barrierInP well

r

r

well

barrierInP well

rStrip PR

Mo

InGaAs

PR

PR PR

Dummy gateNo regrowth

ISCS 2008

MOSFET characterstics

0

20

40

60

80

100

0 0.5 1 1.5 2

Dra

in C

urre

nt,

uA

Vds, Volts

steps V 0.25in V 2 toV 0V

microns 50 Wmicrons, 10

g

g

gL

0

20

40

60

80

100

0 0.5 1 1.5 2

Dra

in c

urr

ent

( A

)

Vgs

(Volts)

Lg=10m, W

g=50m

Vds

=2V

• Extremely low drive current: 2 A/m• Extremely high Ron= 10-100 k

• Why is Rs so high?

Rs ~ 1 Mm!

ISCS 2008

Rough InGaAs regrowth

After regrowth SEM

Source Resistance 1: Poly Growth on InP

InGaAs regrowth on unprocessed thin InP*

* Wistey (in preparation)

Sheet resistance doesn’t explain 1 MΩ-µm source resistance.

• Spotty RHEED during regrowth: faceted growth• InP desorbs P during hydrogen clean or regrowth: InP converts to highly-

strained InAs*

• From TLM measurement, Rsh= 310 /, c=130 m2 and Rs= 300 m

ISCS 2008

Source Resistance 2: Gap in Regrowth

W / Cr / SiO2

gateW / Cr / SiO2

gate

SEM

No regrowth

Electron depletion No regrowth

SEM

InGaAs regrowth

InGaAs regrowth

• No regrowth within 200 nm of gate because of shadowing by gate

• Gap region is depleted of electrons

• Breakdown at Vg=0V, ~ 8V, consistent with 400 nm gap and InGaAs breakdown field of 20V/m*

0

200

400

600

800

1000

1200

0 2 4 6 8

I d (A

)

Vds

(V)

L = 10 m W=10 m Vg=0.0 V

r

InGaAs

barrier

InP

W

Cr

SiO2N+ regrowthGap~ 200 nm

Electron depletion

High source resistance because of electron depletion in the gap*http://www.ioffe.rssi.ru/SVA/NSM/Semicond/

ISCS 2008

Regrowth: Solutions

*Wistey, EMC 2008 Wistey, ICMBE 2008

smooth InGaAs regrowth on thin InGaP* High T migration enhancedEpitaxial (MEE) regrowth*

regrowth interface

gateNo Gap

ISCS 2008

• Scalable III-V MOSFET process with self-aligned source/drain with MBE regrowth

• Gate proces and H clean leave a epi-ready 5 nm channel

• Low drive current in initial devices because of break in regrowth

• Improved regrowth techniques in next generation of devices

Conclusion

This work was supported by Semiconductor Research Corporation under the Non-classical CMOS Research Program