Improving the thermal management of powerGaN devices

ATW on Thermal Management, Los Gatos

Chenjiang YU1, Cyril BUTTAY2, Éric LABOURÉ1

1 LGEP (GEEPS), Paris Sud, France2Laboratoire Ampère, Lyon, France

23/9/15

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Outline

Introduction

Thermal Management Strategies

Experimental Characterization

Conclusions

2 / 29

Outline

Introduction

Thermal Management Strategies

Experimental Characterization

Conclusions

3 / 29

GaN Devices for Power Management

I Low on-state specific resistance(100 times lower than Si)

I Fast-switching deviceI Low cost (GaN-on-Si substrate) [5]

I Gan on SiC: 20 $/cm2

I Gan on Saphire: 5 $/cm2

I Gan on Si: 0.5 $/cm2

I Lateral devices (no GaN substratesavailable)

Ü Specific thermal managementP. Roussel, “SiC market and industry update,” presented at the Int. SiC Power Electron. Appl.Workshop, Kista, Sweden, 2011.

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Overview of Available GaN Devices – 1

Manufacturers:I Panasonic (600 V, 71 mΩ)

enhancement modeI GaN Systems (650 V, 27 mΩ)

enhancement modeI Transphorm (600 V, 52 mΩ)

Cascode with HeMTI EPC (30 V, 4 mΩ)

enhancement modePackaging options from standardto highly specific

Source: Transphorm TPH3205WS datasheet

Source: GaNSystems GS66516T datashee

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Overview of Available GaN Devices – 2

I EPC 2015 GaN transistor chosen for this studyI 30 V, 33 A, 4 mΩI 4x1.6 mm2, die 685 µm thick

I Wafer-level packagingI Land Grid Array (solder bumps on die)I simple configuration for modelling, processing. . .

I Mounting technique: flip-chip on board, cooling via the bumps.

Lidow, A. et al. “A New Generation of PowerSemiconductor Packaging Paves the Way forHigher Efficiency Power Conversion” (IWIPP2015) [3]

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Packaging Requirements for GaN Devices – 1

I Most devices are very sensitive to overvoltage, noavalanche allowed

I EPC eGaN transistors:recommended gate voltage 5 V, absolute maximum: 6 V

I Switching frequency: 100s to 1000s of kHzI Stray inductances of power circuit will cause large losses

I Small package sizeI High power density, need to provide good thermal

management.

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Packaging Requirements for GaN Devices – 2

I Very low layout inductance(ideally < 1 nH)

I Driver and capacitors as close aspossible to power devices

I Use of multi-layer PCBI Short interconnexionsI Die stacking

Source: Lee, F. C. et al “A New Package of High-Voltage CascodeGallium Nitride Device for High-Frequency Applications” (IWIPP 2015)[2]

Kangping, W. et al. “An Optimized Layout with Low ParasiticInductances for GaN HEMTs Based DC-DC Converter” (APEC 2015) [1]

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Substrates for Power Electronics – 1

0

1e+07

2e+07

3e+07

4e+07

5e+07

6e+07

7e+07

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Ele

ctr

ica

l C

on

du

ctivity (

S.m

−1)

Thermal Conductivity (W.cm−1

.K−1

)

Cu

Al

Ag

Au

Ni

Sn

PbTi

Thermal conductivityλ = λe + λp

I λe : charge carriers(electrons)λe = LTσ

I λp : phonons (vibrations ofthe atomic lattice)

Ü Few materials are both Thermal conductors and electricalinsulators (diamond, AlN, Si3N4, Al2O3).

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Substrates for Power Electronics – 1

0

1e+07

2e+07

3e+07

4e+07

5e+07

6e+07

7e+07

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Ele

ctr

ica

l C

on

du

ctivity (

S.m

−1)

Thermal Conductivity (W.cm−1

.K−1

)

Cu

Al

Ag

Au

Ni

Sn

PbTi

Wiedemann−Franz law

Thermal conductivityλ = λe + λp

I λe : charge carriers(electrons)λe = LTσ

I λp : phonons (vibrations ofthe atomic lattice)

Ü Few materials are both Thermal conductors and electricalinsulators (diamond, AlN, Si3N4, Al2O3).

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Substrates for Power Electronics – 1

0

1e+07

2e+07

3e+07

4e+07

5e+07

6e+07

7e+07

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Ele

ctr

ica

l C

on

du

ctivity (

S.m

−1)

Thermal Conductivity (W.cm−1

.K−1

)

Cu

Al

Ag

Au

Ni

Sn

PbTi

Wiedemann−Franz law

Al2O3 AlNSi3N4 BeO

Thermal conductivityλ = λe + λp

I λe : charge carriers(electrons)λe = LTσ

I λp : phonons (vibrations ofthe atomic lattice)

Ü Few materials are both Thermal conductors and electricalinsulators (diamond, AlN, Si3N4, Al2O3).

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Substrates for Power Electronics – 1

0

1e+07

2e+07

3e+07

4e+07

5e+07

6e+07

7e+07

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Ele

ctr

ica

l C

on

du

ctivity (

S.m

−1)

Thermal Conductivity (W.cm−1

.K−1

)

Cu

Al

Ag

Au

Ni

Sn

PbTi

Wiedemann−Franz law

Al2O3 AlNSi3N4 BeO

Thermal conductivityλ = λe + λp

I λe : charge carriers(electrons)λe = LTσ

I λp : phonons (vibrations ofthe atomic lattice)

Ü Few materials are both Thermal conductors and electricalinsulators (diamond, AlN, Si3N4, Al2O3).

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Substrates for Power Electronics – 2

I (a) DBC: ceramic dielectric(Al2O3, AlN, Si3N4)

I high thermal conductivity(20-180 W/K.m)

I expensiveI (b) IMS: organic dielectric clad on

thick metalI low thermal conductivity

(≈ 1–2 W/K.m [4])I thin dielectric layer

Ü medium thermal resistanceI low cost

I (c) PCB: organic dielectricI low thermal conductivityI multi-layer possibleI low cost

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Outline

Introduction

Thermal Management Strategies

Experimental Characterization

Conclusions

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Overview of Prototypes

GaN device on thin PCB

GaN device on DBC

“flip-flip” GaN device DBC

I 4-point resistance measurementI RDSon used as a temperature measurementI GaN transistors have very low RDSon (4 mΩ)

I Interleaved pattern for LGA packageI 400 µm pitch (200 µm features)

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Manufacturing of the PCB prototype

I Ultra-thin PCB(70 µm resin, 35 µm copper)

I CleaningI Mounting of GaN transistors using BGA

repair equipment (Zevac Onyx 21)I flip-chip alignment featureI reflow of SAC bumps (217 °C)I no additional solder (only tacky flux)

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Manufacturing of the DBC prototype

Plain DBC board

I Two-step etching:I thinning of copper in high-resolution

areas (300 µm down to 50 µm)I patterning of remaining copper

I Mounting using Zevac ONYX 21

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Manufacturing of the DBC prototype

Plain DBC board Photosensitive resin coating

I Two-step etching:I thinning of copper in high-resolution

areas (300 µm down to 50 µm)I patterning of remaining copper

I Mounting using Zevac ONYX 21

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Manufacturing of the DBC prototype

Plain DBC board Photosensitive resin coating Exposure and development

I Two-step etching:I thinning of copper in high-resolution

areas (300 µm down to 50 µm)I patterning of remaining copper

I Mounting using Zevac ONYX 21

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Manufacturing of the DBC prototype

Plain DBC board Photosensitive resin coating Exposure and development Partial Etching of 250µm

I Two-step etching:I thinning of copper in high-resolution

areas (300 µm down to 50 µm)I patterning of remaining copper

I Mounting using Zevac ONYX 21

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Manufacturing of the DBC prototype

Plain DBC board Photosensitive resin coating Exposure and development Partial Etching of 250µm

Resin coating

I Two-step etching:I thinning of copper in high-resolution

areas (300 µm down to 50 µm)I patterning of remaining copper

I Mounting using Zevac ONYX 21

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Manufacturing of the DBC prototype

Plain DBC board Photosensitive resin coating Exposure and development Partial Etching of 250µm

Resin coatingExposure and development

I Two-step etching:I thinning of copper in high-resolution

areas (300 µm down to 50 µm)I patterning of remaining copper

I Mounting using Zevac ONYX 21

14 / 29

Manufacturing of the DBC prototype

Plain DBC board Photosensitive resin coating Exposure and development Partial Etching of 250µm

Resin coatingExposure and developmentFull Etching

I Two-step etching:I thinning of copper in high-resolution

areas (300 µm down to 50 µm)I patterning of remaining copper

I Mounting using Zevac ONYX 21

14 / 29

Manufacturing of the DBC prototype

Plain DBC board Photosensitive resin coating Exposure and development Partial Etching of 250µm

Resin coatingExposure and developmentFull EtchingSingulating

I Two-step etching:I thinning of copper in high-resolution

areas (300 µm down to 50 µm)I patterning of remaining copper

I Mounting using Zevac ONYX 21

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Manufacturing of the “Flip-Flip” Prototype – 1

I Preparation of a flex substrate(70 µm Cu)

I Mounting of GaN transistorI Preparation of a DBC substrateI Deposit of silver paste, alignmentI Low-temperature sintering of

Flex-transistor assembly on DBC

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Manufacturing of the “Flip-Flip” Prototype – 1

I Preparation of a flex substrate(70 µm Cu)

I Mounting of GaN transistorI Preparation of a DBC substrateI Deposit of silver paste, alignmentI Low-temperature sintering of

Flex-transistor assembly on DBC

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Manufacturing of the “Flip-Flip” Prototype – 1

I Preparation of a flex substrate(70 µm Cu)

I Mounting of GaN transistorI Preparation of a DBC substrateI Deposit of silver paste, alignmentI Low-temperature sintering of

Flex-transistor assembly on DBC

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Manufacturing of the “Flip-Flip” Prototype – 1

I Preparation of a flex substrate(70 µm Cu)

I Mounting of GaN transistorI Preparation of a DBC substrateI Deposit of silver paste, alignmentI Low-temperature sintering of

Flex-transistor assembly on DBC

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Manufacturing of the “Flip-Flip” Prototype – 1

I Preparation of a flex substrate(70 µm Cu)

I Mounting of GaN transistorI Preparation of a DBC substrateI Deposit of silver paste, alignmentI Low-temperature sintering of

Flex-transistor assembly on DBC

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Manufacturing of The “Flip-Flip” Prototype – 2

Preparation of dies:I Grinding of silicon substrate

I use of mounting waxI grinding with P1200 grit paper

I ≈ 600 µm substrate ground down to200-400 µm

I PVD plating (50 nm Ti, 150 nm Ag)I Mounting on flex susbtrateI Sintering

I Nano-Tach-X (NBE tech)I 210 °C process (bump melt @ 217°C)

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Manufacturing of The “Flip-Flip” Prototype – 2

Preparation of dies:I Grinding of silicon substrate

I use of mounting waxI grinding with P1200 grit paper

I ≈ 600 µm substrate ground down to200-400 µm

I PVD plating (50 nm Ti, 150 nm Ag)I Mounting on flex susbtrateI Sintering

I Nano-Tach-X (NBE tech)I 210 °C process (bump melt @ 217°C)

16 / 29

Manufacturing of The “Flip-Flip” Prototype – 2

Preparation of dies:I Grinding of silicon substrate

I use of mounting waxI grinding with P1200 grit paper

I ≈ 600 µm substrate ground down to200-400 µm

I PVD plating (50 nm Ti, 150 nm Ag)I Mounting on flex susbtrateI Sintering

I Nano-Tach-X (NBE tech)I 210 °C process (bump melt @ 217°C)

16 / 29

Manufacturing of The “Flip-Flip” Prototype – 2

Preparation of dies:I Grinding of silicon substrate

I use of mounting waxI grinding with P1200 grit paper

I ≈ 600 µm substrate ground down to200-400 µm

I PVD plating (50 nm Ti, 150 nm Ag)I Mounting on flex susbtrateI Sintering

I Nano-Tach-X (NBE tech)I 210 °C process (bump melt @ 217°C)

16 / 29

Manufacturing of The “Flip-Flip” Prototype – 2

Preparation of dies:I Grinding of silicon substrate

I use of mounting waxI grinding with P1200 grit paper

I ≈ 600 µm substrate ground down to200-400 µm

I PVD plating (50 nm Ti, 150 nm Ag)I Mounting on flex susbtrateI Sintering

I Nano-Tach-X (NBE tech)I 210 °C process (bump melt @ 217°C)

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Simulation – Conditions

Thermal Cond.W/K · m

Copper 400Alumina 27Solder bumps 62Silicon substrate 130PCB prepreg 0.4Sintered silver 200

I FEM simulation using COMSOLI External boundaries: convection conditions (h=8 W/m2 · K )I backside of substrate:

I TIMI Heatsink with natural convection boundary (TA = 25 °C)

I Surface power dissipation for GaN device: 10 W.

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Simulation – Results

PCB

I TJ=206°CI RTh=18 K/W

DBC

I TJ=76°CI RTh=4.9 K/W

“Flip-flip”

I TJ=75°CI RTh=4.8 K/W

I Dissipated power: 10 W

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Outline

Introduction

Thermal Management Strategies

Experimental Characterization

Conclusions

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Photograph of the Prototypes

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Experimental Characterization – Calibration

Use of RDSon as a temperature sensitive parameterI Allow for temperature estimation during operationI Good sensitivity to temperatureI RDSon is lowI non-linearities at low drain current

10-1 100 101

Drain current [A]

0

1

2

3

4

5

6

7

8

On-s

tate

resi

stance

[m

illio

hm

s]

49.7 C

75.3 C

100.1 C

125 C

150.3 C

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Experimental Characterization – Identification

40 60 80 100 120 140 160Junction Temperature [C]

3

4

5

6

7

8

Dra

in-t

o-S

ourc

e r

esi

stance

[m

illio

hm

s]

0.00336 x (T/300)^ 2.154

0.00351 x (T/300)^ 1.983

PCB

Alumine

I Calibration curve useable from 1 to 40 A drain currentI Voltage-drop to monitor of 50–300 mV

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Experimental Characterization – Measurement of RTh

I Test vehicle attached to a largeheatsink with TIM

I Device continuously onI Monitoring of VDS for 20 minI Estimation of temperature from

RDSon variationI “Flip flip” prototype not functionnalI Ambient: 26 °C

V4V

ID

ID =20 A ID =30 A ID =40 APCB 85 °C Run-awayDBC 36 °C 49 °C 73 °C

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Measurement Results

ID Power TJ RTh(A) (W) (°C) Experimental Simulation

PCB 25 3.9 125 25 K/W 18 K/WDBC 40 7.46 73 6.2 K/W 4.9 K/W

I High experimental RTh for PCB might be due to bendingI Clear improvement of ceramic substrate over PCB

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Integrated Half-Bridge on DBC

I Layout: design reference from TII Substrate: DBCI Thinned-down copper on

high-res areas:I GaN devices (EPC 2015)I Gate driver (TI 5113)I Capacitors for driver

I Remaining copper 300 µm thickI On par with 4 mΩ transistors

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Outline

Introduction

Thermal Management Strategies

Experimental Characterization

Conclusions

26 / 29

Conclusions

I Clear advantage of ceramic substrate for thermal managementI Proposed manufacturing technique for high-resolution etching of DBCI Electrical-based junction temperature measurement method

inaccurate, improvements needed

Future Work:I Assemble operating “flip-flip” structuresI Investigate AlN ceramic (expected improvement ≈1 K/W in RTh)I Improve thermal measurements, including ZTh measurement

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Conclusions

I Clear advantage of ceramic substrate for thermal managementI Proposed manufacturing technique for high-resolution etching of DBCI Electrical-based junction temperature measurement method

inaccurate, improvements needed

Future Work:I Assemble operating “flip-flip” structuresI Investigate AlN ceramic (expected improvement ≈1 K/W in RTh)I Improve thermal measurements, including ZTh measurement

27 / 29

Conclusions

I Clear advantage of ceramic substrate for thermal managementI Proposed manufacturing technique for high-resolution etching of DBCI Electrical-based junction temperature measurement method

inaccurate, improvements needed

Future Work:I Assemble operating “flip-flip” structuresI Investigate AlN ceramic (expected improvement ≈1 K/W in RTh)I Improve thermal measurements, including ZTh measurement

27 / 29

Conclusions

I Clear advantage of ceramic substrate for thermal managementI Proposed manufacturing technique for high-resolution etching of DBCI Electrical-based junction temperature measurement method

inaccurate, improvements neededFuture Work:

I Assemble operating “flip-flip” structuresI Investigate AlN ceramic (expected improvement ≈1 K/W in RTh)I Improve thermal measurements, including ZTh measurement

27 / 29

Thank you for your attention,

This work was funded by ANR (National Agency for Research) underthe grant name “ETHAER”.

Many thanks to the 3DPHI technological platform, Toulouse, Francefor their contribution to this work.

cyril.buttay@insa-lyon.fr 28 / 29

References

Wang Kangping, Ma Huan, Li Hongchang, Guo Yixuan, Yang Xu, Zeng Xiangjun, and Yu Xiaoling.An Optimized Layout with Low Parasitic Inductances for GaN HEMTs Based DC-DC Converter.In Proceedings of the Applied Power Electronics Conference and Exposition (APEC 2015), pages 948 – 951,Charlotte, mar 2015. IEEE.

Fred C Lee, Wenli Zhang, Xiucheng Huang, Zhengyang Liu, Weijing Du, and Qiang Li.A New Package of High-Voltage Cascode Gallium Nitride Device for High-Frequency Applications.In Proceedings of the International Workshop on Integrated Power Packaging (IWIPP 2015). IEEE, 2015.

Alex Lidow and David Reusch.A New Generation of Power Semiconductor Packaging Paves the Way for Higher Efficiency PowerConversion.In Proceedings of the International Workshop on Integrated Power Packaging (IWIPP 2015), pages 99 – 102,Chicago, may 2015. IEEE.

A. Ostmann, L. Boettcher, D. Manessis, S. Karaszkiewicz, and K.-D. Lang.Power modules with embedded components.In Microelectronics Packaging Conference (EMPC) , 2013 European, pages 1–4, September 2013.

International Rectifier.GaNpowIR – An Introduction.Technical report, International Rectifier, feb 2010.

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