Improving NoC-based Testing Through Compression Schemes

Improving NoC-based Testing Through Compression Schemes

Érika Cota1 Julien Dalmasso2 Marie-Lise Flottes2 Bruno Rouzeyre2

WNOC 2007

1 2

2

Introduction

NoC-based SoC

available access to each embedded core efficient communication mechanism

reuse the NoC as Test Access Mechanism (TAM)

SoC design communication among cores Network-on-chip

SoC testing access to cores 1500 standard

3

NoC-based system

SoC

core core core

corecorecore

Router

Wrapper

4

NoC-based testing

ATE

SoC

core core core

corecorecore

5

Reuse Model

SoC

core core core

corecorecore

ATE

6

Reuse Model

SoC

core core core

corecorecore

ATE

7

Reuse Model

SoC

core core core

corecorecore

Wrapper: - test mode - basic 1500 modes

8

NoC-based Testing

Minimize total test time:– Maximize the use of network resources during test

Test scheduling techniques– Preemptive– Non-preemptive

Wrappers design– NoC protocol – 1500-compliant

9

NoC-based Testing Approaches

CUT

packet headertest header

flitflitflittail

1 0 1 10 1 0 00 0 0 1

1 0

0 1

1 0

1

Preemptive testing– One vector per message, non-reserved paths

Non-preemptive testing– All vectors in one message, dedicated paths

10


CUT


Slice 1flitflittail

1 0 1 10 1 0 00 0 0 1

1 0

0 1

1 0

1Slice 2


Non-preemptive testing– All vectors in one message, dedicated paths– More than 1 scan slice per flit

11


CUT


Slice 1flitflittail

1 0 1 10 1 0 00 0 0 1

1 0

0 1

1 0

1Slice 2


Non-preemptive testing– All vectors in one message, dedicated paths– More than 1 scan slice per flit

12

Reuse Model: number of Test Ports

SoC

core core core

corecorecore

ATE = 2W channels

w

w ww w

1 core under test

13

Reuse Model: number of Test Ports

SoC

core core core

corecorecore

ATE = 4W channels

w

w

w w

w

w w

w w

2 cores under test

14

Test Time

DfT Costs

Number of Extra Pins

p93791•103 Inputs •79 Outputs•66 Bidirs•32 Cores

15

ATE Costs

P93791 - Test time and ATE cost

0

50000

100000

150000

200000

250000

300000

350000

400000

450000

3/3 4/4 5/5 6/6

Test ports configuration: #INPUTS / #OUTPUT PORTS

Tes

t ti

me

0

50

100

150

200

250

300

350

400

450

Nu

mb

er o

f A

TE

ch

ann

els

Test Time Number of ATE Channels

p93791•103 Inputs •79 Outputs•66 Bidirs•32 Cores

16

Problem

How to increase the number of test portsIncrease test parallelism

Maximize NoC channels usage

without increasing the ATE cost?

17

Goal

Goal: Use Horizontal compression to reduce the number

of ATE channels required for each NoC test port, i.e. to increase the number of test ports

How ? Combine a horizontal compression scheme with a

non–preemptive test scheduling approach to reduce test time

18

Compression applied to NoC-based testing

Horizontal compression method

Test scheduling algorithm

Experimental results

Final remarks

Outline

19

Compression Applied to NoC-based Test

router

wrapper

N

W

Core

W

router

wrapper

W

Core

router

wrapper

W

Core

router

wrapper

W

Core

input

W

20


Core i

router

wrapper

Communication channels

W

WW

decompressor

Fi

W

NoCFunctional input pins

M

M≤ Fi ≤ W

21


Core i

router

wrapper


W

WW

compressor

Fi

W

NoCFunctional output pins

M

M≤ Fi ≤ W

22


Core i

router

wrapper


W

WW

decompressor

Fi

W

NoCFunctional input pins

Wk

Wk≤ Fi ≤ W

Each test port needs less than W bits

Less ATE channels per port

Increase the number of possible test ports

Increase test parallelism

23


Horizontal compression– Test width reduction is the primary goal

Test vectors compression– Implies extra hardware at NoC-level (decompressor

sharing)– May increase cores test time

Test responses compression– Implies extra hardware at NoC-level – Does not affect core test time

24

Horizontal Compression TechniquesT

est

Dat

a

Com

pres

sion

ATE

On

-ch

ip D

ec

om

pre

ss

or

CoreMW WM

W S

can

Cha

ins

Co

mp

ress

ed

Te

st D

ata

M < W





Final remarks

Outline

25

Horizontal Compression: Requirements

Features Circuit netlist independent (suitable for IPs) Test data independent (additional test patterns) Specific tools independent Low cost hardware decompressor

No impact on fault coverageAllow Shared decompressor for several cores

26

Horizontal Compression

Many published methods Take advantage of Don’t Care

bits (X’s) in test sequence May increase core Test Time

Virtual scan chains (VTS'00)Illinois scan architecture (DATE'02)Ring generator+phase shifter (ITC'02)Circular scan (DATE'04)Test data mutation encoding (DATE'02)Xor network (DAC'01)Reconfigurable Switch (ITC'01)

Dictionnary based methods (TDAES'03 / & ITC'04)

Netlist dependent

Test data dependent

Specific tool dependent

27

Decompressor architecture

W

0 0 0 0Add Cells

OutputShift Register

To scan chains

From ATEM

[1] Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains - DELTA 2006: 295-300

28

Decompression synchronization

0 0

Scan enable Control

CLK

S1 1 0 0 0

S2 1 0 0 1

S3 1 1 1 0

S4 0 1 1 0

S1 -> S2 : 0 1

S2 -> S3 : 1 1

S3 -> S4 : - -

X X X X

XXXX

X X X X

1 0

X 1 X 0

1 1

X X X X

XXXX

X X X X

0 0

1 0 0 0

1 1

1 0 0 1

0001

X X X X

1 1

1 1 1 0

1 0

1 0 0 0

XXXX

X X X X

0 1

1 0 0 1

1 0

1 1 1 0

1001

1 0 0 0

1 0

0 1 1 0

1 1

1 1 1 0

1001

1 0 0 0

0 1

1 0 0 1

1 1

Original test Sequence

Compressed test Sequence

FSM

Sc1 1 0Sc2 0 0Sc3 0 1Sc4 1 1Sc5 0 1Sc6 1 0

29

Compression Applied to NoC Data


01101

tail

01101

01110

Test pattern: 011010110101110

Original test packet (W= 5)

Compressed test packet (M = 2)

packet header

test header

01

tail

101X0001

packet header

packet header

test header

test header


01101

tail

01101

01110

Uncompressed test packet (W = 5)

compressor decompressor

30


CoreOriginalPayload(32-bits)

Comp.32 -> 12

Comp.32 -> 10

1 12 22 30

2 511 949 1198

3 2400 2400 2400

4 5670 5670 5670

5 6050 10976 14000

6 9594 11918 12171

7 3230 4069 5054

8 4462 4462 4462

9 768 1426 1791

10 370 6876 8780

Example for d695 ITC’02 benchmark– uncompressed and compressed data (#flits)

Compression may increase test time of individual cores

31


Conclusion:Þ Local increase in test timeÞ Increase test parallelism

Global test time reduction

System Configuration Test time

1 32-bit input port 36588 cycles

3 input ports of 12, 10, and 10 bits 24395 cycles

32 ATEchannels

d695•32 Inputs •32 Outputs•10 Cores

33%

32





Final remarks

Outline

33

Test Scheduling Using Dedicated Paths

Each core is associated with a routing path

Includes input and output ports

All resources are reserved until test completed

Test pipeline maintained

No complex logic

Similar to a circuit switching

Efficiently assign I/Os and paths to core

Each input port leads to a different core test time

[2] C. Liu, E. Cota, H. Sharif, D.K. Pradhan: Test Scheduling for Network-on-Chip with BIST and Precedence Constraints - ITC 2004: pp. 1369-1378.

34

Test Scheduling with Compression

Two test packets per core – Compressed test vectors– Uncompressed test responses

Pre-defined number of test interfaces – Number of inputs = number of outputs– List of I/O pairs

For each core and for each I/O pair – Input width changes (compression ratio changes)– size of input test packets pre computed

35


Define test packets

Define access paths for each core

Select a core

Find available access path

Schedule packet

36


Define test packets


Select a packet


Schedule packet

Packets sorted by probable test time

37


Define test packets


Select a packet


Schedule packet

Select I/O pair that leads to minimal

total test time


38


Define test packets


Select a packet


Schedule packet

If no path is found, try next core

Select I/O pair that leads to minimal

total test time


39

Out

Out

d695 from ITC02 benchmark

Channel width=32

3 inputs 10, 10, 12 bits

3 outputs I/O pairs

3/9 6/7 8/4

6 5 4 8 10 7 3 9 2 1


2

3

5 10

6 4

1

79 8

In

In

In

Out

10

10

12

40

Out


2

3

5 10

6 4

1

79 8

In

In

In

OutOut

98696

6 5 4 8 10 7 3 9 2 1

108566

108566

10

10

12

41

154595

Out


2

3

5 10

6 4

1

79 8

In

In

In

OutOut

98696

68265

5 4 8 10 7 3 9 2 1

68505

10

10

12

42

126554


2

3

5 10

6

1

9 8

In

In

In

Out

OutOut

98696

68265

58294

4

7

4 8 10 7 3 9 2 1

151154

10

10

12

43

104348


2

3

5 10

6

1

9 8

In

In

In

Out

OutOut

98696

68265

58294

4

7

8 10 7 3 9 2 1

114318

140138

10

10

12

44


2

3

5 10

6

1

9 8

In

In

In

Out

OutOut

98696

62065

58294

4

7

104348

10 7 3 9 2 1

1006910

10

10

12

45

7 3 9 2 1


2

3

5 10

6

1

9 8

In

In

In

Out

OutOut

98696

62065

58294

4

7

10434810069

1013328

7

10

10

12

46

3 9 2 1


2

3

5 10

6

1

9 8

In

In

In

Out

OutOut

98696

62065

58294

4

7

10434810069

1013328

7

125763

10

10

12

47

9 2 1


2

3

5 10

6

1

9 8

In

In

In

Out

OutOut

98696

62065

58294

4

7

10434810069

1013328

7

125763

110222

10

10

12

48

110471

9 1


2

3

5 10

6

1

9 8

In

In

In

Out

OutOut

98696

62065

58294

4

7

10434810069

1013328

7

125763

110222

10

10

12

49

Out

9


2

3

5 10

6

1

9 8

In

In

In

Out

Out

98696

62065

58294

7

10434810069

1013328

7

125763

110222

110471

134129

4

7

10

10

12

50

110471

9 1


2

3

5 10

6

1

9 8

In

In

In

Out

OutOut

98696

62065

58294

4

7

10434810069

1013328

7

125763

110222

10

10

12

9

51


Define test packets


Select a packet


Schedule packet

Permutate coresPermutate I/O pairs

52

Experimental Setup

SOCIN Network– developed at UFRGS– grid topology– 32-bit channels

ITC’02 SoC Test Benchmarks – Cores’ placement from design– Random test vectors (80% X's)

Test time versus ATE cost

53

System D695: 3 ports example

System Configuration

Test time (cycles)

Number of ATE input channels

1 input port(32-bit)

36588 32

3 input ports(32-bit each)

15293(-58.2%)

96(+200%)

3 input ports (12, 10, and 10

bits)

24395 (-33.3%)

32(+0%)

54

Experimental Results – d695

Test time and ATE cost without compression

05000

10000150002000025000300003500040000

1/1 2/2 3/3 4/4 5/5

I/O configurations

Test

tim

e

020406080100120140160180

# o

f inp

ut A

TE

chan

nels



55


Test time and ATE cost with compression

0

5000

10000

15000

20000

25000

30000

35000

40000

1/1 2/2 3/3 4/4 5/5

I/O configurations

Te

st

tim

e

0

20

40

60

80

100

120

140

160

180

# o

f in

pu

t A

TE

c

ha

nn

els



56


System

Number of Inputs/

Outputs

No Compression With Compression

Test time (cycles)

# of input ATE

channels

Test time (cycles)

# of input ATE

channels

d695

1/1 36588 32 n/a n/a

2/2 19788 64 22737 32

3/3 15293 96 20945 32

4/4 9652 128 18067 32

5/5 9652 160 12853 32

57


System

Number of Inputs/

Outputs


Test time (cycles)

# of input ATE

channels

Test time (cycles)

# of input ATE

channels

d695

1/1 36588 32 n/a n/a

2/2 19788 64 22737 32

3/3 15293 96 20945 32

4/4 9652 128 18067 32

5/5 9652 160 12853 32

- same ATE cost- 65% test time reduction

58


System

Number of Inputs/

Outputs


Test time (cycles)

# of input ATE

channels

Test time (cycles)

# of input ATE

channels

d695

1/1 36588 32 n/a n/a

2/2 19788 64 22737 32

3/3 15293 96 20945 32

4/4 9652 128 18067 32

5/5 9652 160 12853 32- Test time roughly equivalent- 50% ATE cost reduction

59

Experimental Results – g1023

System

Number of Inputs/

Outputs


Test time (cycles)

# of input ATE

channels

Test time (cycles)

# of input ATE

channels

g1023

2/2 23777 64 25453 52

3/3 16051 96 18883 56

4/4 14453 128 14865 50

5/5 14453 160 14865 56

60

Experimental Results – g1023

System

Number of Inputs/

Outputs


Test time (cycles)

# of input ATE

channels

Test time (cycles)

# of input ATE

channels

g1023

2/2 23777 64 25453 52

3/3 16051 96 18883 56

4/4 14453 128 14865 50

5/5 14453 160 14865 56- 38% test time reduction - 20% ATE cost reduction

61

Final Remarks

Combination of NoC-based testing and horizontal compression – Reduces SoC test time– Reduces ATE costs

Compression technique– compliant with SoC Testing

Future works– seek for the best partition of ATE channels into test

interfaces at NoC-level– test time reduction / area overhead trade-off

62

Thank You…

Documents

Improving NoC-based Testing Through Compression Schemes