ImplementingandAnalyzingSingle EdgeNibbleTransmission(SENT ...1162587/FULLTEXT02.pdf · JTH, Prof Shashi Kumar Scope: 30ECTS RegNr: JTH-Jönköping2014 SchoolofEngineering JönköpingUniversity

Implementing and Analyzing SingleEdge Nibble Transmission (SENT)

Protocol for Automotive Applications

Naseem Ullah

Master’s ThesisElectrical EngineeringEmbedded Systems

2014

Avdelningen för data- och elektroteknikDepartment of Computer and Electrical Engineering

Master’s Thesis

Implementing and Analyzing Single EdgeNibble Transmission (SENT) Protocol for

Automotive ApplicationsNaseem Ullah

This exam work has been carried out at the School of Engineering in Jönköpingin the subject area Electrical Engineering. The work is a part of the two-year ofMaster of Science programme with a specialization in Embedded Systems. Theauthors take full responsibility for opinions, conclusions and findings presented.

Supervisor:JTH, Alf Johansson

Examiner:JTH, Prof Shashi Kumar

Scope: 30 ECTS

Reg Nr: JTH-Jönköping 2014

School of EngineeringJönköping University

SE-551 11 Jönköping Sweden

AbstractWith advancement in automotive systems, it is not just the combination of me-chanical devices like in old days. Almost all the systems of today’s modern carare controlled electronically by a number of ECUs (Electronics Control Unit) withthe combination of sensor modules. To exchange information between the ECUand sensor modules a number of communication standards are used. The mostcommonly used standards are CAN, LIN, and PWM etc.

The data transmission between the ECU and sensor modules can be easily es-tablished with a PWM (Pulse Width Modulation) techniques in comparison withCAN or LIN. PWM provide a convenient solution in terms of cost and perfor-mance when the data-rate is upto 10-bits. While for higher resolution data ratesits performance are not satisfied. Extra effort is needed to implement diagnosticinformation for the integrity of data. Also, the accuracy of PWM signal is depen-dent on the noise voltage and channel bandwidth. In 10-bit system a single bitis represented by 4mV which face serious problem in automotive system due tothe noise voltage pulses which effect the resolution of the PWM. The alternativesolution for safe and high data rate which is more than 10-bit resolution is to usedCAN and LIN protocols.Both CAN and LIN have availability of diagnostic modesfor an ensured data transmission. Also, their capabilities for interconnecting anumber of nodes (sensors-modules) on the same network can significantly reducedthe wiring cost. But in automotive a number of systems need to communicatethrough point-to-point link, and it seem to be too expensive to used CAN andLIN for point-to-point communication because of its development complexity andwiring cost for a standalone system. To overcome these issues and to providean alternative low cost solution the SAE (Society of Automotive Engineers) devel-oped a 3-wire new digital point-to-point protocol called SENT. SENT (Single EdgeNibble Transmission) Protocol is now an international standard (SAE J2716).

SENT is unidirectional point-to-point communication protocol, which can be usedfor high resolution data transmission between sensor module and ECU. The dataare transmitted by sensor module in a series of pulses each pulse is 4-bit (onenibble) long and the data are measured between two falling edges by the receivingmodule. There are total of nine pulses which defined the SENT frame. The firstpulse is called calibration pulse, it is used for compensating to recalibrate all theother pulses in case of transmitter clock deviation, this is the best feature of SENTand can be implemented in the decoder design.

This thesis work focuses on the development of SENT protocol decoder and itssignal robustness analysis in comparison with the conventional PWM signal. Ourfirst goal is to developed SENT-Protocol decoder in software on the available

iii

iv

microcontrollers is to check how much memory foot print is used and how muchthe processor overhead. Two platforms has been used for this purpose. First,two implementation designs prototype were made with fixed-point and floating-point development techniques on the 32 bit platform for SENT decoder. SecondlySENT-decoder were developed with 8-bit platform and compared with the twoprevious designs to check how much memory foot print is used and how much isthe processor overhead. Finally, the signal integrity analysis has been performedfor PWM and SENT signal using spice simulation. The purpose is to check themaximum data rate limit that the PWM signal support with out creating any biterror in the transmitted signal. The same data rate is then used for SENT signalto be compared with PWM signal.

Keywords

SENTCANLINPWMPSI5Nios IIDE 2 BoardGPIOSOPC BuilderADCDACSPICE Simulation

v

Acknowledgments

First and foremost I want to thank my supervisor Alf Johansson for his continuoussupervision and suggestions throughout this thesis and during my complete Mas-ter’s study. I appreciate all his contributions of time, ideas and his great patienceto make my M.Sc. I had a great opportunity of learning so many things from himin the meetings during our discussions.

I would like to thank Professor Shashi Kumar for his continuous support andmotivation throughout my master study program. I really appreciate his invaluabletime and advises that he gave me during my complete study program.

I would also like to thank all my teachers for their full time support and providinginvaluable knowledge during my Master’s study. I had a good time while studyingin JTH. I want to thank to JTH and Sweden for providing a beautiful environmentand a realistic study atmosphere during my study.

Last but not least, I would like to pay a special thank you to my parents whosemoral support and prayers has always been with me.

vii

List of Figures1.1 SENT senor and receiver communication interface . . . . . . . . . 2

2.1 LIN typical applications in automotive . . . . . . . . . . . . . . . . 92.2 LIN typical network overview . . . . . . . . . . . . . . . . . . . . . 102.3 LIN frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . 102.4 LIN frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . 112.5 Point-to-Point communication with PWM . . . . . . . . . . . . . . 122.6 PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . 122.7 PWM waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.8 CAN nodes connection diagram . . . . . . . . . . . . . . . . . . . . 132.9 CAN bus typical applications in automotive . . . . . . . . . . . . . 142.10 CAN bus typical applications in automotive . . . . . . . . . . . . . 152.11 CAN extended frame structure . . . . . . . . . . . . . . . . . . . . 152.12 RTL design of SENT IP . . . . . . . . . . . . . . . . . . . . . . . . 162.13 MLX90324 functional block diagram . . . . . . . . . . . . . . . . . 172.14 SENT frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.15 SENT frame structure . . . . . . . . . . . . . . . . . . . . . . . . . 192.16 SENT synchronization pulse . . . . . . . . . . . . . . . . . . . . . . 202.17 Nios II core architecture . . . . . . . . . . . . . . . . . . . . . . . . 212.18 Different Cores of Nios II Processor . . . . . . . . . . . . . . . . . . 222.19 Block Diagram of DE2 Board . . . . . . . . . . . . . . . . . . . . . 232.20 PIC18F67J50 Development Board [1] . . . . . . . . . . . . . . . . . 242.21 PIC18F67J50 64-Pins Package . . . . . . . . . . . . . . . . . . . . 252.22 PIC18F87J50-Microcontroller Family Member [2] . . . . . . . . . . 262.23 A typical output buffer equivalent circuit . . . . . . . . . . . . . . 272.24 Some typical automotive sensors . . . . . . . . . . . . . . . . . . . 282.25 Position/Speed Sensor Construction . . . . . . . . . . . . . . . . . 292.26 Thermistor Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . 312.27 Engine Coolant Sensor . . . . . . . . . . . . . . . . . . . . . . . . . 312.28 TEL4998 Linear Hall Sensor . . . . . . . . . . . . . . . . . . . . . . 32

3.1 Automotive electronics systems classifications with respect to SAEclasses [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2 Automotive protocols comparison based on their data rates [3] . . 37

4.1 System Development research method . . . . . . . . . . . . . . . . 424.2 SENT-Receiver and Transmitter . . . . . . . . . . . . . . . . . . . 444.3 DEV PIC18F67J50 Board [1] . . . . . . . . . . . . . . . . . . . . . 454.4 SENT- Transmitter (Sensor) Module . . . . . . . . . . . . . . . . . 464.5 Sensor Oscilloscope output . . . . . . . . . . . . . . . . . . . . . . 464.6 Complete Frame Timing Diagram . . . . . . . . . . . . . . . . . . . 474.7 Structure of Status Pulse . . . . . . . . . . . . . . . . . . . . . . . 484.8 Pulse shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.9 Frame Structure of Short serial message . . . . . . . . . . . . . . . 514.10 Creating Project in Nios II IDE . . . . . . . . . . . . . . . . . . . . 52

4.11 Project Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 524.12 System Hardware Architecture . . . . . . . . . . . . . . . . . . . . 534.13 System configuration in SOPC-Builder . . . . . . . . . . . . . . . . 544.14 Data Types of C-Language [4] . . . . . . . . . . . . . . . . . . . . . 554.15 Detection of Synchronization Pulse . . . . . . . . . . . . . . . . . . 584.16 Software Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 614.17 Pulse time measurement . . . . . . . . . . . . . . . . . . . . . . . . 624.18 Data and Serial Message With CRC . . . . . . . . . . . . . . . . . 634.19 Prototype Hardware Design . . . . . . . . . . . . . . . . . . . . . . 644.20 SENT Transceiver Simulator . . . . . . . . . . . . . . . . . . . . . 66

5.1 A typical IBIS file . . . . . . . . . . . . . . . . . . . . . . . . . . . 685.2 An electrical equivalent model of an output buffer . . . . . . . . . 685.3 Model Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 695.4 The Spartan-3 FPGA-Flash Memory interface and simulation setup 705.5 Representation of 12-bits data in the form of SENT-Encoding . . . 725.6 Transmission line effects on rise-fall times of the SENT-Signal . . . 735.7 Representation of 12-bits data in the form of PWM-Encoding . . . 735.8 Transmission line effect on Rise-Time of PWM pulse . . . . . . . . 745.9 Transmission line effect on Fall-Time of PWM pulse . . . . . . . . 755.10 Frequency is 1KHz and data bits are 10 bits . . . . . . . . . . . . . 755.11 Frequency is 1KHz and data bits are 100 bits . . . . . . . . . . . . 765.12 Frequency is 10KHz and data bits are 100 bits . . . . . . . . . . . 765.13 Frequency is 50KHz and data bits are 10 bits . . . . . . . . . . . . 775.14 Frequency is 1MHz and data bits are 10 bits . . . . . . . . . . . . 775.15 Frequency is 10MHz and data bits are 10 bits . . . . . . . . . . . . 785.16 Frequency is 50MHz and data bits are 20 bits . . . . . . . . . . . . 785.17 Frequency is 100MHz and data bits are 20 bits . . . . . . . . . . . 795.18 Frequency is 150MHz and data bits are 50 bits . . . . . . . . . . . 795.19 Frequency is 200MHz and data bits are 50 bits . . . . . . . . . . . 795.20 Frequency is 250MHz and data bits are 10 bits . . . . . . . . . . . 805.21 Frequency is 1KHz and data bits are 100 bits . . . . . . . . . . . . 805.22 Frequency is 100KHz and data bits are 100 bits . . . . . . . . . . . 815.23 Frequency is 50MHz and data bits are 100 bits . . . . . . . . . . . 815.24 Frequency is 150MHz and data bits are 100 bits . . . . . . . . . . . 815.25 Frequency is 250MHz and data bits are 100 bits . . . . . . . . . . . 82

6.1 Execution power comparison of fixed-point and floating-point designs 896.2 Resource utilization of Fixed-point and Floating-point Designs . . 906.3 Memory Footprint Comparison of all the Design Prototypes . . . . 916.4 Experimental Setup Nios based design . . . . . . . . . . . . . . . . 926.5 Experimental Setup PIC based design . . . . . . . . . . . . . . . . 93

B.1 SENT Transceiver Simulator . . . . . . . . . . . . . . . . . . . . . 105B.2 Experimental Setup Of SENT-Decoder and Transmitter . . . . . . 106

List of Tables3.1 Features comparison of vehicles protocols . . . . . . . . . . . . . . 39

4.1 Data Nibble pulses and its duration . . . . . . . . . . . . . . . . . 504.2 Construction of Data Messages . . . . . . . . . . . . . . . . . . . . 504.3 Fixed point algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.1 SENT data-signal start and stop timing . . . . . . . . . . . . . . . 73

6.1 Execution Power Comparison of Floating Fixed Point Implementation 876.2 CPU Utilization of Fixed-Point and Floating-Point Designs . . . . 886.3 Resource utilization of Fixed-point and Floating-point Designs . . 896.4 CPU Utilization of an 8-Bit Platform . . . . . . . . . . . . . . . . . 906.5 Resource utilization of 8-bit Platform Prototype . . . . . . . . . . 91

Contents

List of Figures xi

List of Tables xiii

Contents xv

1 Introduction 11.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Automotive protocols challenges: . . . . . . . . . . . . . . . . . . . 21.3 Thesis Objectives and Tasks . . . . . . . . . . . . . . . . . . . . . . 31.4 Delimitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Theoretical Background 72.1 Communication Protocols in Automotive . . . . . . . . . . . . . . . 7

2.1.1 Communication Requirements for Automotive System . . . 72.1.2 Local Interconnect Network . . . . . . . . . . . . . . . . . . 82.1.3 Pulse Width Modulation . . . . . . . . . . . . . . . . . . . . 112.1.4 Controller Area Network . . . . . . . . . . . . . . . . . . . . 132.1.5 Single Edge Nibble Transmission Protocol . . . . . . . . . . 15

2.2 Hardware Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . 212.2.1 Nios II Processor . . . . . . . . . . . . . . . . . . . . . . . . 212.2.2 DE2 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.2.3 Microchip-PIC Microcontroller . . . . . . . . . . . . . . . . 24

2.3 IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.4 ADS-Advanced Design System Tool . . . . . . . . . . . . . . . . . 272.5 Sensors in automotive . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.5.1 Position or Speed sensor . . . . . . . . . . . . . . . . . . . . 292.5.2 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . 302.5.3 Linear Hall Sensors TLE4998X . . . . . . . . . . . . . . . . 322.5.4 Mass air flow sensors - MAF . . . . . . . . . . . . . . . . . 332.5.5 Tire pressure sensors or TPMS . . . . . . . . . . . . . . . . 332.5.6 Throttle Position sensors - TPS . . . . . . . . . . . . . . . . 332.5.7 Manifold air pressure sensor - MAP . . . . . . . . . . . . . 332.5.8 Fuel pressure sensor - FPS . . . . . . . . . . . . . . . . . . . 33

xiii

xiv Contents

2.5.9 Crash sensors . . . . . . . . . . . . . . . . . . . . . . . . . . 332.5.10 Airbag side impact sensor . . . . . . . . . . . . . . . . . . . 342.5.11 Exhaust gas Sensors . . . . . . . . . . . . . . . . . . . . . . 34

3 Comparison of Automotive Communication Protocols 353.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.2 Comparison of Network Protocols . . . . . . . . . . . . . . . . . . . 363.3 Features Comparison of Network and Point to Point Protocols . . 38

4 SENT-Protocol Implementation on two different platforms 414.1 Research Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.2 Decisions and method . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.1 Hardware Platforms . . . . . . . . . . . . . . . . . . . . . . 434.2.2 SENT-Decoder design on Altera FPGA DE2 Board . . . . 434.2.3 SENT-Decoder design using Microchip PIC18 . . . . . . . . 444.2.4 SENT-Transmitter (Sensor) Module . . . . . . . . . . . . . 45

4.3 SENT data frame Transmission and Reception . . . . . . . . . . . 474.3.1 SENT data frame Structure . . . . . . . . . . . . . . . . . . 474.3.2 Data Message Encoding . . . . . . . . . . . . . . . . . . . . 484.3.3 Data-Message Decoding . . . . . . . . . . . . . . . . . . . . 484.3.4 CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . 504.3.5 Short serial message . . . . . . . . . . . . . . . . . . . . . . 51

4.4 Nios-II Based Prototype . . . . . . . . . . . . . . . . . . . . . . . . 514.4.1 Development Environment Setup . . . . . . . . . . . . . . . 514.4.2 Integration of Hardware and Software . . . . . . . . . . . . 534.4.3 System design in SOPC builder . . . . . . . . . . . . . . . . 534.4.4 Software Design . . . . . . . . . . . . . . . . . . . . . . . . 554.4.5 Design with Floating-point . . . . . . . . . . . . . . . . . . 564.4.6 Design with Fixed-point . . . . . . . . . . . . . . . . . . . . 574.4.7 Software Algorithm . . . . . . . . . . . . . . . . . . . . . . 604.4.8 Code profiling . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.5 Prototyping with PIC-Microcontroller . . . . . . . . . . . . . . . . 634.5.1 Hardware setup . . . . . . . . . . . . . . . . . . . . . . . . . 634.5.2 Software Design . . . . . . . . . . . . . . . . . . . . . . . . 64

5 Signal Integrity Analysis of SENT and PWM with Simulation 675.1 Design Overview and IBIS Models . . . . . . . . . . . . . . . . . . 675.2 Simulation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 695.3 Signal integrity analysis of SENT and PWM signals . . . . . . . . 715.4 SENT and PWM signal simulations at frequency range ( 1KHz-

250MHz) with different data rate (10-Bits-100-Bits) . . . . . . . . 755.5 Conclusion of the simulations . . . . . . . . . . . . . . . . . . . . . 82

Contents xv

6 Results and Discussion 856.1 Study of SENT-Protocol . . . . . . . . . . . . . . . . . . . . . . . . 856.2 Comparison of automotive communication protocols . . . . . . . . 866.3 Design prototypes comparison implemented with fixed-point and

floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.4 Design prototypes comparison implemented on an 8-bit and a 32-bit

platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896.5 Functional testing of the Nios Based design prototype . . . . . . . 926.6 Functional testing of the PIC Based design prototype . . . . . . . 93

7 Conclusions and Future Work 957.1 Summary of Contribution . . . . . . . . . . . . . . . . . . . . . . . 95

7.1.1 Design with fixed-point and floating-point arithmetic . . . . 957.1.2 Prototype design on 8-bit and 32-bit platforms . . . . . . . 967.1.3 SPICE-Simulation Model . . . . . . . . . . . . . . . . . . . 96

7.2 Limitation and Future Work . . . . . . . . . . . . . . . . . . . . . . 967.2.1 SENT-signal EMC emissions analysis . . . . . . . . . . . . 967.2.2 Performance comparison of software-design with the IP-core 967.2.3 Sensor fusion prototype with SENT-Interface . . . . . . . . 967.2.4 ON-Chip Interconnect Communication . . . . . . . . . . . . 97

Bibliography 99

A SENT-Decoder CRC Implementation 103

B Schematics Diagrams 105

Chapter 1

Introduction

This thesis focuses on the implementation and signal analysis of the Single EdgeNibble Transmission protocol (SENT) described by SAE J2716 SENT [46]. SENTis a point-to-point digital protocol used to interface high resolution sensors toElectronic Control Unit (ECU) in modern automotive systems. In this chapter wewill focus on some features of SENT protocol and their applications in automotivesystems. The complete introduction of SENT protocol and its comparison withthe conventional PWM (Pulse Width Modulation) also with some other point topoint digital protocols will be described in details in up coming chapters. Thischapter also includes thesis objectives and layout of thesis report.

1.1 BackgroundToday modern vehicles are equipped with a large number of smart sensor moduleswhich are capable of accurate sensing, signal conditioning and produced digitaloutput that can be interface with microcontroller without any prior conversion(ADC or DAC). In order to retrieve the high resolution information remotelyfrom these sensors the signal integrity and robustness should be ensured. Up tothe recent times the conventional Pulse Width Modulation (PWM) was the mostcommonly use interface between sensors and ECU in automotive systems [5]. Butthe high resolution output form sensors, real time, safety critical, electromagneticcompatibility (EMC) requirements and low cost overhead demands for more robustand standardized interface. To accommodate the previously mentioned require-ments the Society of Automotive Engineer (SAE) has developed a low cost digitalpoint-to-point interface for unidirectional sensor data the interface is called SingleEdge Nibble Transmission (SENT) protocol [46].

SENT protocol was initially adopted for the powertrain [6] applications in automo-tive but because of its low implementation cost and maintaining greater integrityof high resolution sensor data, also due to its more robustness to noise make it moreappealing for other automotive and non-automotive applications. The situation

1

2 Introduction

where data transmission from a sensor module to an ECU is required, interfaceusing bus communication protocols such as Controller Area Networks (CAN) [37]and Local Interconnect Network (LIN) [38] are not suitable due to their high im-plementation costs. In such situation SENT protocol is a better replacement forCAN and LIN. As mentioned earlier SENT protocol overcome some of the defi-ciency of PWM. For example the resolution of PWM greatly degrades with thehigher clock frequency Fc and also PWM provides limited information regardingdiagnoses and status of data message. Due to the steep edges from high to lowor low high transition of a PWM pulse make it more prone to noise while in theSENT pule rise and fall time are longer compare to PWM which makes it lessimmune to noise. A complete SENT frame allows transmission of multiple datamessages.

1.2 Automotive protocols challenges:Efficiency of modern cars is measured in terms of safety, fuel efficient and low cost.Electronics modules are included at high speed in automotive systems with theevolution of automotive system design [36]. A number of ECUs are used in today’scar these ECUs communicate to each other and also to off-ECU sensor modulesby using communication standards and channels. In recent years a numbers ofcommunication protocols have been proposed to reduce the communication costbetween ECUs and sensing units. Safe and high resolution data transmissions arethe two main challenges for developing automotive communication standards forcommunication between sensors and ECUs. Twisted pair cables are commonlyused for communication between ECU and sensor module as depicted in the figure1.1.

Figure 1.1: SENT senor and receiver communication interface

Due to the long distance between the ECUs and off-sensor modules the wire lengthplays a vital rule in the distortion of signal-(data). A pair of parallel wires actslike a transmission line when high frequency, short period pulses are applied tothe channel for high resolution data transmission. The channel line behaves aseries of inductance and capacitance which can be model as a lumped circuit anelement of wire segment is shown in figure 1.1. A number of techniques are used toachieve high data rate with less signal loss for designing automotive communicationstandards such as PWM technique. There is a trade-off to achieve high resolution

1.3 Thesis Objectives and Tasks 3

data transmission and signal using the PWM technique. The development ofSENT protocol was intended to overcome these issues [46].

1.3 Thesis Objectives and TasksAs previously stated performance and signal integrity are the important factors tobe considered while developing new communication standards for an automotivesystem. Due to the advancement more electronic are included in to automotivesystem to increase the safety and performance while doing this a huge numberof wires are used for communications among ECUs and sensors units. Due tothis the wiring cost become significant high and also the transmission line effectsproduces a number of bit error in the signal which destroy the integrity of data.The motivation for developing Single Edge Nibble Transmission (SENT) protocolwas to overcome these issues.

This thesis work focuses on the development of SENT protocol decoder and itssignal robustness analysis in comparison with the conventional PWM signal.Thefirst goal of this thesis work is to perform a comparative study of different automo-tive communication protocols in order to understand the challenges that demandfor new communication standards. The comparison will be based on their fea-tures and feasibility for specific applications. The second goal is to developedSENT-Protocol in software on the available microcontrollers to check how muchmemory foot print is used and how much the processor overhead. To achieve thepurpose of this goal two platforms has been used. The software implementationis done with two different design algorithms fixed-point and floating-point. The32 bit platform (Nios-II soft-core processor) has been used, which is provided byAltera FPGA DE2 board for SENT decoder. To check for a low cost and highperformance solution, SENT-decoder are developed with 8-bit platform and arecompared with the two previous designs prototype to check how much memoryfoot print is used and how much is the processor overhead. The last goal is to an-alyze the signal integrity for PWM and SENT signal using spice simulation. Thiscan be achieved by developing the complete transceiver and channel SPICE modelin SPICE simulation tool. The purpose is to check the maximum data rate limitthat the PWM signal support with out creating any bit error in the transmittedsignal. The same data rate is then used for SENT signal to be compared withPWM signal.

In order to achieve these goals first a details study has been performed on dif-ferent point-to-point and network based protocols. The SENT-decoder prototypeis designed by first performing a details study of SENT protocol to specify therequirements for implementation. The SENT decoder system has been design inthe SOPC builder a utility provided by the Quartus II IDE. The design systemis compiled and loaded to DE2 board to program the FPGA chip. To evaluatethe performance and resource usage analysis of SENT decoder two applicationsare developed in NIOS II IDE (Integrated Development Environment) using C-Programming language with fixed-point and floating point algorithms. The de-

4 Introduction

sign prototype is tested by connecting the SENT sensor module to DE2 boardand receiving the data messages from the sensor module in NIOS II IDE console.Secondly to check for the alternative low cost solution another prototype has beendeveloped on 8-bit platform using PIC18 microcontroller together with MP-LABIDE which is provided by Microchip. The performance and resource usage of bothprototypes are also compared to check for a good design prototype. To analysethe signal distortion over the channel for PWM and SENT. The SPICE simulationmodel has been designed in the ADS-2008 (Advanced System Design) tool fromAgilent technology which is a very powerful tool for signal integrity analysis. Thechannel is model as lumped circuit elements and IBIS model are used for bothinput and output buffers models. To analyse the effect of the transmission line onboth SENT and PWM signals different frequencies range and data rate are set forperforming simulation.

1.4 DelimitationIn this thesis our focus is mainly on implementation of SENT protocol on twodifferent platforms to evaluate the performance and robustness of the SENT signal.For verification and analysis of our implementation we will not use any off-the-shelf sensor with the SENT-decoder module instead we will use a custom developedSENT-transmitter (sensor) module which is described in chapter 2 section 4.2.4for evaluation of the design SENT-decoder prototypes. In this thesis work theanalysis of SENT protocol is mainly based on prospective of its use in automotivesystems and no other application areas.

1.5 Thesis StructureThis chapter describes the motivation for this thesis work and also provides thelayout and delimitation of our work.

In Chapter 2 a detailed study of most commonly used automotive communica-tion are performed.SENT protocol and specially the frame structure of SENT hasbeen described in detailed to specify the requirements for implementation. Thedevelopment platforms for SENT decoder implementation are also described inthis chapter.Some sensors that are most commonly used in automotive system aredescribed at the end of this chapter.

In chapter 3 a comparative study has been performed on the most common point-to-point protocols with SENT protocol which are used nowadays in the automotiveindustry. Also the features of network based protocols are described in comparisonwith the point-to-point protocols.

Chapter 4 describes the details of SENT decoder prototype design. Also it de-scribes how the design decisions are made to implement the SENT decoder insoftware. The two different software algorithm are explain in details. The IDEs

1.5 Thesis Structure 5

set-up for development are also presented in this chapter.

The signal integrity analysis of SENT and PWM signal are performed in thischapter. In Chapter 5 also a complete description are given about the SPICE-simulation model of the SENT receiver module, transmitter module and the chan-nel SPICE model. Each module of the SPICE simulation design is describe in thischapter. Finally in this chapter the complete simulation design are presented.

The results are presented in chapter 6. The performance analysis of the designprototypes are presented in this chapter. This chapter also describes evolution ofthe resource usage of the design prototypes. Simulation results for signal integrityanalysis are evaluated for both SENT and PWM in this chapter.

Chapter 7 describes the contribution of our work and gave some ideas for furtherresearch in this area. The appendixes consists some schematics and tables whichhas been used in this thesis work.

Chapter 2

Theoretical Background

This chapter will described the background for this thesis. We will describe someof the important protocols standards that are used nowadays in the automotivesystem. These protocols standards are either serial (point-to-point) or networkbased. The structure and applications of these protocols will be describe in thischapter and their comparison will be presented in the next chapter. This chapterwill also describe the platforms that are used for the implementation of the designprototypes. The description of Altera DE2 board and SOPC builder together withthe Nios II soft-core processor are given in this chapter. PIC18F67J50 developmentboard for 8-bit processor based prototype is also describe in this chapter. Someof the the most commonly used sensors in the automotive system are describe.ADS (Advanced Design System) SPICE simulator from Agilient technology whichis used for signal integrity analysis is also describe in this chapter.

2.1 Communication Protocols in AutomotiveIn this section we will present different bus and point-to-point protocols to interfacesensors modules to ECUs in the automotive systems.

2.1.1 Communication Requirements for Automotive SystemThe selection of a communication protocol in a vehicle depends on types of com-ponents. For example for adaptive damping system [7] FlexRay [8] is a suitableprotocol due to its high data rates . The general requirements for in-vehicle com-munication protocols are described as:

Determinism:

In automotive system some of the system are time critical and their exact responsetime should be known. For example in safety critical systems a protocol must ful-filled the deterministic behavior of messages between two components in a vehiclewhich are responsible for safety related functions.

7

8 Theoretical Background

Tolerance:

Its not necessary in vehicles that all systems should have fault tolerant functional-ity but some systems should continue their proper operation even in the presenceof faults. A communication protocol in automotive system should be capable of re-liable communication. The examples of the systems which requires highly reliablecommunication are X-by-wire systems.

Bandwidth:

The communication bandwidth in vehicle is application as well as protocol depen-dent. For example a bus protocol which connect several ECUs requires greaterbandwidth. Multimedia application require higher data rates and communicationchannel bandwidth.The requirement for the higher bandwidth in point-to-pointprotocol is less than bus protocol.

Flexibility:

The performance of a communication protocol should not be degraded with theaddition of system or sub-system functionality. Due to the rapid advancements inaddition of new features in automotive systems the communication protocol needsto be more flexible and scalable.

Security:

In order to secure the data transmission in automotive systems the data encryptionmechanism should be described for communication standards [42]. The securitybecome more important when vehicle system are exposed to out side world suchas remote diagnosis and inter vehicle communication.

2.1.2 Local Interconnect NetworkLocal Interconnected Network Overview

Local Interconnected Network(LIN) [38] is serial asynchronous bus protocol. To-day, auto-mobiles are extensively equipped with electronics modules for safety,control and luxury. As the complexity and requirements for addition of morefeatures increases the cost of the system increases too. In 1999 LIN Consortiumconsists of a group of the world leading car manufacturing companies presentedLIN to reduce implementation cost for low data rates systems. LIN is based onexisting UART protocol. The key features of LIN protocol are:

• LIN is a bidirectional used single wire

• 20Kbits/sec transfer rate

• Support for power management

• Single master and multiple slaves architecture exclude the cost for additionalsynchronization

2.1 Communication Protocols in Automotive 9

• Based on existing and highly available UART technology exclude the specialconsideration for hardware

• No protocol license fee is required [9].

LIN Application Areas

LIN is a low speed and low cost sub-bus protocol which target application in ve-hicles in non-safety components. Figure 2.1 shows LIN application in automotive.Some of the typical applications of the LIN protocols are [10]:

Figure 2.1: LIN typical applications in automotive

• Vehicle roofs (rain sensor,light sensor,light control,sun roofs,etc.)

• Vehicle doors (Mirrors, Central locking, Mirror switch, Window lift, etc.)

• Steering wheel(Cruise control, wiper, radio climate control switches, etc.)

• Seat (Set position motor, set heater, occupancy sensor)

• Vehicle roofs

LIN Protocol Description

LIN protocol exploit the features of I2C [45] and RS232 [11]. Like I2C bus is pulledhigh via resistor while open collector driver is used to pull the bus low, instead ofusing clock line as in I2C the message is transmitted asynchronously byte by bytemarked with start and stop bits as in RS232. In LIN nodes are arranged in masterand slave relationship. A LIN master can have upto 16 slaves. The informationbetween nodes is exchanged via LIN frames. The master node is responsible for


synchronization and communication initialization with slaves. Figure 2.2 showsthe nodes arrangement in a typical LIN network.

Figure 2.2: LIN typical network overview

LIN Frame Structure

A typical LIN frame comprises of header and response. The header part of LINframe is always generated by the master node while response can be generatedby master or slave. As shown Figure 2.4 in the header consist of three fieldssynch break, synch field and ident field. The synch break has fixed 13 bits length.Synch break is issue by master node to inform the slaves that a message is ready.Synch field set the clock for entire bus. Its value is HEX-55 including start andstop bits plus 1 bit synch delimiter. A 15% clock drift is allowed between masterand slaves. The inclusion of this field in LIN frame eliminate the use of crystalfor precise clock synchronization. The third part of the LIN header is ident fieldwhich specify what type of data will be on the bus which node should respond to itand how long should be response. In ident field is further divided into three fields4 bits (0-3) are used to address devices, 2 bits (4-5) indicate the message length tofollow and the last 2 bits (6-7) are parity bits. A slave can respond when mastercommands it. the slave response can be 2, 4 or 8 byte long. The slave nodescan transmit and receive data directly to each other without involving master ifcommanded by the master.

Figure 2.3: LIN frame structure


2.1.3 Pulse Width Modulation

Pulse Width Modulation Overview

Pulse Width Modulation(PWM) is a way of representing an analog signal levelsinto digital waveform. To achieve PWM a digital waveform width is varied withrespect to a specific instantaneous value of the analog signal. Different chip ven-dors includes PWM modules in their products. In microcontrollers the encodingand decoding of PWM is performed using timers and comparators modules butthe hardware can also be produced with simple electronics circuits without anycentral controller. PWM has a simple point to point connection as shown in Figure2.5 1 a sensor module which transmit PWM signal is directly connected to PWMdecoder for information retrieval. The main features of PWM are:

• Ease of implementation

• Better noise immunity

• Highly available hardware

• One wire requirement for data transmission

• Wide applications domain

Figure 2.4: LIN frame structure

1The signal timing diagram and the interface line are represented by a single line for figurenumber 2.5 and figure 2.6


Figure 2.5: Point-to-Point communication with PWM

PWM Application Area

PWM controllers are widely used for DC motors speed control, LED light controland switching mode power supplies due reduce power losses in power switching.In automotive the most obvious uses of PWM are:

• Electronic throttle control

• Seats heating

• Back lights LED lamps control

PWM Encoding and Decoding

Some characteristics of signal are used to express PWM signal: period is the timefor complete cycle of PWM pulse and duty cycle is the percentage of period forwhich the signal is high. The simplest technique to generate PWM signal is bymodulating the sawtooth waveform with analog waveform this scheme is shown inFigure 2.6 and the resultant PWM waveform is shown in Figure 2.7.

Figure 2.6: PWM signal generation


Figure 2.7: PWM waveform

2.1.4 Controller Area NetworkController Area Network Overview

Controller Area Network(CAN) [37] is message based serial bus protocol developedand released by BOSCH in 1986. CAN is a two wire bus protocol, all nodes accessesthe bus with same speed. Figure 2.8 shows typical CAN nodes connection diagram.The BOSCH CAN specifications [37] is divided into two parts: Standard CAN andExtended CAN. The major difference between two is the length of identifier. CANhas been standardized by International Standardization Organization (ISO). CANdefinitions can be found in ISO 11898 and ISO 11519 standards. CAN applicationsdomain is not limited to automotive only but also has applications in industrialautomation and medical equipments. The main features of CAN protocols are:

Figure 2.8: CAN nodes connection diagram

• Multiple master serial bus protocol which allows simultaneous access to bus


• Real time communication upto 1 Mbits/sec speed

• Supports high saturation of nodes in a single CAN network(theoreticallymore than 2K nodes)

• Hardware support available from all major chips vendors

• supports robust error handling and remote diagnosis

• Provides extremely flexible and scalable system integration

CAN Application Area

CAN protocol initial design was specific for automotive application but it hasbeen adapted for several industrial automation and real time control in variousindustrial applications. Figure 2.9 shows the typical CAN applications for bothCAN high speed and CAN low speed buses in automotive.

Figure 2.9: CAN bus typical applications in automotive

CAN Protocol description

CAN allows multiple master nodes to exist in a single network. It utilizes CarrierSense Multiple Access/Collision Detection(CSMA/CD) algorithm to check the busstatus before sending messages on the network and uses arbitration based on mes-sage identifier. When bus is free any CAN unit can start transmission, if two ormore CAN nodes start transmission at same time the node with higher messagepriority succeed while the node with lower priority back off and wait for randomamount of time until the bus become free again. CAN CSMA/CD differ fromEthernet protocol in the respect that if a collision is detected the messages are notcompletely destroyed but the message with higher priority always succeed.

CAN Data Frame Structure

CAN has four types of frames: Data frame, Remote frame, Error frame and Over-load frame but here we will discuss only the data frame. Figure 2.10 and Figure2.11


Figure 2.10: CAN bus typical applications in automotive

Figure 2.11: CAN extended frame structure

shows the CAN data frames structures for standard frame and extended frame.As described earlier the main difference between the two formats is the length ofidentifier field. The first field of the CAN message is Start Of Frame(SOF) is 1bit long, indicate the beginning of the message. SOF field is followed by Arbi-tration field which comprises of 11 bits or 29 bits message identifier depends onwhether the frame is of standard or extended version and 1 bit Remote Transmis-sion Request(RTR)fields which is used to request data from another CAN node. Inextended frame format arbitration field includes two extra 1 bit long fields: Substi-tute Remote Request(SRR) used for arbitration between standard and extendedframes and Identifier Extension(IDE) which differentiate the two formats. Arbi-tration field is followed by 6 bits control field which consists of two parts Reservedbits(r0, r1) 2 bits in length and 4 bits Data Length Code(DLC) which specify thenumbers of bytes in the data field that will follow. Data field is 0 to 64 bits. A 15bits Cyclic Redundancy Check(CRC) field and 1 bit CRC delimiter(DEL). CRCfield is followed by acknowledge(ACK) field which includes 1 bit ACK slot anddelimiter DEL. The last field in a CAN frame is End Of Frame(EOF) consistingof 7 bits to indicate the end of message.

2.1.5 Single Edge Nibble Transmission ProtocolSingle Edge Nibble Transmission(SENT) is a new digital point to point commu-nication protocol. It is a unidirectional communication between sensors and theECU. There is no coordination signal from the receiver (ECU). SENT frame con-sist a series of pulses in which the data can be measured between two fallingedges times. It was first introduced by the power train division of General Mo-tors and several other partner companies in 2005. SENT was first developed bya workgroup of Society of Automotive Engineers(SAE) later on it became an in-ternational standard SAE J2716 [46]. It is promising low cost alternative to theCAN and LIN standards. SENT can be used in those application where high res-olution data needs to be transmitted from sensors to ECU. Multiple derivative ofSENT protocol are developed like Short PWM Code(SPC) [40] which is similar tothe SENT basic standard proposed by SAE but SPC provides a synchronization


mechanism and shorter transmission time due to the utilization of the numberof nibbles for encoding data. The developed SENT/SPC driver has the supportfor all Infineon Technologies programmable linear Hall sensors such as TLE4998C[12] it is also compatible with TLE4998C supported SPC modes and SENT/SPCframe formats. Another SENT decoder implementation is provide by Infineontechnologies called SENT decoder for XC2000 [47] which is a complete softwarepackage. The receiver has the support for the following features:

• Reception and decoding of SENT frames

• Configurable number of data nibbles per frame

• Configurable SAE SENT or Infineon specific SENT protocol receiver

• Serial data decoding Error detection

The INTRINSIX technology developed a SENT Silicon IP transmitter module [13]which is fully compatible with SAE international J2716 communication standard.This IP is flexible and the data nibbles can be configure for different sensorsaccording to the required application. The IP has also interfaces for AMBA andAPB. The developed IP is based on Verilog RTL design that can be used for anyFPGA technology. It can be consider an alternate to lower resolution 10-bit A/Dsand PWM. The design of SENT silicon IP module is depicted in the given Figure2.12 a detailed explanation will be presented in section 4.5.

Figure 2.12: RTL design of SENT IP[14]

Melexis (Microelectronic Integrated Systems) developed MLX90324 [15] which isa monolithic sensor IC and only sensitive to the flux density coplanar with the IC


surface. MLX90324 sensor IC has support to decode the rotary angular positionfrom 0 to 360 degrees. The application area is mostly in automotive industries.MLX90324 produces an output signal which is proportional to the decoded angle.The output is selectable between Analog, PWM and SENT (SAE-J2716) Proto-col. The functional block diagram of MLX90324 is depicted in Figure 2.13 [15].According to the functional description shown in Figure 2.13 it is clear that theoutput can be selected among three different formats. The details explanationabout MLX90324 will be presented in section 4.5.

Figure 2.13: MLX90324 functional block diagram

SENT Application Areas

SENT protocol is an alternative to conventional CAN and LIN communicationstandards. So the targeted area of applications is all most same as CAN and LINbut it is rather simple to implement and has the possibility of high data rate.Some of the typical applications of SENT protocol are given below.

• Vehicle steering system for measuring steering angle or steering torque.

• Automotive chassis

• Rotary Position sensors and pressure sensors

• Throttle Position Sensors

• Mass air flow sensors

• Can be use as an alternative to lower resolution 10-bit A/Ds and PWM

• Temperature sensors

SENT Protocol description

The SENT frame is defined by a series of pulses in which the data are measuredbetween the two falling edge times. The first pulse is synchronization or calibrationpulse which is followed by Status or communication pulse. After the synchroniza-tion pulse all the 8 pulses are 4 bit (one nibble) long and there are eight nibbles


after the synchronization pulse is depicted in Figure 2.14. The pause pulse is op-tional and it is defined in the new SAE J2716, JAN2010 standard. There are sixdata nibbles the nibble value can be varied between (0-15). CRC nibble is usefor signal integrity purpose. Figure 2.14 describe the basic telegram of the SENTprotocol. The following are some features of the SENT protocol.

Figure 2.14: SENT frame

• It is a unidirectional (one wire) point to point protocol

• The data transmission is independent of the receiver no calibration from theMCU

• Simple Electromagnetic Compatibility(EMC) filter for the detection of SENTsignal

• 20% clock variation is allowed for transmitter

• Due to the large rise and fall time of the pulse, SENT signal is more robustto noise

SENT Data Frame Structure

The transmitted SENT frame from the sensor module is represented by a sequenceof pulses. The complete message contains two 12 bits sensors information thewhole frame is divided into 8 nibbles after the synchronization pulse. The lengthof Synchronization pulse is 56 clock ticks if there is no variation in the transmitterclock frequency. SAE J2716 standard described a 20% variation in the transmitterclock frequency according to this feature of SENT specification the synchronizationpulse time can be varied between (48.8 - 67.2) clock ticks. The basic unit of time iscalled a clock tick and its value can be in the range (3usec to 10usec) according toSAJ J2716 specification. Figure 2.15 describe the SENT frame format the secondpulse after the synchronization is called status or communication pulse which is4 bits (one nibble) wide.The length of each nibble can be calculated as (12 + N)where N is the nibble values which can be varied between (0 -15).


Figure 2.15: SENT frame structure

The nibble value depends on the amount of data being encoded in the data nibble.The 24 bits data are represented into two signals each 12 bits long. To understandthe complete SENT transmission sequence each pulse can be individually explainas follows:


Synchronization or Calibration pulse: The synchronization pulse is 56 clockticks long. The receiver can resynchronize with the sensor module by measuringthe exact time unit from the synchronization pulse of the transmitted signal. Thetotal length of the pulse is 56 CTs the first five CTs are low and the reamingis high is shown in Figure 2.16. The actual sensor data is measured during thesynchronization pulse.

Figure 2.16: SENT synchronization pulse

Status or Communication pulse: The status nibble is use for diagnostic pur-pose. The first two bits are reserved for specific applications like part number anderror information. The 3 and 4 bit of the status nibble can be used to send a shortor enhanced serial message specified by SAE J2716. One bit of a serial messagecan be send during each SENT complete frame transmission to send a 16 bit serialmessage 16 consecutive transmissions are needed.

Data Pulse: The data nibble pulse is used to transmit the actual of the sensorsmodule to the ECU. A maximum of six data nibbles (24 Bits data) can be transmitin one complete frame. The 24 bits data are divided into two signals each carriesthree data nibbles is depicted in figure 4. The width of the data nibble pulse variedwith the nibble value and can be calculated according to the formula. Data nibblepulse width = (12 + Nibble Value) where the nibble value change from 0 to 15.

CRC Pulse: For the data integrity the SAE J2716 Specification provide a 4bit CRC checksum nibble. The CRC checksum is calculated using the polynomialx4 +x3 +x2 + 1 with the seed value 5 (0101). The checksum is only calculated fordata nibbles and not for status nibble. The following error can be detected withthis crc checksum:

• All single bit errors.

• All odd number of errors.

• All single burst errors of length â 4

• 87.5% of single burst errors of length = 5

• 93.75% of single burst errors of length > 5

2.2 Hardware Platforms 21

Pause Pulse: According to the new SENT specification SAE J2716 JAN2010 anew pulse is defined in the frame this pulse is called a pause pulse which is use toprovide equidistant SENT transmission. The length of this pulse can be 12 to 768clock ticks.

2.2 Hardware PlatformsTo achieve the goals of the thesis which are described in the first chapter. Theselection of hardware platforms is made on the bases of the thesis requirements.In this section we will introduce the hardware platforms and their respective toolsthat are used for the prototyping and implementing of SENT protocol to achievethe goals of this thesis work. The SENT has been implemented on two differenthardware-platforms: Altera Nios II and Microchip PIC microcontroller for theanalysis of cost, resource utilization and performance. In the coming sections wewill present each of these platforms and their accessories for development of SENTprotocol. The complete details of their implementation will be described in thenext chapter.

2.2.1 Nios II Processor

Nios II is 32-bits Reduce Instruction Set Computer (RISC) soft core architecturedeveloped by Altera for their FPGA families. Because of its soft core Nios II isvery configurable and flexible. It provides customization options to its developerthat can be selected on the bases of system design requirements. The Nios IIprocessor core block diagram is shown in Figure 2.17.

Figure 2.17: Nios II core architecture


The general features offered by Nios II cores are:

• 32-bit instruction set, data path and address space

• 32 general purpose registers with optional shadows registers

• Floating point instructions for single precision floating point operations

• up to sex-stage pipeline depth(differ within cores)

• Single instruction multiply and barrel shifter

• Access to 2 GB of external address space

• Branch prediction

• Optional memory management unit (MMU)and Optional memory protectionunit(MPU)

• Hardware-assisted debug module enabling processor start, stop, step, andtrace under control of the Nios II software development tools

Nios II processor has three different types of cores: Nios II/f (Fast), Nios II/s(Standard) and Nios II/e (Economy). These cores are shown in the Figure 2.18,which is taken from the SOPC builder in quartus II design tool. The processorthat we use for the implementation of our design is Nios II/e (economy) type whichis highlighted in yellow in the Figure 2.18. The difference among these cores interm of performance, area, and memory utilization is given in the Figure 2.18.

Figure 2.18: Different Cores of Nios II Processor


Nios II/f (Fast): This is the most powerful core of Nios II family with the 25percent high performance then the standard core. This core has six-step instruc-tion pipeline and can execute one instruction per clock cycle which is higher thanthe both cores standard and economy type.

Nios II/s (Standard): Nios II/s "standard" processor core implements a smallprocessor core without a significant trade-off in software performance. The ALUof standard and fast cores provides the same performance. The standard core hasthe five instruction pipeline.

Nios II/e (Economy): The core size is smaller than standard and fast type.There is no instruction pipe line in this core only fetches one instruction at thetime. It is good for those applications where the implementation cost is requiredto be less.

2.2.2 DE2 Board

Altera DE2 is a development and educational board which is based on CycloneII Field Programmable Gate Array (FPGA) chip. DE2 board [16] is a completeembedded system and provides the ideal vehicle for learning and quick prototypingof design project in industries and academic sectors. The DE2 board provides avariety of features for the implementation of huge number of design projects alsouse for development of digital systems. The block diagram of the DE2 board isshown in the Figure 2.19

Figure 2.19: Block Diagram of DE2 Board


All these devices which the DE2 board provides are connected through the cycloneII FPGA so the user can configure the FPGA according to the requirement fortheir system design. DE2 board is provided with the quartus II hardware designtool and Nios II embedded processor a software design tool. The three tools DE2board, Nios II and Quartus II provides complete platform for the hardware andsoftware co-design of any system design. There is a large amount of learningmaterial for students and researchers are available on Altera website and also withthe de2 board accessories. For the design and prototyping of our system designwe use the DE2 board along with Quartus II software and Nios II processor IDE.The complete description of our implementation and how we used these tools willbe presented in the next chapter. Some of the devices that we used in our systemdesign are highlighted in yellow in Figure 2.19.

2.2.3 Microchip-PIC Microcontroller

We used PIC-microcontroller as an 8-bit processor for the implementation to becompare with the Nios II 32-bit processor. This section provides a short intro-duction to the PIC-microcontroller and the details description will be given inthe implementation part. Microchip Technology Corporation introduced an 8-bitmicrocontroller in 1989 called PIC (Peripheral Interface Controller). Later onthey introduced an array of 8-bit processors. The PIC microcontroller families in-clude PIC10XXX, PIC12XXX, PIC14XXX, PIC16XXX and PIC18XXX. Besidesthis Microchip now also produces 16-bit and 32-bit microcontroller they called(PIC24-16) bit and (PIC32-32 bit) series respectively.

Figure 2.20: PIC18F67J50 Development Board [1]


All PIC microcontrollers come in various size and functionality. The data process-ing speed of PIC is 8-bit at a time the data larger then 8-bit should be dividedinto 8-bit pieces to be processed. The PIC18 is an ideal choice for new systemdesigns because of its availability in different pins packages from 18 pins packageto 80 pins package also it is inexpensive and all the required hardware is availableon the one chip. We select the PIC18F67J50 member PIC18 family for the designof our system due to its low power consumption and USB boot loader which isreally easy to reprogram the device. The PIC18F67J50 is available in the form ofsmall development board as shown in Figure 2.20 on the previous page from theRobot-Electronics UK [1]. The details description about the implementation ofthis board will be presented in the implementation part.

PIC18F67J50 Microcontroller

PIC18F67J50 has RISC (Reduced Instruction Set Computer) architecture. Thisis the member of a new PIC18 family called PIC18F87J50 USB microcontrollers.This family has an advantage over the traditional PIC18-microcontrollers becauseof its high computational power, low-voltage USB and low-price. These featuresmake PIC18F87J50 family an ideal choice for low-cost applications. The devicesin PIC18F87J50 family come in two different pin packages 64-pins and 80-pinsFigure 2.21 show the 64 pins package of PIC18F67J50 microcontroller.

Figure 2.21: PIC18F67J50 64-Pins Package


As shown in the Figure 2.21 there are multiple ports available with some of theports pins are multiplexed with an alternate function from the peripheral featureson the device. Some of the key features of PIC18F87J50 USB microcontroller are

• USB (Universal Serial Bus) V2.0 with low speed 1.5Mb/s and High speed12Mb/s

• Flexible oscillator structure: two external clock modes up to 48MHz.

• Peripheral Features:

– Four programmable external interrupts– Two capture/compare/PWM (CCP) modules– Three capture/compare/PWM(ECCP) modules– I2C master and slave modes– Dual analog comparators with input multiplexing– Two enhanced USART modules (RS-485,RS-232 and LIN 1.2) supports

• External memory up to 2MB addressable

• Low power high speed CMOS technology

• Run, idle and sleep modes saving power

There are a number of features which make PIC18F87J50-microcontroller familyunique. Some of the family members of this family with the supports they provideare describe in the following table we use PIC18F67J50-microcontroller as a partof our system design which is highlighted in Figure 2.22.

Figure 2.22: PIC18F87J50-Microcontroller Family Member [2]

2.3 IBIS ModelThe simulation of digital I/O buffers with its chip packages and PCB can be doneusing traditional transistor level model approach. To use this approach the ven-dors should provide the complete spice model about their devices which reveals theproprietary device information to solve this problem, behavioral models of devices

2.4 ADS-Advanced Design System Tool 27

such as IBIS input/output (I/O) Buffer Information Specification model are intro-duced. IBIS became a standard later on for describing the analog behavior of thebuffers of digital devices. The IBIS model is use for signal integrity analysis suchas transmission line effect, crosstalk and ringing phenomenon on PCB (PrintedCircuit Board). The I/O buffer information is given in the form of voltage-current(VI) and voltage-time (VT) tables together with a set of rise and fall times of thedrive output voltage and packages parasitic in an IBIS model. The IBIS model ofa digital (I/O) buffer is show in the Figure 2.23.

Figure 2.23: A typical output buffer equivalent circuit

The V/I characteristics of upper and lower device as depicted in figure are givenin an IBIS model in two different tables each table consists of max and min valuesof VI characteristics. The actual VI curve varies between these two set of VIcharacteristics.

2.4 ADS-Advanced Design System ToolAdanced Design System is an electronic design automation software for RF, mi-crowave, and high speed digital applications. ADS software is introduced byKeysight EEsof EDA [17]. ADS provides easy to use interface, with a vast veritiesof simulation modes and models. The most common used is for circuit simula-tion, DC analysis, transient analysis, AC analysis, and S-paramets analysis. Thecomplete tutorial how to make project in ADS can be found here [18].

Applications

• MMIC Design: A Monolithic Microwave Integrated Circuit, or MMIC is atype of integrated circuit (IC) device that operates at microwave frequencies(300 MHz to 300 GHz)

• Signal Integrity Engineers


• RFIC Designers

• RF Microwave Board Designers

• RF System-in-Package RF Module Designers

• Power Electronics Designers

Key Features

• Complete schematic capture and layout design in the same environment

• Circuit and system simulators

• RFIC Designers

• Vast Varities of wirless libraries

• Simulation of IBIS Models

2.5 Sensors in automotiveThe luxury of today’s modern automotive would not be possible without the useof smart sensors. In order to enhanced the driving experience and provided moresafety the modern automotive is equipped with a huge number of smart sensors.These sensors can be used in different part of the automotive systems as shown infigure 2.24

Figure 2.24: Some typical automotive sensors

2.5 Sensors in automotive 29

The list of most common type of sensors that are used in modern automotive aregiven below. Some of the sensors are further described in details, such as positionsenors and temperature sensor because they used SENT interface which is relatedto the work of this thesis.

• Rotational motion sensors

• Temperature Sensors

• Positional/Speed Sensors

• Mass air flow sensors

• Throttle Position sensors

• Linear Hall Sensors TLE4998X

• Manifold air pressure sensor

• Fuel pressure sensor

• Crash sensors

• Airbag side impact sensor

• Exhaust gas Sensors

• Tire pressure sensors

2.5.1 Position or Speed sensorThere are different applications of the position sensor in automotive system. Themost commonly used is for determining the speed of the vehicle. The position sen-sor can be design using Hall-effect, photo electric effect, and inductive (variablereluctance/pick up coil) principles. The variable reluctance (pick up coil type) isa conventional way of measuring position of the gear tooth. The new speed de-termining sensors are based on the Hall-effect principle. We will describe in detailthe construction principle of position sensor based on inductive type technology(Faradayâs law). This sensor consists of a permanent magnet, soft-core and a coilis depicted in the Figure 2.25.

Figure 2.25: Position/Speed Sensor Construction


Advantages

• Manufacturing cost is low

• High level EMC low static internal resistance no extra electronic circuitryneed for protection.

• Due to the dynamic measuring there is no dc voltage drift problem.

• High temperature range

Disadvantages

• Due to the coil technology the size cannot be reduced.

• The output signal depends on the rpm unsuitable for quasi-static moments

• It is really sensitive to air-gap fluctuations.

Applications

These are some application areas in automotive where the position or speed sensorcan be used

• The sensor can be used as an engine speed sensor to measure the crankshaft-rpm.

• As a wheel speed sensor

• Camshaft sensor

• Needle-motion sensor

2.5.2 Temperature SensorVarious types of temperature sensor are used to measure temperature of differentparts of automotive system. The design of all these sensors use for temperaturemeasurement based on the principle of thermistor or Temperature sensitive re-sistor, thermocouple and semiconductor barrier layer or PN-Junction diode. Tomonitor the engine temperature for the proper amount of fuel injection the ECUmust know the correct engine temperature. The engine temperature can be mea-sure with ECT (engine coolant temperature) sensor, intake air temperature sensor(IAT) and Exhaust recirculation gases (ERG) sensor. To understand the workingprinciple these mentioned sensors it is important to first understand the operationof a simple thermistor. Most of the thermistor is NTC (Negative temperature co-efficient) its resistance increases with the decrease in temperature. Figure ?? showthe typical circuit diagram of thermistor the MCU can measure the temperaturefrom Vout of the thermistor. R1 and thermistor resistance make a voltage dividerthe change in thermistor resistance results a varying voltage at the junction.


Figure 2.26: Thermistor Circuit Diagram

The ECT sensor works on the same principle of thermistor. The change in temper-ature produces a change in resistance that causes a voltage change on the junction.The ECU sends a reference voltage to the sensor and received the change in volt-age by a feedback line. ECU determines the temperature of engine using the Vrefand the feedback voltage this process is describe in the Figure 2.27.

Figure 2.27: Engine Coolant Sensor

A typical engine coolant sensor can measure temperature from -40 to +130Câ

degrees. Applications of temperature sensor beside the engine coolant sensor and


there measuring temperature ranges used in various parts of the automotive systemas follows

• Air-temperature sensor: it is installed in an intake air passage for calculatingthe intake air mass the operating range is (-40 to +120Câ).

• Engine-oil temperature sensor: This sensor is use for calculating the serviceinterval operating range is (-40 to +170Câ).

• Fuel-temperature sensor: This sensor is use for calculating the precise in-jected fuel quantity operating range is (-40 to +120Câ).

• Exhausted gas-temperature sensor: The measuring range is (-40 to +1000Câ).

2.5.3 Linear Hall Sensors TLE4998XThe Infineon technologies [19] introduced a product family of programmable linearHall sensors called TLE4998X these sensors can be used in a verities of applicationsin automotive and non-automotive systems. The working principle is based on thehall-effect phenomenon. These sensors provide digital output protocol which isbased three different standards such is SENT (SAJ2716 Standard), PWM, andshort PWM codes (SPC). The family is divided into three different types of sensordue to its output protocol they are given below.

• Programmable PWM output-TLE4998P3

• SENT (SAJ2716 standard)-TLE4998S4

• SPC (Short PWM code)-TLE4998C3

The TLE4998S4 [20] is designed for the detection of position and rotation. Theoperation of TLE4998S module consists of a sequence of steps which is describedin simple block diagram is shown in the following Figure 2.28.

Figure 2.28: TEL4998 Linear Hall Sensor

The change in magnetic flux is detected by the hall-effect cell the output signalfrom hall-effect cell is then converted from analog to digital in the ADC cell tostabilize magnetic offset low pass filtering is done in the LPF cell and the outputsignal send to DSP unit for signal processing the final output from the TLE4998Smodule is a SENT signal based on SAJ2716 standard with the resolution of 16 bit.


2.5.4 Mass air flow sensors - MAF

The mass air flow sensors are used to deliver the correct fuel mass to the engine.The MAF sensors are more suitable than the volumetric flow sensors because thedensity of the air change with temperature and pressure. The most common useis in the electronic fuel injection engines.

2.5.5 Tire pressure sensors or TPMS

The tire pressure monitoring system TPMS is used to gives the information to thedriver by a display that the air in the tire are low.

2.5.6 Throttle Position sensors - TPS

The throttle position of the vehicle is monitored by TPS. The throttle positionsensor reports the position of the gas pedal to the ECU. The ECU then determinethe amount of air flow to the engine and the amount of fuel to be injected to theengine.

2.5.7 Manifold air pressure sensor - MAP

The manifold air pressure senses the engine load. The MAP senses the intakevacuum and respond accordingly. If the vacuum in the intake manifold is wide,the engine sucks in more air and which intern increase the fuel to air ratio. Whenthe intake vacuum drops the engine sucks less air and thus reduced the fuel con-sumption.

2.5.8 Fuel pressure sensor - FPS

The fuel pressure sensor or also called fuel tank pressure sensor is an electronicdevice, which is used in automotive to measured the quantity of fuel remains inthe fuel tank. The measurements are made by sensing the internal pressure of thetank. This data is then passed to power train module (PCM) which in turn passesthe fuel need for the engine to the fuel pump.

2.5.9 Crash sensors

Crash sensors make the decisions about the deployment of the air bag on the basesof data it collects from surroundings. There are different types of crash sensorsthat are equipped in the vehicle, such as frontal crash sensors which is located inthe front of the vehicle, near the engine, in the passenger compartment or in theECU, other examples of crash sensors are side impact sensor and rollover crashsensors.


2.5.10 Airbag side impact sensorAirbag side impact crash sensors is located in the doors of the vehicle. The sensorsare activated when the vehicle is hit on either right or left of the vehicle. They aremost commonly installed in the front doors.

2.5.11 Exhaust gas SensorsThe primary purpose of exhaust gas or exhaust gas temperature sensors is to sup-port catalytic converters. But these sensors are also very important for protectingcomponents from overheating which are located in the flow of hot exhaust gas.

Chapter 3

Comparison of AutomotiveCommunication Protocols

This chapter presents the comparative study of some of the communication pro-tocols that were introduced in previous chapter. In the previous chapter the mainfocus was on the protocol description and their features and applications in generalwhile in this chapter we will try to dig a little deeper to explore the challengesthat demands for a new communications protocols and their features comparisonthat makes them feasible for certain applications.

3.1 OverviewToday’s modern cars are the wonderful combination of electronics and mechan-ics. As computer systems are becoming more pervasive, they are also becomingintegral parts of objects all around us and cars are no exceptions. The vehiclesmanufactures are competing for market edge and satisfy their costumers needsby inserting more and more new sophisticated features and gadgets with lowercost. They also have to fulfill regulation requirements related to safety, emission,environment, etc. All these factors somehow contribute in more semiconductorconsumption in vehicles. The insertion of semiconductor eliminate some of thebulky and complex mechanical and hydraulic system that results in reduction ofover-all system cost, weight and better performance. The inclusion of smart elec-tronics control units makes modern vehicles a complex distributed system with thecapabilities of better control, monitoring, scalability, ease of configuration, safetyand communication. The intercommunication among these ECUs requires robustand highly efficient communication interfaces with the ability to satisfy the stricttiming requirements from different subsystems.

Couple of decades ago in vehicles communication among ECUs was mostly donethrough point to point interfaces. The side effects of dedicated point to pointinterface was the size of wiring harness that ultimately results in increase in cost,

35

36 Comparison of Automotive Communication Protocols

weight and difficulties in maintenance. To overcome this problem the networkprotocols were introduced that effectively reduced the amount cabling harness,brought a lot more flexibility. Embedded systems in vehicles are classified accord-ing to their functionality, architecture and constraints into different domains: pow-ertrain domain, chassis domain, body domain, telematic domain and the passivesafety domain. The unique communication requirements of each domain enablesthe coexistence of multiple protocols in vehicles. SAE classified the in vehicle net-work protocols based on their data rates and functionality. As Figure 3.1 showsthe different electronics modules classified according to SAE classifications. Thedetails of the SAE network protocols classes will be presented in the next session.There are a number of protocol standard available for in-vehicle communication.

Figure 3.1: Automotive electronics systems classifications with respect to SAEclasses [3]

The existence of standards facilitate the integration of components from suppli-ers that have expertise in the specific product. The industrialization of in-vehiclecommunication significantly improves the quality of the product and reduces thecost of the system.

3.2 Comparison of Network ProtocolsIn the previous section we shortly described SAE classification of network pro-tocols. Figure 3.2 shows the most commonly adopted protocols for automotiveaccording to their data rates. As it can be seen in the diagram that a protocolfalls in a specific class based on its data rates. It is also clear from the diagramthat the protocols with higher data rates have relatively higher communication

3.2 Comparison of Network Protocols 37

cost per node. It is also one of the reason to have more than one communicationprotocols in an automotive system.

Figure 3.2: Automotive protocols comparison based on their data rates [3]

SAE classify in-vehicle protocols into four classes: Class A, Class B, Class Cand Class D. Specific protocol standards exist for each class except Class D. Anyprotocol with data rates higher than 1Mb/s comes under Class D.

Class A: The protocols with data rates lower than 10kb/s comes under theClass A category. As in Figure 3.1 have been shown the automotive electronicmodules associated with the body domain are mostly implemented with low datarates protocols. Low implementation cost is the most attractive feature of ClassA protocols. But there is lack of globally accepted Class A standard. There areseveral Class A protocols but the widely adapted are LIN and Time TriggeredProtocol (TTP)/A [48]. CAN can also be implemented as Class A protocol.

Class B: Class B protocols have data rates between 10kb/s to 125kb/s. Themajor uses of Class B protocols in vehicles are for general information sharing, di-agnosis, instrumentation and body electronics. J1850 [21] adapted by SAE as ClassB standard and has wide acceptance among North American car manufactures.

38 Comparison of Automotive Communication Protocols

J1850 has two versions: 10.4kb/s single wire with Variable Plus Modulation(VPM)encoding and 41.6kb/s two wires with PWM encoding. While its counter part andwidely accepted among European car manufactures is CAN.

Class C: The data rates ranges from 125kb/s to 1Mb/s. Class C protocols aremainly used for real time control, powertrain control, engine management, etc. Amore comprehensive list of Class C protocols applications are shown in Figure 3.1.CAN 2.0 is the most dominate Class C standard protocol. Other Class C protocolstandards are SAEJ1939 and SAEJ2284. These protocols adapt CAN as a base somedium access and message formate is consistence with CAN. Another feature ofJ1939 and J2284 is they target all layers of network model.

Class D: As stated earlier SAE does not specify any standard for the Class Dnetwork. Class D protocol targeted area is multimedia applications. The widelyadapted protocol for such applications across Europe among car manufactures isMedia Oriented System Transport (MOST) [22]. MOST is de-facto standard formultimedia networks in automotive industry. The alternatives to MOST are D2B[43] and IEEE1394 [23].

3.3 Features Comparison of Network and Pointto Point Protocols

Table 3.1 gives features comparison of some of the network and point to pointprotocols that are widely adapted by the automotive industry. In previous sectionswe emphasised on the use of network protocols, their advantages and how theycontributes in the cost reduction of the system but it will be worth mentioninghere. why point to point protocols still exists? Since lowering the cost of systemis one of the major factor behind existence of numerous network protocol insidea vehicle, this is also a reason behind the existence of point to point protocols invehicles. Another reason why point to point protocols still exists is the situation tointerface a standalone system. In such situations or the scenarios where only onesided data traffic is required the use of network protocols is waste of bandwidthand resources. These and some other reasons dictate the car manufactures tokeep exploring more efficient and cost effective point to point protocol solutionsalong with network protocols. There are several point to point protocol standardsexists that are supported by some of the leading automotive solution providerand actively used by the major automotive vendors. Some of these protocols areSENT, PSI5, PWM, etc.

3.3 Features Comparison of Network and Point to Point Protocols 39

Table3.1:

Features

compa

rison

ofvehicles

protocols

Features

Protocols

CAN[24]

J1939[25]

J2284[26]

LIN[27]

MOST

[28]

PSI5[29]

PWM[30]

SENT[46]

TTP/

A[31]

Med

ium

Twist

edPa

irTw

isted

Pair

Twist

edPa

irSing

leW

ireOptical

Fibe

rSing

leW

ire3

to4

Wire

sSing

leW

ireSing

lewire

/Twist

edPa

ir/Opti-

cal

Encoding

NRZ

NRZ

NRZ

NRZ

Dua

lPh

ase

Man

chester

Encoding

-Fa

lling

toFa

lling

Edge

NRZ

Med

iaAccess

Con

tention

Con

tention

Con

tention

Master-

Slave

CSM

APo

int-to-

Point

Point-to-

Point

Point-to-

Point

TDMA

ErrorDe-

tection

CRC

CRC

CRC

CRC

CRC

Parit

yBit

-CRC

CRC

Data

Rate

10kb

/s-

1Mb/

s250k

b/s

500k

b/s

20kb

/s24Mb/

s125k

b/s

-24kb

/s-

37kb

/s>1M

b/s

Data

Leng

th0-8b

ytes

0-8b

ytes

0-8b

ytes

8bytes

60by

tes

10bits

-24bits

-

Cost

Med

ium

Med

ium

Med

ium

Low

High

Low

Low

Low

Low

Num

ber

ofNod

es32

3232

1-15

-1to

man

y1

1-

Protocol

Typ

eBus

Bus

Bus

Bus

Bus

point-to-

point

point-to-

point

point-to-

point

Bus

Func

tion

Con

trol

and

Diagn

ose

Con

trol

and

Diagn

ose

Con

trol

and

Diagn

ose

Sensors

and

Actua

tor

Multim

edia

Sensors

and

Actu-

ator

Sensors

and

Actua

tor

sensors

and

Actua

tor

Sensorsa

ndActua

tor

Chapter 4

SENT-ProtocolImplementation on twodifferent platforms

In the previous chapters we described SENT protocol. We also discussed someresearch questions in the introduction chapter. SENT protocol is specially designfor software implementation on microcontrollers. The aim of this chapter is toimplement SENT protocol in software using two different platforms (32-bit and8-bit). The purpose of implementing SENT on two different platforms is to findhow much memory footprint is used and how much the processor overhead on8-bit and 32-bit platforms.The comparison of memory footprint and processoroverhead is also checked with two different implementation techniques (Floatingpoint and Fixed point). The design prototype of the SENT protocol its hardwareand software setup will be discussed. The implementation process has a numberof steps to achieve the main goal of the thesis and these steps are individuallyexplained in this chapter.

4.1 Research Method

A procedural approach is use for a systematic process in research in order tobetter understand the design process to achieve the final goal. "Research methodis defining a way of investigating an empirical topic by following a set of pre-specified procedures" [49], we used the "System Development Research Method" toachieve the goal of this thesis. The systems development method consist a numberof steps which is depicted in figure 4.1.

41

42 SENT-Protocol Implementation on two different platforms

Figure 4.1: System Development research method

"The system development research approach denotes a way to perform researchthrough exploration and integration of available technologies to produce an artifact,system or system prototype" [49].

Concept building

In this thesis research in the first phase we made a pre-study related to SENT,PWM and some other commonly use automotive protocols. The aim of the thesiswas clear and understood from the mentioned research questions in chapter 1 ofthis document.

4.2 Decisions and method 43

System building

According to the research questions a procedural approach was use for achieving ofour goals. The development of SENT protocol is performed on different platformsfor the better performance and a simulation based approach is use for SENTsignal integrity check. Some of the design decisions were made according to thearchitectural design which was created for the system development.

System evaluation

The developed software on two different platforms was tested for better perfor-mance and less resource utilization with respect to the research questions. Therobustness of the SENT and PWM signals was tested using Spice simulations. TheSENT protocol provides a better solution in term of performance as well as signalintegrity comparing to PWM according to our research questions.

4.2 Decisions and methodThe main aim of this thesis is to implement SENT receiver in software on twodifferent platforms for the comparison of resource utilization and memory con-sumption. The decisions are made according to the requirements of the thesismain goals. To understand and analyze the performance of a good design solutionour implementation are based on two implementation methods using fixed pointand floating point integers implementation design further we will extend our im-plementation designs to two different processors implementation design and willcompare it for the best solution in terms of cost, resource utilization and memoryconsumption. The last part of this implementation is the signal integrity compar-ison of the SENT and the conventional PWM signal which will be presented inthe next chapter.

4.2.1 Hardware PlatformsWe divide the SENT-receiver design into two implementation designs accordingto the different platforms used for implementation.

• SENT-receiver Hardware-design with Altera FPGA Board.

• SENT-receiver Hardware design with Microchip PIC

The platforms that have been used for implementation will be described in thefollowing section.

4.2.2 SENT-Decoder design on Altera FPGA DE2 BoardIn this section we will give a review of the design prototype. The system has beendesigned using Altera DE2 board which is commonly used in different educationorganizations for prototyping. The components that are used in the design of


SENT decoder prototype are depicted in figure 4.2. The system consists of SENT-transmitter which is a custom developed sensor module on Xilinx Spartan IIIFPGA board which is mentioned in section 4.2.4 of this chapter.

Figure 4.2: SENT-Receiver and Transmitter

The above diagram gives the complete design overview of the system. The XilinxFPGA board is used for the prototype of the SENT-transmitter the data are sentin a serial way. Two wires are used for communication one is common GND andother is used for serial data transmission. DE2 board provides us the GPIO forcommunication with the external devices we used GPIO pin to receive SENT-datamessage. The received data are displayed in two ways the first it is displayed inthe Nios II console and another way is to display it on the DE2 board LCD. Thereceived data-message has been printed the data in both ways. Quartus II wasused to first designed the system in the SOPC builder and then to download it tothe DE2 board for prototyping of the system.

4.2.3 SENT-Decoder design using Microchip PIC18PIC microcontroller is vastly used for the prototyping of embedded system ineducational and industrial organization. To fulfill the requirement for the imple-mentation for our thesis we used PIC18F67J50 development Board with microchipMP-Lab IDE Version 8.80. This Board contains a UBS-boot loader due to whichit is really easy to download the program from the MP-Lab IDE and can be re-programmed easily. The hardware resources that are providing by this board wereenough for our implementation purpose. Figure 4.3 show the PIC18F67J50 devel-opment board. The details features of this board are mentioned in section 2.2.3 ofchapter 2.

4.2 Decisions and method 45

Figure 4.3: DEV PIC18F67J50 Board [1]

The module can be powered form the USB or in case of external power source4.5 to 9V to pin 50 and 0V Ground to pin 25 of the board should be given. Thismodule is compatible to use with the microchip MP-Lab and the program can bedownload through boot loader. A character LCD is being used with this boardfor displaying results. The complete hardware interface for this implementationdesign will be presented in the hardware setup section.

4.2.4 SENT-Transmitter (Sensor) ModuleSENT transmitter has been developed using Memec design Spartan-3 LC develop-ment broad. This board is commonly used for developing designs and applicationsbased on Xilinx Spartan-3 FPGA family. It provides a good platform for mod-ular development. The block diagram is depicted in figure 4.4 which shows thedemonstration of the board and the available resources.

SENT data signal are defined using 10 usec clock tick according to the require-ment of the thesis work. The encoding scheme and the frame structure of theSENT data frame are the same as described in chapter 2 section 2.1.5. The out-put signal of SENT-transmitter module is depicted in figure 4.5 it is measuredwith digital oscilloscope.The encoded signal consists of two data messages and one


Figure 4.4: SENT- Transmitter (Sensor) Module

serial message. The first three data nibbles which are marked by Data1,Data2and Data3 represents the first message. The second message is represented byData4,Data5,and Data6. The details information about serial message are givenin section 4.3.5 of this chapter.

Figure 4.5: Sensor Oscilloscope output

4.3 SENT data frame Transmission and Reception 47

4.3 SENT data frame Transmission and Recep-tion

In this section we will give a complete review of the SENT-frame how the data isencoded also how we will decode the encoded signal transmitted from the sensormodule as described in section 4.2.4. Also how the CRC algorithm is implementedin software for both data and short serial messages will be presented in this section.

4.3.1 SENT data frame StructureSENT protocol message consist a sequence of pules which are sent by the trans-mission module repeatedly after a specified pause pulse in the same pattern. Thesequence of these pules are depicted in figure 4.6 . There are total of nine puleswhich is followed by a pause pulse.

Figure 4.6: Complete Frame Timing Diagram

The first pulse is called the calibration or synchronization pulse which is 56 clockticks long but there is the possibility of 20 percent variation due to the crystaloscillator frequency variation in the sensor. According to the requirements of thethesis we implement one clock tick equal to 10µsec there fore the synchronizationpulse is 560µsec long. The clock frequency variation in the transmitter (Sensor)can be corrected with this calibration pulse.

Synchronization pulse is followed by status pulse. This pulse is use for the errorcode or information about the part number etc. Status pulse is four bits long. Thefirst two bits are reserved for specific applications the remaining two bits define aserial message. A complete serial message is 16 bits long and can be completedin 16 consecutive SENT-data message transmission. The 3rd bit is use for thestart of the serial message and the 4th bit consists of one bit data in one completetransmission of the SENT-message. The status nibble is depicted in figure 4.7.

Status nibble is followed by six data nibbles which consist of 24 bits data. Firstthree nibbles of the data nibbles define message1 which consists of 12 bits dataand the second three nibbles define message2.

The checksum nibble is a four bit CRC which is use for diagnosing the error in


Figure 4.7: Structure of Status Pulse

the data messages of the data nibbles only. To calculate the CRC the followingpolynomial shall be used x4 + x3 + x2 + 1 and the seed value is 5(0101) which ismentioned in chapter 2 section 2.1.5.

Pause pulse can be used for the equidistant SENT- frames transmission, or con-stant number of clock ticks. The minimum length will be 12 ticks and the max-imum length will be 768 clock ticks in our case the length of the pause pulse is730µsec by using 1 clock tick equal to 10µsec the details description is give inchapter 2 section 2.1.5.

4.3.2 Data Message EncodingSENT message are encoded in the form of continuous pulses. These pulses arerepeatedly transmitted from the sensor module with a specified gap that is definedin the pause pulse. Each pulse is four bit long that is equal to one nibble. Theminimum length of the pulse is 12 clock ticks which is equal to 120µsec in ourcase. The pulse is driven low for 5 clock ticks and driven high for the rest of theperiod. The shortest period pulse is shown in the figure 4.8 it is driven low for50µsec and high for the rest of the period.

Sensor module continuously transmitting SENT data frames, it shall start a newmessage immediately in case of reset. The length of the data nibble pulse widthcan be defined by Data Nibble Pulse Width = (12 + NibbleV alue) = 12 + Mwhere M is the nibble value and can have the value from 0 to 15. The minimumand maximum value that data nibble pulse can have, are lies between this range12 + 0 = 12 clocks (120µsec at 10µsec clock tick) or 12 + 15 = 27 clocks ticks (270µsec at 10µsec CT). One complete SENT-transmitted frame and the value ofeach nibble are shown in figure 4.6 that is mentioned before.

4.3.3 Data-Message DecodingThe receiver module captured the SENT encoded signal by measuring time be-tween the two consecutive falling edges of the calibration pulse. The period ofcalibration pulse is equal to the pulse duration plus ∓20 percent variation of sen-sor module clock frequency. To get the correct period of all the remaining pulses

4.3 SENT data frame Transmission and Reception 49

Figure 4.8: Pulse shape

after calibration pulse its measured period shall be used for adjusting the succeed-ing pulses period time. A delta factor is used for correction which is the ratiobetween the calibration pulse period and the nominal 56 clock ticks in our case560µsec period.

∆ = Measured Calibration pulse560µsec (4.1)

To calculate the nibble value of each data nibble pulse the SAE J2716 standarddefined the following algorithm.

Data Nibble Value = Round

Measured Pulse Period∆ − 120

10

(4.2)

By using this algorithm we can find the correct values of all the data nibbles pulsesand the CRC pulse. Table 4.1 show the duration of each nibble pulse period andits binary equal values. These values are further used in table 4.2 in such an orderthat we can construct and decode the real data messages that has been encodedin the SENT-transmitted signal. As we discussed earlier our unit time is 10µsecso all the data nibbles pulses will be decoded according to this unit.

Table 4.2 show the data message in the decimal notation and this is the real datathat has sent by the sensor-module in an encoded form of SENT-frame. We will


Data Nibbles Pulse Period Time Unit(10µsec) Nibble Value - 12 BinaryData Nibble 1 150µsec 15 3 0011Data Nibble 2 260µsec 26 14 1110Data Nibble 3 200µsec 20 8 1000Data Nibble 4 190µsec 19 7 0111Data Nibble 5 250µsec 25 13 1101Data Nibble 6 120µsec 12 0 0000

Table 4.1: Data Nibble pulses and its duration

MSB LSBData_1 Data_2 Data_3 Data_4 Data_5 Data_6

0011 1110 1000 0111 1101 000012 Bits Message 1 12 Bits Message 2Decimal = 1000 Decimal = 2000

Table 4.2: Construction of Data Messages

implement this algorithm to find the value of the data nibble and CRC will bedescribed in details in software design section.

4.3.4 CRC Calculation

The integrity of the data can be check with CRC nibble value according to thealgorithm defined in SAE J1627 [46] standard. To check error in the received datathe checksum is first initialize with the seed value 5. The checksum then multipliedby 16 and added to the current nibble value. The calculated value of the tempCSis located in the 256 array lookup table and adding 1 to the value picked fromthe table will us the update value of checkSum. This new value of the checkSumwill be used as a seed for the second data nibble value and this way all the datanibbles checksum will be find. listing of the following algorithm is given

CheckSum=5;f o r i =1: l ength ( data )

tempCS=data ( i )+CheckSum∗16 ;CheckSum=CRC4Table (tempCS+1);

end

As shown in the listing CRC checksum as multiplied by 16 which is a series of shiftleft by 4 and followed by a 256 element array lookup table. The CRC checksum canalso be implemented as a bit-wise exclusive OR operation with a reduced sized of16 element array lookup table, these both 256 element array lookup and 16 arraylookup are given in the appendix A.

4.4 Nios-II Based Prototype 51

4.3.5 Short serial messageBesides six data nibbles that are available in the SENT frame for data transmis-sion there is also one 16 bits serial message that is sent in the 16 consecutivetransmission of the SENT frame in which the first four bits are the message ID,the second 8 bits are the data and the remaining four bits is the CRC for theserial message. The serial message is sent one bit in one complete transmissionthis encoding technique is demonstrated in figure 4.9.

Figure 4.9: Frame Structure of Short serial message

In one complete SENT transmission we sent 24 bits data in the data nibbles with 1bit data of the serial message in the 3rd bit of the status nibble. After successfullycapturing 16 frames of SENT protocol we can send 32 bits data. According to SAEJ2716 [46] Standard there is also an enhanced serial message which can providelarger bandwidth for data transmission but we mainly focused on short serialmessage.

4.4 Nios-II Based PrototypeIn this we will discussed about the software design,IDEs setup both for hardwaredesign and software design (Quartus-SOPC), and hardware setup (DE2) for imple-mentation of SENT-protocol using fixed point and floating point implementationapproaches.

4.4.1 Development Environment SetupNios II IDE is used for software development, It is an interface for the Nios IIprocessor. All the tasks of the software development is accomplished in the IDE,which include editing, building, and debugging of the developed program. TheIDE includes flash programmer that can be used to program flash memory onthe target board (DE2). A new project is created in the Nios II IDE is depictedin the figure 4.10. After creating project a sample c-file is created called hello-world which can be modified to write code. Nios-II uses GCC-compiler to compile


c-programs.

Figure 4.10: Creating Project in Nios II IDE

SRAM and JTAJ-UART setting is configured in the system library setting of theproject as shown in the figure 4.11. The SOPC system file called .ptf is selectedfrom the SOPC builder box. All the configuration is make in the Nios-II IDE.

Figure 4.11: Project Configuration


4.4.2 Integration of Hardware and SoftwareTo build the prototype of the system for achieving the goals of this thesis softwaredevelopment envelopment is build for testing and writing of the software. In section4.2 we mentioned about the hardware platforms that has been used to prototypeof SENT-decoder. The prototype is based on the combined design of hardware andsoftware. The software is written in C-programming language. As we mentionedearlier our development environments or IDEs are Nios-II and Quartus-II. Thefundamentals components that build a HW/SW software system are depicted inthe figure 4.12.

Figure 4.12: System Hardware Architecture

Nios II soft-core is connected with JTAG, on-chip RAM and PIOs through Avalonbus. SRAM is used to store the instructions of Nios II core during execution ofthe program. Communication between the host PC and system are performed byUSB-Blaster cable. Sensor module is connected to Nios-II core through PIO. NiosII core receive data from the sensor module using PIO pin.

4.4.3 System design in SOPC builderThe design of the system is first made in the SOPC builder by creating a newproject in Quartus II software. SOPC Builder is also a development tool and is partof the Quartus II software. The system is generated and configured in System-on-Programmable-Chip (SOPC) Builder tool. SOPC automatically connects systemcomponents with the Avalon bus. The clock frequency is generated by 50 MHz onboard crystal oscillator to run the system. The system was generated in SOPCBuilder with Nios II, SRAM memory, JTAG and PIO as depicted in figure 4.13.

How the system components are configured in the SOPC builder will be presentedas follow.

Nios II Processor: We used the economy core of Nios II (e). There are threetypes of Nios II soft-core and they were described in detailed in section 2.2.1 of


Figure 4.13: System configuration in SOPC-Builder

chapter 2. The detail about each core has been discussed in chapter 2. Our systemis based on the economy type of Nios II, it optimized for minimum logic usage. itused 600-700 logic elements as shown in the figure 4.13.

SRAM: An external SRAM(Static Random Access Memory) is used for storingthe instructions during the execution process. The size of SRAM is 512 KBytes ofexternal memory and the width is 32bits. SRAM is initialize in the SOPC builder.

Parallel input output (PIO): PIO is initialized to receive the data from thesensor module. The parameter settings is change according to our requirement ofcapturing the SENT-signal. The edge capture registered is set to falling edge. Thewidth register is set to 1 bit because the data is coming in serial form. Interruptis set to generate IRQ and it is set to edge captured mode so whenever a fallingedge occurred it should generate an interrupt. JTAG UART is initialized and itswidth is set to 16 bytes.

Character LCD: To display the data message on the display the character LCDis institutionalized in the SPOC Builder.

Timer-IP: Two timer-IPs (Timer0andT imer1) are included and configured inthe SOPC builder Timer0 is used for the pulse period time calculation and Timer1is used to measure time of functions such as printf(), calculation() and delta.

Performance Counter Core: Performance counter core has been added in thedesign code profiling. It is a set of counters which keep track clock cycles timingeach section of the code. How it can be use to measure the time of the code sectionit will be described in the code profiling section of the this chapter.


4.4.4 Software DesignBefore starting the development of decoder prototype application in software usingfloating point and fixed approaches it will be worth to discuss about data typesand differences between fixed and floating point data. In computer programminglanguage a data type is defined as the range of permitted values and operationsthat can be performed on the data type. The data types are use to classified andidentified different types of data such as integers, floating point number, character,and strings etc. The language defined the range of values for the given data types.The data type also called intrinsic data types supported by C-Language that aredepicted in the figure 4.14. According to the format use to store and manipulatenumbers in the devices (Processors) these devices can be categorized into Fixedpoint and Floating point.

Figure 4.14: Data Types of C-Language [4]

Fixed point and floating point numbers have its own advantages and disadvantagesin computer programming such as most of the low-cost embedded processors doesnot provide Floating Point Unit (FPU) for representing fractional values in thatcase fixed point integer are useful. In general Fixed point processor are cheapercomparing to floating point but floating point processor provides better precision,higher dynamic range, and a shorter development cycle.

Fixed Point Integers: In fixed-point representation each number is most com-monly represented by a minimum of 16 bits, although different number of bitlength can be use for number representation. A significant improvement in exe-cution speed can be obtained by inheriting integer math-hardware support in alarge number of processors by implementing algorithms using fixed-point integersmathematics. This increase in speed will come at the cost of reduced range andaccuracy of the algorithms variables. A meticulous algorithm can be build byimplementing a double or single precision floating-point data but there is a sig-nificant processor overhead needed for floating-point calculation due to the lackof hardware based floating-point support. To Increase the execution rate of thealgorithm for mathematical calculations two’s complement signed fixed-point rep-resentations can be used for this reason the programmer need to create a virtual


decimal place in between two bit locations for a given length of data.

Floating Point Integers: To represent real numbers on computers today themost commonly use standard is IEEE-754 [39] floating point standard. The IEEE-754 floating point standard can be implemented in software, hardware or both.The floating point integers implementation provides higher computation accuracyfor execution of speed instead of fixed point integers. The reason why the floatingpoint processor are better than the fixed point because the floating point provideshigh dynamics range, precision and shorter development cycle on the other handthe fixed point processors are cheaper than the floating point processors. The keyfactor that a floating point processor can perform better than the fixed point isthe signal-to-noise ratio (SNR). In general the floating point processor has veryless quantization noise than the fixed point processor. We implement the SENTprotocol receiver by using both techniques fixed point and floating point. Thesetechniques are further discussed in details in section 4.4.5 and 4.4.6 of this chapter.

4.4.5 Design with Floating-pointBefore we start to describe the developing the program using floating point somecomponents should be configured for developing the application program.

Timer: Timer-IP is included in the design from the SOPC builder for measuringtime. The timer-IP is import in the Nios IDE through the system header fileso it communicate through the system file that is generated automatically aftergeneration and compilation of the quartus design. The timer configuration isshown in the listing.

#de f i n e TIMER_START IOWR_32DIRECT(TIMER_0_BASE,4 , 0 X80000000 )#de f i n e TIMER_STOP IOWR_32DIRECT(TIMER_0_BASE,4 , 0 X00000000 )#de f i n e TIMER_RESET IOWR_32DIRECT(TIMER_0_BASE,4 , 0 X40000000 )#de f i n e TIMER_READ IORD_32DIRECT(TIMER_0_BASE, 0 )

Timer 1 f o r time c a l c u l a t i o n#de f i n e TIMER1_START IOWR_32DIRECT(TIMER_1_BASE,4 , 0 X80000000 )#de f i n e TIMER1_STOP IOWR_32DIRECT(TIMER_1_BASE,4 , 0 X00000000 )#de f i n e TIMER1_RESET IOWR_32DIRECT(TIMER_1_BASE,4 , 0 X40000000 )#de f i n e TIMER1_READ IORD_32DIRECT(TIMER_1_BASE, 0 )

Interrupt: To capture the falling edge the interrupt is set in the PIO configura-tion in the SOPC builder design. Whenever a falling edge occur at the PIO anIRQ is generated. The NIOS II architecture provides 32 non-vectored hardwareinterrupts. The processor will jump to a single exception address that is used forall interrupt and exception processing in the system [41].

In this implementation method we use floating point representation for the calcu-lation of the data nibble value. Floating-point representations provides a widerdynamic range programmers do not need to specify the number of digits after the


radix point. Nios II processor have the support for floating point operation. Wedeveloped the algorithm described in section 4.4.3 using floating point representa-tion to calculate the data nibble values.

Pulse time = Round

Timer read value∆ − 120

10

(4.3)

Where Delta is equal to

∆ = Calibration pulse time = T2-T1560µsec (4.4)

The implemented algorithm is shown in the listing, here we defined a function forthe calculation of data nibble values. Delta time is a fraction of timer measuredvalue and calibration pulse time.

i n t c a l c u l a t i o n ( f l o a t a )s t a t i c i n t data_value ;data_value=round ( ( ( a/delta_time ) −0 .000120)/0 .000010) ;r e turn data_value ;

delta_time=(t [ i ] [ 0 ] / 5 0 0 0 0 0 0 0 . 0 ) / . 0 0 0 5 6 0 ;

The delta time is declared as a float to have a support for wide range of memoryspace for storing its value. The value that is store at the first element of the arrayis use to find the first pulse width. We will explain the complete algorithm thatcapture and decode the data messages using the floating point algorithm in section4.4.7 here we will focus on detection of the synchronization pulse. PIO status aremonitored by an interrupt service routine when whenever a falling edge is detectat PIO an IRQ request is send to processor the free running timer value is readat that particular time and it is stored in a variable "T1" this process is shownin the flowing figure 4.15 with the detection of another falling edge a new IRQ issend and the timer is read and its value is store in a variable "T2". The difference"T1" and "T2" gave us the synchronization pulse time, if the synch pulse time isnot equal the synch pulse (560 ∓20 percent) the process repeat for another synchpulse. All the pulse periods after synchronization pulse is measured in the sameway and stored in array. The described algorithm is for the calculation of the datanibble values with having tolerance of ∓20 percent clock variation. Which meansour synchronization pulse value shall lies between 448µSec and 672µSec.

4.4.6 Design with Fixed-pointHigh level language have the support for floating point math. Floating pointprocessor are high language friendly and thus programmer need less time for im-plementation. Besides this most of the modern microprocessor have hardware


Figure 4.15: Detection of Synchronization Pulse

floating point unit for calculation. Microprocessor that only support integer sig-nificant overhead can be encounter to follow floating point both in ROM size andexecution time. To solve this problem fixed point calculation can be done by ex-ecuting this with inter function. In our second implementation method we usedfixed point arithmetic for the calculation of the data nibble value. To developedthe program using fixed point another algorithm shall be implemented for findingthe data nibble values. To understand how we can implement in the fixed pointarithmetic we will use an example for demonstration. Suppose we have a value.1234 we can represent this number 1234 in fixed point data type by a scalingfactor of 1

10000 similarly a huge number like 50000000 can be represented 50 by ascaling factor of 1000000. In general we can scale any small or big number usingthe scaling factor by performing two integers operations a multiplication followedby division. 1.234 = 1234/1000 −→ M/D = 1234/1000 where "M" and "D" in-tegers scaling factors. To calculate the synchronization pulse time in fixed pointimplementation method. We ignored the six zeros of the 50000000 Hz frequencycomponent and multiplied the resultant value of the synchronization pulse with ascaling factor of 10000 it is shown in the following code section.

sync_time=(t [ i ] [ 0 ] / 5 0 ) ∗ 1 0 0 0 0 ;

where t [ i ] [ 0 ] i s our f i r s t pu l s e measured time


Now the next step is to calculate the delta time and data nibbles values. Wedeveloped a new algorithm that is used to find the data nibbles values using fixedpoint arithmetic calculation. The shortest period of pulse is 120µSec and thelongest is 270µSec depends on the nibble values from 0→ 15. To find the rangesof all data nibbles values we take the mean of maximum and minimum data valuesthat is

Mean = 12+272 = 19.5

with∓ 20Percent Variation20

100 × 19.5 = 3.9rounding this value give us 4

(4.5)

Now the rang of can be defined by subtracting and adding 4 with each data nibblevalues as illustrated below in table 4.3. All the values are in µSec 12 + 0 = 12using 10 µ Sec unit time will give 120 µ Sec and then adding and subtracting 4respectively produces 124 and 116 the same for all 15 values.

Data Nibble Values Maximum Minimum0 116 1242 126 1343 136 1444 146 1545 156 1646 166 1747 176 1848 186 1949 196 20410 206 21411 216 22412 226 23413 236 24414 246 25415 256 264

Table 4.3: Fixed point algorithm

We use these range to developed the calculation function for the fixed point arith-metic operation instead of using the algorithm that is described in the floatingpoint section. This solution is more efficient and the memory footprint is low


comparing to FP implementation. To measure the time for synchronization pulsethe same approach is used as we described in section 4.4.5 the hardware and IDEssetup is the same for both prototypes. The implemented algorithms are differentin calculating the data nibble values for these prototypes. The algorithm can beimplemented in C-Language using If statement.

IF (Data value ≥ 116 and ≤ 124)

Data value = 0

Else IF (Data value ≥ 126 and ≤ 134)

Data value = 1

.........

.........

.........Else IF (Data value ≥ 256 and ≤ 264)

Data value = 15

The hardware and software configuration for this implementation is the same

as we described in the beginning of section 4.4 for Nios II based implementation.

4.4.7 Software AlgorithmIn previous sections we discuss how we find the calibration pulse using fixed pointand floating point algorithms in this section we will describe the complete softwarealgorithm for capturing the complete frame and decoding the real data for bothdesigned prototypes. The software application is developed in the C-Programminglanguage. The algorithm depicted in the figure 4.16 is used for the implementationdesigns to accomplished the goal of this thesis work.

The process start when a falling edge is detected an IRQ signal is send from PIOto the processor for execution of ISR routine. In ISR current value of the timeris read with an IRQ request after reading the timer value the capture register isreset for the upcoming IRQs if they are on waiting. The value of the timer is storein a variable "T1". When another falling edge is detected a new IRQ request issend to the processor and timer value is read at that particular time, the value oftimer is store in another variable "T2". at the occurrences of each falling edge anIRQ signal is send to the processor. the process is shown in the figure 4.17.

The difference between "T1" and "T2" gave us the pulse time. PulseT ime =T2 − T1 if this time equal to calibration pulse duration 560µsec then "T2" isbecome our "T1" for the measurement of the next pulse time. After getting theright calibration pulse the difference between the next "T2" and "T1" is measured


Figure 4.16: Software Algorithm


Figure 4.17: Pulse time measurement

and this time the pulse time is stored in an array. Every time we get a new fallingedge our previous time become current time T2 −→ T1. The process repeat for allthe nine pulses time measurement. After successfully measuring the time of ninenibble pulses. The process repeat for sixteen frames as we mentioned in section4.3 about the frame structure and serial message. The data values are the samefor all the frames. The difference is just in the serial message data so the datanibbles values is overwrite in the arrays elements every time we measured it for thesixteen frames. The serial message data is measured after successfully capturingsixteen frames. After getting all the 16 frames we check the CRC for the datamessages if it matched then message1 and message2 are calculated by rearrangingand shifting of array elements it is shown in the code section below. This shiftingand rearranging is necessary to get the actual encoded data and serial message.The serial message is calculated by rearranging all the 16 frames for the start bitof serial message. CRC is calculated for the serial message after matching CRCserial message value can be find. The complete step by step process is depicted infigure 4.16.

t [ i ] [ 2 ]= t [ i ] [2 ] < <8;t [ i ] [ 3 ]= t [ i ] [3 ] < <4;Message1=t [ i ] [ 2 ]+ t [ i ] [ 3 ]+ t [ i ] [ 4 ] ;t [ i ] [ 5 ]= t [ i ] [5 ] < <8;t [ i ] [ 6 ]= t [ i ] [6 ] < <4;Message2=t [ i ] [ 5 ]+ t [ i ] [ 6 ]+ t [ i ] [ 7 ] ;

Data messages, CRC, serial message and CRC of the serial message is display inthe Nios II console and also on the character LCD of the altera DE2 board it isdepicted in the figure 4.18.

4.4.8 Code profilingThe performance counter core with Avalon interface provide a very accurate execu-tion time measurement to profiled software program sections. There are multiplecounter that can be used to measure the time of different sections of code simul-

4.5 Prototyping with PIC-Microcontroller 63

Figure 4.18: Data and Serial Message With CRC

taneously.

4.5 Prototyping with PIC-MicrocontrollerAccording to to requirements of the research questions that has been addressed inthe first chapter we used PIC18 for an eight bit platform to prototype the systemfor comparison with an 32-bit platform. In this section we will discussed aboutthe software design,software setup, and hardware setup to achieve our goal.

4.5.1 Hardware setupThe hardware setup consists of SENT-Sensor module, DEV-PIC18 developmentboard as mentioned in section 4.2.3 of this chapter. DEV-PIC18 board is interfacedwith the PC for downloading hex-file from the MP-Lab IDE. The hardware designof the prototype is shown in the figure 4.19.

Sensor module is interface through serial link. Dev-PIC18 board is powered fromthe USB cable that is connected to PC. LCD-Module is used for display the datamessages and serial message. LCD is interfaced with the microcontroller. The datapins of the LCD are connected to board by PORTD of PIC18 microcontroller andthe control pins are connect to to RC2,RC3, and RC4 of PORTC of microcontrollerthe schematics diagram is given in the appendix B. SENT-Sensor are connectedto I/O pin number 48 (RB0) of PIC18F67J50 microcontroller. RB0 is an externalinterrupt 0 input (INTO). To test our developed software for 8-bit platforms wedesign the complete SENT-transmitor (sensor) and SENT-decoder in the ISIS-


Figure 4.19: Prototype Hardware Design

Proteus VSM simulator for testing the functionality of the system before we burnthe program on the real chip.

4.5.2 Software DesignAs we described in section 4.4.6 about the fixed point algorithm implementation forNios II design. We will implement the same algorithm for the data nibbles pulseperiods measurement using PIC18 microcontroller and C18 C-compiler. Timerneed clock tick and the clock tick are generated with an external 12MHz crystaloscillator. The PLL (Phase Lock loop) required 4MHz signal so the PLL pre scalarselection bit is set to divide by 3 mode. To create HEX file which be burn onthe PIC18 microcontroller with programmer we must set configuration registers.These configuration can be done with progama.

#pragma con f i g XINST = OFF // Extended i n s t r u c t i o n s e t#pragma con f i g STVREN = ON // Stack over f l ow r e s e t#pragma con f i g PLLDIV = 3 // 12 MHz c r y s t a l used on

// t h i s board#pragma con f i g WDTEN = OFF // Watch Dog Timer#pragma con f i g CP0 = OFF // Code pro t e c t#pragma con f i g CPUDIV = OSC1 // OSC1 = d iv id e by 1 mode

An interrupt service routine is defined for the detection of the falling edge andread the timer value whenever a falling edge occurred. Three timers are used forperforming different tasks in the program.

Timer0: Timer0 is used in the 16 bit mode for the pulse periods measurement.The T0CON (Timer0 Control register) register controls all aspects of the mod-uleÂs operation, including the prescale selection. Timer0 can be accessed in 8-bitor 16-bit mode. In 16-bit mode it can be accessed as 8-bit TMR0L (lOW byte)register and 8-bit TMR0H (high byte) register due to the fact of 8-bit architectureof PIC18. Timer0 used timer flag for overflow condition.

4.5 Prototyping with PIC-Microcontroller 65

Timer1: Timer1 is used for the measurement of the complete program execu-tion and the time taken by the calculation function to calculate the data value.

Timer3: Timer3 is to create specific delays for the LCD module to functionproperly all the timers setting is done from the PIC18 data sheet [32].

Interrupt Service Routine (ISR): In our ISR the "TMR0L" low byte is readand store it in the variable "time" and the timer0 high byte "TMR0H" is store invarible "timer1" and irq − status is enable. The following initialization are madebefore or main while loop.

TRISB=1; //To make i t input PORTBTRISD=0; //To make i t output PORTDTRISC=0; //To make i t output PORTCINTCONbits . INT0IE=1; // In t e r rup t enableINTCON2bits . INTEDG0=0;// f a l l i n g edge t r i g g e rRCONbits . IPEN = 1 ; // enable p r i o r i t y l e v e l sINTCONbits .GIEH = 1 ; // enable i n t e r r up t sINTCONbits .TMR0IE = 0;// Disab le Timer0 i n t e r r up tINTCONbits .TMR0IF = 0;//T0CONbits .T0CS=0; //Timer ModeT0CONbits . T08BIT=0; //16 b i t Timer0T0CONbits .PSA=1;T1CON = 0x80 ;T3CON = 0x81 ;

Character LCD: L2032 2*20 Character LCD [33] is used to displaying data mes-sages and CRCs. We modify the fixed point implementation program to includeLCD configuration. Timer3 used for creating the required delay for LCD.

SENT Transceiver simulation: After developing the code in the MPLAB IDEwe build the project and create the Hex (executable-file) for the microcontroller.The developed algorithm is working in the same way as we described in section4.4.7 except in this implementation we used the fixed point algorithm on the 8-bitplatform. The simulation of the whole system (SENT-Sensor and SENT-Decoder)has been performed by using the ISIS-Proteus simulator. The purpose was to testthe functionality of our developed prototype before transferring the design to realhardware. The screen shot of the ISIS IDE-simulator is depicted in figure 4.20.


Figure 4.20: SENT Transceiver Simulator

PIC16F677 Microcontroller is used as a SENT-Sensor module, and PIC18F67J50is used as a SENT-Decoder. The sensor module is designed by creating a newproject in the MPLab IDE. The code is written in C-Language. We build theproject, after building the project the hex-file (Executable file) is generated.Theexecutable hex-file is linked to the PIC18 microcotroller.ISIS Proteus support theexecutable hex file which can be used for I/O simulation.

Chapter 5

Signal Integrity Analysis ofSENT and PWM withSimulation

One of the task of the this thesis work is to investigate the SENT signal andPWM signal that how robust is the SENT signal comparing to PWM signal. Themain purpose of this task is to find the highest frequency limit at which PWMtransmit 12-bit data correctly without creating any bit errors. First we will givea short introduction to the importance of this signal analysis and simulation. Atlow frequency data rate there is no need to consider the signal integrity issues, itcomes into action at high data rate or at high resolution data transferred. Whenthe digital high frequency signal passing through a (channel) wire, the wire ex-hibits as a transmission line. Due to the transmission line phenomenon the inputsignal is subjected to ringing, overshoot, cross talk, undershoot, and rise fall timesincrease. These are the majors causes that produces bit errors (ISI-Inter SymbolInterference) in the transmitted data over a communication channel. Our goal is tosee the effects of these factors which cause signal integrity issues on data integrityby simulating both SENT and PWM signals with the same data rates. To achievethis goal we developed a spice model of the whole system for analyzing the signalintegrity issues of both the signals. This chapter described how we modeled thetransmitter, receiver and channel to design the platform for signal analysis.

5.1 Design Overview and IBIS ModelsTo design a SPICE model for simulation we need to consider different parametersthat can affect the data rate such as cross talk, coupling and delays in transmissionline have a great impact on the signal integrity. In order to study these parameterswe need to have a complete transistor level models of the driver and receiver ICs.Due to the proprietary information the vendor’s does not provide the completecircuit description. To solve this problem in 1990 the Intel introduced the concept

67

68 Signal Integrity Analysis of SENT and PWM with Simulation

of IBIS (Input/output Information Specification) Model which is introduced insection2.3 of chapter 2. The IBIS model provides tabular time-voltage pairs ofdata describing the rising and falling waveform at the output when triggered bythe input signal. In Figure 5.1 an IBIS data file of an output buffer is givenwhich consist of pullup and pulldown devices information and power clamp andground clamp diodes and ramp response. Pull-up describes the transistors whenthe output is high. Pulldown describes the transistor when the output is low.

An electrical equivalent model of an output buffer is depicted in figure 5.2, Theupper and lower blocks represent the pullup and pulldown devices also Power-clamp and Groundclamp diodes are shown. To use IBIS model in a simulationenvironment,the tools need to have an equivalent behavioral model and need toextract SPICE equivalent parameters from IBIS data.

Figure 5.1: A typical IBIS file

7

Figure 5.2: An electrical equivalent model of an output buffer

5.2 Simulation Overview 69

To study the signal integrity issues of the system, we need to have a model of thetransmitter (Digital I/O Driver), the model of receiver (Digital Buffer) and channelmodel. To model digital I/O driver we will used the IBIS model of Spartan-3FPGA. The receiver will be model with the IBIS Model of M58BW32F [34] 32-bitflash memory and the channel is model using lumped circuit elements. In figure5.3 a general overview is given how our system will look.

Figure 5.3: Model Description

We have the model of transmitter (Sensor), the model of the receiver and channelmodel. We used ADS (Advanced Design System) tool from Agilent Technologiesfor the simulation of our system, It is a powerful tool for signal integrity analysisand it provides the facility for IBIS models simulation. ADS is described in section2.4 of chapter 2.

5.2 Simulation Overview

Simulation were performed using ADS tool. IBIS models are used for spartan-3FPGA and M58BW32F [34] 32-bit flash memory devices. Simulation frequency isset to 200MHz. The purpose of selecting this frequency because it is high enoughto analyze the step edges of the PWM signal because these edges are really sensi-tive to noise. The main difference between a PWM signal and SENT signal is itsrise and fall times. The SENT pulse have a large rise time (18.5 µ Sec) and falltime is (6 µ Sec) due to this feature it is more robust to high voltage spikes whichis common in automotive system. We will study the effect of rise and fall timeon both signals. The next problem for the signal integrity is the transmission linewhenever a fast edge signal passed through a transmission line the output signalwill have a long rise-time. The rise time increase due to the losses in the transmis-sion line. To study this increase in rise time will will model a transmission line,The ADS components library provides transmission line component for modelingthe transmission line. We use the transient/convolution simulation mode for theanalysis. We use two memory chip as a buffer. The complete simulation setup forthe transmitter (Driver), receiver (Buffer) and channel is given in figure 5.4.


Figure 5.4: The Spartan-3 FPGA-Flash Memory interface and simulation setup

5.3 Signal integrity analysis of SENT and PWM signals 71

As we see from our simulation setup in figure 5.4 there are different modules thatbuild the whole setup which are describe as follows:

Signal generator: The input PWM and SENT signal are generated by using the”V tBitSeq” (Voltage Source, Pseudo Random Pulse Train Defined at ContinuousTime by Bit Sequence) which is available in ADS. VtBitSeq is used for transientsimulations. BitSeq allows you to vary the waveform of a pulse. The frequency isset to 200MHz and the rise and fall time can be change according to the require-ment for PWM and SENT signal in the VtBitSeq edit menu.

Spart-3 IBIS-Model: PIN 126 of spartan-3 FPGA is used for modeling thedriver. It is called SSTL18 − I (Stub series terminated logic 1.8V) single endedstandard I/O. The pullup powerclamp network is connected to 1.8V VDD and thepulldown and groundclamp network is connected to 0V Vdc. The input signal isapplied at terminal T of the IBIS-Model.

Termination Network: When the round-trip delay of an output signal exceedsrise and fall times, then we need to use the termination resistor to the line carryingthe signal. To solve this problem we use 50Ω impedance together with a 1000Ωseries resistor which is depicted in the termination network.

Channel Model: To model the transmission line we use lumped circuit elements.The total length of the transmission line is set to approximately 5 inches from thedriver to the memory chip. Which is model with the Transmission line librarycomponents in ADS

Buffer Model: To model the receiver we use the IBIS Model of M58BW32F32-bit flash memory.

We run a number of simulation to see the affect of transmission line losses on therise and fall times, and how it can effect the signal waveform all these outcome ofthe simulation will be presented in the next chapter.Wire Model: The transmission line has been model using the lumped circuitelements network. The value of the capacitance and inductance is set according tothe Twisted wire data sheet [35]. We used two branch of lumped network whichrepresents 2 meters long twisted pair cable.

5.3 Signal integrity analysis of SENT and PWMsignals

To study the robustness of the SENT and PWM signals against the transmissionline losses, high voltage spikes due to the switching of high current loads and highvoltage pulses due to the electromagnetic injection. But we are mainly concernedwith the transmission line effects such as overshoot, undershoot, ringing, and rise-fall time increased. Transmission line behave as lumped circuit elements at a high


frequency. Our goal is find the maximum data rate of the PWM signal, and tocheck the maximum PWM data rate at which it performance is assured and thereis no ISI occurred. To performed this analysis we need to consider the effect ofwires which mainly contribute in the data lost if it is not terminated properly. Acomplete SPICE-Model is design in the ADS as mentioned in section 5.2 of thischapter for analyzing the effects of these parameters on the signal integrity. Toachieve our goal we made the complete transceiver SPICE-Model that is describedin section 5.2 of this chapter. As we described earlier that the transmission lineeffects occurred at high frequency there fore we select different data rates to findthe critcal data rate at which PWM faced ISI problem which intern creates biterrors. The choices that we made for selecting the simulation setup and the de-tails explanation about how we got the results are presented in section 5.2. Tomake our design simple three data nibbles of the SENT signal are considered fordata encoding which represents 12-bit data. The same 12-bit data will be usedfor both signals. A number of simulations were performed to see the effects ofdifferent parameters of the design system on both signals PWM and SENT. Firstwe will present the obtained simulation results for both SENT and PWM signalsand after presenting the results we will describe the conclusions from these results:

Figure 5.5: Representation of 12-bits data in the form of SENT-Encoding

Figure 5.5 show the simulation result of SENT signal. The red graph with themarkers position represents the input SENT-signal which is a complete three datanibbles message. In which the first data-nibble start time is 9.426nsec and the lastdata-nibble stop time (marker 2) is 319.5nsec. While the output SENT signal isshown in the blue graph which is slightly delayed the start time is 14.03nsec andstop time is 325.0nsec. These values are also given in the table 5.1. Equations 5.1and 5.2 is used for calculation in the table 5.1.

Pulse period = Stop time of the pulse - Start time of the pulse (5.1)

5.3 Signal integrity analysis of SENT and PWM signals 73

Error in pulse period = Pulse period of output pulse - Pulse period of input pulse(5.2)

SENT Signal PSPT PST Pulse period ErrorINPUT 9.42 nsec 319.5 nsec 310.08 nsec 0.89 nsecOUTPUT 14.03 nsec 325.0 nsec 310.97 nsec

Table 5.1: SENT data-signal start and stop timing

Figure 5.6: Transmission line effects on rise-fall times of the SENT-Signal

The rise-fall times increase occurred in the output signal due to the transmissionline losses which is shown in figure 5.6.

Figure 5.7: Representation of 12-bits data in the form of PWM-Encoding


When rise-time is equal to the bit-period then the Inter Symbol Interfere (ISI)occur which destroy the integrity of the data. ISI occurred in a long bits of streamas (11111110111111) where after many 1s one 0 occurred and the actual voltage-level of this 0− bit depends on the previous bits voltage-levels, due to the rise-falltimes increase all bits voltage-levels overlapped which create bit-errors.

The complete representation of the 12-bit data in form of PWM-Encoding is givenin figure 5.7. The the blue graph represent PWM input signal and the red graphrepresent the PWM output signal. The start and stop times of the signal arerepresented by the markers position is shown as (m1,m2,m3 and m4). We can seefrom the figure that due to the ISI the second bit as shown in red in figure 5.7become an error bit, because at the input signal as shown in blue in figure 5.7this bit should be low but it is high, similarly the remaining bits also overlappedin the neighbor bits slot times. Our goal was to investigate that how the ringing,overshoot, undershoot and rise-fall time effect the signal integrity it is seen in theresults that upto 50KHz the PWM data rate is reliable and does not create anybit error. While at 1MHZ ringing and overshoot occurred but by using some lowpass filtering this problem can be solved. But at 20MHz ISI occurred and the bitsgoes to their neighbor bits slots and due to this bit error occurred. While on theother hand even at 200MHz the SENT protocol does not produced any bit error.In conclusion if PWM is used for high data rate we need high resolution whilehaving high resolution with the fast clock cycles create ISI problem. To use PWMfor high data rate either we need a long period pulse or we need a high resolutionand they both are possible upto some extent that we have shown in the simulationresults. On the other hand SENT protocol maintain high data rate even at veryhigh frequency that can be seen in the results. The complete simulation results ofPWM and SENT signals are presented in the next section.

Figure 5.8: Transmission line effect on Rise-Time of PWM pulse

The effect of transmission line on rise time of the PWM pulse are depicted in figure

5.4 SENT and PWM signal simulations at frequency range ( 1KHz-250MHz) with different data rate (10-Bits-100-Bits) 75

5.8.

Figure 5.9: Transmission line effect on Fall-Time of PWM pulse

The effect on fall-time of the PWM is given in figure 5.9.

5.4 SENT and PWM signal simulations at fre-quency range ( 1KHz-250MHz) with differentdata rate (10-Bits-100-Bits)

The complete simulation results at different frequencies range are given in thefollowing section. The representation of PWM signal at frequency 1KHz and thedata rate is 10 bits is depicted in figure 5.10.

Figure 5.10: Frequency is 1KHz and data bits are 10 bits

The representation of PWM signal at frequency 1KHz and the data rate is 100bits is depicted in figure 5.11. The output signal is the same as input with no bit


error.


The representation of PWM signal at frequency 10KHz and the data rate is 100bits is depicted in figure 5.12. The output signal is still the same and there is nobit error occurred yet.


The representation of PWM signal at frequency 50KHz and the data rate is 10bits is depicted in figure 5.13. There is slightly ringing effect occurred at 50KHzbut the signal can be decode correctly with the right information.



The representation of PWM signal at frequency 1MHz and the data rate is 10 bitsis depicted in figure 5.14. The effect of ringing start at 1MHz frequency. Whichcreates overshoot and undershoot at the edge of the pulse transition as depictedin figure 5.14.

Figure 5.14: Frequency is 1MHz and data bits are 10 bits

The representation of PWM signal at frequency 10MHz and the data rate is 10 bitsis depicted in figure 5.15. At 10MHz the ringing is high also the ISI occurred whichcreates bits errors and there is some information lost occurred at this frequency.The input signal is not matching with the output signal due to the change in thepulse period time.



The representation of PWM signal at frequency 50MHz and the data rate is 20bits is depicted in figure 5.16. At 50MHz the output signal is changed due to theringing and ISI effects, the original data which is encoded in the input signal iscompletely lost now since the periods of the pulse changed.


The representation of PWM signal at frequency 100MHz and the data rate is 20bits is depicted in figure 5.17. At 100MHz the output signal completely changeddue to the ringing and ISI effects, the original data which is encoded in the inputsignal is completely lost now since the periods of the pulse changed.



The representation of PWM signal at frequency 150MHz and the data rate is 50bits is depicted in figure 5.18. At 150MHz the signal is distorted due to ringingand transmission line effects. Also the shape of the signal is changed.


The representation of PWM signal at frequency 200MHz and the data rate is 50bits is depicted in figure 5.19. At 200MHz the signal is completely distorted dueto ringing, ISI and transmission line effects.



The representation of PWM signal at frequency 250MHz and the data rate is10 bits is depicted in figure 5.20. At 200MHz the signal is completely distorteddue to ringing, ISI and transmission line effects. The markers position is used tomeasured the period of the input and output signal. It is clear from the followingfigure that PWM is not suitable for high data rates.


The representation of SENT signal at frequency 1KHz and the data rate is 100bits is depicted in figure 5.21.


The representation of SENT signal at frequency 100KHz and the data rate is 100bits is depicted in figure 5.22.



The representation of SENT signal at frequency 50MHz and the data rate is 100bits is depicted in figure 5.23.


The representation of SENT signal at frequency 150MHz and the data rate is 100bits is depicted in figure 5.24.


The representation of SENT signal at frequency 250MHz and the data rate is100 bits is depicted in figure 5.25. According to SENT protocol data encodingscheme even at such a high frequency the data are still secured, since we are only


interested in measuring the data nibble period between the two consecutive fallingedges of the SENT signal. It does not matter if the signal is distorted due ringingor transmission line effects as long as the period between the two falling edges isthe same.


5.5 Conclusion of the simulations

The following table described the outcome of simulation for both PWM and SENTsignals:

SENT PWMWhen the data are decoded in the SENTapproach then the existing noise voltagepulses do not have any effect on the sig-nal integrity since it is time critical sys-tem. Also SENT protocol has ∓20 percenttransmitter clock compensation.

PWM is a three wires digital system, wherethe spark type noises are inductively cou-pled to the data line and produces edges atthe wrong places which produces ISI prob-lem and destroy the signal integrity.

The rise-fall times has been increasedas mentioned before. This rise-fall timedegradation is due to the losses in thetransmission line. Which produces inter-symbol interference (ISI) which cause sig-nal integrity issues.

The main cause of this degradation in rise-fall times is the high frequencies compo-nents (step-edges of PWM) of the signal,which is more attenuated more then thelower frequency components

5.5 Conclusion of the simulations 83

While in case of SENT the integrity of datais dependent on time not on the voltagelevels. Also the availability of transmit-ter clock variation compensation which en-sured the integrity of data.

In a typical 10-bit system one bit is a singlebit is represented by 4mV, which in 12-bitsystem a single bit is represented by 1mV,due to the noise voltage pulses in auto-motive system the 4mV presents a severeproblem. So to use PWM for 12-bit datatransmission 1 bit is equal 1mV which caneasily be corrupted due to the noise volt-ages.

According to the difference in time dueto the rise-fall time increase which cause1.2nsec difference in the pulse width it doesnot affect the SENT data because of thecompensation feature of the SENT signal.

While this 1.2 nsec delay can cause thePWM data pulse edges at the wrongplaced which intern produce bit error.

While SENT provides a high resolutioncomparing to PWM. According to thespecification of the SENT 24-bits data canbe transmitted by data nibbles while 8 bitcan be transmitted in each serial messageof the SENT frame. So a total of 32-bitscan be transmit in less than 1 msec.

The resolution of the PWM depends onthe Fclock and Fpwm Resolution =Log2(Tpwm/Tclock. The PWM works fineupto 10-bit resolution but for the datarates higher then 10-bit its resolution de-grades.

Higher resolution more then 16-bits can betransmitted with TLE4998 which is a linearhall sensor described in the first chapter.

If 32-bits are transmit with PWM a eithera very long pulse period will be need ora very high resolution which is impracticalwith today high speed MCU.

From the depicted figures we saw that therise-fall times (at high frequencies com-ponents) ringing occurred. It effects thePWM signal due to the encoding mecha-nism of the PWM where each bit is rep-resented by some voltage level as 4mV incase of 10-bit system and 1mV in case of12-bit system. The signal become stableafter some time whenever the signal levelchanged which may cause bit error

Every transmitter has a source impedanceZs also an inductance Lthat could lead toringing and intersymbol interference ISIas we saw in the figure at the high frequen-cies components of both signals. Ring-ing can be reduced by the rise-time of theinput signal wave-form. By reducing thehigh frequency components of the inputless energy is coupled into the tank circuitto cause the ringing. Which is problem inPWM case

SENT used two wires one is common GNDand other wire is use for data as well aspower.

In case of PWM we use three wires power,GND and data in case of three wires systemwe need an extra power supply. So thepower consumption is more and also thewiring cost.

In digital system jitter are produce whenrising and falling edges are occur at timethat is different than ideal time . Or jitterproduced due to the misalignment of risingand falling edges. Due to jitter the problemthe signal integrity are effected. But incase of SENT protocols we measured databetween the two falling edges which solvedthis problem

The deviation in the clock frequency due tothe bad crystal oscillator cause these prob-lem (jitter and rise-fall time increase) fre-quently so we need a more precise crystaland it is also expensive but SENT can have∓20 percent tolerance rate that can solvedthis problem.


Cross talk also occurs in the lossy transmis-sion line.Cross talk happens between thesignal and return paths of one wire andthe signal and return paths of another wire.Cross talk produces due to the capacitiveor inductive coupling.

In the case of the capacitive coupling ef-fect, the moving edge on the aggressornet induces positive-going current pulseson the victim net in both the forward andreverse directions. while inductive couplingis opposite to capacitive coupling.

Inductive coupling produces switchingnoise and ground bounce, Inductive cou-pling is more dominated then the capaci-tive coupling.

As we designed the transmission line withthe lumped elements all these elementsmake some contribution in the SI problemswhich are more effective at high frequency.

In SENT case two signals share the samewire. Low susceptibilty is required forSENT protocol against EMI so we do notneed shield or twisted pair cable reducecost for wiring.

To ensured a secure high data rate withPWM we need to have more then onechannel (parallel-wires) should be usedwhich increase the cost as well as moreEMI problems.

From this discussion and simulation results we conclude that SENT provide a bestsolution in either case comparing to the conventional PWM. The goal is achievedin this task by simulation and analyzing the physical layer comparison of bothPWM and SENT signals.

Chapter 6

Results and Discussion

This chapter will describe all the experiences and performance analysis that hasbeen made during the implementation and simulation as we mentioned in the pre-vious chapters. The aim of this thesis work was to compare SENT-Protocol withother serial communication protocols for an alternative best solution in terms ofcost, performance, execution power and robustness for an automotive high data-rate communication. We will describe the comparison among all the implemen-tation designs and simulations; also we will perform the functional testing of ourdesign prototypes. We divide our thesis work into tasks as describe in chapter 1section 1.3. We will discuss the experience gained during completion of these tasksfor achieving our thesis goals.

6.1 Study of SENT-ProtocolThe purpose of this task is to familiarize with the SENT Protocol. A detail studyof the SENT protocol is performed in regard to understand the data encodingscheme of the SENT data frame which can be then implemented on the describedplatforms. We explore the best features of the SENT protocol signal, like toler-ance for clock frequency deviation which was deeply investigated to find the rightsoftware-algorithm for tolerance ability to be implemented and make the movetowards the best decoder implementation for the SENT data-transmission. SENTusing the time trigger architecture in which the data are transmitted in the form ofseries pulses each 4-bit long (Nibble) where the data are measured from falling tofalling edges time by the receiver device. The integrity of data is time dependentso the existing noise voltages pulses do not affect it, in addition to this there is acyclical redundancy check (CRC) nibble by the end of data nibbles. But in caseof other three-wire system like PWM these spark type noise can be inductivelycoupled with the transmitted data signal which can produce edges in the wrongplace and can destroy the integrity of data.

Another feature of SENT is studied which is its ability for high resolution datatransmission which can replace the lower-resolution methods using 10-bit ADC

85

86 Results and Discussion

and PWM techniques and can provides a low cost alternatives to CAN and LINprotocols in some specific applications of the automotive system. It is seen that ifwe use PWM or ADC for high resolution data transmission, how the data integritycan be affected this topic will be describe in detail in section 6.5 of this chapter.By using SENT we can also reduce the wiring cost because SENT interface usestwo wires one is common GND and another wire is used for Power as well as datatransmission.

6.2 Comparison of automotive communication pro-tocols

The aim of this task was do a comparative study of the communication protocolsthat are used in the automotive industry nowadays. We explore the challenges thatdemands for new communications protocols and their features comparison thatmakes them feasible for certain applications. The embedded systems in vehiclesare divided into different domains: according to their functionality, architectureand the constraints: powertrain domain, chassis domain, body domain, telematicsdomain and safety domain which are described in section 3.1 of chapter 3. Thecommunication among the ECUs of these domains interconnect with different sen-sor modules require a robust and highly efficient communication interfaces withthe ability to satisfy the strict timing constrains from the different subsystems,also having the mechanism for data integrity. To fulfill these requirements a num-ber of communication protocols were developed by different vendors according totheir needs for specific task, these standards are divided into two main categoriesnamely point-to-point and network protocols.

Networks protocols are further subdivided into classes described by SAE (Soci-ety of automotive engineer) according to their data rates versus cost which aredepicted in figure 3.2 as mentioned earlier in detail in section 3.2 of chapter 3.Why different types protocols exist? To answer this question we made a completefeatures comparison and the feasibility for specific applications of networks andpoint-to-point protocols which is described in table 3.1 section 3.3 of chapter 3.Networks protocols effectively reduce the amount of cabling which reduce cost andeasy to do the maintenance of the system. But for a standalone system or whenone sided data traffic is require the use of network protocols is waste of band-width and resources so point-to-point protocol is the best solution for this kind ofscenarios. Due to these different requirements and the aim for reducing cost themanufactures of automotive industry are keep looking for new protocols they arebase on network and point-to-point protocols.

6.3 Design prototypes comparison implemented with fixed-point andfloating-point 87

6.3 Design prototypes comparison implementedwith fixed-point and floating-point

Two prototypes of SENT-Decoder have been implemented and tested using fixedpoint and floating point data type specification to achieve the goal of this task.To obtain an approximate floating point 32-bit number to be stored in memoryrounding has been performed in the calculation of data nibble value. The floatingpoint arithmetic provides high accuracy but with a significant processor overhead.While fixed point algorithm are not so easy to implement because the program-mers should utilize all the performance of processor by utilizing the idle time ofthe processor when it is not doing any task. But to do so more efficient algorithmneed to be design. To design efficient algorithm repeated division and multipli-cation instruction should be avoided to save the processor execution time. Bykeeping all these considerations we implemented the fixed point design with scalarmultiplication factor as described in section 4.4.6 of chapter 4. It is seen thatdesign with floating point arithmetic was taking more time for calculating thedata nibble value due to its internal algorithm complexity but it gives accurateresults. To avoid the accumulator overflow in the fixed-point design we used thetechnique of scalar multiplication factor with an updated algorithm as describedin Section 4.4.6 of Chapter 4. Timer-3 has been used to measure time taking bydifferent functions such as calculation() and printf() function also the code profil-ing is done with performance counter core. The results are depicted in figure 6.1also described in table 6.1.

ImplementationDesign

CompleteProgram

Execution

Printf()

M1

Printf()

M2

Printf()

M3Delta Calculation()

Function

Fixed Point 84 msec 476 usec 898 usec 877 usec 39 usec 89 usecFloating Point 250 msec 507 usec 729 usec 667 usec 934 usec 1348 usec

Table 6.1: Execution Power Comparison of Floating Fixed Point Implementation

To get more accurate results a performance counter core has been added to designin the SOPC builder. Performance counter core is a set of counters which keeptrack of the clock cycles timing different section of the code.There are three defaultcounters unit in the performance counter core for profiling purpose and can be canbe increase according to the requirements if more sections of the code need to beexamined for optimization purposes. The details explanation about code profilingand performance counter is given in section 4.4.6 of chapter 4. The performancecounter measured the number clock cycles each section of the code takes. Tomeasured the time in seconds we used the formula T = n 1

F which give us the timein seconds ”n” represents the number of clock cycles each code section takes toexecute.

To measured the CPU utilization in percentage we need to find the CPU idle


time when it is waiting for the interrupt and doing no operation. To do so oursoftware design algorithm consists two idle loops in both fixed and floating pointimplementation designs one for synchronization pulse capturing and another tocaptured all the nine nibbles of the SENT frame. it is explain in detailed insection 4.4.6 of chapter 4. The formula used for finding CPU utilization is givenas:

Percentage Idle Time = Idle TimeTotal Program Execution Time × 100(6.2)

Percentage CPU Utilization = 100% −Percentage Idle Time(6.4)


Idle Time

1st

Idle Time2nd

Total Idle

Time

% CPU

UtilizationFixed-Point 0.58msec 1.56msec 2.14msec 97.45%

Floating-Point 0.64msec 1.48msec 2.12msec 99.15%

Table 6.2: CPU Utilization of Fixed-Point and Floating-Point Designs

By using values from table 6.2 and table 6.1 into these equation we measured theCPU utilization in percentage of both designs which is given in table 6.2. It is clearthat the floating point design utilize more CPU then the fixed point design due tothe fact that floating point arithmetic need more processor overhead because of itsinternal complex algorithms. Most of the modern processor consist of a separateunit called co-processor for floating point operation. So designing with floatingarithmetic processor overhead significantly increased.

The resource usage of both designs is depicted in figure 6.2 and the description isalso given in table 6.3. It is the program linking memory footprint with reducedevice driver option and without reduce device option that can be selected in theproject properties of Nios II IDE for optimized C-code generation. The memoryfoot print play an important role in the system design. The designers shouldalways focus to make sure that the design is optimized for less memory usagebecause high memory foot print increase the system cost, While fabricating thesystem will need more CMOS logic gates which means more silicon and it cansignificantly increase the cost of the system due to the price of the silicon. It isobvious from the results that the fixed-point design is more efficient in executionpower with less memory footprint comparing to floating point implementation

6.4 Design prototypes comparison implemented on an 8-bit and a 32-bitplatforms 89

design. The goal of implementing with the fixed point arithmetic is to make thedesign prototype more efficient and reduce the resource utilization which was ourgoal that is achieve in this task.

Figure 6.1: Execution power comparison of fixed-point and floating-point designs


Memory footprint(Without reduce

device driver)

Percentageusage of total

Memory

Memory footprint(With reducedevice driver)

Percentageusage of total

MemoryFixed Point 13KB 2.53% 57KB 11.13%Floating Point 17KB 3.32% 59KB 11.52%

Table 6.3: Resource utilization of Fixed-point and Floating-point Designs

6.4 Design prototypes comparison implementedon an 8-bit and a 32-bit platforms

The purpose of the task was to design a low cost and low power prototype with an8-bit platform. To achieve our goal we made the selection of a small development(DEV-PIC18F67J50 [1]) board as mention in section 4.2.3 of chapter 4 whichis based on PIC18 microcontroller and can be powered from the USB port aswell as from an external source (4.5V - 9V). There is no support available forfloating point arithmetic in the available platform. The software algorithm hasbeen developed using the fixed point arithmetic technique Which is described in


Figure 6.2: Resource utilization of Fixed-point and Floating-point Designs

detailed in section 4.5.2 of chapter 4. The implementation is performed withthe interrupt service routine (ISR) for the edge detection. Which make a greatcontribution for reducing the power consumption, due to the fact that the systemdo not poll for the detection of falling-edge all the times. The system is in the idlestate and do no operation until a falling edge occurred at the I/O pin.


Idle Time

1st

Idle Time2nd

Total Idle

Time

Complete

ProgramExecution

Calculation

FunctionTime

% CPUUtilization

PIC18 withFixed Point 0.68msec 1.7msec 2.38msec 64msec 80usec 96.28%

Table 6.4: CPU Utilization of an 8-Bit Platform

The source code is compiled in MPLAB IDE and executable Hex-file is generatedby building the project,to be burned on the targeted board. The size of theHex-file is the actual memory footprint of the source code. PIC18F67J50 provide128KBytes of flash program memory that can be reprogrammed. The executiontime taken by the complete program and calculation function are measured thehelp of time1. It is obvious from the results that the best solution for the designof SENT-decoder is Fixed-Point implementation design on the 32-bit platformamong all the designs prototypes. But if we consider interms of cost then the

6.4 Design prototypes comparison implemented on an 8-bit and a 32-bitplatforms 91

8-bit platform provide a convenient and efficient design. Table 6.4 only describesthe execution power of the 8-bit platform based design, the other two designs weredescribed in table 6.3. The comparison resource utilization of the design prototypesare depicted in figure 6.3. Also table 6.5 describe the resource utilization for PIC-Based design.

Figure 6.3: Memory Footprint Comparison of all the Design Prototypes

Implementation Design MemoryFootprint

Percentage usageof total memory

PIC18 with Fixed-Point 21.5KB 16.79%

Table 6.5: Resource utilization of 8-bit Platform Prototype

The aim of our compassion among these three different implementation designswas to find an optimal solution for designing SENT-decoder prototype. As wesee the FPGA base design will be more effective because of the 32-bit NiosIIarchitecture but the cost is high comparing to the PIC prototype. One of themost important aim was also to reduced the memory footprint and we try tooptimize the code using the fixed point algorithm technique. It was due the factthat memory footprint represents the actual physical IC chip size it means highfootprint will required more logic elements (LEs) or memory elements which willrequired more silicon and it will significantly increase the cost. By comparingthe design prototypes of an 8-bit platform and a 32-bit platform interms of cost,resource utilization, execution power and power consumption we reached to the


conclusion that the 8-bit platform provide a more convenient and best solution forthe design of SENT-Decoder. The aim was to compare an 8-bit platform prototypewith a 32-bit platform as described earlier which was our goal that is achieved inthis task.

6.5 Functional testing of the Nios Based designprototype

The design prototype testing has been performed to check correct functionalityof the system. The system testing is performed at the component level. Eachcomponent is individually tested during the development process of the prototype.The experimental setup for the nios based prototype is given in figure 6.4. Thefunctionality of the system is tested for ∓20 percent clock variation. The sensordata are being displayed in the nois console as we as in the the DE2 board charterLCD. Two tests have been performed one for the fixed values of sync pulse whichis equal to 560 usec and one for the variable sync pulse its range 448 usec to 672usec.

Figure 6.4: Experimental Setup Nios based design

6.6 Functional testing of the PIC Based design prototype 93

6.6 Functional testing of the PIC Based designprototype

The prototype testing has been performed to ensured the correct functionality ofthe system. After developing the software in the MPLab environment a simulationsetup has been created in the hardware I/O simulator Proteus 7.10V to check thefunctionality of the system before burning on the real PIC microcontroller chip.The Proteus simulation setup consist of SENT transmitter which is designed tosend a series SENT pulses according to the SENT specification. Also we SENTdecoder microcontroller and the LCD for displaying the data and serial messages.The setup is given in the Appendex B. After successfully running the simulationthe hex file is downloaded to the target board as shown in the figure 6.5 whichread the SENT sensors messages and display it on the character LCD which isinterfaced with the PIC microcontroller.

Figure 6.5: Experimental Setup PIC based design

Chapter 7

Conclusions and FutureWork

In modern automotive system a number of communication interfaces are usedfor the exchange of information between the ECU and sensors modules. Thesecommunication standards have many advantages and disadvantages due to theirperformance and signal integrity. The aim of automotive engineering industry isto always have high performance with low cost. This thesis focuses on the de-velopment of SENT-Decoder prototype in order to provide a low cost and higherperformance prototype. Secondly it focus on the SENT and PWM signal band-width analysis through simulations also with a theoretical comparison of bothsignals.

7.1 Summary of ContributionIn order to achieve the goals of our thesis work, two prototypes of SENT protocoldecoder have been developed. The development is performed by using two differentimplementation design techniques. Two prototypes are developed one on an 8-bitand another on 32-bits platform for processor utilization and cost comparison, Thesignal robustness and bandwidth analysis are performed with a SPICE simulationsystem model which is developed in ADS (Advanced Design System).

7.1.1 Design with fixed-point and floating-point arithmeticOne of the key challenge in auto system is to reduce the system cost withouteffecting the performance of the system. In this thesis we developed two proto-types of the SENT-Decoder with two implementation designs by using fixed-pointarithmetic and floating-point arithmetic on the 32-bit platform. Our developedprototype with fixed-point provide high performance with less resource usage byreducing the cost with slightly less accuracy as provide by the prototype developedwith floating point.

95

96 Conclusions and Future Work

7.1.2 Prototype design on 8-bit and 32-bit platformsAnother prototype of the SENT decoder is developed on the 8-bit platform withthe fixed-point arithmetic which reduced the system cost by the platform cost,because 8-bit microcontroller are cheaper. The performance of this prototype isnot as compare to 32-bit fixed-point design performance, But by looking to theoverall system cost and also performance this prototype is better option for simpleapplications.

7.1.3 SPICE-Simulation ModelA spice simulation model are developed for the bandwidth and signal robustnessanalysis of SENT and PWM signals. It is seen that PWM techniques is notsatisfactory for the high data rates, due to its steep edges which is sensitive totransmission line losses and noise voltages in automotive system. The change inresolution of the PWM signal changed with noise voltage pulses in the automotivesystem. The degradation in rise-fall times occurred due to the transmission linelosses. There are so many other factors that cause the signal integrity (SI) issuesare described in the this thesis work.

7.2 Limitation and Future WorkThere are some limitations of this thesis work, we provide some suggestions forthe future work:

7.2.1 SENT-signal EMC emissions analysisOur current work is only focus on the transmission lines losses and rise-fall timeseffects on the signal integrity. We did not consider the EMC emissions and theirminimization for SENT signal pulse. It will be nice to developed a prototype ofSENT-Decoder for EMC emissions analysis.

7.2.2 Performance comparison of software-design with theIP-core

We developed the prototype using software design. The SENT-decoder prototypecan be developed in hardware using VHDL for the future SENT-sensor fabricationon real CMOS level. Also its performance can be compared with the softwaredesign prototype. The performance of software design is not good then IP-corebut the software design provides more flexibility which can be used to improvingthe performance of the IP-core.

7.2.3 Sensor fusion prototype with SENT-InterfaceDue to the sensitivity of the analog sensors to noises digital senors are emergingwith high speed in the automotive industry. Comparing to the analog links digital

7.2 Limitation and Future Work 97

links are more immune to noise. There fore more and more sensors are going toconvert to digital interfaces. Many sensors can be pack together in a single modulewhich communicate with the ECU through digital channel this sensor fusion canreduced the wiring cost and improve the data integrity. SENT is digital interfacesand having the capability of high resolution so a sensor fusion prototype can bedesigned using two or three sensor to share the same signal wire. SENT two signalsshare the same wire this can help for future sensor fusion.

7.2.4 ON-Chip Interconnect CommunicationSENT is designed for off-chip sensors and ECUs intercommunication. Due toits data encoding technique and slow rise and fall times of its pulse, it is morerobust to noise and can be try to use it for on-chip communication. Huge numberof transistor are fabricated on single chip so large number of metal interconnectwhich produces high capacitance. The performance of SENT protocol can betested for on-chip communication to reduce the effects of high capacitance andswitching activities [44].

Bibliography

[1] URL:http://www.robot-electronics.co.uk/acatalog/Processor_Modules.html.

[2] URL:ftp://http://ww1.microchip.com/downloads/en/DeviceDoc/39775b.pdf.

[3] URL:http://www.seekdl.org/nm.php?id=223.

[4] URL:http://www.circuitstoday.com/wp-content/uploads/2012/06/Data-Types.jpeg.

[5] URL:http://www.digikey.com/us/en/techzone/sensors/resources/articles/digital-communication-for-smart-modern-sensors.html.

[6] URL:http://www.digikey.com/us/en/techzone/sensors/resources/articles/digital-communication-for-smart-modern-sensors.html.

[7] URL:http://www.startekinfo.com/manual/volumes/cd1/3_4/content.pdf.

[8] URL:http://www.onsemi.com/pub_link/Collateral/TND6015-D.PDF.

[9] URL:http://www.atmel.com/images/doc7548.pdf.

[10] URL:http://www.freescale.com/webapp/sps/site/overview.jsp?code=APLBDYELCTR.

[11] URL:http://www.omega.com/techref/pdf/rs-232.pdf.

[12] URL: http://http://www.infineon.com.

[13] URL:http://www.design-reuse.com/sip/23668/sae-j2716-sent-transmitter-ip-single-edge-nibble-transmission-silicon-ip/.

[14] URL:http://www.intrinsix.com/pdf/Intrinsix_SENT_Transmitter_IP.pdf.

[15] URL:http://www.melexis.com/Hall-Effect-Sensor-ICs/Triaxis%C2%AE-Hall-ICs/MLX90324-707.aspx.

99

http://www.robot-electronics.co.uk/acatalog/Processor_Modules.html

http://www.robot-electronics.co.uk/acatalog/Processor_Modules.html

ftp://http://ww1.microchip.com/downloads/en/DeviceDoc/39775b.pdf

ftp://http://ww1.microchip.com/downloads/en/DeviceDoc/39775b.pdf

http://www.seekdl.org/nm.php?id=223

http://www.circuitstoday.com/wp-content/uploads/2012/06/Data-Types.jpeg

http://www.circuitstoday.com/wp-content/uploads/2012/06/Data-Types.jpeg

http://www.digikey.com/us/en/techzone/sensors/resources/articles/digital-communication-for-smart-modern-sensors.html




http://www.startekinfo.com/manual/volumes/cd1/3_4/content.pdf

http://www.startekinfo.com/manual/volumes/cd1/3_4/content.pdf

http://www.onsemi.com/pub_link/Collateral/TND6015-D.PDF

http://www.atmel.com/images/doc7548.pdf

http://www.freescale.com/webapp/sps/site/overview.jsp?code=APLBDYELCTR

http://www.freescale.com/webapp/sps/site/overview.jsp?code=APLBDYELCTR

http://www.omega.com/techref/pdf/rs-232.pdf

http://http://www.infineon.com

http://www.design-reuse.com/sip/23668/sae-j2716-sent-transmitter-ip-single-edge-nibble-transmission-silicon-ip/

http://www.design-reuse.com/sip/23668/sae-j2716-sent-transmitter-ip-single-edge-nibble-transmission-silicon-ip/

http://www.intrinsix.com/pdf/Intrinsix_SENT_Transmitter_IP.pdf

http://www.intrinsix.com/pdf/Intrinsix_SENT_Transmitter_IP.pdf

http://www.melexis.com/Hall-Effect-Sensor-ICs/Triaxis%C2%AE-Hall-ICs/MLX90324-707.aspx

http://www.melexis.com/Hall-Effect-Sensor-ICs/Triaxis%C2%AE-Hall-ICs/MLX90324-707.aspx

100 Bibliography

[16] URL:ftp://ftp.altera.com/up/pub/Altera_Material/12.1/Boards/DE2/DE2_User_Manual.pdf.

[17] URL:http://www.keysight.com/en/pc-1475688/keysight-eesof-electronic-design-automation-EDA-software?cc=SE&lc=eng&cmpid=zzfindeesof.

[18] URL:http://www.uio.no/studier/emner/matnat/ifi/INF5481/h11/undervisningsmateriale/ADS.pdf.

[19] URL:ftp://http://www.infineon.com/.

[20] URL:http://www.infineon.com/dgdl/Infineon-TLE4998C4-DS-v01_00-en.pdf?fileId=db3a304325afd6e00126328423dc648f.

[21] URL:http://www.chipsoft.ru/index.php/download/category/6-protokols.

[22] URL:http://www.mostcooperation.com.

[23] URL:http://standards.ieee.org/findstds/standard/1394-1995.html.

[24] URL:http://www.kvaser.com/software/7330130980914/V1/can2spec.pdf.

[25] URL:http://vector.com/portal/medien/cmc/application_notes/AN-ION-1-3100_Introduction_to_J1939.pdf.

[26] URL:http://standards.sae.org/j2284/3_201003/.

[27] URL:http://www.cs-group.de/fileadmin/media/Documents/LIN_Specification_Package_2.2A.pdf.

[28] URL:http://www.mostcooperation.com/publications/specifications-organizational-procedures/.

[29] URL:http://psi5.org/fileadmin/user_upload/01_psi5.org/04_Specification/Specifications_PDFs/psi5_specification_v13_080729.pdf.

[30] URL:http://www.embedded.com/electronics-blogs/beginner-s-corner/4023833/Introduction-to-Pulse-Width-Modulation.

[31] URL:http://mobile.aau.at/~welmenre/ttpa/download/ttpaspec_v200.pdf.

[32] URL:http://ww1.microchip.com/downloads/en/devicedoc/39775b.pdf.

[33] URL:ftp://ftp.ehu.es/cidira/dptos/depjt/DataBook/Optoelectronica/Lcd.pdf.

[34] URL:https://www.micron.com/resource-details/9ead67ed-2d88-48dd-ba31-fb4cc6ebaf69.

ftp://ftp.altera.com/up/pub/Altera_Material/12.1/Boards/DE2/DE2_User_Manual.pdf

ftp://ftp.altera.com/up/pub/Altera_Material/12.1/Boards/DE2/DE2_User_Manual.pdf

http://www.keysight.com/en/pc-1475688/keysight-eesof-electronic-design-automation-EDA-software?cc=SE&lc=eng&cmpid=zzfindeesof



http://www.uio.no/studier/emner/matnat/ifi/INF5481/h11/undervisningsmateriale/ADS.pdf

http://www.uio.no/studier/emner/matnat/ifi/INF5481/h11/undervisningsmateriale/ADS.pdf

ftp://http://www.infineon.com/

http://www.infineon.com/dgdl/Infineon-TLE4998C4-DS-v01_00-en.pdf?fileId=db3a304325afd6e00126328423dc648f

http://www.infineon.com/dgdl/Infineon-TLE4998C4-DS-v01_00-en.pdf?fileId=db3a304325afd6e00126328423dc648f

http://www.chipsoft.ru/index.php/download/category/6-protokols

http://www.chipsoft.ru/index.php/download/category/6-protokols

http://www.mostcooperation.com

http://standards.ieee.org/findstds/standard/1394-1995.html

http://www.kvaser.com/software/7330130980914/V1/can2spec.pdf

http://www.kvaser.com/software/7330130980914/V1/can2spec.pdf

http://vector.com/portal/medien/cmc/application_notes/AN-ION-1-3100_Introduction_to_J1939.pdf

http://vector.com/portal/medien/cmc/application_notes/AN-ION-1-3100_Introduction_to_J1939.pdf

http://standards.sae.org/j2284/3_201003/

http://www.cs-group.de/fileadmin/media/Documents/LIN_Specification_Package_2.2A.pdf

http://www.cs-group.de/fileadmin/media/Documents/LIN_Specification_Package_2.2A.pdf

http://www.mostcooperation.com/publications/specifications-organizational-procedures/

http://www.mostcooperation.com/publications/specifications-organizational-procedures/

http://psi5.org/fileadmin/user_upload/01_psi5.org/04_Specification/Specifications_PDFs/psi5_specification_v13_080729.pdf



http://www.embedded.com/electronics-blogs/beginner-s-corner/4023833/Introduction-to-Pulse-Width-Modulation

http://www.embedded.com/electronics-blogs/beginner-s-corner/4023833/Introduction-to-Pulse-Width-Modulation

http://mobile.aau.at/~welmenre/ttpa/download/ttpaspec_v200.pdf

http://mobile.aau.at/~welmenre/ttpa/download/ttpaspec_v200.pdf

http://ww1.microchip.com/downloads/en/devicedoc/39775b.pdf

ftp://ftp.ehu.es/cidira/dptos/depjt/DataBook/Optoelectronica/Lcd.pdf

ftp://ftp.ehu.es/cidira/dptos/depjt/DataBook/Optoelectronica/Lcd.pdf

https://www.micron.com/resource-details/9ead67ed-2d88-48dd-ba31-fb4cc6ebaf69

https://www.micron.com/resource-details/9ead67ed-2d88-48dd-ba31-fb4cc6ebaf69

Bibliography 101

[35] URL:http://www.element14.com/community/docs/DOC-45401/l/3m-twisted-pair-flat-cable-3782-series.

[36] "Pulse Width Modulation for On-chip Interconnects". Division of ElectronicDevices Department of Electrical Engineering Linkoping University, Sweden2005.

[37] CAN Specification 2.0. Bosch-September 1991.

[38] LIN-"Local Area Network" Specification Package Revision 2.0. September 232003.

[39] IEEE. "IEEE Standard for Binary Floating-Point Arithemtic". The Insti-tute of Electrical and Electronics Engineers,Inc 345 East 47th Street, NewYork,USA 1985.

[40] Josef Kramolis. SENT/SPC Driver for the: MPC5510 Microcontroller Fam-ily. Freescale Semiconductor: Application Note 2010.

[41] Lennart Lindh and Tommy Klelvin. "HW/SW Embedded System Design withFPGA Technology an Engineering Approach". 2009. pp 149- 152.

[42] Andre Weimerskirch Marko Wolf and Kristof Paar. "Security in AutomotiveBus System".

[43] Mercedes-Benz. "Domestic Digital Bus D2B". Mercedes Benz USA, LLC,2004.

[44] Laurent Beaurenaut, Christoph Eggiman, Ferdinad Gastinger,Hagen Platz-dasch, Friedrich Rasborning and Michael Strasser. "Single-Edge Nibble Trans-mission: Challenges and Evolutions". Infineon Technologies AG, SAE Inter-national 2009.

[45] Philips Semiconductors. "The I2C-Bus Specification". Version 2.1 January2000.

[46] SAE J2716 SENT. "Single Edge Nibble Transmission for Automotive Appli-cations". Version JAN 2010.

[47] Infineon Technologies. XC2000: SENT Decoder for XC2000. Infineon: Ap-plication Note 2008.

[48] W.Elmenreich and R.Ipp. "Introduction to TTP/C and TTP/A". Institutfur Technische Informatik, Vienna University of Technology Vienna, Austria,2001.

[49] Kristy Williamson. "Research Methods for Students, Academics and Profes-sionals". New South Wales. Charles Sturt University, 2002. pp 150- 155.

http://www.element14.com/community/docs/DOC-45401/l/3m-twisted-pair-flat-cable-3782-series

http://www.element14.com/community/docs/DOC-45401/l/3m-twisted-pair-flat-cable-3782-series

Appendix A

SENT-Decoder CRCImplementation

CRC Implementation using 256 element array

The SENT-Decoder is using a 4-bit CRC checksum. Which is implemented as aseries of shift left by 4 (multiply by 16) followed by a 256 element array lookuptable as shown below. The checksum can be calculated by using all the datanibbles in sequence and then checksumming the result with an extra zero value.An example MATLAB implementation is given [46].

CRC table for 256 element array:CRC4Table = [ 0 ,1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 13, 12, 15, 14,

9, 8, 11, 10, 5, 4, 7, 6, 1, 0, 3, 2, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8,10, 11, 8, 9, 14, 15, 12, 13, 2, 3, 0, 1, 6, 7, 4, 5, 14, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4,5, 2, 3, 0, 1, 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12, 9, 8, 11, 10, 13, 12,15, 14, 1, 0, 3, 2, 5, 4, 7, 6, 4, 4, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11, 1, 0, 3,2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14, 12, 13, 14, 15, 8, 9, 10, 11, 4, 5, 6, 7, 0, 1,2, 3, 6, 7, 4, 5, 2, 3, 0, 1, 14, 15, 12, 13, 10, 11, 8, 9, 11, 10, 9, 8, 15, 14, 13, 12, 3,2, 1, 0, 7, 6, 5, 4, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 2, 3, 0, 1, 6, 7, 4,5, 10, 11, 8, 9, 14, 15, 12, 13, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 5, 4,7, 6, 1, 0, 3, 2, 13, 12, 15, 14, 9, 8, 11, 10 ]

CheckSum=5;f o r i =1: l ength ( data )

tempCS=data ( i )+CheckSum∗16 ;CheckSum=CRC4Table (tempCS+1);

end

CRC Implementation using 16 element array

The CRC checksum can also be implemented by using 16 element array [46]. This

103

104 SENT-Decoder CRC Implementation

implementation using a bit-wise exclusive OR and a 16 element array lookup. asshown below. An example MATLAB implementation is also given.

CRC table for 16 element array CRCTable = [1 13 7 10 14 3 9 1 12 6 11 152 8 5];

CheckSum16=5;f o r i =1:numNibblesChecksum16 = b i txo r ( u int8 ( data ( I ) ) ,u int8 ( crc4_table (CheckSum16+1)) ) ;end

For Checksum with an extra zero "0" value the following MATLAB algorithm shallbe implemented.

CheckSum16=5;f o r i =1:numNibblesCheckSum16 = b i txo r ( u int8 ( 0 ) , u int8 ( crc4_table (CheckSum16+1)) ) ;end

Appendix B

Schematics Diagrams

PIC18 Microcontroller (SENT-decoder) Interfacing with the Sensor-Module and LCD Module 4.19

In this section we present the schematic diagram B.1of the SENT-Transmitter andSENT-Receiver modules. The system is design for testing purpose. ISIS-Proteus7.10 simulator has been used for testing before transferring the design to realhardware (PIC18 Microcontroller).

Figure B.1: SENT Transceiver Simulator

Experimental Setup of SENT-Decoder and Transmitter

105

106 Schematics Diagrams

Experimental setup of the decoder and transmitter mudules is depicted in thefollowing figure B.2. There are total of three wires which are used for communica-tion with the transmitter module. The red wire is a power line (+5V). The yellowwire is use for SENT communication. The black wire is used for common GNDbetween the two modules. The DE2 board and the transmitter are connectedthrough GPIO of the DE2 board.

Figure B.2: Experimental Setup Of SENT-Decoder and Transmitter