Implementing Triple-Rate SDI with Virtex-6 FPGA GTX ......The GTX wizard creates a directory structure with various files, including an example design using the GTX transceiver. If

XAPP1075 (v2.0) June 21, 2011 www.xilinx.com 1

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Summary The triple-rate serial digital interface (SDI) supporting the SMPTE SD-SDI, HD-SDI, and 3G-SDI standards is widely used in professional broadcast video equipment. SDI interfaces are used in broadcast studios and video production centers to carry uncompressed digital video along with embedded ancillary data, such as multiple audio channels.

Virtex®-6 FPGA GTX transceivers are well-suited for implementing triple-rate SDI receivers and transmitters. The LogiCORE™ IP triple-rate SDI core available in the CORE Generator™ tool supports implementation of triple-rate SDI interfaces using Virtex-6 FPGA GTX transceivers.

This application note provides three example SDI demonstrations using the triple-rate SDI core. These demonstrations run on the Xilinx® ML605 board with an attached Broadcast Connectivity FMC mezzanine card (CTXIL671).

Introduction This document describes three SDI demonstrations that illustrate various applications of the triple-rate SDI core in Virtex-6 FPGAs.

The first demonstration contains four SDI receivers and four SDI transmitters, all of which are independent. The video for each transmitter is provided by a video test pattern generator located in the FPGA. Each transmitter has its own video test pattern generator. The SDI mode, video format, and test pattern for each transmitter are selectable using the ChipScope™ Pro analyzer GUI. The video data received by each SDI receiver can be examined using the ChipScope analyzer, which is also used to examine the status of each receiver and transmitter. All of the receivers and transmitters are located in one GTX Quad, illustrating that SDI receivers and transmitters implemented in the same Quad are completely independent of each other. They can all be in different SDI modes (HD, SD, 3G) and running at different bit rates with no restrictions.

The second demonstration is a pass-through SDI interface. A single SDI transmitter and receiver are implemented. The transmitter retransmits the SDI signal received by the SDI receiver. This is not a simple reclocker implementation. The SDI signal is fully converted into parallel video data and checked for errors by the SDI receiver. The SDI transmitter converts the video data back into an SDI stream and retransmits it. This demonstration illustrates how jitter is reduced on the clock recovered by the SDI receiver using an external phase-locked loop (PLL) and then used as the reference clock for the SDI transmitter. In SD-SDI mode, the GTX receiver does not recover a clock. This demonstration shows one technique for recovering a clock in SD-SDI mode.

The third demonstration is also a pass-through SDI interface and is identical in functionality to the second demonstration. The only difference is that a GTX transmitter is used to generate a recovered 270 MHz clock in SD-SDI mode, illustrating a different method of recovering a clock for SD-SDI.

Precompiled FPGA configuration files for all three demonstrations as well as source code for the demonstrations in both Verilog and VHDL can be downloaded from https://secure.xilinx.com/webreg/clickthrough.do?cid=145958.

Application Note: Virtex-6 Family

XAPP1075 (v2.0) June 21, 2011

Implementing Triple-Rate SDI with Virtex-6 FPGA GTX TransceiversAuthor: John Snow

http://www.xilinx.com

https://secure.xilinx.com/webreg/clickthrough.do?cid=145958

Generating Cores for SDI Applications


For more information about the Xilinx triple-rate SDI LogiCORE IP, refer to LogiCORE IP Triple-Rate SDI v1.0 User Guide [Ref 1] and LogiCORE IP Triple-Rate SDI v1.0 Product Specification [Ref 2].


Starting with ISE® Design Suite 13.1, the triple-rate SDI core for Virtex-6 FPGAs is available in the CORE Generator tool. This is a free core and does not require a license. The core is supplied as unencrypted source code, and both Verilog and VHDL versions of the source code are provided.

When using the triple-rate SDI core in a project, two cores must be generated using the CORE Generator tool: the triple-rate SDI core and the GTX wrapper. The following sections describe how to use the CORE Generator tool to generate these cores.

Generating the Triple-Rate SDI Core

The CORE Generator tool used to generate the triple-rate SDI core can be launched stand-alone or from within Project Navigator by adding a new source to the project. The triple-rate SDI core is found in the CORE Generator IP catalog under the Video & Image Processing category, as shown in Figure 1.

After selecting the triple-rate SDI core, the GUI for the core opens, as shown in Figure 2.

X-Ref Target - Figure 1

Figure 1: Triple-Rate SDI Core in IP Catalog

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The GUI for the triple-rate SDI core has a single user-selectable option: the frequency of the dynamic reconfiguration port (DRP) clock. The allowed frequency range for this clock is 10 MHz to 100 MHz. The frequency of the clock that is supplied to the drpclk input of the triple-rate SDI core must be specified here. This same clock must also connect to the DCLK input of the GTX transceiver. Because the triple-rate SDI core uses this clock to generate certain timing sequences, the frequency of this clock must be specified to the core.

When the CORE Generator tool is used to generate the triple-rate SDI core, it creates a directory structure under the ipcore_dir directory of the project. The top-level directory of the structure is given the name supplied by the user to the CORE Generator tool as the file name of the core. Under this directory, the source code for the core is in the hdl directory. Both Verilog and VHDL files are available in the hdl directory. Depending on the preferred language set in the ISE project, the ISE software uses either the Verilog or VHDL files, but not both. In addition, there is also a dru directory that holds a file called dru.ngc. This is an encrypted, pre-compiled module that implements the data recovery unit (DRU) for recovery of 270 Mb/s SD-SDI data. This is the only portion of the triple-rate SDI core that is not provided in source code form.

If the .xco file for the triple-rate SDI core is in the ISE project, the ISE software automatically finds the source code and the dru.ngc file for the triple-rate SDI core in the directory structure generated by the CORE Generator tool. However, the individual source code files can also be manually added to an ISE tools project. When doing so, the dru.ngc file must be copied into the project directory so that the tools can find it during the build process.

Generating the GTX Wrapper

The Virtex-6 FPGA GTX transceiver wizard in the CORE Generator tool is used to create the GTX wrapper files. These wrapper files contain SDI-specific settings for GTX transceivers that are used to implement SDI interfaces.


Figure 2: Triple-Rate SDI GUI

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When launching the CORE Generator tool from within Project Navigator to generate the GTX wrapper, it is recommended that the Add to project box be unselected, as shown in Figure 3. The GTX wizard creates a directory structure with various files, including an example design using the GTX transceiver. If the entire GTX core is added to the project, the ISE software tries to build this example design instead of just instantiating the GTX transceivers into the project. This problem is avoided by not selecting the Add to project option and adding the necessary files to the project after the GTX wizard has generated them. After the GTX wrapper is generated by the wizard, three files must be manually added to the ISE project.

After unselecting the Add to project box, IP should be selected as the source type and the file name should be entered. The file name is used as the module name of the GTX wrapper generated by the CORE Generator tool. This file name is also the name used when instantiating the GTX wrapper in the HDL code of the project. When finished with this page, the Next button should be clicked to move to the second page of the New Source Wizard, as shown in Figure 4.

The Virtex-6 FPGA GTX transceiver wizard is located in the IP catalog under the FPGA Features and Design > IO Interfaces category. Selecting the wizard in the catalog and clicking on the Next button launches the GTX wizard.


Figure 3: New Source Wizard Page 1 for GTX Wrapper

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The first page of the GTX transceiver wizard is shown in Figure 5. For any SDI application, the hd sdi protocol template should be selected. This template is always used when generating a GTX wrapper to be used with an SDI application, even if the application implements SDI modes other than HD-SDI. Choosing the hd sdi protocol configures all of the defaults in the GTX wizard to correct values to be used with the triple-rate SDI core.

The reference clock frequencies for the TX and the RX default to 74.25 MHz. The pull-down lists for the reference clock frequencies allow the user to choose from any of the frequencies supported for SDI applications. In Figure 5, the reference clock frequencies for both the RX and the TX are set to 148.50 MHz, which is the frequency supplied by the CTXIL671 board to the ML605. The reference clock frequency should be set to 148.50 MHz in the GUI even if the actual frequency of the reference clock is 148.5/1.001 MHz.


Figure 4: New Source Wizard Page 2 for GTX Wrapper

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If an application is going to have only an SDI receiver or only an SDI transmitter, the unused portion of the GTX transceiver is disabled with the TX off and RX off checkboxes. The triple-rate SDI core controls the GTX transceiver through the DRP interface, so Use Dynamic Reconfiguration Port must be selected.

Clicking the Next button advances the GTX transceiver wizard to the second page, as shown in Figure 6. This page of the wizard is used to select one or more GTX transceivers and the associated reference clocks. If multiple GTX transceivers are selected on this page, they are all configured identically using the hd sdi template and the other settings chosen in the GTX transceiver wizard. All the selected transceivers are then instantiated into a single GTX wrapper file. Alternatively, a single GTX transceiver can be selected on this page (it does not matter which GTX transceiver is selected) and the resulting GTX wrapper can be instantiated multiple times in the application. All of the SDI demonstrations described in this document use the latter approach with the GTX wrapper containing just a single GTX transceiver, even when multiple GTX transceivers are used.


Figure 5: Virtex-6 FPGA GTX Transceiver Wizard - Page 1

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The selection of reference clocks in Figure 6 does not matter, except that a reference clock should normally be chosen for both the RX clock source and the TX clock source, unless the application can use the RX PLL as the clock source for the TX clock. For most SDI applications, this is not recommended. Choosing a clock source for both the RX and the TX configures the GTX transceiver to use both PMA PLLs, allowing them to be clocked independently. All demonstrations in this application note require independent clocking of the GTX RX and TX. Thus, reference clocks must be chosen for both the RX and the TX so that both PMA PLLs are enabled.

It does not matter which reference clocks are chosen because the reference clock ports on the GTX transceivers are only wired up to the reference clock sources selected on this page in the example file generated by the CORE Generator tool. The GTX wrapper generated by the CORE Generator tool has its reference clock input ports exposed, allowing them to be connected to the desired reference clock sources in the application regardless of what reference clock sources are selected on this page of the GTX wizard.

Clicking on the Next button opens the third page of the GTX wizard, as shown in Figure 7. For the SDI demonstrations in this application note (and for most SDI applications), the default settings on this page should not be changed.



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Xilinx does not recommend bypassing the RX and TX buffers for SDI applications in most cases. Bypassing these buffers requires advanced synchronization techniques to ensure that data is not lost as it is transferred between the GTX transceiver and the programmable logic of the FPGA. Enabling the RX and TX buffers greatly simplifies these interface requirements.

When the hd sdi template is chosen, the set of optional ports shown on this page is selected. All of the optional ports selected in Figure 7 are required by the triple-rate SDI core.

Clicking the Next button opens page 4 of the GTX wizard, as shown in Figure 8. The RX termination settings on this page should not be changed from the default values shown in Figure 8. The internal AC coupling of the GTX RX should be disabled, and the termination voltage should be set to MGTAVTT for proper operation of the receiver in SDI applications.

The pre-emphasis, post-emphasis, and differential swing settings configure the GTX TX driver. The values chosen for these settings are specific to the board and can be adjusted to optimize the performance of the GTX TX for each application. When used with the CTXIL671 board and the demonstrations in this application note, the settings shown in Figure 8 should be used. The post-emphasis setting is controlled by the application through the TXPOSTEMPHASIS port to optimize the TX output driver based on the current SDI mode.

The RX equalization settings are also board specific. The wideband/highpass ratio setting has a dramatic effect on the receiver jitter tolerance of the GTX receiver in SDI applications. Each application should test the receiver jitter tolerance of the SDI receivers to identify the best value for this setting. When used with the CTXIL671 board, a setting of 100 should be chosen.

This page also contains some optional ports. The RXCDRRESET port is required by the triple-rate SDI core.



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The settings on pages 5 through 7 of the GTX wizard are not applicable to SDI applications and should be left at their default values. Page 8 of the GTX wizard is a summary page. The generate button can be selected on page 4 or any of the subsequent pages to cause the CORE Generator tool to generate the GTX wrapper.

After the CORE Generator tool has finished generating the GTX wrapper, three files must be manually added to the ISE project to include the GTX wrapper in the project. The first file is the top-level GTX wrapper. The file name is the same as the name supplied by the user when the CORE Generator tool is launched to generate the GTX wrapper. In all of the demonstrations in this application note, that name is v6sdi_wrapper. Thus, the files v6sdi_wrapper.v or v6sdi_wrapper.vhd must be added to the ISE project. This file is located in the ipcore_dir directory.

The second file has the same name as the first, but with _gtx added to the end. In the demonstrations, this file is named v6sdi_wrapper_gtx.v or v6sdi_wrapper_gtx.vhd and is also located in the ipcore_dir directory.

The third required file is called double_reset.v or double_reset.vhd. In the ISE Design Suite 13.1, this file is located in the example_design directory of the GTX wrapper core directory tree. Thus, for the demonstrations described in this application note, the path is <project>\ipcore_dir\v6sdi_wrapper\example_design. This file implements some reset logic for the GTX transceiver.



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Building the SDI Demonstrations


Building the SDI Demonstrations

All three SDI demonstrations are provided both in source code form (in both Verilog and VHDL) and as a pre-generated .bit files. It is not necessary to build the demonstrations to run them on the ML605 board. The bit file can be loaded into the Virtex-6 FPGA on the ML605 board using the ChipScope Pro analyzer or the iMPACT software.

To build the demonstrations, ISE Design Suite 13.1 or later must be used. Directions for building each demonstration can be found in the readme.txt file of each demonstration directory. The CORE Generator tool must be used to generate the triple-rate SDI core and the GTX wrapper as described in Generating Cores for SDI Applications, page 2.

Only one non-default property is recommended when building the demonstrations. The XST synthesis property Safe Implementation, located on the HDL Options tab page of the XST properties window should be set to Yes.

Triple-Rate SDI Demonstrations

This section describes the three triple-rate SDI demonstrations. Block diagrams of each demonstration are provided together with instructions for running each demonstration on the ML605 board.

Requirements

The demonstrations require an ML605 board for the Virtex-6 FPGA and a Cook Technologies broadcast connectivity FMC mezzanine card (CTXIL671) connected to the high pin count (HPC) FMC connector of the ML605 board. The FMC mezzanine card must have a Cook Technologies Si5324 clock module (CTSLCM1) connected in the clock module L site.

The FMC mezzanine card has a Spartan®-3A FPGA. This FPGA is configured from a flash device on the FMC mezzanine card. Each SDI demonstration checks the revision of the design running in the Spartan-3A FPGA to verify that the requirements of the demonstration are met. If the Spartan-3A FPGA design does not meet the requirements of the demonstration, a warning message is displayed on the LCD of the ML605 board. If this message appears, the flash device on the FMC mezzanine card needs to be programmed with the required (or higher) revision. To update the flash device, the ML605 USB JTAG port must be connected to a USB port on a PC. The JTAG jumpers on both the ML605 board and the FMC mezzanine card must be set as described in Hardware Setup. The iMPACT software is then launched on the PC. The iMPACT software should detect the XCF02S Platform Flash PROM on the FMC mezzanine card as the first device in the JTAG chain. An MCS file can then be programmed into the XCF02S device. The MCS files for the FMC mezzanine card are named avbfmc##.mcs, where ## is the revision code.

The ChipScope Pro analyzer controls and monitors these demonstrations. The demonstrations work with the ChipScope Pro analyzer versions 13.1 and later.

The demonstrations also check that an Si5324 clock module is installed in the L clock module site of the FMC mezzanine card. The demonstrations read the contents of an identification PROM on the clock module to verify that the correct module is present. If the Si5324 module cannot be found in the L clock module site, the LCD display on the ML605 indicates a clock module error. Some cases have been reported of the PROM on Si5324 clock modules not having been correctly programmed. In those cases, the demonstration still runs correctly, but the LCD display continuously reports the clock module error.

Hardware Setup

Figure 9 shows how the ML605 board and FMC mezzanine card must be connected. The FMC connector on the FMC mezzanine card must plug into the HPC FMC connector on the ML605 board. The HPC FMC connector is the right-most of the two FMC connectors at the top of the ML605 board. Before the FMC mezzanine card is installed onto the ML605 board, the HPC JTAG jumper (located immediately to the right of the HPC connector on the ML605 board) must be moved between the HPC FMC connector and the large USB connector so that the jumper




covers the lower two pins of the jumper block. This includes the FMC mezzanine card in the JTAG chain of the ML605 board.

Caution! Power must be removed from the board before moving the JTAG jumper. It is easy to short the exposed power connector pin to the JTAG chain when changing this jumper. Power is present on the power connector even when the power switch is off and also when power is applied to the board via a different connector.

It must be verified that a jumper is present on the JTAG CONFIG jumper block on the FMC mezzanine card. This jumper block is located near the bottom-left corner of the FMC mezzanine card, just above the bottom-mounted FMC connector. The jumper must be installed in the EXP-OUT position, covering the two right pins of the jumper block. When the HPC JTAG and JTAG CONFIG jumpers are in the correct positions, the FMC mezzanine card can be plugged securely into the ML605 board’s HPC FMC connector.

When connected to the ML605 board, the FMC mezzanine card blocks the main ML605 power connector. Thus, a short adapter cable is provided with the FMC mezzanine card to convert the standard ML605 power brick’s connector to an ATX-style connector. With this cable, power can be supplied to the ML605 board through the alternative ATX-style power connector, located just below the main power connector, as shown in Figure 9.

A USB cable must be connected between the computer (with the ChipScope Pro software installed) and the ML605 board’s USB JTAG connector (the lower of the two mini-USB


Figure 9: ML605 Board and FMC Mezzanine Card

Broadcast FMCJTAG Jumper

Power BrickCord

USB ConnectorFor JTAG

HPC JTAG Jumper

Broadcast FMC

Si5324 Clock ModuleIn Clock Module L Site

ML605 Board

ATX StylePower Connector

N,S,E,W,CPushbuttons

Power BrickAdapter Cable

TX4 TX3 TX2 TX1 RX4 RX3 RX2 RX1

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connectors on the left edge of the ML605 board). This connection is required because control and monitoring of the demonstrations is done through the ChipScope Pro analyzer.

LCD Status Display

The LCD on the ML605 board displays status information about the demonstration. It provides warnings if the hardware configuration does not match the requirements of the demonstration. The status of any SDI receivers in the demonstration can be monitored on the LCD.

Five pushbuttons are positioned immediately to the right of the LCD, configured in a cross pattern. These five pushbuttons control the information displayed on the LCD. They are referred to as the North, South, East, West, and Center pushbuttons. The pushbutton in the center of the cross is the Center pushbutton. The other four pushbuttons are located per the directions of a compass, where the North pushbutton is at the top of the cross, South is at the bottom, West is at the left, and East is at the right.

When a demonstration is loaded, the LCD shows the demonstration name and revision. If the hardware configuration of the FMC mezzanine card and clock modules does not match the requirements of the demonstration, warning messages are displayed on the LCD screen indicating what is wrong.

If the hardware configuration is correct, the East, West, and Center pushbuttons can be used at any time to display information about the hardware configuration. Pushing the Center pushbutton causes the LCD to display the firmware revision of the FPGA on the FMC mezzanine board as long as the pushbutton is held down. Pushing the West pushbutton displays the part number of the clock module installed in the clock module L slot. Pushing the East pushbutton displays the part number of the clock module installed in the clock module H slot. If a particular demonstration does not require a clock module in a slot, the part number of the clock module in that slot, if there is one, cannot be displayed. For the three demonstrations provided with this application note, clock module H is not used. Thus, the part number of any clock module installed in the clock module H slot cannot be displayed.

Pushing the North or South pushbuttons cycles through the status of the various SDI receivers. Only the status of SDI receivers used in the demonstration can be displayed. If there are four active receivers, pushing the North pushbutton one time causes the status of RX1 to be displayed. Pushing it again causes the status of RX2 to be displayed, and so on. When the status of RX4 is displayed, pushing the North pushbutton again causes the name of the demonstration to be displayed. Pushing the South pushbutton cycles through the receiver status in the reverse order.

The status information displayed about each receiver includes the type of SDI input signal (SD-SDI, HD-SDI, 3G-SDI level A, or 3G-SDI level B), and the video format, including the frame or field rate. If a valid input SDI signal is not received, the receiver status is shown as Not locked. The video format is the transport format, and not necessarily the picture format. For example, if 1080p 60 Hz video is transported on a 3G-SDI level B signal, the video format is reported as 1080i 60 Hz because this is the transport format of each of the two HD-SDI data streams carried on the 3G-SDI level B interface.

Demonstration 1: Quad SDI RX/TX

This demonstration has four active triple-rate SDI transmitters and four active triple-rate SDI receivers. Figure 9, page 11 shows these eight golden side-launch BNC connectors at the top of the FMC mezzanine card. The transmitters are driven by internal video pattern generators and always output an SDI signal. The transmitters can be connected to SDI test gear or to the SDI receivers on the FMC mezzanine card. The SDI receivers can also be driven by external SDI signal sources.




Figure 10 shows a block diagram of one SDI RX/TX pair in the Quad SDI demonstration. This block is replicated four times in the demonstration, with the exception that all four SDI RX/TX blocks share the 27 MHz, 148.5 MHz, and 148.5/1.001 MHz reference clock sources that are located on the FMC mezzanine card.

The Virtex-6 FPGA configuration file for this demonstration is Demo_Bit_Files\v6sdi_4rx4tx_demo_v2.bit. It must be loaded into the Virtex-6 FPGA through JTAG using the ChipScope Pro analyzer or the iMPACT software. When the demonstration is loaded, the ChipScope Pro analyzer project file called ChipScope_Projects\v6sdi_4rx4tx_demo_v2.cpj should be loaded.

Figure 11 shows the ChipScope Pro analyzer window as it should appear when the ChipScope Pro software project is loaded. The figure shows the layout of the project. The individual windows are described later in this section. If the screen resolution is different than that used when the ChipScope tools project was originally created, the layout of the windows might vary from that shown in Figure 11.


Figure 10: Quad SDI Demonstration: Block Diagram

148.5 MHz

Si5324

27 MHz

148.5/1.001 MHz

Si5324

GTX Transceiver

MGTREFCLKTX_IN[0]

MGTREFCLKTX_IN[1]

SDI TX OUT TXP_OUTTXN_OUT

MGTREFCLKRX_IN[1]

CableEQ

Cable Driver

RXP_INRXN_IN

SDI RX IN

RXRECCLK_OUT

RXUSRCLK2_IN

Triple-Rate SDI

rx_usrclk

TXOUTCLK_OUT tx_usrclk

BUFG

BUFG

TXDATA_IN20

gtx_txdata

RXDATA_OUT20 gtx_rxdata

GTX Status Signals GTX Status

BUFG

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DCLK_IN gtx_drpclk

DRP Bus DRP Bus

GTX Reset Signals GTX Resets

RXRATE_IN gtx_rxrate2

TXUSRCLK2_IN

VideoPattern

Generators

10tx_video_a_y_in10

tx_video_a_c_in

ChipScopeTX VIO

11tx_line_a

tx_line_b 11

TX VPID data VPIDGen

tx_mode

ChipScopeRX VIO

ErrorCounter

RX Errors

RX Format & Status

RX VPID data

Clr Errs

ChipScopeRX ILA

rx_ds1a

rx_ds2a

rx_ds1b

rx_ds2b

RX Video Timing

Clock En Gentx_ce 3

2

40

32

10

10

10

10




Each SDI transmitter has a control and status virtual input/output (VIO) window, and each SDI receiver has both a status VIO window and an Integrated Logic Analyzer (ILA) window. By default, the only ILA window open when the project starts is the ILA window for RX1; it is normally pushed behind all other windows. The ILA windows for the other three receivers can be opened using the New Window option under the Windows menu. The windows that can be opened are all in DEV 3 and are called MyILA 5 for RX1, MyILA 7 for RX2, MyILA 9 for RX3, and MyILA 11 for RX4.

TX1 Control Window Details

Figure 12 shows a detailed view of the TX1 control and status VIO windows.


Figure 11: Quad SDI Demonstration: ChipScope Pro Analyzer Project Window

RX1 VIOWindow

RX2 VIOWindow

RX3 VIOWindow

RX4 VIOWindow

RX1 ILATriggerWindow

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TX1 VIOWindow

TX2 VIOWindow

TX3 VIOWindow

TX4 VIOWindow

RX1 ILAWindow




The TX1 GTX PLL Locked indicator shows the status of the GTX TX PMA PLL in the Virtex-6 FPGA. This indicator should always be green. If it is not green, there is an issue with the FMC mezzanine card supplying reference clocks to the ML605 board.

The SDI Mode selection value allows the user to select the SDI mode for the transmitter, where:

• 0 = HD-SDI

• 1 = SD-SDI

• 2 = 3G-SDI

This SDI Mode selection value must not be set to 3. In this demonstration, when 3G-SDI mode is selected, the transmitter always generates a 3G-SDI Level A signal, never Level B.

The Video Format selection value selects the TX video format. The Rate/1.001 toggle button controls the HD-SDI and 3G-SDI bit rate. Together, these two select the video format generated by the video pattern generator, as shown in Table 1. Not all format codes are valid in 3G and SD modes. It is not legal to have the Rate/1.001 switch set to 1 for all formats. Therefore, if an invalid combination of settings is selected, the FPGA code ignores the selections and chooses a valid configuration for the transmitter. The TX Rate toggle switch has no effect in SD-SDI mode.


Figure 12: Quad SDI Demonstration: TX Control Window

Table 1: Video Format Selection

Video Format Setting

HD-SDI 3G-SDISD-SDI

Rate/1.001 = 0 Rate/1.001 = 1 Rate/1.001 = 0 Rate/1.001 = 1

0 720p 50 Hz Not Valid Not Valid Not Valid NTSC

1 1080pSF 24 Hz 1080pSF 23.98 Hz Not Valid Not Valid PAL

2 1080i 60 Hz 1080i 59.94 Hz Not Valid Not Valid NTSC

3 1080i 50 Hz Not Valid Not Valid Not Valid PAL

4 1080p 30 Hz 1080p 29.97 Hz 1080p 60 Hz 1080p 59.97 Hz NTSC

5 1080p 25 Hz Not Valid 1080p 50 Hz Not Valid PAL

6 1080p 24 Hz 1080p 23.98 Hz Not Valid Not Valid NTSC

7 720p 60 Hz 720p 59.94 Hz Not Valid Not Valid PAL

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Virtex-6 FPGA GTX TX PMAPLL Locked Status

TX SDI Mode Selection Field

TX Video Format Selection Field

TX Rate Toggle Button

TX Test Pattern Selection Field




The Video Pattern select value selects the video pattern, where:

• A value of 0 selects SMPTE RP 219 color bars

• Values of 1 and 3 select the SDI pathological checkfield

• A value of 2 selects 75% color bars

RX Status Window Details

Figure 13 shows the RX status window for RX1.

The RX1 PLL Locked indicator shows the locked status of the GTX RX PMA PLL, which is green for normal operation. If it is not green, there is an issue with the reference clock supplied by the FMC mezzanine card to the ML605 board. The RX PMA PLL is not part of the clock and data recovery (CDR) circuit. It is the reference clock multiplication PLL for the RX.

The SDI Mode Locked indicator is green when the SDI receiver has detected and locked to the SDI mode. When this indicator is grey, the SDI receiver is not detecting a valid SDI signal.

The SDI Mode value shows the SDI mode of the incoming SDI signal. This value indicates SD-SDI, HD-SDI, 3G-SDI Level A, or 3G-SDI Level B, depending on the mode of the incoming SDI signal.

Next are three values related to cyclic redundancy check (CRC) errors. The CRC Error indicator is red if any CRC errors have been detected. It turns red when a single CRC error is detected and stays red until the Clear CRC Error pushbutton is pushed. Below the CRC Error indicator is a count of the number of CRC errors detected. This count is also cleared by the Clear CRC Error pushbutton. It is normal for the CRC Error detector to detect errors during changes of either the SDI mode or the bit rate of the incoming SDI signal. In SD-SDI mode, error detection and handling (EDH) errors are captured and indicated by the CRC Error indicator and the CRC Error counter.

Below the Clear CRC Error button are two signals related to SMPTE 352 payload Identification packets. There is a 32-bit hexadecimal display of the captured payload ID packet data and an indicator that is green when the SMPTE 352 packets are present in the input SDI signal. If the indicator is grey, the SDI signal does not contain any SMPTE 352 packets. The SDI transmitters in this demonstration only insert SMPTE 352 packets in 3G-SDI mode.

The bottom two values show the video format and frame rate of the incoming SDI signal. These always indicate the transport format and frame rate, which are not always the same as the


Figure 13: Quad SDI Demonstration: RX Status Window

Virtex-6 FPGA GTX RX PMA PLL Locked StatusSDI Mode Detector Locked Status

SDI Mode

CRC Error Indicator

CRC Error Count

CRC Error Clear Button

SMPTE 352 Payload ID Data

SMPTE 352 Payload ID Valid Indicator

Transport Format

Transport Frame RateXAPP1075_13_040611




picture format and frame rate. For example, if 1080p 60 Hz video is carried on a 3G-SDI level B interface, the video format is reported as 1080i 60 Hz because this is the transport format of the two HD-SDI streams that combine to carry the 1080p 60 Hz signal in 3G-SDI level B mode.

In addition to the status of the receivers, the video data being received can be viewed using each receiver’s ILA window. Figure 14 shows such an ILA window. In this example, an HD-SDI 1080i 59.97 Hz signal is received.

The CE trace shows the clock enable generated by the triple-rate SDI receiver. For HD and 3G modes, this is always High. For SD-SDI mode, the clock enable is asserted every five or six clock cycles, and the other data captured by the ILA is only valid when CE is High.

The 3G Data Ready signal is normally High. In 3G-SDI level B mode only, this signal toggles every other clock cycle, and the other data captured by the ILA is only valid when this signal is High.

The end-of-active-video (EAV) and start-of-active-video (SAV) signals are standard digital video timing signals that delineate the active portion of the video line from the horizontal blanking portion of the line.

The A Y, A C, B Y, and B C buses are the video data streams from the SDI receiver.

In SD mode, only A Y is valid. The data on A Y in SD mode is interleaved Y and C components and is only valid when CE is High. In SD mode, it is useful to set up the ILA to qualify storage only when CE is High.

In HD mode, A Y is the Y component, and A C is the C component.

In 3G-SDI level A mode, A Y is data stream 1, and A C is data stream 2. For 1080p 50 or 60 Hz video, data stream 1 is the Y component, and data stream 2 is the C component. For other video formats carried by level A, the data is mapped according to the SMPTE 425M data mapping requirements.

In 3G-SDI level B mode, all four components are active. The data is in SMPTE 372M dual-link HD-SDI format. This means that the data is formatted to be carried by two HD-SDI links. Level B takes the four video components (Y and C for each of the two HD-SDI links) and interleaves them onto the 3G-SDI level B signal. The triple-rate SDI receiver separates the 3G-SDI level B signal back into the four components. The A Y and A C buses carry the Y and C component for link A, and the B Y and B C buses carry the Y and C components for link B. Because the recovered clock frequency is 148.5 MHz in 3G-SDI mode but the data rate of the four component outputs of the receiver is 74.25 MHz, the 3G Data Ready signal indicates when the data changes on the four component buses.


Figure 14: Quad SDI Demonstration: Receiver ILA Window

XAPP1075_14_040611




Demonstration 2: SDI Pass-Through

This demonstration receives the SDI signal on RX2 and then retransmits it on TX2. The signal is not modified, but the SDI receiver does check for CRC and EDH errors on the incoming signal. The status of these error detection circuits and other status can only be observed using the ChipScope Pro analyzer.

This demonstration does not provide an SDI signal source. An external SDI signal source must be connected to the RX2 BNC connector for this demonstration to function. To evaluate the operation of the SDI transmitter output, the TX2 connector must be connected to an external SDI receiver or SDI waveform monitor.

As shown in Figure 15, this demonstration uses a single GTX transceiver and a single triple-rate SDI core. The data received by the SDI receiver is retransmitted by the SDI transmitter. A 148.5 MHz clock is provided to the GTX transceiver as the receiver reference clock.

In HD-SDI and 3G-SDI modes, the clock recovered by the GTX receiver (RXRECCLK_OUT) is used to clock the fabric interfaces of both the GTX receiver and the GTX transmitter, as well as the receive and transmit sides of the triple-rate SDI core. Thus, all data transfers from the SDI receiver to the SDI transmitter are synchronous and in the same clock domain. The recovered clock is also connected to the input of an Si5324 digital PLL. The Si5324 reduces the jitter on the recovered clock and, in HD-SDI mode, multiplies it by 2 to provide a 148.5 or 148.35 MHz reference clock to the GTX transmitter. This reference clock is frequency locked to the clock recovered by the GTX receiver, but has lower jitter.

In SD-SDI mode, the GTX receiver does not recover a clock. The RXRECCLK_OUT output of the GTX transceiver is frequency locked to the 148.5 MHz GTX receiver reference clock. This clock is used to clock the GTX receiver fabric interface and the receive side of the triple-rate


Figure 15: SDI Pass-Through Demonstration: Block Diagram

148.5 MHz

Si5324

Clock EN Gen

27 MHz

TX Reference Clk

Si5324

Async FIFO

RC

LK

DO

UT

RE

N

DIN

WE

N

WC

LK

GTX Transceiver

MGTREFCLKRX_IN[0]

MGTREFCLKTX_IN[0]


CableEQ

Cable Driver

RXP_INRXN_IN

SDI RX IN

RXRECCLK_OUT

RXUSRCLK2_IN

Triple-Rate SDI

rx_usrclk

TXOUTCLK_OUTtx_usrclk

BUFG

BUFGMUX

SD-SDI

SD-SDI

SD-SDI

1

0

1

0

0

1

TXDATA_IN20

gtx_txdata

RXDATA_OUT20

10

10

10

10

10

10

10

10

2

gtx_rxdata


BUFG

XAPP1075_15_041211

DCLK_IN gtx_drpclk

DRP Bus DRP Bus



TXUSRCLK2_IN

tx_video_a_y_in

tx_video_a_c_in

tx_video_b_y_in

tx_video_b_c_in

tx_din_rdy

tx_mode

rx_mode

rx_dout_rdy_3G

rx_ds2b

rx_ds1b

rx_ds2a

rx_ds1a

rx_ce_sd

tx_ce




SDI core. However, the GTX transmitter needs a 148.5 MHz clock that is frequency locked to the 27 MHz recovered data rate. The Si5324 generates such a clock by multiplying the 27 MHz rx_ce_sd clock enable signal from the triple-rate SDI core by 5.5. The resulting low-jitter 148.5 MHz clock is always exactly 5.5X the 27 MHz recovered data rate and is provided to the GTX transmitter as the reference clock. The GTX TXOUTCLK_OUT is essentially a copy of the GTX transmitter reference clock and is used to clock the fabric interface of the GTX transmitter and the transmit side of the triple-rate SDI core. In this case, the receive and transmit sides of the triple-rate SDI core are clocked by different clocks that have no real frequency relationship. Thus, an asynchronous FIFO is used to move the data from the receive clock domain to the transmit clock domain.

The Virtex-6 FPGA configuration file for this demonstration is called Demo_Bit_Files\v6sdi_pass_demo_v2.bit. It must be loaded into the Virtex-6 FPGA through JTAG using the ChipScope Pro analyzer or the iMPACT software. When the demonstration is loaded, the user opens the ChipScope Pro analyzer file called ChipScope_Projects\v6sdi_pass_demo_v2.cpj.

Figure 16 shows the ChipScope Pro analyzer window when the ChipScope Pro tool project is opened. The figure shows the layout of the project. If the screen resolution is different than that used when the ChipScope tool project was originally created, the layout of the windows might vary from that shown in Figure 16.


Figure 16: SDI Pass-Through Demonstration: ChipScope Pro Analyzer Project Window

XAPP1075_16_040611

RX ILA TriggerWindow TX ILA Window

TX ILA TriggerWindow

VIOWindow

RX ILAWindow




Figure 17 shows the ChipScope Pro analyzer VIO window that indicates the status of the demonstration.

When a CRC error is detected on the input SDI signal in HD-SDI and 3G-SDI modes, the RX CRC error indicator turns red. It stays red until the Clear CRC Errors button is pushed in the VIO window. In SD-SDI mode, the RX EDH Error Count indicator indicates the number of EDH errors that have been detected. It is also cleared to zero by pushing the Clear CRC Errors pushbutton. The RX CRC error indicator only indicates CRC errors in HD-SDI and 3G-SDI modes and does not indicate EDH errors in SD-SDI mode. Likewise, the RX EDH Error Count indicator only indicates the number of detected EDH errors in SD-SDI mode and does not count the number of CRC errors in HD-SDI and 3G-SDI modes.

The RX PMAPLL Locked signal is green when the GTX transceiver’s RX PMA PLL is locked to the reference clock. The reference clock is generated by the main Si5324 clock module. This PLL is not used for clock and data recovery. It is a clock multiplier for the reference clock. If this PLL is not locked, it indicates a problem with the reference clock supplied by the Si5324 on the FMC board.

When the SDI receiver has determined the SDI mode of the input signal and is locked to it, the RX Mode Locked indicator is green, and the SDI mode is reported on the RX SDI Mode line. If this indicator is not green, the SDI receiver is trying to determine the SDI mode of the input signal.

After the SDI receiver has locked to the input SDI signal, it attempts to determine the video format of this signal. If the video format is successfully identified, the RX Locked indicator turns green, and the video format is reported by the RX Transport Family value. Additionally, the frame rate of the SDI transport is shown by the RX Transport Frame Rate value. These two values indicate the transport characteristics that are not always the same as the picture characteristics.

The main Si5324 loss-of-lock (LOL) indicator is red if the main Si5324 device on the FMC mezzanine card is not locked. This device generates the reference clock for the GTX receiver. If this indicator is red, there is an issue with the local reference clock, and the demonstration does not function correctly.


Figure 17: SDI Pass-Through Demonstration ChipScope Pro VIO Window

CRC and EDH Errors Clear Button

HD-SDI and 3G-SDI CRC Error Indicator

SD-SDI EDH Error Count

GTX RX PMA PLL Locked Indicator

RX SDI Mode Locked Indicator

RX Video Format Detection Locked Indicator

Main Si5324 Loss-of-Lock Indicator

Si5324 B Loss-of-Lock Indicator

GTX TX PMA PLL Locked Indicator

RX SDI Mode

RX SDI Transport Family

RX SDI Transport Frame Rate

XAPP1075_17_040611




The current mode logic (CML) Si5324 B LOL indicator is red if the Si5324 B on the clock module is not locked. This device serves as the clock cleaner PLL in this demonstration and generates the reference clock for the GTX transmitter. In HD-SDI and 3G-SDI modes, the Si5324 B takes in the recovered clock from the SDI receiver, reduces the jitter on that clock, and then provides a reference clock of either 148.5 MHz or 148.35 MHz to the SDI TX. In SD-SDI mode, this device takes in the 27 MHz receiver clock enable and produces a reference clock with a frequency of 148.5 MHz. It is normal for this LOL indicator to be red when the SDI receiver is not locked to the input signal and for a few seconds after the SDI receiver becomes locked. When this Si5324 device is not locked, the SDI transmitter is disabled.

The TX PMAPLL Locked indicator is green when the GTX TX PMA PLL is locked to the reference clock provided by the CML Si5324 B. It is normal for this LOL indicator to be red when the SDI receiver is not locked to the input signal and for a few seconds after the SDI receiver becomes locked.

The received data can be observed in the RX ILA window. The TX ILA window can be used to observe some of the transmitter signals, but this window is primarily for debug purposes. By default, these two ILA units are set up to capture data only when their clock enable signals are asserted. The tx eav and tx sav signals in the TX ILA window are not active in SD-SDI mode.

Demonstration 3: SDI Pass-Through with SD-SDI Clock Recovery Using GTX TX

This demonstration works identically to Demonstration 2: SDI Pass-Through, page 18. It is a pass-through demonstration where the signal received by RX2 is retransmitted on TX2. The method used to generate the recovered clock for SD-SDI is identical to that used in Demonstration 2. However, this demonstration adds a second SD-SDI clock recovery method using an additional GTX transmitter to generate a 270 MHz recovered clock. The clock recovered by the GTX transmitter is not used to retransmit the SDI signal in SD-SDI mode. Instead, it is output from the ML605 board and the FMC mezzanine card so that its behavior and performance can be observed with an oscilloscope.

Figure 18 shows a block diagram of this demonstration. Only the bottom GTX transceiver (identified as GTX transceiver B in the figure) and associated blocks are different from the regular SDI pass-through demonstration shown in Figure 15. Only the TX portion of GTX transceiver B is used. GTX transceiver B uses the same 148.5 MHz reference clock that is used as the receiver reference clock for GTX transceiver A. The TXUSRCLK2_IN of GTX transceiver B is driven by the same clock that drives the RXUSRCLK_2 of GTX transceiver A. Thus, GTX transceiver B’s FPGA fabric interface operates synchronously with the SDI receiver. This is essential for proper operation of this clock recovery technique.




The DRU in the triple-rate SDI core generates a data stream and outputs it on the rx_recclk_txdata port of the core. This data stream is connected to the TXDATA_IN port of GTX transceiver B. The DRU generates this data stream such that the output of the GTX transceiver B transmitter is a 270 MHz clock that is frequency locked to the recovered SD-SDI data rate.

The output of the GTX transceiver B transmitter is connected to the TX1 BNC connector on the FMC mezzanine board. This 75 output can be connected to an oscilloscope to view the recovered 270 MHz clock.

The output of the GTX transceiver B transmitter is routed back into the Virtex-6 FPGA on the ML605 board. This 270 MHz recovered clock is divided by 10 to generate a 27 MHz clock. Both the 270 MHz and 27 MHz recovered clocks are connected to a multiplexer in the FPGA that drives an output buffer connected to the USER CLK SMA connectors on the ML605 board. DIP switch 1 on SW1 (upper left corner of the ML605 board) selects whether the recovered clock output on the SMA connectors is 270 MHz (ON) or 27 MHz (OFF).


Figure 18: SD-SDI Recovered Clock Demonstration: Block Diagram

148.5 MHz

Si5324

Clock EN Gen

27 MHz

TX Reference Clk

Si5324

Async FIFO

RC

LK

DO

UT

RE

N

DIN

WE

N

WC

LK

GTX Transceiver A

GTX Transceiver B

MGTREFCLKRX_IN[0]

MGTREFCLKTX_IN[0]

MGTREFCLKTX_IN[0]


TXP_OUTTXN_OUT

IBUFDS270 MHz

27 MHz/10

CableEQ

SY89540UBuffer

Cable Driver

270 MHzRecoveredClock onTX1 BNC

27 MHz or 270 MHz Recovered Clock onML605 USER CLKSMA Connectors

CableDriver

RXP_INRXN_IN

SDI RX IN

RXRECCLK_OUT

RXUSRCLK2_IN

Triple-Rate SDI

rx_usrclk

TXOUTCLK_OUTtx_usrclk

BUFG

BUFGMUX

SD-SDI

SD-SDI

SD-SDI

1

0

1

0

0

1

TXDATA_IN

TXDATA_IN

20

20

gtx_txdata

RXDATA_OUT20

10

10

10

10

10

10

10

10

2

gtx_rxdata


BUFG

XAPP1075_18_041211

DCLK_IN gtx_drpclk

DRP Bus DRP Bus



TXUSRCLK2_IN

TXUSRCLK2_IN

tx_video_a_y_in

tx_video_a_c_in

tx_video_b_y_in

tx_video_b_c_in

tx_din_rdy

tx_mode

rx_recclk_txdata

rx__mode

rx_dout_rdy_3G

rx_ds2b

rx_ds1b

rx_ds2a

rx_ds1a

rx_ce_sd

tx_ce

DIP Switch 1

OBUFDS 27 MHz RecoveredClock Enable onML605 USER DATASMA Connectors

OBUFDS1

0




For reference purposes, the ce_sd clock enable signal from the SDI receiver is output on the USER GPIO SMA connectors. This clock enable is a 27 MHz signal that is asserted whenever the SDI receiver has a 10-bit video data word ready on its output. The ce_sd signal represents the actual data rate of the recovered SD video data. This signal can be observed to verify that the recovered clock is frequency locked to the recovered video data rate by comparing the ce_sd signal to the recovered clock using an oscilloscope.

With the oscilloscope, the recovered clock can also be compared to the SD-SDI output signal on TX2. The recovered clock used to generate the SD-SDI output on TX2 is generated by an entirely different clock recovery mechanism using an Si5324 DPLL device locked to the ce_sd output of the SDI receiver. By comparing the SD-SDI output on TX2 with the recovered clock on either TX1 or the USER CLK SMA connectors on the ML605 board, the two clock recovery methods are seen to be generating frequency-locked signals. Figure 19 shows this comparison. The top trace is the 270 MHz recovered clock on the TX1 connector, and the bottom trace is the SD-SDI output on TX2.

This demonstration does not provide an SDI signal source. An external SDI signal source must be connected to the RX2 BNC connector for this demonstration to function. To evaluate the operation of the SDI transmitter output, the TX2 connector must be connected to an external SDI receiver or SDI waveform monitor. To analyze the performance of the clock recovery scheme, an oscilloscope can be used to look at the recovered clock.

The Virtex-6 FPGA configuration file for this demonstration is called Demo_Bit_Files\v6sdi_mgt_recclk_demo_v2.bit. It must be loaded into the Virtex-6 FPGA through JTAG via the ChipScope Pro analyzer or the iMPACT software. After the demonstration is loaded, the user opens the ChipScope project file called ChipScope_Projects\v6sdi_mgt_recclk_demo_v2.cpj. This project file is identical to v6sdi_pass_demo_v2.prj, so either one can be used.

The operation of this demonstration is the same as Demonstration 2: SDI Pass-Through, page 18. The figures and descriptions in that section can be referred to for details of how the ChipScope Pro analyzer GUI monitors the operation of the demonstration. The pass-through function of this demonstration works in HD-SDI and 3G-SDI modes, as well as SD-SDI mode,


Figure 19: Comparing the SD-SDI TX Output with the 270 MHz Recovered Clock

X1075_19_040611


Conclusion


but the focus of this demonstration is the SD-SDI clock recovery, which is only active in SD-SDI mode.

Conclusion This document describes how to use the Xilinx LogiCORE IP triple-rate SDI interface for Virtex-6 FPGAs in three different applications. The Virtex-6 FPGA GTX transceivers are well suited for implementing SDI interfaces, providing a high degree of performance and reliability.

References This section provides links to documents referenced here:

1. UG791, LogiCORE IP Triple-Rate SDI v1.0 User Guide

2. DS828, LogiCORE IP Triple-Rate SDI v1.0 Product Specification

3. UG366, Virtex-6 FPGA GTX Transceivers User Guide

4. XAPP875, Dynamically Programmable DRU for High-Speed Serial I/O

5. DS152, Virtex-6 FPGA Data Sheet: DC and Switching Characteristics

Additional Resources

These documents and product pages provide additional information useful to this application note:

• Virtex-6 FPGA Broadcast Kit product page

http://www.xilinx.com/products/devkits/DK-V6-BCCN-G.htm

• Virtex-6 FPGA ML605 Evaluation Kit

http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm

• Virtex-6 FPGA Broadcast Kit documentation page

http://www.xilinx.com/products/boards/v6bck/reference_designs.htm

• UG753, FPGA Broadcast Mezzanine Card User Guide

http://www.xilinx.com/support/documentation/boards_and_kits/ug753_FMC_Broadcast.pdf

Revision History

The following table shows the revision history for this document.

Notice of Disclaimer

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use ofXilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "ASIS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OFMERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2)Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of

Date Version Description of Revisions

06/08/10 1.0 Initial Xilinx release.

11/02/10 1.1 In Triple-Rate SDI Receiver Reference Design under Figure 1, the bit rate for SMPTE 292 was changed to 1.485/1.001 Gb/s HD-SDI. In Figure 7 and Figure 10, added TXPLLLKDET in the GTX TX block connecting to txplllkdet in the v6gtx_sdi_control block. In Table 8, changed the name of the do port to drpdo and added the txplllkdet port description. In Transmitter Functions, added sentence about asserting GTXTEST[1] twice in bulleted paragraph on page 42. Added “or later” to ISE software version entry in Table 10.

06/21/11 2.0 Updated for ISE Design Suite 13.1.


http://www.xilinx.com/support/documentation/ip_documentation/ds828_triple_sdi.pdf

http://www.xilinx.com/support/documentation/ip_documentation/ug791_triple_sdi.pdf

http://www.xilinx.com/support/documentation/application_notes/xapp1014.pdf

http://www.xilinx.com/products/devkits/DK-V6-BCCN-G.htm

http://www.xilinx.com/support/documentation/data_sheets/ds152.pdf

http://www.xilinx.com/support/documentation/user_guides/ug366.pdf

http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm

http://www.xilinx.com/products/boards/v6bck/reference_designs.htm

http://www.xilinx.com/support/documentation/boards_and_kits/ug753_FMC_Broadcast.pdf

Notice of Disclaimer


liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, theMaterials (including your use of the Materials), including for any direct, indirect, special, incidental, orconsequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damagesuffered as a result of any action brought by a third party) even if such damage or loss was reasonablyforeseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation tocorrect any errors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materials without priorwritten consent. Certain products are subject to the terms and conditions of the Limited Warranties whichcan be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and supportterms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to befail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability foruse of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.


http://www.xilinx.com/warranty.htm

http://www.xilinx.com/warranty.htm#critapps

Documents

Implementing Triple-Rate SDI with Virtex-6 FPGA GTX ......The GTX wizard creates a directory structure with various files, including an example design using the GTX transceiver. If