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Investigation of Reusable and Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical Engineering, University of Washington

Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

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Page 1: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Investigation of Reusable and Reversible Logic Gate

with LGAFinal project for CSE599D/EE590A, fall 2013

Tsung-Wei Huang

Department of Electrical Engineering, University of Washington

Page 2: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Abstract

• Title: Investigation of Reusable and Reversible Logic Gate with LGA

• Abstract:

First, we construct some logic gates in LGA model using the scheme of billiard-ball model. We find out that the limit of the LGA model may result in some undesired properties of these gates. Therefore, rather than number of particle to build some logic structures, we use time-encoding method. It is shown that this method can produce reusable and reversible logic gate, which does not cost energy in the thermodynamic point of view. Finally, we investigate the properties of the logic structures and gates, and proposed some ideas which may make the construction easier. Since the construction of a logic gate is not easy (NP problem), an efficient way to calculate the output of a logic structure is necessary for building a non-trivial logic gate.

Page 3: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Outline

• LGA logic gates in the scheme of billiard-ball model

• The intrinsic limit of LGA model• Trajectory

• Time-encoding Boolean value under LGA model• Orbit and path• Orbit level representation

• Logic gates• Orbit level• Layout and LGA simulations – NOT gate

• Properties of logic structures and gates• Reusable and reversible• Vector representation• Challenges in designing logic gates

• Conclusion

Page 4: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

LGA logic gates in the scheme of billiard-ball modelPresence of particle -> 1

No particle -> 0

• I1

• I2

• I3

• O1=I1(I2I3)

• O2=I2(I3I1)

• O3=I3(I1I2)

I1

I3

I2

O1

O3

O2

Page 5: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

I1

1

1

0

O1

O2

1

I2

I1

O1 I1

C1

C1

O1

NOT gate NAND gate SWITCH gate

COPY gate OR gate

3 particles collision gates (NOT, NAND, Switch)

4, 5 particles collision gates (COPY, AND, OR)

I1

O2

O1

1

1

1

1

1

1

O1

I1

12

AND gate

I1

O1

1

1

I2

However, back reflection sometimes occur, and extra control bit is required.

Page 6: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

The intrinsic limit of LGA model• Define the trajectory of a particle as the path the particle can run

through when there are no other particles.

=>All of the “deterministic” collisions cannot switch any particles from their original path, which is different from that in billiard ball model.

I1

I3

I2

O1

O3

O2

T1

T2

T3

I1 I2

O1

O2

T1

T2

T3

O1’

O2’

Page 7: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Intrinsic limit: trajectory• Closed trajectory: number of particles is constant

n(t+1) = n(t)

• Open trajectory: the number of output equals to the number of input if there is no reflection

no = ni

• As a result, if there is no collision from opposite direction (which produce random outcome), the numbers of particles cannot be used to conduct logic calculation (i.e. a particle for 1, and 0 particle for 0).

1 1

Page 8: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Time encoding Boolean value under LGA model• Since the number of output particles is equal to the

number of input particles, we can only change the time of arrival of an output particle.

(1,1,0) (1,0,1)gate

Page 9: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Time encoding: orbit and path• Orbit (green line): pairs of particles move between sites

on their orbits.• If the distances between each pairs are 2nΔ for some integers

n, then every pairs do not interfere with other pairs.

• Path (blue line): one bit particle moving from left to right.• Bit particle can only collide with pair particles on the sites

shared with orbit(s).

The time needed to move to the next site is Δ.

A B C D

Page 10: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Represent the structure in orbit level

A B C D

A B C D

collision site non-collision site

In vector:Orbit = [ 0, 1, 0, -1]Path = [ 1, 0, 0, 0, 0, 0]

Page 11: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (orbit level)

1

0

t = 0Δ

A B C

A B C 0

1

t = 8Δ

Page 12: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (operation detail)

1

t = 0Δ

0

t = 0Δ

Page 13: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (operation detail)

1

t = 1Δ

0

t = 1Δ

Page 14: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (operation detail)

1

t = 2Δ

0

t = 2Δ

Page 15: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (operation detail)

1

t = 3Δ

0

t = 3Δ

Page 16: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (operation detail)

1

t = 4Δ

0

t = 4Δ

Page 17: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (operation detail)

1

t = 5Δ

0

t = 5Δ

Page 18: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (operation detail)

1

t = 6Δ

0

t = 6Δ

Page 19: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (operation detail)

1

t = 7Δ

0

t = 7Δ

Page 20: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (operation detail)

0

t = 8Δ

1

t = 8Δ

Page 21: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT -reusable and reversible

1

0

t = 0Δ

0

1

t = 8Δ

The gate returns to its initial state after operation.

Page 22: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (layout)

t=0input=0 (top gate)Input=1 (bottom gate)

t=8*Δ=128output=1 (top gate)output=0 (bottom gate)

Layout using Δ=16

Page 23: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Logic gate: NOT (layout)-sequential input

t=0input=[0, 1] (top gate)Input=[1, 0] (bottom gate)

t=2*(8*Δ)=256output=[1, 0] (top gate)output=[0, 1] (bottom gate)

Layout using Δ=16

t=8*Δ=128output=[1] (top gate)output=[0] (bottom gate)

Page 24: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Possibility to connect more than one path using orbits

Page 25: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Properties of the logic structures and gates: reusable and reversible

• Reusable:• There are no garbage particles in these designing.• If a gate can return to its initial state after some steps,

then it is reusable.

• Reversible:• Since every step is deterministic, any structure build

from orbits and paths are reversible.

• In the thermodynamic point of view, theseproperties imply the gate does not dissipate energy,while the need to erase garbage particles in“number of particle” gate makes it cost energy.

Page 26: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Vector representation of paths and orbits• We can map a site to an entry of a path vector and orbit vector.

• Path vector “p”:• “1” for particle moving to the output end• “-1” for particle moving to the input end• “0” for no particle

• Orbit vector “o”:• “1” for pair moving counterclockwise• “-1” for pair moving clockwise• “i” for 2 pairs meeting on the same site• “0” for no pair

• Moving rule:• All “1” will move to its next site of the vector• All “-1” will move to its previous site of the vector• If “1” and “-1” move to the same site, assign the value “i” to the site• All “i” will transform into a “1” at its next site and a “-1” at its previous site

Page 27: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Vector representation of paths and orbits (cont.)• Collision rule:

• Define CCW/CW site as the site shared by a path vector entry p[i] and an orbit vector entry o[j] on which a CCW/CW pair is moving to the output end

• CCW site:• if p[i] == -o[j], then p[i] = -p[i] and o[j] = -o[j]

• CW site:• if p[i] == o[j], then p[i] = -p[i] and o[j] = -o[j]

CCW site

CW site

Page 28: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Challenges in designing logic gates

• Since the complexity of the state and outcome of a time-encoding gate grows exponentially with the number of sites in the gate (NP problem), it is not easy to design a logic gate by trial and error.

• Furthermore, since the operation is non-linear, the vector representation does facilitate the computer simulation, but does not reduce the computation.

• However, it might be possible to use computer to randomly generate some logic structure under some constrains to get some non-trivial logic gates.

Page 29: Implementation of Reusable, Reversible, and Universal ... fileand Reversible Logic Gate with LGA Final project for CSE599D/EE590A, fall 2013 Tsung-Wei Huang Department of Electrical

Conclusion

• The principle of particle collision in LGA model results in the limit of constructing a logic gate, making the LGA model differs from billiard-ball model.

• It is impossible to build a reusable “number-of-particle” logic gate if every collision used in the gate is deterministic.

• An alternative way is to build a “time-encoding” logic gate, which can be reusable and reversible under LGA model.

• The complexity of the state and outcome of a time-encoding gate is too large. Therefore, an efficient way to calculate the state and output of a logic structure is required.