Implementation of a sic based MC-CDMA base station receiver

1 Multi- Carrier Spread-Spectrum and Related Topics 1

Implementation of A SIC Based MC-CDMA Base Station Receiver*

ANDREW C. MCCORMICK Alpha Data F’arallel Systems Ltd. 58 Timber Bush, Edinburgh EH6 SQH, Scotland

JOHN s. THOMPSON, PETER M. GRANT, TUGHRUL ARSLAN AND AHMET T. ERDOGAN School of Engineering and Electronics, The University of Edinburgh, Kings Buildings, Edinburgh, EH9 3JL, Scotland

3ohn.Thompson @ed.ac.uk

Abstract. The implementation of a multi carrier-code division multiple access (MC-CDMA) base station receiver incorporating decision statistic ordered successive interference cancellation multi-user detection in low power CMOS hardware is investigated. Serial and panllel cancellation architectures an compared and i t is shown that the parallel one operates in far fewer clock cycles than its serial counterpart. A detailed description of architecture is given including the parallel algorithm used to implement the multi-user detection. Results show the power consumption and fixed point performance of the circuit.

1 INTRODUCTION

Multi-carrier Code Division Multiple Access (MC- CDMA) was first proposed in [ I ] and is a multiple access modulation technique which combines the advantages of orthogonal frequency division multiplexing (OFDM) and code division multiple access (CDMA). The signal is spread by transmitting each code chip on a different orthogonal sub-camer. The main benefit of combining these approaches is that it allows CDMA multi-user detection receivers such as the linear minimum mean square error (MMSE) solution [Z] to be implemented using a simple single tap equaliser on each carrier. An OFDM cyclic-prefix can be used to prevent degradation due to multipath and small asynchronous timing errors.

However, better performance can be obtained using non-linear detectors, such as the maximum likelihood joint symbol estimate which can also be obtained, as in a di- rect sequence CDMA system [3] by finding the minimum Euclidean distance between the received signal and all possible transmitted signals, weighted by the channel. HOW- ever, this receiver has exponentially increasing computational complexity as the number of users increases, therefore some form of sub-optimal solution is required to support a large number of users.

Investigation of the performance of uplink MC-CDMA

‘An earlier version of this paper has been presented at the Third International Workshop on Midti-Ciirrier Sprericl-S]ircrrutn

(MCSS 2001).

receiver designs [5] has indicated that the inclusion of decision statistic ordered successive interference cancellation (SIC) [6] in the receiver provides good performance for a large number of users with an algorithm of only N 2 complexity, where N is the number of users. Accurate channel estimation can be a problem in uplink MC-CDMA, but if the channels have a small delay spread, narrowband pilots and interpolation can be applied to provide accurate channel estimates, without requiring a high pilot signai to noise ratio.

The hardware implementation of low power MC- CDMA mobile stations has been considered in [7]. This work is extended to the uplink base station receiver in this paper. In particular the implementation of the decision statistic ordered SIC algorithm is considered. Although much of the SIC algorithm requires serial operation, some par- allelisation can be applied to reduce the number of clock cycles required from N 3 to N . A 48 user QPSK system is considered and therefore a reduction of clock rate from 9216 times the symbol rate to 96 times the symbol rate is desirable.

Other implementation aspects of the base station receiver such as channel estimation and users’ synchronisation will also be described. A Verilog model of the entire baseband receiver will be presented in detail and used to provide an indication of hardware performance, including the effects of fixed point arithmetic and power consumption.

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A.C. McComick, J.S. Thompson, P.M. Grant, T. Arslan, A.T. Erdogan

2 COMPARISON OD SIC AND ML UPLINK MC-CDMA

The performance of decision statistic ordered SIC compares favourably with many other multi-user detection algorithms, although it cannot match the performance of the maximum likelihood (ML) joint detection algorithm. Un- der cenain circumstances however the difference between their performance is small. Figure 1 shows the performance of ML and SIC algorithms for uplink MC-CDMA. In this case a system with processing gain of 8 is simulated to keep the simulation time short. Random codes were used and up to 16 simultaneous users were Simulated. The graph shows the signd power required to obtain bit error probabilities of loe2 and

9 1 4

- 2 4 8 I 10 12 14 16 H m b r d U m

Figure I : Comparison of ML and SIC algorithm performance for an 8 chip MC-CDMA uplink system in Rayleigh fading channels.

Clearly for up to 7 users in this system, the performance of the algorithms is almost identical. However when the number of codes is larger than the processing gain, the performance of SIC deteriorates rapidly. Therefore the algorithm is a very good candidate for systems where the number of carriers divided by number of users required is at most 1, and the quality of service requirement is for uncoded probability of error of around to

3 UPLINK MC-CDMA IMPLEMENTATION

In this section, two important practical issues related to the operation of an uplink MC-CDMA system are described. Firstly, synchronisation issues are discussed. Sec- ondly, the channel estimation approach that has been assumed for this work is explained.

3.1 UPLINK SYNCHRONISATION

The potential asynchronism between users on the uplink will affect the orthogonality between users and can re- sult in multi-user interference from different symbol inter- vals being present in the received signal. This can be solved through a block level approach to multi-user detection 141 but this can be very computationally complex. In the case of multi-carrier CDMA, an alternative solution is to en- force synchronisation of all users to a fraction of the symbol length. This is easily achieved in small cells when the delays due to radio propagation are short. In larger cells, a closed loop feedback system may be used periodically to advance or retard the transmission as required. Then all users cyclicly-extend the symbol, with a sufficient duration to deal with two effects. Firstly, the cyclic extension duration Td must be long enough to absorb any multipath present in the channel. Secondly, an additional time pe- nod is required to ensure that the permitted asynchronism of users does not lead to inter-symbol interference. This gives a quasi-synchronous MC-CDMA system [8], which ensures a symbol length with no overlap is present at the receiver.

The length of the guard time T, required to deal with user asynchronism depends on the operation of the receiver. There are two distinct situations, depending on whether the receiver synchronises to the earliest or the strongest user. The first case arises when the portion of the receiver can always be synchronised to the earliest arriving user. This case is illustrated for four users in Figure 2(a), with user 1 being the earliest arriving user. It can be seen in this figure that no symbol transitions occur during the receiver FFT window, so no inter-symbol interference will occur. Thus, the guard t ime duration T, need be no greater than the maximurn permitted relative delay between users, T, .

The second situation arises when the FFT portion of the receiver synchronises to the strongest received signal'. In this case, it is no longer possible to guarantee that the receiver will synchronise to the earliest arriving user. In fact, the receiver could synchronise to any of the received users, depending on which one is the strongest. Figure 2(b) shows this scenario for two extreme cases when the receiver FFT synchronises to the earliest arriving user (user 1) and to the latest arriving (user 2). In this case, there is also a cyclic prefix of duration T d + T, . However, the transmitter must also insert an additional cyclic postfix of duration T, at the end of each symbol. By doing this, it can be seen from the figure that no symbol transitions occur in the FFT window of the receiver. This is true regardless of whether the receiver is synchronised to user 1, or user 2. Thus, inter- symbol interference is again avoided in either case, but this time the total length of the guard time T, devoted to tack- ling the users' asynchronism must now be double the max-

'The authors thank their MCSS 2001 session chairman. Professor S. Ham from the University of Osaka in Japan, for pointing out this possibil- ity.

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Implementation Of A SIC Based MC-CDMA Base Station Receiver

frequency positions of the pilots of users 2 and 9 indicated.

synchronird to urn 1:

Symhmnhd to U u r E

I

. Figure 2 : Overview of quasi synchronous MC-CDMA systems

when (a) FIT is synchronised to earliest arriving user and (b) FFT is synchronised to the user with the strongest signal.

imum permitted relative delay time, i.e. 2T,.

3.2 CFHANNEL ESTIMATION

The performance of any receiver is critically dependent on the quality of the channel estimation. In the case of MC-CDMA a number of options are available, and the ap- propriate choice of pilot symbols has to be made.

Transmitting wideband pilot symbols produces several problems in uplink MC-CDMA. Firstly, since multi-user interference will degrade the channel estimation severely, each user needs to be allocated an individual time slot, heavily impacting spectral efficiency. Secondly, since each user transmits an individual pilot (compared to a single joint pilot for the downlink) the available signal power will be much lower.

A more effective method of channel estimation can be easily achieved if the delay spread of the channel is short and hence there is a strong correlation between channel CO- efficients in neighbouring channels. In these cases, pilots can be transmitted on a few caniers and the rest of the channel estimated by linear interpolation. A large number of users can be supported, transmitting their pilot symbols on different carriers. A time slot for all users to transmit pilot symbols can be allocated of several symbol lengths and each user can transmit several single carrier pilot symbols on different frequencies providing sufficient information to estimate the channel. Figure 3 shows the structure of pilots transmitted in a 16 used16 canier system with the time and

Figure 3: Structure of Pilot Symbol Time Slot for Uplink MC- CDMA.

Simulations of an uplink MC-CDMA system using this channel estimation method were performed. The specifi- cation of the system chosen is a 64 carrier system based on a 20 MHz sampling rate with symbol lengths of 80 samples including a 16 sample cyclic-prefix to compen- sate for the multipath and asynchronism. This produces a 250 kHz symbol rate. The data were divided into blocks of 40 symbols, of which 8 are pilots. Only 48 of the 64 caniers are used to cany data in a similar way to the IEEE 802.1 I and HIPERLAW2 OFDM wireless local area net- work standards [9. 101. With QPSK modulation on the data symbols this produces a s ystem which will have a spectral efficiency of 1 bitsMHz with 40 active users, and a 48 user spectral efficiency of 1.2 bits/dHz. Figure 4 shows the bit error performance for SIC and channel matched filter (MF) receivers, in 3 tap Rayleigh fading channels.

1 I

- - - *- - - .,

Figure 4: Performance of Uplink MC-CDMA System in Rayleigh Fnding Channels.

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4 S E R I A L IMPLEMENTATION OF SIC

In a quasi-synchronous uplink MC-CDMA system, the receiver operates as shown in figure 5. Firstly, the guard period of the signal is removed. The remaining signals are passed through an FFT. At the FFT output, the receiver re- covers the kth user’s signal by multiplying each carrier by the complex conjugate of the corresponding channel estimate for user k. The output of this operation is then multi- plied by the chip of the kth user’s spreading code that cor- responds to the given carrier. The results from all carriers are finally summed to yield a single decision variable for user k, which can be given as:

d k ) o = R(k, k ) r ( k ) + R(i, k ) z ( i ) -+ g(k) (1) i f k

where z ( i ) represents user a’s data bit and ~ ( k ) the addi- tive Gaussian noise after channel matched filtering. The !V * N matrix R represents the cross-correlation matrix between the users after the channel matched filtering and despreading operations have been applied. The notation R(i, k) denotes the ith row and kth column of this matrix.

-hc. I

Figure 5 : Structure of rhe Receiver Circuit.

In the decision statistic ordered SIC algorithm, the user with the largest (in magnitude) value for y(maz)o is decoded first. where mar denotes the index of the user with the largest magnitude decision statistic. This means that a hard decision for that user’s transmitted data bit z(mar) is now available. Thus, the interference caused by that user to all other users may be reconstructed. For a given user k, the interference caused by user m a r to user k can be calculated as R(mar, k)z (maz) , where z (mar ) is obtained as the receiver’s hard decision for this transmitted data bit. This interference term is then subtracted from the decision variable of user k , y(k)o , to form a new decision statistic y(k) l . This interference cancellation process is repeated for all other users, who have yet to be detected. Having removed the interference from user mar, it is now possible to re-order the decision statistics of the remaining undetected users, g(k) 1, to find the one who now has the largest mng- nitudc decision statistic. This process is repeated until the data from dl users are decoded.

Figure 6 shows an architecture for this based on a single cancellation (addition/subtraction) circuit, which is switched by the sign of the data value being cancelled. The

circuit also computes the absolute value of the new decision statistic and compares this with the existing maximum value at that stage. During the initial cycle, no cancellation is made, but comparisons are used to determine which user’s decision statistic has the maximum absolute ‘value. In the subsequent cycles, the operation:

is performed, and the new maximum decision statistic is computed. In this equation mu2 denotes the index of the user with the largest magnitude decision statistic from the last cycle.

Figure 6: Serial Architecture for SIC.

To fully compute all user’s data symbols requires N’ clock cycles. If a QPSK 48 user system is considered this requires more than 9000 cycles per symbol. A symbol rate of 2.5 x lo5 symbolds would require a clock rate of over 2 GHz. The circuit was synthesised using Verilog and .35p CMOS library. Using this technology a clock rate of less than 100 MHz was achievable. Assuming a symbol rate of 2.5 x lo5 symbolds. 20 BPSK or 10 QPSK users could be supported. Obviously a higher clock rate can be obtained by moving to a higher power technology, but the paralleli- sation of the algorithm also needs to be considered.

5 PARALLEL IMPLEMENTATION OF SIC

Figure 7 shows a parallel architecture for SIC implementation for 4 users. This is not parallel interference cancellation as only one user is cancelled at a time, however the cancellation is applied to all undetected users simulta- neously, and the comparisons made to determine the largest magnitude decision statistic are all performed within one clock cycle. This reduces the time to process the symbols to N cycles (2N for QPSK. if each data bit is treated indepen- dently). Therefore to support 48 QPSK users at 2.5 x lo5 symbolds (0.5 Mbit/s) would only require a clock rate of 24 MHz which is easily achievable in low power CMOS hardware.

The parallel SIC circuit was simulated and rested using Verilog for a 48 QPSK (or 96 BPSK) users. A 12-bit word length was assumed. This was then synthesised using a .R5p CMOS library. producing ;I circuit with a total area

Implementation Of A SIC Based MC-CDMA Base Station Receiver

I I I I - - - I I I I - - - - Figure 7 : Parallel Architecture for SIC.

equivalent to 61636 two input gates and this was validated showing that it could operate at a clock rate of 25 MHz. The power consumption of this circuit was 251 mW for a full load of 48 QPSK users, given typical test data. When a smaller number of users’ signals are being received, the power consumption will obviously be less.

6 CIRCUIT IMPLEMENTATION AND ANALY- SIS

The SIC circuit was incorporated into a full baseband receiver circuit, incorporating most of the components required to produce the uncoded output. Figure 5 shows the structure of the receiver circuit, incorporating the main ele- ments: F’FT, channel estimation, channel matched filtering and interference cancellation.

For this circuit, a fixed packet format was chosen for data transmission. The transmitted signals were assumed to be quasi-synchronous, with all users attempting to ensure that their signals arrive at the base station at the cor- rect time. A packet length of 160 symbols was chosen. As- suming a 20 MHz sample rate with each symbol being 80 samples long (64 samples from IF‘FT + 16 sample cyclic- prefix), this gives a block length of 640~s. 12 pilot symbols are transmitted in the middle of the packet with 74 data symbols transmitted either side.

The circuit requires 4 major processing operations. For the FFT, the processing requirement is over 250,000 64- point FIT’S per second, requiring over 96 million multiplications per second. This was implemented using a 6-stage pipelined architecture, with each stage performing a radix- 2 FFT operation. This circuit could provide the required processing if clocked at 17 MHz or above.

The channel estimation circuit performs three main sub-tasks. It first has to extract the pilot symbols for each of the users from the 12 demodulated data symbols from the FFT. Interpolation is then applied to obtain full channel estimates. Finally the cross-correlation matrix R needs to be calculated. With 48 users, this requires the cross correlation of 48 complex vectors with 48 complex vectors all

of length 48. Requiring 963 multiplications in 6 4 0 p or 1.3 billion multiplications per second. By taking advan- tage of the symmetries in the cross-correlation matrix, this number can be halved. By restricting the system somewhat a much more drastic reduction can be made. Since many users may require higher bit rates, and could be using multiple codes, it was assumed that a maximum of 24 different users could use the system. This reduces the number of cross-correlation multiplications by a factor of 8 to ap- proximately 80 million multiplications per second. Doing 4 multiplications in parallel allows the circuit to run at 20 MHz.

The large computation times involved means that the circuits must operate as a pipeline. There are three major operations going on in parallel. The FFT operation produces a block of data and pilot symbols. The next stage is the channel estimation and computation of R. Finally with the channel and cross-correlation information available, the channel matched filtering and interference cancellation can be applied to the data symbols. The channel matched filter block consists of 24 complex filters which can correlate using 2 codes - with each filter producing 2 QPSK symbol estimates. These are’then fed into the successive interference cancellation block to produce better data estimates.

The circuit was simulated in Verilog and the main computational components were synthesised and power simulations performed. Table 1 shows the area required and power consumed by these components using .35p CMOS, with the area being the equivalent number of 2 input gates and the power shown in mW. These results only show the power consumed in the computational blocks and do not incorporate the power which would be consumed in the as- sociated memory. The total power consumed will also be affected by the proportion of the total time each circuit is required to be on; the FFT needs to be on for only 77% of the time and the cross-correlation calculation for only 90% of the time. The total circuit area comes out at over 250000 gates with total power consumption around 2 W.

Table I : Power and Area of Main Circuit Components.

Sub-Circu it Area (no. gates) PowerImW FFr 51533 233 Cross-Correlation 11337 163 Marched Filtering 130678 1335 SIC 61636 25 I

The bit error performance of the register transfer level Verilog circuit design was also investigated to compare the 12-bit fixed point arithmetic with floating point simulations. Figure 8 compares the bit error performance for 16 and 48 QPSK users. Clearly there is some discrepancy between the two results, with the finite word length causing additional errors, and giving performance about 2d B worse than the floating point simulation, although some of this

Vol. 13, No. 5 , September-October2002 5 17

may be due to different pilot symbol structures in the two systems. A change to a 16-bit word length could improve things although at a cost of increasing the circuit size and power consumption by a quarter.

Manuscript received on April Sth. 2002.

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I

Figure 8: Bit Ermr Performance of Verilog Model.

7 CONCLUSIONS

The implementation of a successive interference cancellation base station MC-CDMA receiver has been investigated. Verilog implementation and synthesis using a CMOS library show that using current technology, it is quite easy to support 24 users at I Mbitfs in a 20 MHz bandwidth system. Using a parallel algorithm, the decision statistic ordered SIC can be implemented without causing excessive processing delays .

ACKNOWLEDGMENT

This work was funded by the U.K. Engineering and Physical Sciences Research Council (EPSRC) grant number G W 98091 for research into Multi-Carrier CDMA.

AC. McCormick, IS. Thompson, P.M. Grant. T. Arslan, A.T. Erdogan

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Implementation of a sic based MC-CDMA base station receiver