IMPLEMENTATION OF A FIXED HARDWARE STRUCTURE USED FOR BUILT-IN GENERATION OF FUNCTIONAL BROADSIDE TESTS

8/10/2019 IMPLEMENTATION OF A FIXED HARDWARE STRUCTURE USED FOR BUILT-IN GENERATION OF FUNCTIONAL BROADSI

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INTERNATIONAL JOURNAL

OF PROFESSIONAL ENGINEERING STUDIES Volume IV/Issue3/OCT2014

IJPRES

IMPLEMENTATION OF A FIXED

HARDWARE STRUCTURE USED FOR

BUILT-IN GENERATION OF FUNCTIONALBROADSIDE TESTS

N.LAKSHMI PARVATHI(1)

U.V.RATNA KUMARI(2)

M.Tech, Computers And Communications, Jntu College Of Engineering, Kakinada(1)

Assistant Professor, Department Of Ece, Jntu College Of Engineering, Kakinada(2)

Email:[email protected], [email protected]

ABSTRACT Functional broadside tests were defined as

broadside tests that detect target faults using reachable statesthat are only states that the circuit can visit during functionaloperation. During these tests power dissipation doesntexceed that possible during functional operation. Built-ingeneration of functional broadside tests is done using a fixedhardware structure to achieve higher fault coverage. Thestructure is added to a given circuit that needs to be tested.On-chip test generation avoids the need to compute reachablestates offline by generating the reachable states during testapplication.

Index TermsFunctional Broadside Tests, reachable

states, Built-In Test generation, fault coverage

INTRODUCTION

Testing a circuit is necessary to make sure that all designerrors have been fixed. Over testing occurs due to non-functional operation conditions created by unreachable scan-in states. Tests applied under nonfunctional operationconditions, which are made possible by scanning in anunreachable state, may lead to unnecessary yield loss. Slow

paths that cannot be sensitized may cause circuit to fail andwhen current demands higher than possible cause voltagedrop leading to the circuit failure.

Functional broadside tests allow only reachable states asscan-in states. As broadside tests are two pattern tests, thecircuit undergoes state transitions that are possible duringfunctional operations. Delay faults can effect functionaloperation and current demands dont exceed the limit. Thisavoids overtesting. Power dissipation also dont exceed that

possible.Functional and pseudo functional scan based tests compute

reachable states offline. Pseudo functional tests use functionalconstraints to avoid arbitrary states. These tests are notsufficient for avoiding unreachable states. Delay fault

coverage in pseudo functional scan based tests and

arbitrary broadside tests is higher than the fault coverage infunctional broadside tests due to the fact that functional

broadside tests doesnt allow unreachable states where asother methods allow them. Moreover, the need for higherfault coverage is the one of the reasons to cause overtestingand power dissipation exceed more than possible duringfunctional operation.

In the proposed method we use the on-chip generation offunctional broadside tests where on-chip generation has theadvantages of speed and reduces test data volume. On-chipgeneration doesnt impose any constraints on delay faultsas in pseudo functional scan based tests. Functional

broadside tests ensure that scan-in state is only a reachable

state. The reachable states are generated during testapplication by the circuit. This avoids computing themoffline.

If a primary input sequence A is applied in functionalmode starting from a reachable state, all the states traversedunder A are reachable states. Any one of these states isused as initial state. For the detection for set of faults F weneed |F| different reachable states. Typically it is smallfraction of A. So, primary input sequence A doesnt need totake the circuit through all reachable states but only anumber relative to |F| in order to be effective.

LFSR DESIGN

The hardware used for generating a primary input sequenceconsists of a Linear Feedback Shift Register and a smallnumber of gates. Gates are used to modify the randomsequence in order to avoid repeated synchronization that isthe sequence takes the circuit to repeat the same or similarstates. In addition to this, a single gate is used fordetermining the tests to be applied based on primary inputsequence.

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FIG 1.On-chip generation of A

TABLE 1

LFSR SEQUENCE

The fixed hardware structure needs to be tailored to the

given circuit through these parameters.1)

The number of LFSR bits.2)

Seeds for the LFSR to generate different primaryinput sequences and several subsets of tests.

3)

The length of primary input sequence.4) The specific gates used to modify LFSR sequence

into primary input sequence A.5) Specific gates for selecting the type of functional

broadside tests that will be applied to the circuitbased on primary input sequence A.

The on-chip test generation hardware is based on theone described in [7]. It differs from this paper hardwarein following ways.

1)

In [7], a circuit with n primary inputs and aparameter mod, the LFSR used for producing A hasn + mod bits. n left most bits are used for driving the

primary input sequence and mod right most bits areused for modifying random sequence in order toavoid repeated synchronization. The same mod rightmost bits are used for modifying all primary inputsand this may lead to modifying the primary inputs tosame values and some primary inputs receive shifted

or by initializing sequence. S(u) is state of circuit at time u for

2) In [7] for selecting the tests that applied to thecircuit based on A, a large multiplexer and asignificant number of gate is used. In this paper asingle gate is used for selecting the tests by fixingthe gate in advance and make sure that all primaryinputs fit with the preselected gate.

3)

In [7] the lengths of primary inputs are varied tocontrol the number of tests. In our design primaryinputs are of uniform length, this make theapplication process uniform.

This paper design is independent of the number ofsequences used. Sequences differ only in seeds of theLFSR. The seeds can be stored on-chip, or a seed can

be scanned in together with the initial state of thecircuit before the application of every primary inputsequence. This paper solely focuses on application oninput sequence, so for output testing an outputcompactor such as Multiple Input Shift Register(MISR) is assumed.

If a circuit under test is embedded in a larger design,the primary inputs may drive other logic blocks insame design and addition with external inputs, theymay drive circuit under test. The primary outputs maydrive some logic blocks or primary output is the outputof the design. To avoid these complexities we assumethat the primary sequence is of any combination ofvalues. Functional constraints on primary inputsequence are accommodated in following ways.1)

The logic used for generating primary inputsequence is extended to impose some functionalconstraints.

2)

A separate logic block is used for modifying A to

satisfy functional constraints.3) Placing the on-chip test generation hardware for a

logic block on the inputs of the logic blocksdriving it can create some of the functionalconstraints for the block.

PROPOSED METHOD FOR ON-CHIPGENERATION OF FUNCTIONAL BROADSIDETESTS

In this paper the circuit is initialized to a known statebefore functional operation is assumed. Initialization isachieved by applying a synchronizing sequence or by

hardware reset or by combination of both. The initialstate is denoted by Sr. As Sr is the initial state offunctional operation, it is a reachable state. In the setof reachable states produced by Sr consists of everystate Si,there exist a primary input sequence that takesthe circuit from Sr toSi. Since Si is generated from Sr,Siis a reachable state.

On-chip generation for reachable states is also done byusing Srand primary input sequence A= a(0)a(1)a(L-1) of length L. Circuit is initialized using scan in operation

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0uL and S(0)= Sr. Every state S(u) can be used as initialstate for functional broadside test (S(u), a1, a2) where S(u) is ascan in state and a1and a2are primary input vectors applied toS(u) using a slow and fast clocks respectively. Everysequence of length two of A defines a functional broadsidetest, t(u)=(S(u),a(u),a(u+1)). By using these vectors adifferent source for producing primary vectors is avoided.For producing primary input sequence ISCAS 89 S27

benchmark circuit is used. For initial state Sr=000Primary input sequence is obtained. For every time unit uthere is S(u) and primary input vector is generated. Table 1shows S(u) and a(u) for every u. Functional broadside testst(0)=(000,1001,1110),t(1)=(010,1110,0010),.t(14)=(101,1111,1110).For detecting faults circuit is placed on initial state and testsare generated using primary input sequence.

Fig 2: S27

TABLE 2PRIMARY INPUT SEQUENCE FOR S27

The faults are detected in following ways1)

An output vector z(u+1) in response to s(u+1) iscalculated and if it is different from the expectedoutput vector.

2)

If final state s(u+2) is different from expected fault

free vector.z(u+1) and s(u+2) is captured by output compactor, MISR.But the tests t(u) and t(u+1) may overlap because for t(u)s(u+1) is generated and for t(u+1) also s(u+1) is generated.For application of both tests we need special hardware.Thus to avoid the hardware we use non overlapping testssuch that in the form {t(u0),t(u1),t(uk-1)} whereui+1


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Fig: On chip test selection.For generating LFSR sequence we need seeds for LFSR.

Selecting the seeds depend up on the parameters L, M, modand sel. Test data compression technique is used for selectingthe seeds for LFSR. The parameters used here also havelimitations. Parameter mod tells the probability of avoidingrepeated synchronization. Increasing L and d and can

potentially increase the fault coverage. Increasing L increasesthe number of available tests, and increasing d reduces thedependencies between the values of the primary inputs.Increasing sel can potentially decrease the fault coveragesince it decreases the number of tests that will be applied tothe circuit.

RESULTS

The functional broadside tests for various benchmark circuitsare evaluated.

TABLEFUCTIONAL TEST SEQUENCES

From above table it is known that the proposed method offunctional broadside tests achieve high fault coverage thanfunctional test sequences.

CONCLUSION

A fixed and simple hardware structure is implemented toconduct functional broadside tests on-chip. The hardware isimplemented using the primary input sequence to a circuitwith known reachable state to achieve additional reachablestates. Random sequences are chosen to avoid repeatedsynchronization. Two pattern tests are done to achieve higherfault coverage. The parameters that are tailored the circuit

under test to conduct functional broadside tests on-chip arelength of LFSR, seeds for LFSR, length of primary sequence,gates for modifying the sequence and gates for selecting tests

based on primary input sequence.

REFERENCES

[1] J. Rearick, Too much delay fault coverage is a bad

thing, in Proc. Int. Test Conf., 2001, pp. 624633.

Test Conf., 2003, pp. 10981104.

[2] I. Pomeranz and S. M. Reddy, Generation of

functional broadside testsfor transition faults,IEEE Trans.

Comput.-Aided Design Integr. Circuits Syst., vol. 25, no.

10, pp. 22072218, Oct. 2006.

[3] J. Savir and S. Patil, Broad-side delay test, IEEE

Trans. Comput.- Aided Design Integr. Circuits Syst., vol.

13, no. 8, pp. 10571064, Aug.1994.

[4] Z. Zhang, S.M. Reddy, and I. Pomeranz, On

generating pseudo-functional delay fault tests for scan

designs, in Proc. Int. Symp. Defect Fault Toler. VLSI

Syst., 2005, pp. 398405.

[5] I. Pomeranz and S. M. Reddy, On reset based

functional broadside tests, in Proc. Design Autom. TestEuro. Conf., 2010, pp. 14381443.

[6] Y.-C. Lin, F. Lu, and K.-T. Cheng, Pseudofunctional

testing, IEEE Trans. Comput.-Aided Design Integr.

Circuits Syst., pp. 15351546,2006.

[7] I. Pomeranz, Built-in generation of functional

broadside tests, presented at the Design Autom. Test Euro.

Conf., Grenoble, France, 2011.

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IMPLEMENTATION OF A FIXED HARDWARE STRUCTURE USED FOR BUILT-IN GENERATION OF FUNCTIONAL BROADSIDE TESTS