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phys. stat. sol. (c) 5, No. 1, 47–51 (2008) / DOI 10.1002/pssc.200776574

Impact of strain on scaling ofDouble Gate nanoMOSFETs usingNEGF approach

A. Martinez1,*, K. Kalna1, A. Svizhenko2, M. P. Anantram3, J. R. Barker1, and A. Asenov1

1 Device Modelling Group, Dept. Electronics & Electrical Engineering, University of Glasgow, Glasgow G12 8LT, United Kingdom2 Silvaco International Inc., Santa Clara, USA3 Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada

Received 10 July 2007, revised 15 August 2007, accepted 28 August 2007Published online

PACS 71.70.Fk, 85.30.De, 85.30.Tv, 85.35.-p

∗ Corresponding author: e-mail antonio@elec.gla.ac.uk, Phone: +44-141-330-4792, Fax: +44-141-330-4907

The effect of biaxial strain on double gate (DG)nanoscaled MOSFET with channel lengths in thenanometre range is investigated using Non-EquilibriumGreen’s Functions (NEGF) simulations. The NEGF sim-ulations are fully 2D in order to accurately evaluate theeffects of strain in strongly confined channels. Startingwith a 14 nm gate length DG MOSFET with a corre-sponding body thickness of 9 nm we scale the transistorsto gate lengths of 10, 6 and 4 nm and body thicknesses

of 6.1, 2.6 and 1.3 nm, respectively. The simulated ID-VG characteristics show 11% improvement in the on-current for the 14 nm gate length transistor due to the∆ valley splitting. This improvement in the on-current isdue to separate contributions from the 2 fold and 4 foldvalleys to the carrier transport. However, in the devicewith an extreme body thickness of 1.3 nm the strain hasno impact on its performance because the strong confine-ment itself produces a large valley splitting.

1 Introduction Tensile biaxial strain in the channelenhances the performance of n-channel Si bulk MOSFETs[1,2]. The effect of strain produced by initial growth onan unstrained Si1−yGey buffer by SOI bonding [3] can bememorized in a thin Si layer. Double gate (DG) MOSFETcan be then fabricated in this tensile biaxially strained Silayer. The tensile strain lowers the energy of the two ∆valleys perpendicular (∆⊥) to the initial Si/Si1−yGey in-terface [4,5]. These two fold degenerate valleys have a loweffective mass in the direction of transport which resultsin a higher carrier mobility. Figure 1 illustrates the impactof the applied strain on the ∆ valleys in the case of 〈100〉surface orientation considered in this work. The shift in theconduction band minimum of the two fold energy ∆⊥ andfour fold ∆‖ valleys and corresponding valleys splittingare shown in Fig. 2 [4] as a function of Ge content in thewafer. Monte Carlo studies [6] show that the improvementin the carrier mobility in transport direction is mainly dueto the increased population of electrons in the ∆⊥ valleys.

23 October 2007

© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

-valleys

||,L-valleys

kx

kz

ky

||

E~%Ge

Stress Effect

||,T-valleys

Gate

Gate

Figure 1 Schematic view of the simulated DG MOSFET andthe material orientation under the biaxial tensile stress along thechannel plane.

48 A. Martinez et al.: Impact of strain on scaling of double gate nanoMOSFETs using NEGF approach

© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim www.pss-c.com

The situation becomes more complex in ultra-thin bodydouble gate (DG) transistors because the confinement al-ready produces a similar splitting of ∆ valleys [7]. The ∆‖valleys are shifted upwards relative to the ∆⊥ valleys be-cause of a lower effective mass in the confinement direc-tion. If this energy shift is of the order of several kBT , thenthe ∆‖ valleys will not contribute to the transport in thevery thin Si DG devices. Therefore, the strain in ultra-thinbody DG MOSFETs will deliver a less improvement in theperformance compare to the thick channel device. We aimto estimate at which body thickness the effect of the strainis masked by the confinement effects and ceases to deliverthe improvement in the device performance.

In this work, we have employed fully 2D (in a realspace) Non-Equilibrium Green’s Functions (NEGF) sim-ulations in order to predict the effect of the biaxial tensilestrain on the electron transport in the DG MOSFET witha strongly confined channel. The 2D real-space quantummechanical simulations are essential to accurately deter-mine the combined impact of confinement and strain inthin body devices which is may be masked when using only1D simulation approach [8]. The NEGF approach is one ofthe ways to implement the Landauer-Buttiker (LB) formal-ism [9] widely used to model small nanotransistors [10].The previous ensemble Monte Carlo simulations which caninclude all relevant scattering mechanisms predict that theballistic ratio increases from 38% to nearly 80% when thegate length of DG MOSFET is scaled from 90 nm to 15 nm[11]. Difficulties to include the quantum confinement andparticularly the source-to-drain tunnelling into the ensem-ble Monte Carlo approach make the NEGF simulations asuitable tool for modelling of the transport in nanoscaledtransistors in ballistic regime [12]. We have distinguishedtwo main effects arising from the valleys splitting in theNEGF formalism: (i) the reduction in density of states whichrises the Fermi level and the injection from the source re-gion; (ii) and the low mass of the ∆⊥ valleys which in-creases the tunnelling current.

2 Transport model According to the simplified rep-resentation of the LB formalism [9] the current in a smalltwo terminal device is proportional to the product of thequantum transmission and the difference between the Fermilevel of the two terminals. The NEGF approach allows theimplementation of the LB formalism to calculate the cur-rent and electron density [13]. The current and electrondensity are computed from the statistical propagator G<

[13], which is calculated from the following equations [10]:

G< =(E − H − ΣR

)−1Σ<

[(E − H − ΣR

)−1]†

(1)

where H is the Hamiltonian consisting of the kinetic andpotential terms [−�

2∇2/(2m)+V ], ΣR is the self-energyof contacts and Σ< is the inscattering self-energy. The dag-ger † represents the hermitian conjugate. The solution isself-consistently coupled to Poisson equation solved by ap-plying Neumann boundary conditions in the source/drain

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

1.2

Content of Ge (y) in Si1-y

Gey layer

Ene

rgy

[eV

]

Perpendicular valley

Transversal valley

Valley splitting

Figure 2 The change in energy for ∆⊥ and ∆‖ valleys and theirseparation as a function of Ge content in the SiGe buffer layer.

-20 -10 0 10 20-15

-10

-5

0

5

10

15

X-dimension [nm]

Y-d

imen

sion

[nm

] Oxide

Source DrainChannel

Oxide Oxide

OxideMetal

Metal

Figure 3 2D domain of DG MOSFETs as considered in theNEGF simulator.

and Dirichlet boundary condition at the gate contact. TheHamiltonian H is written using the mass effective approx-imation [13]. Only the lowest six ∆ valleys have been con-sidered in the description of the Si band structure as in-dicated in Fig. 1. The valleys are anisotropic consideringthe parabolic dispersion law. A non-parabolic dispersionwould require more than nearest neighbour coupling in theHamiltonian which would make the Hamiltonian more den-se. Even a second neighbour coupling would lead to a mod-ification in the recursive algorithm [13] resulting in increasein computational time.

The device structure considered in our 2D NEGF simu-lator is schematically illustrated in Fig. 3. The source/draindoping is assumed to be as high as 2 × 1020 cm−3 whilethe channel is undoped.

phys. stat. sol. (c) 5, No. 1 (2008) 49

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0.0 0.3 0.6 0.9 1.2101

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103

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0

5

10

15

2014 nm gate

I D [µ

A/µm

]

VG [V]

Strained Unstrained

VD=0.8 V

I D [m

A/µ

m]

Figure 4 ID-VG characteristics for the 14 nm DG MOSFETswith a body thickness of 9 nm obtained for a device with no strainin the channel compared with the results for a strained Si chan-nel transistor. The strained Si channel device is assumed to beobtained on the Si0.7Ge0.3 buffer layer.

0.0 0.3 0.6 0.9 1.2101

102

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15

20

2510 nm gate

I D [µ

A/µm

]

VG [V]

Strained Unstrained

VD=0.8 V

I D [m

A/µ

m]

Figure 5 ID-VG characteristics for the 10 nm DG MOSFETsfor unstrained and strained material in the channel. The transis-tor with a strained Si channel is assumed to be obtained on theSi0.7Ge0.3 buffer layer.

3 The effect of strain The ID-VG characteristicsof the DG MOSFETs with gate lengths of 14, 10, 6 and4 nm; body widths of 9, 3.2, 2.6 and 1.3 nm; and ox-ide thicknesses of 0.7, 0.6, 0.5 and 0.5 nm, respectively,are presented in Figs. 4, 5, 6 and 7. The figures comparetransistors with a strained channel which have been ini-tially grown on the unstrained Si0.7Ge0.3 buffer with un-strained devices. The change in the electron affinity dueto strain and the corresponding threshold voltage shift arenot included in the simulations. There is additional con-finement threshold voltage shift in the strained devices dueto the valley splitting. For the 14, 10, 6 and 4 nm gatelength strained channels these additional shifts are 30, 30,10 and 0 mV, respectively. Figures 8 and 9 show the po-

0.0 0.3 0.6 0.9100

101

102

103

104

5

10

6 nm gate

I D [µ

A/µm

]

VG [V]

Strained Unstrained

VD=0.8 V I D [m

A/µ

m]

Figure 6 ID-VG characteristics for the 6 nm DG MOSFETs us-ing the unstrained and strained Si channel. The strained Si chan-nel has been prepared on the Si0.7Ge0.3 buffer layer.

0.0 0.3 0.6 0.910-2

10-1

100

101

102

103

2

4

6

4 nm gate

I D [µ

A/µm

]

VG [V]

Strained Unstrained

VD=0.8 V I D [m

A/µ

m]

Figure 7 ID-VG characteristics for the 4 nm DG MOSFETs,again for the both unstrained and strained Si channel. The strainin Si channel has been obtained using Si0.7Ge0.3 buffer layer.

tential barrier in the strained and unstrained channel tran-sistors. Fermi levels at the source have been aligned in or-der to illustrate a smaller energy barrier that the electronsin strained transistors face compared to that in unstrainedchannel device. This causes the threshold shift. The largerenergy difference between Fermi level and the potential inthe source end of the strained device indicates a higherpopulation of ∆⊥ valley compared to the unstrained de-vice.

The source-to-drain tunnelling current in the 14 nmstrained device increases due to a smaller effective massof ∆⊥ valley which has the only contribution to the trans-mission until an energy of 0.4 eV as shown in Fig. 10. Notethat the ∆‖ valley is shifted upwards by 0.2 eV in respectto the ∆⊥ valley. Since the transmission in the strained de-vice starts at the energy of 0.16 eV while the height of thebarrier in Fig. 8 is 0.196 eV, the tunnelling current occurs

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−20 −10 0 10 20−1.5

−1

−0.5

0

0.5

y (nm)

Pot

entia

l Ene

rgy

(eV

)

StrainedUnstrainedFermi level(S)

Figure 8 Potential profile in the 14 nm DG MOSFETs atVD=0.8 V and a low gate bias of 0.05 V showing lowering ofthe potential barrier in the strained channel transistor. Fermi en-ergy at the source (S) is also indicated.

−20 −10 0 10 20−1.5

−1

−0.5

0

0.5

y (nm)

Pot

entia

l Ene

rgy

(eV

)

StrainedUnstrainedFermi level(S)

Figure 9 Potential profile in the 14 nm DG MOSFETs at VD =0.8 V and a high gate bias of 2.0 V showing a presence of thepotential barrier in the strained channel transistor as comparedto the unstrained device whose potential barrier already disap-peared. Fermi energy at the source (S) is again indicated.

in an larger energy range of 0.036 eV as compared to just0.01 eV range for the unstrained device. A fast stepping ofthe transmission coefficient for ∆⊥ can be observed due toa small subband energy separation which is the result of alarger mass in the confinement direction.

The situation is dramatically changed in the 4 nm gatelength DG MOSFET with a body thickness of 1.3 nm. Theeffect of the confinement is so strong that it suppresses anyimpact of the strain in the channel. The energy shift be-tween the valleys due to the confinement is 1.0 eV as illus-trated in transmission coefficients in Fig. 11. The ∆⊥ val-leys in the strained and unstrained devices have the same

0.0 0.1 0.2 0.3 0.4 0.5 0.60

2

4

6

8

10Strained Unstrained

∆⊥ valley

∆||,L

valley

∆||,T

valley

Tra

nsm

issio

n c

oe

ffic

ien

t

Energy [eV]

VG=0.05 V

VD=0.8 V

Figure 10 Transmission coefficient in the 14 nm DG MOSFETsat VD=0.8 V and a low gate bias of 0.05 V . The behaviour ofcoefficients for each of valleys in transistors with a no strain inthe channel and strained Si channel obtained on the Si0.7Ge0.3

buffer layer is compared.

0.0 0.5 1.0 1.50

1

2Strained Unstrained

∆⊥ valley

∆||,L

valley

∆||,T

valley

Tra

nsm

issio

n c

oe

ffic

ien

t

Energy [eV]

VG=0.05 V

VD=0.8 V

Figure 11 Transmission coefficient in the 4 nm DG MOSFETsat VD=0.8 V and a low gate bias of 0.05 V . The behaviour ofcoefficients for each of valleys in transistors with a no strain inthe channel and strained Si channel obtained on the Si0.7Ge0.3

buffer layer is compared.

transmissions starting at the same energy and the impact ofthe remaining valleys is spurious.

Figures 4 and 5 show that the strain in a channel of the14 nm and 10 nm gate length DG transistors improves theon-current by 11% and 16%, respectively, at VG = 1.25 V(at the beginning of saturation). Note that the 10 nm gatelength device has a better electrostatics and therefore thesource/drain barrier disappears at a lower VG as comparedto the 14 nm gate length DG transistor. There is no effectof the strain in the subthreshold region of the 6 nm gatelength DG MOSFET because of the 0.25 eV energy sep-aration between the ∆⊥ and the both ∆‖ valleys due toconfinement. When the applied bias increases above 0.9 V

50 A. Martinez et al.: Impact of strain on scaling of double gate nanoMOSFETs using NEGF approach

phys. stat. sol. (c) 5, No. 1 (2008) 51

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0.0 0.3 0.6 0.9 1.2101

102

103

104

5

10

15

20

14 nm gate

I D [µ

A/µm

]

VG [V]

∆⊥ valley

∆||,L valley

∆||,T valley

VD=0.8 V I D [m

A/µ

m]

Figure 12 ID-VG characteristics for the 14 nm DG MOSFETsobtained from each of separate valleys, the ∆⊥, the ∆‖,T andthe ∆‖,L. There is no applied strain on material in the transistorchannel.

(well above the threshold) electrons start to populate theupper ∆‖ valleys and one observes the increase of 17% inthe drain current for the strained channel transistor. For the4 nm gate length device, the effect of strain is negligibleeven at high gate biases because of the 1 eV energy sepa-ration between the valleys.

In order to understand the reason for a such small im-provement in the performance in 14 nm and 10 nm gatelength devices, we have carried out simulations of devicescontaining separate ∆ valleys, which can be oriented as∆⊥, or one of the two ∆‖,L and ∆‖,T valleys (with thelongitudinal or transversal mass in the transport direction).Fig. 12 shows the ID-VG characteristics (at the same VD =0.8 V) of the three single valley devices. The device withthe ∆⊥ valley has similar ID-VG characteristics than thedevice with a ∆‖ valley with transversal mass in the trans-port direction. Furthermore, the device with a ∆‖ valleyand longitudinal mass in the transport direction have 50%lower current as compared with the other two devices. Amaximum estimate based on the on-current contributionsof the individual valley devices predicts an improvement of30%. This analysis gives a maximum possible gain in theon-current and neglects the misalignment of the valleys at9 nm body thickness which is about 0.5kBT . Note that thesimulations using all the valleys produce an improvementof 11% in the on-current at VG = 1.25 V.

4 Conclusion The effect of strain and quantum con-finement acting together have been investigated in DG MOS-FETs using 2D NEGF simulations. The ID-VG characteris-tics of devices with gate lengths of 14, 10, 6, and 4 nm andcorresponding body thicknesses of 9, 6.1, 2.6 and 1.3 nm,respectively, have been obtained in a ballistic limit [10]at the both low and high drain voltages. The 14 nm gatelength transistor with a strained Si channel (grown on theSi0.7Ge0.3 buffer) can deliver 11% improvement in the on-

in the channel. When the body thickness of the 14 nmgate length DG MOSFET is reduced from 9 nm to 6.1 and2.6 nm in the process of scaling the effect of the strain stillimproves the on-current. However, when the body thick-ness is reduced to 1.3 nm in the 4 nm gate length transis-tor the effect of the strain is totally suppressed because thequantum confinement will separate the ∆⊥ valleys fromthe both ∆‖ valleys by approximately 1 eV. Therefore, thescaling of the body thickness below 3 nm in Si DG MOS-FETs becomes meaningless as also observed in Monte Carlodevice simulations [14].

Acknowledgements This work has been supported by EP-SRC under Grants No. GR/S80097/01 and EP/D070236/1.

References

[1] T. Ghani M. Armstrong, C. Auth, M. Bost, P. Charvat, G.Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B.Mclntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein,S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M.Bohr, IEDM Tech. Dig., pp. 978-981 (2003); M. L. Lee, E.A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochte-feld, J. Appl. Phys. 97(28), 011101 (2005).

[2] V. Aubrey-Fortuna, A. Bournel, P. Dolfus, and S. Galding-Restailleau, Semicond. Sci. Technol. 4, 422-428 (2006); F.M. Bufler and W. Fichtner, IEEE Trans. Electron Devices50, 278-284 (2003).

[3] D. V. Singh, J. W. Sleight, J. M. Hergenrother, Z. Ren, K. A.Jenkins, O. Dokumaci, L. Black, J. B. Chang, H. Nakayama,D. Chidambarrao, R. Venigalla, J. Pan, W. Natzle, B. L.Tessier, A. Nomura, J. A. Ott, M. Ieong, and W. Haensch,IEDM 2005 Tech. Dig., pp. 505-508 (2005).

[4] M. Rieger and P. Vogl, Phys. Rev. B 48, 14276-14287(1993).

[5] D. Rideau, M. Feraille, L. Ciampolini, M. Minondo, C. Tav-ernier, and H. Jaouen, Phys. Rev. B 74, 195208 (2006).

[6] M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K.Rim, J. Appl. Phys. 94, 1079-1095 (2003).

[7] T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S.Horiguchi, Y. Ono, Y. Takahashi, and K. Murase, IEEETrans. Electron Devices 50, 830-838 (2003).

[8] N. Barin, C. Fiegna, and E. Sangiorgi, in: Proc. 34th Eu-ropean Solid-State Device Res. Conf. (ESSDERC 2004),pp. 169-172.

[9] H. L. Engquist and P. W. Anderson, Phys. Rev. B 24, 1151-1154 (1981).

[10] S. Datta, Electronic Transport in Mesoscopic Systems(Cambridge Press, U. K., 1995).

[11] S. Eminente, D. Esseni, P. Palestri, C. Fiegna, L. Selmi, andE. Sangiorgi, IEEE Trans. Electron Devices 52, 2736-2743(2005).

[12] S. Jin, Y. J. Park, and H. S. Min, Proc. SISPAD 2006, editedby P. Oldiges and K. Mayaram (Monterey, USA, 2006), pp.35-38.

[13] A. Svizhenko, M. P. Anantram, T. R. Govindan, and B.Siegel, J. Appl. Phys. 91, 2343-2354 (2002).

[14] V. Sverdlov, S. E. Ungersboeck, and H. Kosina, IEEE Trans.Nanotechnology 6, 334-340 (2007).

current (VG = 1.25 V) at a high drain bias of 0.8 V whencompared to the equivalent gate length device with no strain