Impact of Reprocessing Technique on First Level

9000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com

Impact of Reprocessing Technique

on First Level Interconnects of Pb-

Free to SnPb Reballed Area Array

Flip Chip Devices

Joelle Arnold, Steph Gulbrandsen, Dr. Nathan BlattauIMAPS

9000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com2

o There’s no prize for longest title?

o Damn.

Wait, what?


o Impact of Reprocessing Technique on First Level Interconnects of Pb-Free to SnPb Reballed Area Array Flip Chip Devices

o Reballing: replacement of existing solder spheres with new solder spheres, with the purpose of changing the solder alloy

o Pb-Free to SnPb: Alloy change from a Pb-free alloy (such as SAC305) to eutectic SnPb

o Adoption of RoHS and other legislation to restrict use of lead has made it increasingly difficult to procure BGAs with SnPb solder balls

o High reliability applications that have not transitioned to a Pb-free assembly process are faced with a choice: custom order, reprocess, or adapt

o First Level Interconnects: Wire bonds or C4 bumps between the die and the interposer; should not be affected by reballing

A Little Background


o The risk of damage caused by reballing a commercial off-the-shelf (COTS) active flip chip with a SAC305 ball grid array (BGA) to SnPb eutectic solder balls was studiedo Five (5) different reballers were compared

o Test vehicle was an active flip chip device o Eight (8) differential port pairs with pull-up resistors

o Reballed components compared to one another and unreballed deviceso Path resistance across differential port pairso 2-dimensional x-ray microscopyo Acoustic microscopyo X-ray computer tomography (3-D x-ray)

o These studies indicated that no measureable damage was incurred by the reballing process, implying that reballed devices should function as well as non-reballed devices o Caveat: this statement does not include the impact to the solder joints themselves

Abstract


o Reballing is both ball removal and ball attach

o Ball removal melts off the pre-existing solder balls and prepares the solder pads for new solder balls

o Two types of techniques

o Ball attachment is the placement of new solder spheres on the pads and reflowing them to form an intermetallic bond

o All reballers studied use comparable methods for ball attach

Introduction: Reballing Techniques


o Two types of procedures for removal of solder spheres:

1. Melt the lead-free spheres with a hot implement (soldering iron) to remove the liquid solder by wick absorption

2. Dissolution of the lead-free spheres by touching them to a tin-lead molten solution (wave or fountain)

Introduction: Ball Removal Techniques


Dressed Pads Comparison

A B C

ED

Direct light source,

potential differences

between approaches

noted in strength of pink

reflectance (B) and size

of reflected ring light (E)


X-Ray Images After Ball Removal

VSC3312 flip-chip x-ray image with examples of key features indicated. Solder bumps (first level interconnects) - yellow circles. Plated through holes in component substrate - red arrows. Solder pads from which balls have been removed - blue dotted circles.

Dressed pads on VSC3312 flip chip; solder visible as radiopacity. Dark pads on left image indicate thicker coverage than faintly visible pads on right image.


o Ball placement techniques and tooling are widely considered trade secrets

o All reballers surveyed employ stencils to align new solder spheres with dressed pads

Introduction: Ball Placement


o Does reballing the second level interconnects (B) damage first level interconnects (A)?

Focus


o Vitesse VSC3312 crosspoint switch

o 196 I/O, 1.0mm pitch

o 15mm square package, 3mm die

Test Vehicle: Active Flip Chip


o Eight (8) input pair circuits

o Two 50Ω pull-up resistors between true and complement

o Manufacturer specifies 85Ω to 125Ω as acceptable range

Test Vehicle: Active Flip Chip


o Ten (10) flip chips sent to each reballero Instructed to perform ball removal as they normally would

o Removal of SAC305 sphereso Cleaning and dressing solder pads

o Instructed to simulate ball attach without applying spheres or pasteo Reflowo Cleaningo Bakeout

o Packages returned with no solder ballso Facilitate resistance probing

Sample Preparation


o Upon receipt, components reflowed to simulate assembly

Sample Preparation, cont.

SnPb Liquidus

SAC305 Liquidus

25

50

75

100

125

150

175

200

225

0 60 120 180 240 300 360 420 480 540 600 660 720 780

Te

mp

era

ture

(°C

)

Time (s)

Simulated Reflow of Active Flip Chip Components

Reballer A

Reballer B

Reballer C

Reballer D

Reballer E


o Five reballers employing distinct techniques were audited during reballing of ball grid arrayso Reballers identified as A, B, C, D, & E o Reballers B and D remove solder balls with Technique 1 (soldering

iron)o Reballers A, C, and E remove solder balls with Technique 2

(solder fountain)

o Controlo SAC305 components from same population as those sent for

reballingo Solder balls removed mechanically

o No thermal exposureo Low speed shear with XYZTEC Condor Classic Bond Tester

Reballing Techniques


o All measurements for all components within 85Ω and 125Ω range in specificationo Five (5)

components probed per population

o Eight (8) probe pairs per component

Results: Electrical Characterization


o A contour plot is a graphic representation of the relationships among three numeric variables in two dimensions. Two variables are for X and Y axes, and a third variable Z is for contour levels. The contour levels are plotted as curves; the area between curves can be color coded to indicate interpolated values. (1)

o You can interactively identify, label, color, and move contour levels, and change the resolutions of rectangular grids to get better contouring quality and performance

o The plots on the next slide demonstrate that 95% of the time a resistance reading from the reballed population will overlap with that of the non-reballed population. Each plot indicates reballed and control populations of an I/O pair, and all the plots maintain the same behavior with 95% confidence.

1) SAS Institute Inc.,SAS/INSIGHT User’s Guide, Version 8, Cary, NC: SAS Institute Inc., 1999. 752 pp

What are Contour Plots


Results: Electrical Characterization, cont.

Independence of A0-AN0 Resistance for Reballed Flip Chip Populations

Mean

Std

95.00 100.0096.00 97.00 98.00 99.000.00

2.50

0.50

1.00

1.50

2.00


Mean

Std

95.50 100.5096.50 97.50 98.50 99.500.00

2.50

0.50

1.00

1.50

2.00


Mean

Std

95.00 100.0096.00 97.00 98.00 99.000.00

2.50

0.50

1.00

1.50

2.00


Mean

Std

97.00 102.0098.00 99.00 100.00 101.000.00

2.50

0.50

1.00

1.50

2.00


Mean

Std

97.25 102.2598.25 99.25 100.25 101.250.00

2.50

0.50

1.00

1.50

2.00


Mean

Std

95.00 100.0096.00 97.00 98.00 99.000.00

2.50

0.50

1.00

1.50

2.00


Mean

Std

95.50 100.5096.50 97.50 98.50 99.500.10

2.60

0.60

1.10

1.60

2.10


Mean

Std

95.00 100.0096.00 97.00 98.00 99.000.00

2.50

0.50

1.00

1.50

2.00

o Contour plots demonstrate overlap between most populationso 95% confidence limito Reballer D may be

distinguishable from Reballers A and B

o Not distinguishable from Reballers C, E, or control


o Tomographic acoustic micro-imaging (TAMI) performed

o One flip chip per population

o Focused on two interfaces

o Where C4 bumps adhere to pads on the die

o Where C4 bumps adhere to substrate

o No observed gaps, voids, or delamination on reballed or control components

Results: Scanning Acoustic Microscopy (SAM)


Results: TAMI-SAM, Die to Bump Interface

A B C

Cont

rol

ED


Results: TAMI-SAM, Bump to Substrate Interface

A B C

Cont

rol

ED


o Computed tomography generates a 3-D model from a series of x-ray slices

o One flip chip per population

o No cracks or defects observed on reballed or control components

o Some voiding observed at bump to substrate interface

Results: X-ray Computed Tomography (CT)


Results: CT, Bump Near Substrate Interface Slices

A B C

Cont

rol

ED


o Slices through C4 bumps near substrate provide a snapshot of voiding in the first level interconnects

o Images were threshold corrected in ImageJ

o Enables estimation of percent voiding

Results: CT, Void Measurement


Results: CT, Bump Near Substrate Interface Slices, Void

MeasurementA B C

Cont

rol

ED


o No industry standard for voiding in C4 bumps

o IPC-A-610E allows for 25% voiding in solder balls

o Voiding was well below 25% for all reballers and control

Results: CT, Measured Voiding in C4 Bumps


o Damage was not observed to the first level interconnects as the result of reballing:o No changes in the resistance across solder bump connected input

differential ports o These measurements would be expected to change dramatically if

cracking occurred in the C4 bumps

o Acoustic microscopy indicated that no delamination occurred within the packages during the reballing process

o No evidence of gross void formation or coalescence within the C4 bumps was detected by CTo Voiding in control unit was about the same as the average voiding for all

samples scannedo Changes to the appearance of the C4 bumps that would indicate

cracking or damage accumulation was not observed

Conclusions


This work was supported by a Small Business Innovation Research Grant from the Office of the Secretary of Defense.

The authors also wish to thank the participating reballers for their warm welcome and insight into reballing processes.

Thanks Greg, for giving the talk.

Acknowledgment


o Joelle Arnold spent 8 years at DfR Solutions, focusing on root cause analysis of electronics, with specialization in solder joint reliability, fracture, fatigue mechanics of materials, and electrolytic capacitors

o Her B.S. is in Engineering: Materials Science from Franklin W. Olin College of Engineering and is nearing completion of her M.S. at University of Maryland, College Park

o She is now a Senior Reliability Engineer at MKS Instruments of Andover, MA

Author Biography

Documents

Impact of Reprocessing Technique on First Level