Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

Sejoon Lee,1,2,a) Emil B. Song,2,a) Sungmin Kim,2 David H. Seo,3 Sunae Seo,4

Tae Won Kang,1 and Kang L. Wang2

1Quantum-functional Semiconductor Research Center, Dongguk University-Seoul, Seoul 100-715, Korea2Department of Electrical Engineering, University of California at Los Angeles, Los Angeles,California 90095, USA3Samsung Advanced Institute of Technology, Youngin, Gyeonggi 446-712, Korea4Department of Physics, Sejong University, Seoul 143-747, Korea

(Received 3 October 2011; accepted 16 December 2011; published online 10 January 2012)

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an

Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate

material’s work-function (U) on the memory characteristics is investigated using different types of

metals [Ti (UTi¼ 4.3 eV) and Ni (UNi¼ 5.2 eV)]. The ambipolar carrier conduction of graphene

results in an enlargement of memory window (DVM), which is �4.5 V for the Ti-gate device and

�9.1 V for the Ni-gate device. The increase in DVM is attributed to the change in the flat-band

condition and the suppression of electron back-injection within the gate stack. VC 2012 AmericanInstitute of Physics. [doi:10.1063/1.3675633]

The 2-dimensionality of graphene allows scaling beyond

the complementary metal-oxide-semiconductor (CMOS)

technology, which could be instrumental for high-density

storage memory applications. In recent years, several types

of graphene-based memory devices have been proposed:

resistive-switching memories using graphene-oxide,1–3 ferro-

electric memories with graphene channel,4,5 charge transfer

memories using dielectric stacks on graphene6 or reduced

graphene-oxide,7 a flash memory with graphene floating-

gate,8 and nano-electromechanical switches.9,10 Further-

more, by integrating graphene with polymers and/or flexible

substrates,11–13 a spectrum of graphene-based memory appli-

cations is streaming toward transparent flexible- and

wearable-electronics. Meanwhile, in CMOS technology, 3-

dimensional (3D) integration of memory structures has been

proven to be useful for maximizing memory capacity.14

Thus, combining the advantages in both graphene and 3D

memory-structures could provide solutions to current chal-

lenges in the field of electronic memories. For example, the

scaling limit and the short-channel-effects in CMOS memory

devices can be resolved through the ambipolar carrier con-

duction and the absence of charge depletion in graphene.

In this letter, we report on the electrical characteristics

of a non-volatile charge-trap flash memory composed of a

graphene-channel field-effect-transistor (gFET) and a 3D

charge storage stack of Al2O3/HfOx/Al2O3 (AHA). In order

to maximize the memory effect in an AHA-gFET structure,

we vary the gate electrode material and investigate the

impact of gate work-function difference on the memory

characteristics of AHA-gFETs.

The schematic of the AHA-gFET memory structure is

illustrated in Fig. 1(a). First, the single-layer graphene (SLG)

grown on Cu by chemical vapor deposition15 is transferred

onto a SiO2 (�1000 A)/nþ-Si substrate. As shown in Fig. 1(b),

the Raman spectrum of SLG exhibits single Lorentzian peaks

at the G and 2D bands with a high 2D/G ratio (>2), which

indicates high-quality SLG.16 Second, the SLG channel area

is patterned by photolithography and etched by oxygen

plasma. Then, the Ti/Al source (S)/drain (D) electrodes are

formed by e-beam evaporation and lift-off [Fig. 1(c)]. By

using a graphene-channel and metal S/D, the thermal budget

is reduced compared to CMOS because the high-temperature

processes necessary for forming the S/D junctions are elimi-

nated. Next, to promote the nucleation of Al2O3 on gra-

phene,17 an ultrathin Al layer (�10 A) is deposited onto the

SLG channel and is oxidized in air. The triple stack of the

AHA (71/69/330 A) high-k dielectric layers is subsequently

deposited by atomic-layer deposition. Finally, the gate elec-

trode is formed by a standard lift-off process. We used two

different kinds of gate metals (Ti and Ni) to examine the

effects of the work-function (U) on the memory characteristics

of the AHA-gFETs. Figure 1(d) displays the cross-sectional

transmission electron microscopy (TEM) image of the as-

fabricated AHA-gFET, where the layered structures are

clearly noticeable.

Figure 2(a) shows the drain current vs. gate voltage (ID-

VG) characteristics depending on the program voltage (VP)

of the Ti-gate AHA-gFET. In stand-by mode (VP¼ 0), the

device exhibits a typical V-shaped curve where the charge-

neutrality point (VDirac) is observed at �0 V [gray curve].

After applying VP (�12 V), the VDirac positively shifts, and

the amount of shift (DVDirac) increases with VP. The positive

DVDirac is attributed to the reduction of electrochemical

potential (l) in the AHA gate stack due to the electron

injection18–20 from SLG to AHA. Figure 2(b) shows the

ID-VG characteristics depending on the erase voltage (VE) on

the same device. The VDirac slightly shifts toward the nega-

tive direction when a negative VE (¼ �12 to �14 V) is

applied and is ascribed by the increase of l in the AHA due

to the hole injection from SLG to AHA. However, when VE

exceeds �16 V, the VDirac suddenly turns and moves back

a)Authors to whom correspondence should be addressed. Electronic

addresses: sejoon@dongguk.edu and emil@ee.ucla.edu.

0003-6951/2012/100(2)/023109/4/$30.00 VC 2012 American Institute of Physics100, 023109-1

APPLIED PHYSICS LETTERS 100, 023109 (2012)

toward the positive direction. This is caused by the electron

back-injection from the Ti-gate to the AHA, which will be

explained later in detail.

In conventional CMOS memory devices, the memory

window (DVM) corresponds to the threshold voltage shift of

the FET (i.e., DVM¼DVth � DVFB, where the DVFB is the

flat-band voltage shift due to the electron injection into the

charge storage layer).19,20 Because of the unipolar transport

characteristics in CMOS, the DVth can only be observable in

either the positive or negative direction, which depends on the

charge polarity of majority carriers. Thus, the DVM is only

determined by the positive DVth in n-MOS or the negative

DVth in p-MOS. In the gFET memories, however, the DVM

can be larger because of the ambipolar conduction property.

In other words, the DVM in gFET memories can be defined as

a summation of both the positive maximum DVDirac after a

program operation and the negative maximum DVDirac after

an erase operation [i.e., DVM¼ jþDVDirac(max)jVPj þj�DVDirac(max)jVEj]. As indicated in Fig. 2(c), the maximum

DVM of the Ti-gate AHA-gFET is �4.5 V. Here, it should be

noted that the effect of the ultra-thin Al nucleation layer gives

minimal effect on the memory characteristics, since the final

Al2O3 layer shows a low interface state density

(<9.4� 1010 cm�2),17 which corresponds to a hysteresis of

�16 mV when a �45 nm thickness of Al2O3 gate oxide is

assumed.

According to the above description, the electron back-

injection at larger VE (��15 V) impedes the expansion of

DVM. This is closely related to the U of the gate electrode

because U is a key factor in determining both the barrier

height (/b) and the initial flat-band conditions for the device

[see also Figs. 4(a) and 4(e)]. Thus, in order to suppress the

electron back-injection, we changed the gate electrode from

Ti (UTi¼ 4.3 eV) to Ni (UNi¼ 5.1 eV). Similar to the Ti-gate

device, the VDirac is positively shifted when VP is increased

[Fig. 3(a)]. But, a clearly different behavior is observed

when the erase operation is performed. The device exhibits a

systematic DVDirac towards the negative direction up to

VE¼�30 V where the electron back-injection occurs [Figs.

3(b) and 3(c)]. As a result, the Ni-gate device exhibits a larger

DVM � 9.1 V through an increase in both jþDVDirac(max)jVPjand j�DVDirac(max)jVEj, compared to the Ti-gate device.

On the basis of our device performance, we believe that

the U of gate electrodes plays a crucial role in the memory

characteristics of AHA-gFETs. To understand the impact of

U on the device operation, we compare and explain the car-

rier transport mechanisms in the AHA-gFETs. Figure 4 rep-

resents the energy band diagrams of the Ti-gate and the Ni-

gate AHA-gFET memory devices at various bias conditions.

At zero bias, the /b (¼UGate � UAl2O3¼ 4.3–1.0 eV)20 is

3.3 eV and the DE (¼UGate � USLG¼ 4.3–4.5 eV)20,21 is

�0.2 eV for the Ti-gate device [Fig. 4(a)]. For the Ni-gate

device, since the UNi (¼5.2 eV)20 is larger than the UTi, the

/b is increased to 4.2 eV and the DE is reversed to 0.7 eV

[Fig. 4(e)]. As we apply VP beyond the VDirac (e.g.,

FIG. 1. (Color online) (a) Schematic view of the device structure. (b)

Raman spectrum of SLG. (c) SEM image of SLG channel after the forma-

tion of S/D electrodes. (d) Cross-sectional TEM image of Ti/Al2O3/HfOx/

Al2O3/SLG/SiO2 stacked layers.

FIG. 2. (Color online) (a) ID-VG characteristic curves of Ti-gate AHA-

gFET after programming at various VP (¼þ12 – þ24 V; 10 ms; step: þ2 V).

(b) ID-VG characteristic curves of Ti-gate AHA-gFET after erasing at vari-

ous VE (¼�12 to �24 V; 30 ms, step: �2 V). (c) Variation of DVDirac as a

function of VP and VE for Ti-gate AHA-gFET.

FIG. 3. (Color online) (a) ID-VG characteristic curves of Ni-gate AHA-

gFET after programming at various VP (¼þ16 to þ32 V; 10 ms; step:

þ2 V). (b) ID-VG characteristic curves of Ni-gate AHA-gFET after erasing

at various VE (¼�16 to �32 V, 30 ms; step: �2 V). (c) Variation of DVDirac

as a function of VP and VE for Ni-gate AHA-gFET.

023109-2 Lee et al. Appl. Phys. Lett. 100, 023109 (2012)

VG¼þV1 � VDirac), the electrons are induced in SLG and

some of the electrons are injected into the AHA due to the

high external electric-field (EEX). At steady state [Figs. 4(b)

and 4(f)], the electrons stored in HfOx reduce the l in the

AHA and causes the effective electric-filed (Eeff) to decrease

near the interface region between Al2O3 and SLG. This cre-

ates the positive DVDirac when VP is applied. Here, the dif-

ference in flat-band conditions (i.e., DE¼�0.2 eV for the

Ti-gate device and DE¼þ0.7 eV for the Ni-gate device)

produces a larger DVDirac(max)jVP in the Ni-gate device com-

pared to the Ti-gate device.

In the case of the erase operation [Figs. 4(c) and 4(g)],

the applied VE (e.g., VG¼�V2 � VDirac) induces hole car-

riers in SLG and the EEX gives rise to the hole injection into

the AHA. Similar to the program operation, the holes stored

in HfOx increases the l in the AHA and the increased Dlleads to the negative DVDirac. When VE reaches the critical

turning point (e.g., VG¼�V3 � �V2), the electron back-

injection takes place in the Ti-gate device through Fowler-

Nordheim tunneling [Fig. 4(d)], which is caused by the high

EEX and the relatively low /b. The back-injected electrons

reduce the l and a sudden change in DVDirac to the positive

direction occurs. However, in the case of the Ni-gate device

[Fig. 4(d)], the probability of electron back-injection is low

because of the relatively high /b. This allows a further

increase in negative jDVDiracj. As a consequence, the

increase in both jDVDirac(max)jVPj and j�DVDirac(max)jVEjresults in the enlargement of DVM.

With regard to the overall memory performance, the oper-

ating speed of our graphene charge trap memory would be

limited by the capacitive charging speed of the gate stack,

since the high graphene mobility22,23 of 5000–100 000 cm2/Vs

renders an extremely short transit-time. The retention charac-

teristics show a �30% loss of DVM (/10 years) [data not

shown], which suggests the low-temperature fabrication pro-

cess has to be optimized in order to improve the retention

characteristics. Furthermore, several methods can be proposed

to improve the On/Off ratio. For example, the low On/Off

ratio (e.g., 3–4 in our AHA-gFETs) can be increased by creat-

ing an energy band-gap (Eg) in this otherwise gapless material

through quantum confinement effects (Eg 50 meV) in gra-

phene nanoribbons24 and field-induced effects (Eg 250 meV) in bi or trilayer graphene.25,26

In summary, the AHA-gFETs fabricated with two differ-

ent gate electrodes (Ti and Ni) show a strong dependence of

their memory characteristics on the U of gate materials. In

comparison with the Ti-gate device (DVM � 4.5 V), the Ni-

gate device reveals a larger DVM � 9.1 V arising from a

greater value in both jDVDirac(max)jVPj and j�DVDirac(max)jVEj.The increased jDVDirac(max)jVPj is directly attributed to the

positive DE from the flat-band condition, and the increased

j�DVDirac(max)jVEj is a result of the high /b.

This research was supported by the National Research

Foundation of Korea (Grant Nos. NRF-2011-00125 and

NRF-2011-0000016) funded by the Ministry of Education,

Science and Technology (MEST), the MARCO Focus Center

on Functional Engineered Nano Architectonics (FENA), and

the NSF IGERT Materials Creation Training Program (grant

DGE-11443).

1C. L. He, F. Zhuge, X. F. Zhou, M. Li, G. C. Zhou, Y. W. Liu, J. Z. Wang,

B. Chen, W. J. Su, Z. P. Liu, Y. H. Wu, P. Cui, and R.-W. Li, Appl. Phys.

Lett. 95, 232101 (2009).2S. Wang, J. Pu, D. S. H. Chan, B. J. Cho, and K. P. Loh, Appl. Phys. Lett.

96, 143109 (2010).3J. Y. Son, Y.-H. Shin, H. Kim, and H. M. Jang, ACS Nano 4, 2655 (2010).4E. B. Song, B. Lian, S. M. Kim, S. Lee, T.-K. Chung, M. Wang, C. Zeng,

G. Xu, K. Wong, Y. Zhou, H. I. Rasool, D. H. Seo, H.-J. Chung, J. Heo, S.

Seo, and K. L. Wang, Appl. Phys. Lett. 99, 042109 (2011).5Y. Zheng, G.-X. Ni, C.-T. Toh, C.-Y. Tan, K. Yao, and B. Ozyilmaz,

Phys. Rev. Lett. 105, 166602 (2010).6S. A. Imam, T. Deshpande, A. Guermoune, M. Siaj, and T. Szkopek, Appl.

Phys. Lett. 99, 082109 (2011).7S. Myung, J. Park, H. Lee, K. S. Kim, and S. Hong, Adv. Mater. 22, 2045

(2010).8A. J. Hong, E. B. Song, H. S. Yu, M. J. Allen, J. Kim, J. D. Fowler, J. K.

Wassei, Y. Park, Y. Wang, J. Zou, R. B. Kaner, B. H. Weiller, and K. L.

Wang, ACS Nano 5, 7821 (2011).9K. M. Milaninia, M. A. Baldo, A. Reina, and J. Kong, Appl. Phys. Lett.

95, 183105 (2009).10S. M. Kim, E. B. Song, S. Lee, S. Seo, D. H. Seo, Y. Hwang, R. Candler,

and K. L. Wang, Appl. Phys. Lett. 99, 023103 (2011).11S. K. Hong, J. E. Kim, S. O. Kim, S.-Y. Choi, and B. J. Cho, IEEE Elec-

tron Device Lett. 31, 1005 (2010).

FIG. 4. (Color online) Energy band diagrams of Ti- and Ni-gate AHA-

gFETs at various bias conditions. Ti-gate AHA-gFET: (a) VG¼ 0 V, (b)

VG¼þV1, (c) VG¼�V2, (d) VG¼�V3 (� �V2). Ni-gate AHA-gFET: (e)

VG¼ 0 V, (f) VG¼þV1, (g) VG¼�V2, (h) VG¼�V3 (��V2).

023109-3 Lee et al. Appl. Phys. Lett. 100, 023109 (2012)

12H. Y. Jeong, J. Y. Kim, J. W. Kim, J. O. Hwang, J.-E. Kim, J. Y. Lee, T.

H. Yoon, B. J. Cho, S. O. Kim, R. S. Ruoff, and S.-Y. Choi, Nano Lett. 10,

4381 (2010).13D. I. Son, T. W. Kim, J. H. Shim, J. H. Jung, D. U. Lee, J. M. Lee, W. I.

Park, and W. K. Choi, Nano Lett. 10, 2441 (2010).14International Technology Roadmap for Semiconductors (ITRS), Design,

Semiconductor Industry Association (SIA, San Jose, 2007).15I. Jeon, H. Yang, S.-H. Lee, J. Heo, D. H. Seo, J. Shin, U.-I. Chung, Z. G.

Kim, H.-J. Chung, and S. Seo, ACS Nano 5, 1915 (2011).16H. I. Rasool, E. B. Song, M. J. Allen, J. K. Wassei, R. B. Kaner, K. L.

Wang, B. H. Weiller, and J. K. Gimzewski, Nano Lett. 11, 251 (2011).17S. Kim, J. Nah, I. Jo, D. Shahrjerdi, L. Colombo, Z. Yao, E. Tutuc, and S.

K. Banerjee, Appl. Phys. Lett. 94, 062107 (2009).18S. Oda and D. Ferry, Silicon Nanoelectronics (Taylor & Francis, New

York, 2006).

19D. K. Schroder, Semiconductor Material and Device Characterization, 3rd

ed. (Wiley, New York, 2006).20S. M. Sze, Physics of Semiconductor Devices, 3rd ed. (Wiley, New York,

2006).21Y.-J. Yu, Y. Zhao, S. Ryu, L. E. Brus, K. S. Kim, and P. Kim, Nano Lett.

9, 3430 (2009).22A. K. Geim, Science 324, 1530 (2008).23A. H. Castro Neto, F. Guinea, N. M. R. Peres, K. S. Novoselov, and A. K.

Geim, Rev. Mod. Phys. 81, 109 (2009).24T. Shimizu, J. Haruyama, D. C. Marcano, D. V. Kosinkin, J. M. Tour, K.

Hirose, and K. Suenaga, Nat. Nanotechnol. 6, 45 (2011).25Y. Zhang, T.-T. Tang, C. Girit, Z. Hao, M. C. Martin, A. Zettl, M. F.

Crommie, Y. R Shen, and F. Wang, Nature 459, 820 (2009).26C. H. Lui, Z. Li, K. F. Mak, E. Cappelluti, and T. F. Heinz, Nat. Phys. 7,

944 (2011).

023109-4 Lee et al. Appl. Phys. Lett. 100, 023109 (2012)