IMP Digital Slides

CG-CoreEl Sandeepani School of VLSI Design CG-CoreEl Sandeepani School of VLSI Design

“Digital Logic

For VLSI Design”

Sandeepani School of VLSI Design

Bangalore/Hyderabad


System:


Digital System!


Combinational vs. Sequential


Levels of integrated circuits


Binary Valued Signals


Binary Valued Signals … contd


Binary Valued Signals … contd


Two logic levels but very powerful applications……… possible!


VLSI: but why? Integration improves the design:

lower parasitics = higher speed;

lower power;

physically smaller.

Integration reduces manufacturing cost-(almost) no manual assembly.



VLSI Applications VLSI is an implementation technology for electronic

circuitry - analogue or digital

It is concerned with forming a pattern of interconnected switches and gates on the surface of a crystal of semiconductor

Microprocessors

personal computers

microcontrollers

Memory - DRAM / SRAM

Special Purpose Processors - ASICS (CD players, DSP applications)

Optical Switches

Has made highly sophisticated control systems mass-producible and therefore cheap


What is a Silicon Chip? A pattern of interconnected switches and gates on the

surface of a crystal of semiconductor (typically Si)

These switches and gates are made of

areas of n-type silicon

areas of p-type silicon

areas of insulator

lines of conductor (interconnects) joining areas together

Aluminium, Copper, Titanium, Molybdenum, polysilicon, tungsten

The geometry of these areas is known as the layout of the chip

Connections from the chip to the outside world are made around the edge of the chip to facilitate connections to other devices


Logic families

Commonly used are 3

Transistor-Transistor logic (TTL)

Complementary metal oxide semiconductor (CMOS)

Emitter Coupled Logic (ECL)

Most important characteristics of TTL & CMOS are that

TTL gates switch very fast

CMOS has very low power dissipation


CMOS Technology: Modern Logic Design

First proposed in the 1960s. Was not seriously considered until the severe limitations in power density and dissipation occurred in NMOS circuits

Now the dominant technology in IC manufacturing

Employs both pMOS and nMOS transistors to form logic elements

The advantage of CMOS is that its logic elements draw significant current only during the transition from one state to another and very little current between transitions - hence power is conserved.

In the case of an inverter, in either logic state one of the transistors is off. Since the transistors are in series, (~ no) current flows.

See twin-well cross sections


BiCMOS A known deficiency of MOS technology is its limited load

driving capabilities (due to limited current sourcing and sinking abilities of pMOS and nMOS transistors.

Bipolar transistors have

higher gain

better noise characteristics

better high frequency characteristics

BiCMOS gates can be an efficient way of speeding up VLSI circuits

See table for comparison between CMOS and BiCMOS

CMOS fabrication process can be extended for BiCMOS

Example Applications

CMOS - Logic

BiCMOS- I/O and driver circuits

ECL - critical high speed parts of the system


CMOS Inverter

VDD

A Y

GND


CMOS NAND gates

A

B

Y

Vdd


CMOS NOR gates

A

BY

VDD


NMOS gates

Inverter

Nand

Nor

Nand/Nor preference


Exercise

Implement AND,OR gates using CMOS logic


CMOS Vs Bipolar Technology

CMOS Technology

Low static power dissipation

High i/p impedance (low drive current)

Medium speed

High packing density

Low o/p drive current

Bidirectional capability

A near ideal switching

Bipolar Technology

High power dissipation

Low i/p impedance (high drive current)

High speed

Low packing density

High o/p drive current

Essentially unidirectional


Moore’s Law

Gordon Moore: co-founder of Intel.

Predicted that number of transistors per chip would grow exponentially (double every 18 months).

Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles. Moore’s Law


Moore’s Law plot




CPLD Basics Review:What is a CPLD?

Definition:Complex Programmable Logic Device - A hybrid of PLD blocks and interconnect for mid-size logic designs

IO/Registers/Logic IO/Registers/LogicInterconnect


CPLD Architecture

• I/O - Input Output block. The gateway between the CPLD fabric and the outside world

• MC - Macrocell. The Part of the CPLD architecture containing the register

• Logic Block - Where product terms are built

• Product Term - Single logical function made out of AND and OR terms

• Interconnect Array - Connection between the I/O, MC, and logic blocks

• Function Block - The name for a logic block and its associated macrocells

Inte

rco

nn

ect A

rray

MCn

MC0

I/OI/O

MCn

MC0

I/OI/OLogic

Block

MCn

MC0

Logic

Block

Logic

Block

Logic

Block

MCn

MC0

Function Block


CPLD Definitions:High Performance Pin-to-pin

combinatorial delay Time from input

through interconnect to output (ns)

Maximum registered frequency

Fastest operation of flip-flops (MHz)

Tpd (ns) Fmax (MHz)


CPLDs versus FPGAs

• CPLD architecture

• FPGA architecture

– Product term array

– Interconnect array

– Wide fanin

– Deterministic timing

– Pin locking

– Look-up table based

– X/Y routing matrix

– Higher density

– Additional features• DLL

• Multipliers

Inte

rco

nn

ect A

rray

MCn

MC0

I/OI/O

MCn

MC0

I/OI/O Logic

BlockMCn

MC0

Logic

Block

Logic

Block

Logic

BlockMCn

MC0

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell

Logic

Cell


CPLD or FPGA? CPLD Non-volatile

Consistent pin-to-pin timing

Simple timing model

Very low power consumption

Lowest cost point

Fast internal performance

Small packages (CP56, 132)

Applications - Logic decode/ integration, state machines

• FPGA

– Volatile

– Requires memory device

to load design at power up

– Complex timing model

– Large complex designs

– Memory resources

– Applications - PCI, high-

speed serial

communication, embedded

processors


Field-programmable gate arrays









FPGAs and VLSI FPGAs are standard parts:

Pre-manufactured, shorter design cycle.

Don‟t worry (much) about physical design.

Time to market is less, but FPGAs are slower,

larger, more power-hungry.

Custom silicon:

Tailored to your application.

Generally lower power consumption.

Time to market is more


Embedded Digital System: The big

picture


A Historical Perspective: the PLA

x0 x1 x2

AND

plane

x0x1

x2

Product terms

OR

plane

f0 f1


Two-Level Logic

Inverting format (NOR-

NOR) more effective

Every logic function can be

expressed in sum-of-products

format (AND-OR)

minterm


Array-Based Programmable Logic

PLA PROM PAL

I5 I4

O0

I3 I2 I1 I0

O1O2O3

Programmable AND array

ProgrammableOR array I5 I4

O0

I3 I2 I1 I0

O1O2O3

Programmable AND array

Fixed OR array

Indicates programmable connection

Indicates fixed connection

O0

I3 I2 I1 I0

O1O2O3

Fixed AND array

ProgrammableOR array


Programming a PROM

f0

1 X 2 X 1 X 0

f1NANA

: programmed node


More Complex PAL

From Smith97

i inputs, j minterms/macrocell, k macrocells


Number System & Conversions


• Code conversions

• Self-complementary code

• Weighed & Non Weighed codes

Recap

• Binary Addition

• Binary Subtraction

• Binary multiplication

• Binary Division


Exercise

Convert 101100.101 into hexadecimal, octal and decimal.

Convert F4A into binary

Answers :- 101100.101 (2) = 2C.A (16) = 44.625 (10)- 101100.101 (2) = 54.5 (8)- F4A (16 )=111101001010 (2)


General Positional Number

Conversion radix-r to decimal :

decimal to radix-r :- Successive division of D by r- The remainder of the long division will give the digits starting from the least significant digit

D d ri

i n

p

i

1


Example - Decimal to Binary :

179 (10)179/2 = 89 ( 1 ) LSB

89/2 = 44 ( 1 )44/2=22 ( 0 )

22/2=11 ( 0 )11/2=5 ( 1 )

5/2=2 ( 1 )2/2=1 ( 0 )

1/2=0 (1)MSB

Result : 10110011 (2)


Hexadecimal Addition

Add digits in Convert each digit into decimal

decimal

Convert the result into Hexadecimal

Produce carry when digits sum is > = the radix (16 )

Example1 0 1 0 1 0 1 02 F A 5 2 15 10 5

+ A 9 3 C 10 9 3 12_________ _______________

D 8 E 1 (13) (16+8) (14) (16+1)D 8 E 1


Switching Algebra

Definition

Shannon’s expansion theorem

Principle of duality

Complementation rules

SOP and POS


Duality Axioms and Theorems – come in

pairs

Get one of the pair from the other by:

1. Replacing AND with OR

2. Replacing OR with AND

3. Replacing 1 with 0

4. Replacing 0 with 1

If E is a valid Boolean expression, then Ed (its dual) is also valid


Canonical Forms

Literal – switching variable or its complement (e.g., x or y)

Product Term or Implicant – series of literals related by AND operator

Sum Term – Series of literals related by

OR operator


Boolean AlgebraAXIOMS :

DEFINITIONS:

THEOREMS:


Prove the following:

(Do not use K-maps)

1. A + A’B = A+B

2. Sum of products of three variables is equal to 1.

3. Product of sums of three variables is equal to 0.

4. A’B’C’+A’B’C+A’BC’+AB’C’+ABC’ = A’B’+C’

Problems


Representation Of Numbers: a revision

• Signed magnitude

• 1’s Complement

• 2’s Complement


Signed magnitude representation

Humans use a signed-magnitude system: we add + or - in front of a magnitude to indicate the sign.

We could do this in binary as well, by adding an extra sign bit to the front of our numbers. By convention:

A 0 sign bit represents a positive number.

A 1 sign bit represents a negative number.

Examples:

11012 = 1310 (a 4-bit unsigned number)

0 1101 = +1310 (a positive number in 5-bit signed magnitude)

1 1101 = -1310 (a negative number in 5-bit signed magnitude)

01002= 410 (a 4-bit unsigned number)

0 0100 = +410 (a positive number in 5-bit signed magnitude)

1 0100 = -410 (a negative number in 5-bit signed magnitude)

• Range?

• Limitation?


The MSB represents the sign bit ( 0 = +ve , 1 = -ve )

The range for n-bit is :

Example: n=5* Range : from -15 to 15* 10011= -3 , 01100 = +12* 00000= 0 , 10000 = - 0

Disadvantages :1- Two possible representations of zero2- Complicated digital adders

from ton n ( ) ( )2 1 2 11 1

Signed Magnitude Representation


One’s complement Representation

A different approach, one’s complement, negates numbers by

complementing each bit of the number.

We keep the sign bits: 0 for positive numbers, and 1 for negative.

The sign bit is complemented along with the rest of the bits.

Examples:


0 1101 = +1310 (a positive number in 5-bit one’s

complement)

1 0010 = -1310 (a negative number in 5-bit one’s

complement)


0 0100 = +410 (a positive number in 5-bit one’s complement)

1 1011 = -410 (a negative number in 5-bit one’s

complement)


Why is it called “1’s complement?”

Complementing a single bit is equivalent to subtracting it from 1.

0’ = 1, and 1 - 0 = 1 1’ = 0, and 1 - 1 = 0

Similarly, complementing each bit of an n-bit number is equivalent to subtracting that number from 2n-1.

For example, we can negate the 5-bit number 01101.

Here n=5, and 2n-1 = 3110 = 111112.

Subtracting 01101 from 11111 yields 10010:

1 1 1 1 1- 0 1 1 0 1

1 0 0 1 0


1’s complement addition

To add one’s complement numbers:

First do unsigned addition on the numbers, including the sign bits.

Then take the carry out and add it to the sum.

Two examples:

This is simpler and more uniform than signed magnitude addition.

0111 (+7)+ 1011 + (-4)

1 0010

0010+ 1

0011 (+3)

0011 (+3)+ 0010 + (+2)

0 0101

0101+ 0

0101 (+5)


Two’s complement

Our final idea is two‟s complement. To negate a number, complement

each bit (just as for ones‟ complement) and then add 1.

Examples:


0 1101 = +1310 (a positive number in 5-bit two’s complement)

1 0010 = -1310 (a negative number in 5-bit ones’ complement)

1 0011 = -1310 (a negative number in 5-bit two’s complement)


0 0100 = +410 (a positive number in 5-bit two’s complement)

1 1011 = -410 (a negative number in 5-bit ones’ complement)

1 1100 = -410 (a negative number in 5-bit two’s complement)

• Range?

• Limitation?


Floating – point numbers

• Fixed point number can not represent very large and very small

numbers.

• Example: N = ± M * BE

for 8bit E range from –128 to +127

• IEEE format

N= ± 1. M * 2E‟ - 127 (single precision – 32 bit) E = E‟ -127

± 1. M * 2E‟ - 1023 (single precision – 64 bit) E = E‟ –1023


Problems

Q. Represent the following in single precision format

(i ) 0.0110 * 26

(ii) –1

(iii)(10)10


1. (500.21)10 = ( ? )2

2. (436.71)8 = ( ? )16

3. Convert (231.3)Base 4 to Base 7

Convert Base 4 to Base 10

Convert Base 10 to Base 7

Ans : (63.515) Base 7

Examples

4. 3168 – 4518 = ? (Hint: Use 8’s Complement)

5. CB2H – 972H = ? (Hint: Use 16’s Complement)

6. 0011.10012 – 0001.11102 = ? Using 1’s complement form

7. 79 - 26 in BCD representation? (Hint: Use 9’s

Complement)

8. 5 - 8 in XS-3?

9. Divide (10)10 by (4)10 in binary representation.

10. Convert (847)10 to gray code representation.

11. Perform direct subtraction: (9)10 – (10)10 ?

12. What is Hamming code?


Gates: electronic circuit that realizes a logical expression


Logical Expressions


NAND/NOR Networks

Convert AND/OR Network into NAND/NOR Network

Tips and Tricks Think of bubbles on gates as inverters Think of EXOR & EXNOR as parity ckts that

produce a 1 out if the number of 1’s in is odd or even respectively

Use alternative NAND/NOR symbols A 2 level NAND-NAND /NOR-NOR ckt is

equivalent to a 2 level AND-OR / OR-AND ckt respectively and realize SOP / POS logical expressions


Structural Model of gates


Ideal and real gates are different


Discussion…


K-Maps


SOP and POS Implementation


Some Arithmetic CircuitsAdders:

Half adder

Full adder

Serial adder

Ripple carry adder

Carry Bypass adder

Carry look ahead adder

Carry select adder

Multipliers:

2-bit by 2-bit Multiplier

4-bit by 3-bit Multiplier

Magnitude Comparator

2-bit Comparator

4-bit Comparator


Adders

Adder delay is dominated by carry chain.

Carry chain analysis must consider transistor, wiring delay.

Modern VLSI favors adder designs which have compact carry chains.


Implementation of Half Adder


Implementation of Full Adder


4-Bit Ripple carry adder


Ripple Carries

Cascade 64 full adders to get a 64-bit ripple carry adder

Problem: Slow – carries ripple

If stage delay = 20 nsec, Total delay = 64 X 20 = 1280 nsec


Full adder

Computes one-bit sum, carry: si = ai XOR bi XOR ci

ci+1 = aibi + aici + bici

Half adder computes two-bit sum.

Ripple-carry adder: n-bit adder built from full adders.

Delay of ripple-carry adder goes through all carry bits.


4-Bit Carry Adder-Subtractor


Serial Adder

Delay

Xi

Yi

Si

Ci + 1

Ci

Full Adder

Q. Design a 4-bit serial adder with the help of two shift

register?


Carry Look-ahead Adder


Carry-look ahead adder

First compute carry propagate, generate:

Pi = ai + bi

Gi = ai bi

Compute sum and carry from P and G:

si = ci XOR Pi XOR Gi

ci+1 = Gi + Pici


Carry Equations 4 stage binary carry look-ahead adder A1-4, B1-4 are addends, C0 is input carry Outputs are Sum S1-4 and Carries C1-4

Multiply out equations:C1 = G1 + P1 C0

C2 = G2 + P2 C1 = G2 + P2 G1 + P2 P1 C0

C3 = G3 + P3 C2 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 C0

C4 = G4 + P4 C3 = G4 + P4 G3 + P4 P3 G2 + P4 P3 P2 G1 + P4 P3 P2 P1 C0


Carry Look-Ahead Adder Big speedup – At most 4 logic delays to get all

carries

n = # full adder chips

ttotal = tXOR + log4 n X tLACG + tFA

tXOR = 10 nsec

tLACG = carry lookahead stage delay = 21 nsec

tFA = full adder delay = 15 nsec

ttotal = 10 nsec + 1 X 21 nsec + 15 nsec = 46 nsec


Depth-4 carry-look ahead


Analysis

Deepest carry expansion requires gates with large fan in: large, slow.

Carry-look ahead unit requires complex wiring between adders and look ahead unit—values must be routed back from look ahead unit to adder.

Layout is even more complex with multiple levels of look ahead.


4 bit Carry Look-ahead Adder


Carry-skip adder

Looks for cases in which carry out of a set of bits is identical to carry in.

Typically organized into b-bit stages.

Can bypass carry through all stages in a group when all propagates are true: Pi

Pi+1 … Pi+b-1. Carry out of group when carry out of last

bit in group or carry is bypassed.


Two-bit carry-skip structure

AND

Pi

Pi+1

Pi+b-1

…

OR

Ci+b-1

ci


Carry-skip structure

b adder stages

skip

P[0,b-1]Carry out

b adder stages

skip

P[b,2b-1]Carry out

b adder stages

skip

P[2b,3b-1]Carry out


Worst-case carry-skip

Worst-case carry-propagation path goes through first, last stages:


Delay analysis

Assume that skip delay = 1 bit carry delay.

Delay of k-bit adder with block size b:

T = (b-1) + 0.5 + (k/b –2) + (b-1)

block 0 OR gate skips last block

For equal sized blocks, optimal block size is sqrt(k/2).


Carry-select adder

Computes two results in parallel, each for different carry input assumptions.

Uses actual carry in to select correct result.

Reduces delay to multiplexer.


Carry select adder


Carry-select structure


Carry-save adder

Useful in multiplication.

Input: 3 n-bit operands.

Output: n-bit partial sum, n-bit carry.

Use carry propagate adder for final sum.

Operations:

s = (x + y + z) mod 2.

c = [(x + y + z) –2] / 2.


Pseudo or Carry Save Adder Advantage – only final stage of partial-

product addition needs to propagate carries

A

16

B CIN

Carries Sum

16 16

1616


Carry Save Addition (CSA)

A full adder sums 3 inputs and produces 2 outputs

Carry output has twice weight of sum output

N full adders in parallel are called carry save adder

Produce N sums and N carry outs

Z4

Y4

X4

S4

C4

Z3

Y3

X3

S3

C3

Z2

Y2

X2

S2

C2

Z1

Y1

X1

S1

C1

XN...1

YN...1

ZN...1

SN...1

CN...1

n-bit CSA


CSA Application Use k-2 stages of CSAs

Keep result in carry-save redundant form

Final CPA computes actual result

4-bit CSA

5-bit CSA

0001 0111 1101 0010

+

10110101_

0001

0111

+1101

1011

0101_

X

Y

Z

S

C

0101_

1011

+0010

X

Y

Z

S

C

A

B

S





4-bit CSA

5-bit CSA

0001 0111 1101 0010

+

10110101_

01010_ 00011

0001

0111

+1101

1011

0101_

X

Y

Z

S

C

0101_

1011

+0010

00011

01010_

X

Y

Z

S

C

01010_

+ 00011

A

B

S





4-bit CSA

5-bit CSA

0001 0111 1101 0010

+

10110101_

01010_ 00011

0001

0111

+1101

1011

0101_

X

Y

Z

S

C

0101_

1011

+0010

00011

01010_

X

Y

Z

S

C

01010_

+ 00011

10111

A

B

S

10111


Adder comparison

Ripple-carry adder has highest performance/cost.

Optimized adders are most effective in very long bit widths (> 48 bits).


0

50

100

150

200

250

300

350

8 40 72

Bits

Co

st (

CL

Bs)

0

50

100

150

200

250

300

350

400

8 32 56 80

Bits

Perf

orm

an

ce-C

ost

Rati

o

Ripple

Complete

CLA

Skip

RC-select

© 1998 IEEE

0

20

40

60

80

100

120

8 32 56 80

Bits

Op

era

tio

nal

Tim

e (

ns)


Serial adder

May be used in signal-processing arithmetic where fast computation is important but latency is unimportant.

Data format (LSB first):

0 1 1 0

LSB


Serial adder structure

LSB control signal clears the carry shift register:


BCD Adder


2bit X 2bit Multiplier


4bit X 3bit Multiplier



Q. Design a 2-bit digital comparator that accepts two

words A and B and gives three outputs :

G(>),

E(=) and

L(<).



Q. Design a 4-bit digital comparator that accepts two

words A and B and gives three outputs :

G(>),

E(=) and

L(<).


2-bit Magnitude Comparator

Answer:

let x1 = (A1 ex-nor B1)

x0 = (A0 ex-nor B0)

Z A=B = x1. x0

Z A>B = A1B‟1 + x1. A0 B‟0

Z A<B = A‟1B1 + x1. A‟0 B0


4-bit Magnitude Comparator

Answer:

Z A=B = x3. x2 . x1. x0

Z A>B = A3B‟3 + x3. A2 B‟2 + x3. x2. A1B‟1 + x3. x2. x1. A0 B‟0

Z A<B = A‟3B3 + x3. A‟2 B2 + x3. x2. A‟1B1 + x3. x2. x1. A‟0 B0


A0

B0

A1

B1

A2

B2

A>B

A<B

A=BA=B

output

A<Boutput

A>Boutput


Binary Multipliers

1. Extremely complex even for small word length

2. Very hard to test

3. Truth table expansion varies with word length

4. Must use at least one carry propagating full adder to sum up partial products


Multiplication Equations

Multiplicand A = Ah X 24 + Al

Multiplier B = Bh X 24 + Bl

Product P = A X B = Ah X Bh X 28 + (Ah X Bl + Al X Bh) X 24 + (Al X Bl)

Must sum the 4 partial products

Since A & B are 8 bits, product is 16 bits

Need 5 full adders to do this


74LS274 – Produces 8-bit product

4X4 bit Binary Multiplier


Example

…

…

…

…Cell 1

X11 X12 X1l

Z11 Z12 Z1m

…

……Cell 2

X21 X22 X2l

Z21 Z22 Z2m

Y21

Y22

Y2k

…

……

…

…Cell i

Xi1 Xi2 Xil

Zi1 Zi2 Zim

Yi1

Yi2

Yik

Yi1

Yi2

Yik


Multiplication

Example: 1100 : 1210

0101 : 510

1100

0000

1100

0000

00111100 : 6010


Multiplication

Example:

M x N-bit multiplication

Produce N M-bit partial products

Sum these to produce M+N-bit product

1100 : 1210

0101 : 510

1100

0000

1100

0000

00111100 : 6010

multiplier

multiplicand

partial

products

product


General Form Multiplicand: Y = (yM-1, yM-2, …, y1, y0)

Multiplier: X = (xN-1, xN-2, …, x1, x0)

Product:

1 1 1 1

0 0 0 0

2 2 2M N N M

j i i j

j i i j

j i i j

P y x x y

x0y

5x

0y

4x

0y

3x

0y

2x

0y

1x

0y

0

y5

y4

y3

y2

y1

y0

x5

x4

x3

x2

x1

x0

x1y

5x

1y

4x

1y

3x

1y

2x

1y

1x

1y

0

x2y

5x

2y

4x

2y

3x

2y

2x

2y

1x

2y

0

x3y

5x

3y

4x

3y

3x

3y

2x

3y

1x

3y

0

x4y

5x

4y

4x

4y

3x

4y

2x

4y

1x

4y

0

x5y

5x

5y

4x

5y

3x

5y

2x

5y

1x

5y

0

p0

p1

p2

p3

p4

p5

p6

p7

p8

p9

p10

p11

multiplier

multiplicand

partial

products

product


16X16 Mult. Dot Diagram

Each dot represents a bit

partial products

mu

ltiplie

r x

x0

x15


Parallel Binary Multiplier

+

Y

P C

YX

CO

POX


X

+

Y

P C

YX

CO

PO

One-Bit Multiplier Cell


Comparator Time Delays

Linear connection

tc = individual comparator delay

ttotal = m tc, for m comparators = 4 X 27 = 162 nsec (4-bit slices)

Cascaded connection

ttotal = (log4 m + 1) X tc = 2 X 27 = 54 nsec


Problems

Q.1. Design a circuit which will accept 4-bit binary and

will provide 5-bit BCD code?

Q.2. Design a 3-bit squarer?

Q.3. A circuit accepts a 4-bit I/p data & generates an o/p

Z=1whenever I/p is a prime number. Design the

circuit?


Problems

Q.4. The conditions under which an insurance company

will issue a policy are :

A married female 25 years old or older, or

A female under 25 years or

A married male under 25 years with no accident record, or

A married male with accident record, or

A married male under 25 years or older with no accident

record.

Obtain a simplified logic expression starting to whom a policy can be

issued.


Universal Logic Element


Universal Logic Element

Which of these are Universal logic

elements?

1. 2:1 MUX

2. Ex-or2

3. {f(x,y)=x‟y}

4. {f(x,y,z)=(x+y)z‟}

5. Nand2


Universal Logic Gate

Introduction

A set of gates is said to be universal if any

combinational system can be implemented using

gates just from that set.

The set {AND,NOT} or {OR,NOT} is universal .

So any set of gates that can implement either

{AND,NOT} or {OR,NOT} is universal.


Universal Logic gate : Nand2

Lets start with NAND gate.

• NAND(x,y)= (xy)‟ ⇒ NAND(x,x)=(xx)‟=x‟ ⇒ NOT(x)=NAND(x,x)

NOT gate can be implemented by a NAND gate

• AND(x,y)= xy = ((xy)‟)‟=(NAND(x,y))‟ . From the previous step, we know

how to implement NOT gate by a NAND gate

AND(x,y)=(NAND(x,y))‟=NAND(NAND(x,y), NAND(x,y))

• So,AND gate can be implemented by only using NAND gates

Since we can implement AND and NOT by only NAND gates,

{NAND, NOR} is a universal set,even without NOR gate.


Universal Logic Gate NAND Function

NAND ::= Negative ANDY = ( A • B )´

NOT

OR

AND

YINV

AA Y

AB

A

B AND 2 Y Y

OR 2BY

A

YA

B

=

=

=

NAND 2Y Y

A

BA

YA A

NAND 2BY YNAND 2BB

A

ANAND 2

ANAND 2B

Y

YANAND 2B

Y

A

BY

B


Universal Logic Gate NOR Function NOR ::= Negative OR

Y = ( A + B )´

NOT

OR

AND

NOR 2

YINVAA Y

AB

A

B AND 2Y Y

OR 2BY

AY

A

B

=

=

=

ANOR 2B

YYA

AA

NOR 2BY

YANOR 2B

Y

A

BY

B

YA A

NOR 2BY YNOR 2BB

A


Universal Logic Gate Multiplexor Function

MultiplexorY = A • S + B • S´

NOT OR AND

Y

Y

A

Y

V C C

G N D

G N D

G N DG N D

YS 1 S 0

YD 0

D 1

D 2

D 3

D 0

D 1

D 2

D 3

M X 4 M X 4M X 4

A

B

Y

Y

Y

Y

V C C

S 1 S 0

V C C

YD 0

D 1

D 2

D 3

S 1 S 0

Y

A

B

Y

Y

Implement the same using 2 to 1 Multiplexer


Basic Data Processing Circuits


2-4 line Decoder with Enable Input

CG-CoreEl Sandeepani School of VLSI Design CG-CoreEl Sandeepani School of VLSI Design Decoder (3:8)


Problems using Decoder

Q1. Implement 4:16 Decoder using two 3:8 Decoders

Q2. Realize a full adder using one 3:8 decoder & residual gates

Q3. Design BCD to decimal converter

• with false data rejected

• with false data accepted


4:16 Decoder using 3:8 Decoder


Full Adder using Decoder


Encoder

• Decimal-to-BCD Encoder

• Octal-to-Binary Encoder

Limitations?


4-Input priority Encoder


Multiplexer


4:1 line Multiplexer


Q1. Realize the following using only one 2:1 Mux

1. NOT

2. And2

3. OR2

4. Ex-or2

5. Ex-nor2

6. Latch

Problems


Q2. Show how two 2-to-1 multiplexers (with no added gates)

could be connected to form a 3-to-1 MUX. Input selection should

be as follows:

If AB = 00, select Io

If AB = 01, select I1

If AB = 1 – (B is don`t care), select I2.

Problems

Q3. Realize the function F(A,B,C,D)=Σm(1,2,3,6,8,9,11,14) using an

8-to-1 MUX with control inputs A,B, and C.

Q4. Repeat Q2 with control inputs A,C, and D.

Q5. Repeat Q2 using a 4-to-1 MUX and added gates.


2-input mux as programmable logic block

F

A 0

B

S

1

Configuration

A B S F=

0 0 0 0

0 X 1 X

0 Y 1 Y

0 Y X XY

X 0 Y

Y 0 X

Y 1 X X 1 Y

1 0 X

1 0 Y

1 1 1 1

XY

XY

X

Y


Q6. Design a sequence generator that generates the sequence

“11100011”.

Q7. Design 1:8 demultiplexer using two 1:4 demultiplexers.

Q8. Implement the following boolean function using 8:1 MUX,

F(A,B,C,D) = (0,1,3,4,8,9,15)

Problems, more problems


Buffer

• A Buffer is a logic circuit which has one I/p line & one output line.

• It is a current amplifier & also called as driver.

A Tri-State Buffer

Q. Implement a 2-to-1 Mux with Tri-state buffers


Answer

Or

2-1 line Mux with Tri-state buffer


Wired logic

• Power dissipation in LOW output state increases

• Speed of the operation increases

• Fan out decreases


Clock Generator Circuit ?


Now, solve this?

Look at the circuit diagram is given.

The “thermometer to binary

conversion” logic is a simple

combination circuitry which is to be

designed to provide a natural binary

representation using b1 and b0 for

the analog input Vin, here b1 is the

most significant bit. Also realize the

logic for b1 and bo using 2-input

NAND gates only.

Try to find the resolution of this

circuit.

What circuit is this?


Combinational.

Output depends only on current input values.

Sequential.

Output depends on current input values and

present state of the circuit, where the present

state of the circuit is the current value of the

devices‟ memory.

Sequential circuits…


Bistable Elements

The simplest sequential circuit.

It consist of a pair of inverters connected as

shown below. Notice the feedback loop.


Digital Analysis

Two stable states.

If Q is HIGH then the lower inverter has a HIGH at its

input and a LOW at its output. This in turn forces the

upper inverter‟s input to be LOW and its output to be

HIGH.

If Q is LOW then the lower inverter has a LOW at its

input and a HIGH at its output. This in turn forces the

upper inverter‟s input to be HIGH and its output to be

LOW.


Analog Analysis

Metastable behavior:

Consider the middle intersecting point in the

diagram shown below.

What would happen if a small amount of noise

varies either input voltage.


Latches and Flip-Flops

Binary cells capable of storing 1 bit of

information.

Generates one of two possible stable states.

Two outputs labeled Q and Q‟.

One or more inputs.

These sequential devices differ in the way their

outputs are changed:

– The output of a latch changes independent

of a clocking signal.

– The output of a flip–flop changes at specific

times determined by a clocking signal.


SR Latch with Control Input


D Latch

This latch eliminates the problem that occurs in the S‟R‟ latch when R=S=0.

C is an enable input:

When C=1 then the output follows the input D and the latch is said to be open. Due to this fact this latch is also called transparent latch.

When C=0 then the output retains its last value and the latch is said to be closed.


D Latch

For proper operation the D input must not change during a time interval around the falling edge of C.


Edge Triggered D Flip-Flop

This flip-flop is made out of two D latches. The first latch is the master, and

the second the slave.

When CLK_L = 1 the master is open and the slave is closed. Qm and Ds

follow Dm .


Edge Triggered D Flip-Flop

Positive edge-triggered D flip-flop.

Q* = D


JK Flip Flop(USING D flip flop)


Excitation table of Flip Flops


Flip Flop to Flip Flop conversions


FF – FF conversions

1. D-T D=T⊕Q

2. T-D T=D⊕Q3. D-JK D=Q’J+QK’

4. D-SR

5. T-SR

6. JK-SR

7. SR-JK


D from JK Flip Flop


Problems (doubts)

Q. Design a circuit that generates two waveforms of 90° phase shift.

Q. Design a 50% duty cycle frequency doubler for an input

clk pulse of 50% duty cycle.

More Problems, Many more Problems………. Let us continue!


Timing Issues


Timing Issues

• Timing parameters

• Timing diagram

• Set up time

• Hold time

• Clock Skew

• Slack

• Critical path

• Maximum Frequency of Operation


Timing parameters


Timing parameters…contd


Timing parameters…contd


Timing diagram


Setup and Hold Time

•Setup and hold time define a window of time which the D input must

be valid and stable in order to assure valid data on the Q output.

•Setup Time (Tsu) – Setup time is the time that the D input must be valid before

the Flip-Flop samples.

•Hold Time (Th) – Hold time is the time that D input must be maintained valid

after the Flip-Flop samples.

•Propagation Delay (Tpd) – Propagation delay is the time that takes to the

sampled D input to propagate to the Q output.


FF1 FF2

Q1Q2

CLOCKD

A LONG SLOW PATH

IN

CLK

Clock Skew

Synchronous systems using edge triggered flip-flops work

properly only if all flip-flops see the triggering edge at the

same time.

The difference between arrival times of the clock at different

devices is called clock skew.


Slack

At each node is a group of events modeling signal transitions

Arrival Time (AT) - when the signal arrives

AT

D Q

QB

RT

Required Time (RT) - when the signal is needed

SLEW

Slew (SLEW) - time for signal transition from logic levels


Slack

AT RT

SLEW

Q. Am I meeting timing at this node?

SLACK = RT - AT

+SLACK

Timing is met when slack is greater than or equal to zero


Maximum Operating Frequency


Recap

Shift registers: SISO, PISO, PIPO, SIPO

Shift register counters- ring counters and twisted

ring counters

Asynchronous/ synchronous counters


Counters Clocked sequential circuit with single-cycle state

diagram

Modulo-m counter = divide-by-m counter

Most Common:

n-bit binary counter, where m = 2n n flip-flops, counts 0 …

2n-1

S3

S2

S1

Sm


Ripple CounterQ

Q

T

Q

Q

T

Q

Q

T

Q

Q

T

CLK

Q0

Q1

Q2

Q3

1 bit

divide-by-2

2 bit

divide-by-4

3 bit

divide-by-8

4 bit

divide-by-16

Uses

Minimal

Logic!


Ripple Counter Timing

CLK

Q0

Q1

Q2

0 1 2 3 4

1D

2D

3D


CLK

Q0

Q1

Q2

7 Should be 0! 1 2

n TCQ for MSB change for n-bit ripple counter => minimum clk period

1D

2D

3D

Ripple Counter Problem (It’s Slow!)


Synchronous Counters

All clock inputs connected to common CLK signal

So all flip-flop outputs change simultaneously tCQ after CLK

Faster

More Complex Logic

Most Frequently Used Type of Counter


Synchronous Serial Counter

Flip-flops enabled when all lower flip-flops = 1.

Enable propagates serially — limits speed

Requires(n-1) Dt < TCLK

All outputs change simultaneously tCQ after CLK

>T

QEN

CLK

CNTEN Q0

Q1

Q2

Q3

QEN

>T

QEN

>T

QEN

>TEquation?

Delay?

Dt

Dt

Dt


Synchronous Parallel Counter

Single-level enable logic per flip-flop

Fastest and most complex type of counter

Requires Dt < TCLK

All outputs change simultaneously tCQ after CLK

>T

QEN

>T

QEN

>T

QEN

>T

QEN

CLK

CNTEN Q0

Q1

Q2

Q3

Equation?

Delay?


CLOCK

/S0

/S1

/S2

/S3

/S4

/S5

/S6

/S7

0

1

2

3

4

5

6

7

0

1

Decoded Modulo-8 Counter: Glitches!More than 1 bit changes simultaneously

Glitches NOT a problem for synchronous inputs.

Glitches BAD for asynchronous inputs!


Solve these:

Q1: Design a JK counter that goes through the states

1,2,3,6,7,8,11,13,1,… Implement the circuit and avoid loc-out

condition

Q2. Design a MOD 5 counter (divide by 5) counter using JK

flip-flop. Also construct the timing diagram. Also draw the

timing diagram of MOD 10 counter.


Solve these: …contd

Q3. Design a asynchronous MOD 10 (decade) counter.

Q4. Design a non-sequential ripple counter, which will go

through the states 3,5,7,8,9,10,3,4,…..

Q5. Determine fmax for the 4-bit synchronous counter if tpd

for each flip-flop is 50 ns and tpd for each AND gate is 20 ns.

Compare this with fmax for a MOD-16 ripple counter.


Interesting Problems:

Q1. Design a divide-by-3 counter with 50% duty cycle?

Question: Why in most of the designs only 50% duty cycle clocks

are used? Why can't we use a lesser duty cycle (less than 50%)

clock?


Q2. Design a divide-by 1.5 counter?

Q3. Design a black box whose input clock and

output relationship as shown in diagram

below.

Interesting Problems … contd


Finite State Machines


Topics

FSM Basics

Types of Machines

Example Designs


Example

Assume a stream of 50k bits are given to the

circuit whose output Z=1 when no. of 1`s in

50k bits are odd else Z = 0. Design the circuit.


Finite state machines are so named because thesequential logic that implements them can be inonly a fixed number of possible states.

FSM is a systematic way of specifying any sequential logic.

Ideally suited for complex sequential logic.

Finite State Machines


What is an FSM?

Design Specification Point of View

State machines are a means of specifying

sequential circuits which are generally

complex in their transition sequence

and depend on several control inputs.


State machines are a group of flip-flops, whose

group-state transition pattern from one set of

values to another and depends on several

control inputs

What is an FSM?

Digital Circuit Point of View


CLOCK

ASYNC

CONTROL

CURRENT

STATE

CONTROL

INPUTS

NEXT

STATE

CURRENT

STATE

COMB.

LOGIC

for

NEXT

STATE STATE

REGISTER

FLIP-FLOPS

PORTS

FSM Structure

COMBO. FOR

OUTPUT

OUTPUTS

MEALY


Mealy Machine

The outputs depend on the current state andthe present value of the inputs.

Mealy outputs are asynchronous and canchange in response to any changes in theinputs, independent of the clock.

Glitches-How to avoid?

Require less no. of states compared toMoore Machine.


Moore Machine

The outputs depend only on the present

state.

The outputs are computed by a

combinational logic block whose only

inputs are the flip-flops' state outputs

The outputs change synchronously with the

state transition and the clock edge.


Finite state machine

FSM Structure:-

. State register

- Stores current state

. Next state decoder logic (A)

- Decides next state based on

current state and inputs

. Output logic (B)

-Decodes state (or states and

inputs) to produce outputs

.Outputs from the FSM can be a

function of:

- Current state only (moore)

- Current state and the current

inputs (Mealy)

A B

A B

c1k

c1k Moore FSM

Mealy FSM


FSM Design examples

Q1. Design a circuit that asserts its single output

whenever its input string has two 1's in

sequence.

Cases:

(i) Non-overlapping

(ii) Overlapping of sequence


Q2. Assume a stream of 50k bits are given to the

circuit whose output Z=1 when no. of 1`s in

50k bits are odd else Z = 0. Design the

circuit. (using Mealy machine)

FSM Design examples


Q3. Design a circuit to detect a sequence “010”

(i) non-overlapping

(ii) overlapping

using Mealy machine.

FSM Design examples


FSM design example

Design a circuit to detect a sequence “1010”

(i) non-overlapping

(ii) overlapping

using Mealy machine.


FSM design example

Design a circuit to detect a overlapping

sequence “101”

using

(1) Mealy machine.

(2) Moore machine

And compare the two designs


Q4. A sequential circuit accepts two i/p`s X & Yand generates an o/p Z = 1 whenever the i/p`sare equal & same in the present as well asprevious clock cycle. Design a Mealymachine.

Note: If any state machine has „n‟ inputs, no.

of arrows leaving the state will be 2n .

FSM Design examples


FSM design example

A sequential circuit has one input (X) and one output (Z).The circuit examines groups of 4 consecutive inputs and produces an output Z=1 if the input sequence 0101 or 1001 occurs. The circuit resets after every 4 inputs. Find the Mealy state graph.

Ex: X= 0101 | 0010 | 1001 | 0100

Z= 0001 | 0000 | 0001 | 0000


Q5.Design a Moore finite state recognizer thathas one input (X) and one output (Z). Theoutput is asserted whenever the inputsequence 010 has been observed, as longas the sequence 100 has never beenseen.(Overlapping)

FSM Design examples


Q6. A sequential circuit has one I/p and oneo/p. when I/p sequence “110” occurs the o/pbecomes 1 and remains 1 until the sequence“110” occurs in which case the o/p returnsto zero. The output remains zero until “110”occurs the third time. Draw the statediagram and state table.

FSM Design examples


Q7. State diagram of a transmitter is shown below. Sketch the state diagram for the receiver.

Tx

Rx

X

X

Y

Y

0 11/0

0/0

0/1

1/1Tx

Rx ??

FSM Design examples


Problems, more

problems…Design a pulse train generator circuit using

shift register for the following pulse train:

… 1 0 0 0 1 1 0 …

Next Question: Now can you design a circuit

to generate a specified waveform.


Introduction to Memories


Classification

MEMORY

RAM HYBRID ROM

SRAM

DRAM

FLASH

EEPROM

PROM

EPROM

MASKED


Memory array architecture


Latch and Register based Memory



RAM

Types : SRAM & DRAM

Primary difference: lifetime of the data they

store.

Which to choose & on what basis?

Speed, Area & Cost.



Types : MASKED, PROM & EPROM

They are class of PLD s.

Distinguished by the methods used to write new

data to them (usually called programming) and

the number of times they can be rewritten.

ROM


MASKED : Programmed by manufacturer.

PROM : One time programmable.

EROM : Erased & re-programmable again & again.

ROM


PLD s


ROM


ROM


Exercise on PLAs Design a full adder using PLA

Design a Binary to Gray code converter using PLA

It is desired to generate the following 3 Boolean functions:

F1=ab’c+a’bc’+bc

F2=ab’c+bc+a’bc’

F3=a’b’c’+abc+a’c


BY using OR gate array write down the terms p1,p2,p3,p4 and p5

p1 *

p2 * *

p3 *

P4 *

p5 *

f1 f2 f3




HYBRID

Combine features of both

EEPROM: Once written, the new data will remainin the device forever--or at least until it iselectrically erased.

FLASH: The major difference is that flash devicescan only be erased one sector at a time, not byte-by-byte as in EEPROM.



Comparison: memories

Type Volatile Writeable Erase Size Cost(per Byte) Speed

SRAM Yes Yes Byte Expensive Fast

DRAM Yes Yes Byte Moderate Moderate

RAM No No N/A Inexpensive Fast

PROM No Only once N/A Moderate Fast

EPROM No Yes Entire Chip Moderate Fast

EEPROM No Yes Byte Expensive Fast

FLASH No Yes Sector Moderate Fast


ProblemsExpanding word size, capacity and both

Store 16 8 bit words using 16x4 RAMs

Obtain 1Kx8 module using 1Kx1 RAMs

Store 32 4 bit words using 16x4 chips

Obtain 8Kx8 ROM using 2Kx8 ROMs

Obtain 4Kx8 ROM using 1Kx4 ROMs











Introduction to

STATIC TIMING ANALYSIS


Concepts Covered

Introduction to STA

Timing Paths

Skew

Problems

Clock & Timing Constraints

Exceptional Paths

Multicycle relations with multiple clocks


STA is an exhaustive method of analyzing, debugging and

validating the timing performance of a design.

STA – What is Static Timing Analysis?

Advantages:

Much faster than timing-driven, gate-level

simulation.

Exhaustive

Vector generation NOT required.


Setup Requirement

Hold Requirement

What are our circuit timing requirements?

Clk

100 200 300 400 5000

Data

Data Cannot

Change Within

These Windows

Data

Clk

D Q

QB

Output

OutputBar



Setup Requirement

Hold Requirement

Clk

100 200 300 400 5000

Data

Clk

1000

Data

Early

Required Time

Late

Required Time



Limitations of STA

• Multiple clocks

• False paths: Proper circuit functionality is not checked

• Latches

• Multicycle paths

Works best with synchronous (not asynchronous)

logic

Complex to learn

Must define timing requirements / exceptions

Difficulty in handling:


What is Dynamic Timing Analysis?

Advantage:

Can be very accurate (spice-level)

Disadvantages:

•Analysis quality depends on stimulus vectors

•Non-exhaustive, slow


STA in ASIC Design Flow – Pre layout

Logic Synthesis

Design For test

Floor planning

Constraints(clocks, input drive,

output load)

Static Timing Analysis


(estimated parasitics)


STA in ASIC Design Flow – Post

Layout

Floor planning

Clock Tree Synthesis

Place and Route

Parasitic Extraction

SDF(extracted parasitics)

Constraints(clocks, input drive,

output load)


(estimated parasitics)


(extracted parasitics)


Wire Load Model


Timing Graphs


STA - Timing Graph Introduction

Data

Clk

D Q

QB

Output

OutputBar

A node exists for everyModel pin 4

Cell Pin 8

Bottom

Top

Hierarchical pin 2

14

Q. How many nodes are in our design?

Node: where timing information is stored on the design


STA - Node Types

Data

Clk

D Q

QB

Output

OutputBar

Top

Clock Nodes

All nodes along clock path

Created from “force clock constraints”

Data Nodes


STA - Events

At each node is a group of events modeling signal transitions

Arrival Time (AT) - when the signal arrives

AT

D Q

QB

RT

Required Time (RT) - when the signal is needed

SLEW

Slew (SLEW) - time for signal transition from logic levels


STA - Meeting Timing

AT RT

SLEW

Q. Am I meeting timing at this node?

SLACK = RT - AT

+SLACK

Timing is met when slack is greater than or equal to

zero


STA - Meeting Timing

AT

RT

Q. Am I meeting late mode timing at this node?

SLACK = RT - AT +SLACK

No, the falling edge slack is negative...

AT

RT

-SLACK

HINT: RT should always be after AT


STA - Levels

Q. How many levels of logic are in this design?

1

Q. How many timing levels are in this design?

HINT: Determine the nodes first

2 3 41 2

35

78 9 10

6

HINT: Timing Levels = 2 * Logic Levels + 2

4


1.0

1.0

1.0

1.0

1.0

STA - Calculating AT

STEP 1 : Calculate timing level for each node8

10

7

9

6

1

1

1

1

1

2

2

2

2

2

3

3

9

5

5

4

4

4

STEP 2 : Calculate AT from level 1 to level n

Simplifying assumptions:

Input arrival time of 1

Wire delay 0.2 ; gate delay 0.5

3.81.2

1.2

1.2

1.2

1.2

3.3

4.01.7

1.7

3.1

1.9

1.9

1.9

2.4

2.42.6

2.6


1.0

1.0

1.0

1.0

1.0

STA - Calculating RT

STEP: Calculate RT from level n to level 18

10

7

9

6

1

1

1

1

1

2

2

2

2

2

3

3

9

5

5

4

4

43.8

1.2

1.2

1.2

1.2

1.2

3.3

4.01.7

1.7

3.1

1.9

1.9

1.9

2.4

2.42.6

2.6

Simplifying assumptions:

One number for rise and fall

Output required time of 2.8

Wire delay 0.2 ; gate delay 0.5

2.82.6

2.1

1.9

2.1

1.4

-0.2

1.2

0.5

-0.2

0.5

0.51.2 1.4

0.7

1.4

1.9

1.20.7

0.7

0.0

1.4

0.0


1.0

1.0

1.0

1.0

1.0

STA - Calculating Slack

8

10

7

9

6

1

1

1

1

1

2

2

2

2

2

3

3

9

5

5

4

4

43.8

1.2

1.2

1.2

1.2

1.2

3.3

4.01.7

1.7

3.1

1.9

1.9

1.9

2.4

2.42.6

2.6

2.6

2.1

1.9

2.1

1.4

-0.2

1.2

0.5

-0.2

0.5

0.51.2 1.4

0.7

1.4

1.9

1.20.7

0.7

0.0

1.4

0.0

SLACK = RT - ATQ: What is the formula for late mode slack?

-0.5-1.2

0.2

-0.5

-1.2

-1.2

-0.5

-1.2

-1.2

-1.2

-1.2

-1.2

-0.5

-0.5

-1.2

-0.5

-1.2

-0.5

-0.5

-1.2

-1.2

-0.5

0.2

2.8

Slack is calculated on an as needed basis


What Does Register Bound Mean ?D Q

QB

D Q

QB

D Q

QB

D Q

QB

• Register bound implies that the combinational logic is

bounded by registers on the inputs and the outputs.

• Combinational logic is represented by a symbolic blob.


STA Introduction Summary• Basics (setup, hold)

• Timing Graph (Clock nodes, Data nodes)

• Event description (RT, AT, slew)

• Timing information for a design is stored on nodes

• At each node a group of events models signal

transitions.

• Slack expresses the relationship between signal

arrival time and required time at a node.

• Specifying the clocks constraints all register-to-

register (register-bound) paths.


Basic Terminologies


Concepts Covered

Minimum clock

period

Hold constraint

Clock skew

Clock latency

Clock jitter

Setup time

Hold time

Clock-to-Q time

Cause and effect of

timing violations

Critical path

False path

Multicycle path

Specifying clocks

Ideal and computed

clocks

Generated clocks


Basic Terminologies

Critical path: The slowest path on the chip

between flops or flops and pins. The critical

path limits the maximum clock speed.


Setup time:

The amount of time the synchronous input

must be stable before the active edge of clock.

Hold time:

The amount of time the synchronous input

must be stable after the active edge of clock.

Basic Terminologies


Recovery time: It is the time available between the

asynchronous signal going inactive to the active clock

edge.

Removal time: It is the time between active clock edge

and asynchronous signal going inactive.

Recovery time:

Like setup time for asynchronous port (set, reset)

Removal time:

Like hold time for asynchronous port (set, reset)

Basic Terminologies


Three Steps in Static Timing Analysis

Circuit is broken down into sets of timing

paths.

Delay of each path is calculated.

Path delays are checked to see if timing

constraints have been met.


What is a Timing Path?

A Timing Path is a point-to-point path in a

design which can propagate data from one flip-

flop to another.

Each path has a startpoint and an endpoint

Startpoints:

Input ports, Clock pins of flip-flops

Endpoints:

Output ports, Data input pins of flip-flops


Types of Timing Paths


Organizing Timing Paths Into Groups

Timing paths are grouped into path groups by the

clocks controlling their endpoints.

Synthesis tools like Prime Time and Design

Compiler organize timing reports by path groups.

CG-CoreEl Sandeepani School of VLSI Design CG-CoreEl Sandeepani School of VLSI Design Critical path??


Critical path??


Basic Terminologies

Maximum Clock Frequency/ Minimum Clock

Period

The clock frequency for a synchronous

sequential circuit is limited by the timing

parameters of its flip-flops and gates. This limit

is called the maximum clock frequency for the

circuit. The minimum clock period is the

reciprocal of this frequency.


Condition for Hold time

To satisfy hold time: Tc2q + Tpd (minimum) > Thold

D Q

QB

D Q

QB

clkbar



D Q Combinational

logic

D Q

CLK

tffpd tcomb

tsetup & thold

tffpd - CLK to Q, FF propagation delay (min, max)

tcomb - combinational logic dely (min, max)

tsetup - input stable before clock (min)

thold - input stable after clock (min)

JAL

Synchronous System -Detailed Timing


Example Timing Violations: Good Timing


Required: tclk,min > tffpd,max + tcomb,max + tsetup,min

Difference = Setup time margin>= 0 for guaranteed operation

Required: tffpd, min + tcomb,min > thold,min

Difference = Hold time margin>= 0 for guaranteed operation

Synchronous System - Detailed Timing


tcomb = 2 ns, min and 20 ns, max tffpd = 3 ns, min and 15 ns, max

tsetup = 5 ns, min

thold = 2 ns, min

Setup margin @ 10 MHz clk?

Max Frequency?

Hold Margin?

Combinational

logic

State

Register

Q3

Q2

Q1

in1

in2

JAL

Synchronous System Example


tcomb = 2 ns, min and 20 ns, max tffpd = 3 ns, min and 15 ns, max

tsetup = 5 ns, min

thold = 2 ns, min

Setup margin @ 10 MHz clk? 100 - (15 + 20 +5) = 60 ns

Max Frequency? tclk,min >= 40 ns, so fmax <= 25 MHz

Hold Margin? (3 + 2) -2 = 3ns

Combinational

logic

State

Register

Q3

Q2

Q1

in1

in2

Synchronous System Example


74LS74 Data Sheet Timing

Parameter Min Max Units

tW Pulse Width - Clock High 18 ns

- Preset Low 15 ns

- Clear Low 15 ns

tSU Setup Time 20 ns

tH Hold Time 0 ns

fMAX Max Clock Frequency 20 MHz

tPLH Prop Delay, Clock-to-Q 35 ns

tPLH Prop Delay, Preset-to-Q 35 ns

tPLH Prop Delay, Clear-to-Q 35 ns


Functional Timing Diagram

Shows no delays, so all edges line up

Shows what happens each clock, ignoring exact delays

Illustrates operation, but does not specify upper and lower limits

INSUFFICIENT information for a REAL system designClock

Sig1

Sig2


tH

tL

Clock

tffpd

flip-flop

outputs

combinational

outputs

tcomb

tclk

setup-time

margin tsetup

thold

flip-flop

inputs


Example Timing Violations: Setup Violation


Example Timing Violations: Hold Violation


Clock Skew

• Clock Skew: The maximum difference in arrival time of the

clock signal to each register in the design

clock

Clock arrival

time at 1.1ns

Clock arrival

time at 1.3ns

Skew = 1.3ns - 1.1ns = .2ns


Absolute Clock Skew – A Definition

Your chip

clock input

Flip

Flop

Time from clock input (at pin) to

clock input at a given flip flop


Relative Clock Skew

Your chip

clock input

Flip

Flop

Time between 2 flip flops receiving

the clock signal

Flip

Flop


Failure / Data loss Due To Large

Skew

Combinational

LogicFlip

Flop

Flip

Flop

d delayclk

“B”

AoutAin

“A”

Bin

If new data (Ain) gets to point “Bin” before clock does, system will fail by simply skipping over old data…

For this illustration - ignore tsetup


Combinational

LogicFlip

Flop

Flip

Flop

d delayclk

“B”

AoutAin

“A”

Bin

Clock arrives at point “A”

T = 0ns


Data arrives at combo logic input

Combinational

LogicFlip

Flop

Flip

Flop

d delayclk

“B”

Ain

“A”

BinAout

T = tclk-to-Q


Data Exits Comb Logic

Combinational

LogicFlip

Flop

Flip

Flop

d delayclk

“B”

Ain

“A”

Aoutnew

Bin

Bin

T = tclk-to-Q + tlogic


Clock Reaches “B”

Combinational

LogicFlip

Flop

Flip

Flop

clk

“B”

Ain

“A”

Aoutnew

Bin

Bin

d delay

T = tclk-to-Q + tlogic Tskew = td


Failure!!!

Combinational

LogicFlip

Flop

Flip

Flop

clk

“B”

Ain

“A”

Aoutnew

Bin

Bin

d delay

New

Bin

What happened to old Bin???

If tclk-to-Q+tlogic < td it fails…


Clock Jitter

jitter

clock


Clock jitter is caused by:

• temperature and voltage variations over time

• temperature and voltage variations across different locations on a chip

• manufacturing variations between different parts

• etc.

Clock Jitter


More on Skew


Positive & Negative Skew

R1In

(a) Positive skew

CombinationalLogic

D Q

tCLK1CLK

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

• • •D Q

delay

R1In

(b) Negative skew

CombinationalLogic

D Q

tCLK1

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

• • •D Q

delay CLK


Positive Skew

CLK1

CLK2

T CLK

d

T CLK d

t h d

2

1

4

3

R1In Combinational

LogicD Q

tCLK1CLK

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

• • •D Q

delay


Negative Skew

CLK1

CLK2

T CLK

d

T CLK - d

2

1

4

3

R1In Combinational

LogicD Q

tCLK1

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

• • •D Q

delay CLK


Example Timing Violations: Minimum Clock Period


Example Timing Violations: Hold Constraint


Analysis of Timing Report

#### Path 1 ############################################

Start rp.PC.outreg_reg[0]/Q

End rp.PC.outreg_reg[15]/D

Reference rp.PC.outreg_reg[15]/CK

Path slack 1p

Reference arrival time 704

+ Cycle adjust (clock:R#1 vs. clock:R#2) 13000

- Margin -100

- Setup time -646

---------------------------------------- -----

End-of-path required time (ps) 12957

Starting arrival time 0

+ Clock path delay 704

+ Data path delay 12252

---------------------------------------- -----

End-of-path arrival time (ps) 12956

Starting and ending points

Slack

time = 0

starting and

reference edge

arrival timedata

slack = required time - arrival time

clock period

data arrival

time


A Timing Example:


Example 1

D Q

QCK

Q

TW ≥ max tPFF + tsu

For the 7474, max tPLH = 25ns, max tPHL = 40ns, tsu = 20nsTW ≥ max (max tPLH + tsu, max tPHL + tsu)

TW ≥ max (25+20, 40+20) = 60


D Q

CK

Q

TW ≥ max tPFF + max tPINV + tsu

Example 2


D Q

Q

D Q

Q

MUX

0

1

Q0 Q1

CK

TW ≥ max tPFF + max tPMUX + tsu

Example 3


Paths from Q1 to Q1:




None

TW ≥ max tPDFF +tJKsu = 20 +10 = 30 ns

TW ≥ max tPDFF + max tAND + tJKsu = 20 + 12 + 10 = 42 ns

TW ≥ max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns

TW ≥ max tPJKFF + max tAND + tJKsu = 25 + 12 + 10 = 47

TW ≥ 47 ns

Example 4


Example 5 : Effect of clock skew on clock rate

Q1Q2

D Q

Q

D Q

Q

CK

C1C2

D2

TW ≥ max TPFF + max tOR + tsu

(if clock not skewed, i.e., tINV = 0)TW ≥ max TPFF + max tOR + tsu - min tINV

(if clock skewed, i.e., tINV > 0)

•Clock C2 skewed after C1


Example 6: Maximum Allowable Clock Skew

How much skew between C1 and C2 can be tolerated in the

following circuit?

Case 1: C2 delayed after C1

D Q

Q

D Q

Q

C2

Q1 D2

C1

tPFF > th + tSK

tSK < min tPFF - th


Case 2: C1 delayed from C2

D Q

Q

D Q

Q

C2

Q1 D2

C1


How does additional delay between the flip-flops affect the skew calculations?

tSK ≤ min tPFF - th

tsk ≤ min tPFF + min tMUX - th

Example 7


Understanding

And

Describing Clocks


Defining Clocks

• A clock is defined by its period, waveform and slew time.


Specifying Clocks

• Standard clock

• Inverted clock

• Virtual clock

• Derived clock

• Gated clock


• Blast Fusion(MAGMA) clock command:

force timing clock node period –slew time

-waveform {-rise R –fall F …} –virtual –name name

• Equivalent SDC command:

create_clock –period –waveform –name name

• Example syntax:force timing clock $m/clk 10n

Q. Why aren`t we using –waveform option?

A. The default waveform start at 0 with a 50% duty cycle.

Standard Clock Specification

0 5 10

clk

D Q

QB

D Q

QB

clk


•create_clock -period 20 -waveform {0 8}

•create_clock -period 20 waveform {10 18}

Standard Clock Specification

SDC commands


Inverted Clock

• Blast Fusion clock command

force timing clock $m/clkbar 5n

Q. What is an inverted clock with a 10/50 duty cycle shifted by 2ns ?

-waveform {-fall 2n –rise 3n}

D Q

QB

D Q

QB

clkbar

0 1 2 3 4 5 6

clk clkbar

0 1 2 3 4 5 6

clkbar

0 1 2 3 4 5 6


Virtual Clock

• A virtual clock has no sources. It exists in memory but is not part of

a design. A virtual clock lets you associate arrival and required

times with clocks external to the chip or block.

• The name of virtual clock must be a unique name that is not

associated with any port or instance in the synthesized design.


Generated Clock

clk

D Q

QBD Q

QB

D Q

QB

force timing clock $m/clk 5n

force timing clock $m/f0/Q –generated –source $m/clk –divider 2

f0D Q

QB

• A design might include clock dividers or other

structures that produce a new clock from a

master source clock.


Gated Clock

CLOCK

CLKEN

GCLK

CLOCK

CLKEN

CGLK

•Clock gating reduces power consumption by switching off the clock to flip-flops when the value of those flip-flops does not change.


Gated Clock: Setup and Hold Margins for

AND & NAND gates•The setup margin is measured relative to the falling transition of the gating cell clock input.

•The hold margin is measured relative to the rising transition of the clock input.


Gated Clock: Setup and Hold Margins for OR &

NOR gates


Describing Clock Variations

• Clock latency (delay)

• Clock skew

• Jitter


Source, Network and IO

LatencyChip

D Q D Q D Q D Q

network latency

(on-chip)

source latency

(off-chip)

Clock

IO

latencyIO

latency


Source, Network and IO

Latency


Clock Generation



Summary: Clocks

• A clock is defined by its period, waveform and

slew time

• Clock variations that can be described for timing

calculation include latency, skew and jitter.


False Paths


What are False paths?

• Paths that physically exist in a design but are not

logic/functional paths

• These paths never get sensitized under any input

conditions


Logically Impossible Example

Mux 1

C C1 C2A

B

Mux 2

S

B1 B2

OUT

•A path may exist in the circuit but no combination of input vectors may ever exercise it


Logic Removal Example

•A block may be reused and certain signal functions are no longer required


Most STA`s can`t leave combinational loops in the

design, because a race condition will occur

"I want to break the

combinational loop at

U1/B"

force timing break -from $m/U1/B -to $m/U1/Z

D Q

QBD Q

QB

A

B

Z

U0

A

B

Z

U1

broken arc

Combinational Loop Example


Multicycle Path

A start point, end point and/or "through" point is

specified, along with the number of allowed clock

cycles.

•Multicycle paths are paths which intentionallyrequire more than one clock cycle to propagate.

•This information cannot possibly be inferred by thetiming analyzer, so it must be specified by thedesigner so the analyzer can mark the path andcorrectly compute the timing.


D Q

QB

D Q

QB

CK

U1 U2

force timing multicycle -from $m/U1/Q -to $m/U2/D -cycle 2

Multicycle Path: Example


Handling Multiple Clocks


Multiple Clocks

Step1: Determine the Least Common Multiple (LCM)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

A

(6 ns)

B

(8 ns)

• What is the LCM between these two clocks?

The timer needs to calculate the delays of the

circuit to the LCM to find all path relationships


Setup Relationship: A Rising, B Rising

Find the Setup Relationship between A rising and B rising

• The setup relationship is the closest distance between the launching

clock edge (A) and the receiving clock edge (B)

D Q

QB

D Q

QB


Setup Relationship: A Rising, B Falling

Find the Setup Relationship between A rising and B falling

D Q

QB

D Q

QB


Setup Relationship: A Falling, B Rising

Find the Setup Relationship between A falling and B rising

D Q

QB

D Q

QB


Setup Relationship: A Falling, B Falling

Find the Setup Relationship between A falling and B falling

D Q

QB

D Q

QB


Hold Relationship: A Rising, B Rising

Find the Hold Relationship between A rising and B rising

• The hold relationship is the closest distance between the

launching clock edge (A) and the previous receiving clock

edge (B)

D Q

QB

D Q

QB


Hold Relationship: A Rising, B Falling

Find the Hold Relationship between A rising and B falling

D Q

QB

D Q

QB


Hold Relationship: A Falling, B Rising

Find the hold Relationship between A falling and B rising

D Q

QB

D Q

QB


Hold Relationship: A Falling, B Falling

Find the hold Relationship between A falling and B falling

D Q

QB

D Q

QB


Pipelining Concept


Pipelining

Concept


Anatomy of a Pipeline Stage

Combinational

Logic

Tclock-to-Q Tlogic Tsetup

Flip

Flop

f

Flip

Flop

f

One clock cycle

setuplogicQtoclockcycle TTTT


Anatomy of a Synchronous System

Comb

LogicFlip

Flop

f

Flip

Flop

f

Comb

LogicFlip

Flop

f

Comb

Logic

input input input

• Overall system cycle time

• determined by longest pipeline stage (taking

input arrival times into account)


Latency in Pipelines


Pipelining Example

Original circuit

– Two logic levels between SOURCE_FFS and

DEST_FF

– fMAX = ~207 MHz


Pipelined circuit

– One logic level between each set of flip-flops

– fMAX = ~347 MHz

Pipelining Example…contd


Review Question

Given the original circuit, what is wrong with

the pipelined circuit?

How can the problem be corrected?


Retiming Concept

Register balancing in order to balance the timing


Time Borrowing


TIME BORROWING* Time borrowing occurs in latch-based designs


TIME BORROWING…contd


There is a short delay on the first timing path and a

long delay on the second timing path.

The question is whether time borrowing can

eliminate negative slack

TIME BORROWING…contd


GLUE LOGIC


AVOID GLUE LOGIC

THE NAND GATE AT THE TOP LEVEL SERVERS ONLY

TO GLUE THE INSTATIATED CELLS

OPTIMIZATION IS LIMITED BECAUSE THE GLUE

LOGIC CANNOT BE ABSORBED

X

clock

RegA

X

clock

RegB

X

clock

RegA

GLUE


REMOVE GLUE LOGIC BETWEEN BLOCKS

THE GLUE LOGIC CAN NOW BE OPTIMIZED WITH

OTHER LOGIC

TOP LEVEL DESIGN IS ONLY A STRUCTURAL

NETLIST, DOESN‟T NEED TO BE COMPILED

X

clock

RegA

X

clock

RegB

X+GLUE

clock

RegA


Signal Interface


Signal Interface: Model


Interface Taxonomy (Parallelism)


Interface Taxonomy (Topology)


Interface Taxonomy (Timing)


Interface Taxonomy (Signaling)

Documents

IMP Digital Slides