Midterm Examination Semester II 2008/2009
INTERNATIONAL ISLAMIC UNIVERSITY MALAYSIAMID-TERM
EXAMINATION
SEMESTER II, 2008/2009 SESSIONKULLIYYAH OF ENGINEERING
Course Code: ECE 1231 Course Title: Electronics
Time
: 3:00 pm-5:00 pm Date: 21-Feb-2009Duration: 2 Hours
INSTRUCTIONS TO CANDIDATESDO NOT OPEN UNTIL YOU ARE ASKED TO DO
SO
Do not use your own sheet.
A total mark of this examination is 100.
This examination is worth 30% of the total assessment. Answer
ALL questions.Any form of cheating or attempt to cheat is a serious
offence which may lead to dismissal.Question 1Question 2Question
3Question 4Total Marks
Marks25252525100
Marks Obtained
Q.1 [25 marks](a) Consider a pn junction at K in which A and .
Find the forward-bias voltage to produce a current of 150 A. (6
marks)(b) In the circuit shown in Fig. 1, find the diode voltage
and the supply voltage such that the current is mA. Assume the
diode cut-in voltage is V. Also determine the power dissipated in
the diode. (9 marks)
Fig. 1(c) Consider the Zener diode circuit shown in Fig. 2. The
Zener breakdown voltage is V at mA, and the incremental Zener
resistance is . Determine for and . (10 marks)
Fig. 2Q.2 [25 marks](a) Briefly explain the advantage of
connecting an RC filter to the output of a diode rectifier
circuit.(4 marks)(b) The input voltage to the half-wave rectifier
in Fig. 3 is V. Assume a diode cut-in voltage of V. The ripple
voltage is to be no more than V. If the filter capacitor is 50 F,
determine the minimum load resistance that can be connected to the
output. (4 marks)
Fig. 3(c) The input signal voltage to the full-wave bridge
rectifier circuit in Fig. 4 is V. Assume V for each diode.
Determine (i) the required turns ratio of the transformer to
produce a peak output voltage of 100 V, (ii) the diode PIV rating,
and (iii) the average value of the output voltage.(8 marks)
Fig. 4(d) In the voltage regulator circuit in Fig. 5, V, V, ,
and . Determine , , and . (9 marks)
Fig. 5Q.3 [25 marks](a) Define ripple voltage. How can the
magnitude of the ripple voltage be reduced?
(4 marks)(b) For the diode clipper circuit in Fig. 6, plot
versus time over two periods for sinusoidal input signal. Assume
for each diode and . (7 marks)
Fig. 6(c) A diode clamper circuit with sinusoidal input signal
is shown in Fig. 7. Assume . Plot (i) the capacitor voltage versus
time and (ii) the output voltage versus time. (8 marks)
Fig. 7(d) Consider the circuit in Fig. 8. The output of a diode
OR logic gate is connected to the input of a second diode OR logic
gate. Assume for each diode. Determine the output and for: (i) ;
(ii) V, V; and (iii) V.
(6 marks)
Fig. 8
Name:_______________________________________________
Matric No:____________________ Section:________
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_1296393417.unknown
_1296424172.unknown
_1296424395.unknown
_1296484676.unknown
_1296486331.unknown
_1296509856.unknown
_1296509917.unknown
_1296509952.unknown
_1296509895.unknown
_1296486358.unknown
_1296487034.bin
_1296484931.bin
_1296482660.bin
_1296483818.unknown
_1296425390.unknown
_1296424218.unknown
_1296424349.unknown
_1296424371.unknown
_1296424324.unknown
_1296424197.unknown
_1296394518.unknown
_1296422533.unknown
_1296422582.unknown
_1296397538.unknown
_1296422495.unknown
_1296397332.bin
_1296393811.unknown
_1296393839.unknown
_1296393715.unknown
_1296391009.unknown
_1296393269.bin
_1296393389.unknown
_1296391124.unknown
_1296391205.unknown
_1296389980.unknown
_1296390030.unknown
_1296390784.bin
_1296389738.unknown
_1296389796.unknown
_1295298331.unknown
_1295298320.unknown
